16931 lines
1.2 MiB
16931 lines
1.2 MiB
; --------------------------------------------------------------------------------
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; @Title: ATSAM4C On-Chip Peripherals
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; @Props: Released
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; @Author: ADK
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; @Changelog: 2014-09-11 ADK
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; 2015-05-29 STR
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; @Manufacturer: ATMEL - Atmel Corporation
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; @Doc:
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; atmel_11102_smartenergy_sam4c16c-sam4c8c_datasheet.pdf (2014-04-14)
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; atmel-11203-smartenergy-sam4cmp16c-sam4cmp8c-sam4cms16c-sam4cms8c-datasheet.pdf (2014-04-14)
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; @Core: Cortex-M4
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; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: peratsam4c.per 17736 2024-04-08 09:26:07Z kwisniewski $
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;KNOWN PROBLEMS:
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; GPBR - incorrect addresses of registers in memory map in reference manual
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base ad:0x00000000
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tree.close "Core Registers (Cortex-M4F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes"
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bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes"
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bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes"
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group.long 0x10++0x0B
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending"
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bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x07
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line.long 0x00 "HFSR,Hard Fault Status Register"
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bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
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bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
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bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested"
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group.long 0xD34++0x0B
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line.long 0x00 "MMFAR,MemManage Fault Address Register"
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line.long 0x04 "BFAR,BusFault Address Register"
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line.long 0x08 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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width 10.
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tree "Feature Registers"
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
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bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
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bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
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textline " "
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bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
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line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
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bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
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bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
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bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
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textline " "
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bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
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bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
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textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM4F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x07
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline ""
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
|
|
hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
config 16. 8.
|
|
tree "RSTC (Reset Controller)"
|
|
base ad:0x400E1400
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "RSTC_CR,Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password"
|
|
bitfld.long 0x00 3. " EXTRST ,External Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PERRST ,Peripheral Reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " PROCRST ,Processor Reset" "No effect,Reset"
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "RSTC_SR,Status Register"
|
|
textfld " "
|
|
in
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "RSTC_MR,Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password"
|
|
bitfld.long 0x00 8.--11. " ERSTL ,External Reset Length [Slow Clock cycles (time)]" "2 cycles (60 us),4 cycles (120 us),8 cycles (240 us),16 cycles (480 us),32 cycles (960 us),64 cycles (1.92 ms),128 cycles (3.84 ms),256 cycles (7.68 ms),512 cycles (15.36 ms),1024 cycles (30.72 ms),2048 cycles (61.44 ms),4096 cycles (122.88 ms),8192 cycles (245.76 ms),16384 cycles (491.52 ms),32768 cycles (0.98304 s),65536 cycles (1.96608 s)"
|
|
textline " "
|
|
bitfld.long 0x00 4. " URSTIEN ,User Reset Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " URSTEN ,User Reset Enable" "Disabled,Enabled"
|
|
line.long 0x04 "RSTC_CPMR,Reset Controller Coprocessor Mode Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " CPKEY ,Coprocessor System Enable Key"
|
|
bitfld.long 0x04 4. " CPEREN ,Coprocessor Peripheral Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CPROCEN ,Coprocessor (second processor) Enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "RTT (Real-time Timer)"
|
|
base ad:0x400E1430
|
|
width 11.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "RTT_MR,Real-Time Timer Mode Register"
|
|
bitfld.long 0x00 24. " RTC1HZ ,Real-time Clock 1Hz Clock Selection" "16-bit prescaler,RTC 1 Hz clock"
|
|
bitfld.long 0x00 20. " RTTDIS ,Real-time Timer Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 18. " RTTRST ,Real-Time Timer Restart" "No effect,Restarted"
|
|
bitfld.long 0x00 17. " RTTINCIEN ,Real-Time Timer Increment Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ALMIEN ,Alarm Interrupt Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--15. 1. " RTPRES ,Real-Time Timer Prescaler Value"
|
|
line.long 0x4 "RTT_AR,Real-Time Timer Alarm Register"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "RTT_VR,Real-Time Timer Value Register"
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "RTT_SR,Real-time Timer Status Register"
|
|
textfld " "
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
tree "RTC (Real-time Clock)"
|
|
base ad:0x400E1460
|
|
width 12.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "RTC_CR,Control Register"
|
|
bitfld.long 0x00 16.--17. " CALEVSEL ,Calendar Event Selection" "Week change,Month change,Year change,?..."
|
|
bitfld.long 0x00 8.--9. " TIMEVSEL ,Time Event Selection" "Minute,Hour,Midnight,Noon"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UPDCAL ,Update Request Calendar Register" "No effect,Stopped"
|
|
bitfld.long 0x00 0. " UPDTIM ,Update Request Time Register" "No effect,Stopped"
|
|
line.long 0x04 "RTC_MR,RTC Mode Register"
|
|
bitfld.long 0x04 28.--29. " TPERIO ,Period of the Output Pulse" "1 s,500 ms,250 ms,125 ms"
|
|
bitfld.long 0x04 24.--26. " THIGH ,High Duration of the Output Pulse" "31.2 ms,15.6 ms,3.91 ms,967 us,488 us,122 us,30.5 us,15.2 _s"
|
|
textline " "
|
|
bitfld.long 0x04 20.--22. " OUT1 ,RTCOUT1 Output Source Selection" "No waveform,1 Hz square,32 Hz square wave,64 Hz square wave,512 Hz square wave,Toggle at alarm flag rise,Copy of the alarm flag,Duty cycle programmable pulse"
|
|
textline " "
|
|
bitfld.long 0x04 16.--18. " OUT0 ,RTCOUT0 Output Source Selection" "No waveform,1 Hz square,32 Hz square wave,64 Hz square wave,512 Hz square wave,Toggle at alarm flag rise,Copy of the alarm flag,Duty cycle programmable pulse"
|
|
textline " "
|
|
bitfld.long 0x04 15. " HIGHPPM ,HIGH PPM Correction" "Lower,Higher"
|
|
hexmask.long.byte 0x04 8.--14. 1. " CORRECTION ,Correction"
|
|
textline " "
|
|
bitfld.long 0x04 4. " NEGPPM ,NEGative PPM Correction" "Positive,Negative"
|
|
bitfld.long 0x04 1. " PERSIAN ,PERSIAN Calendar" "Gregorian,Persian"
|
|
textline " "
|
|
bitfld.long 0x04 0. " HRMOD ,12/24 Hour Mode" "24,12"
|
|
if ((((d.l(ad:0x400E1460+0x04))&0x01)==0x01)&&(((d.l(ad:0x400E1460+0x08))&0x000000)==0x000000))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RTC_TIMR,Time Register"
|
|
bitfld.long 0x00 20.--21. " TIME ,Current Hour (tens)" "0,1,?..."
|
|
bitfld.long 0x00 16.--19. ",Current Hour (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--14. ":,Current Minute (tens)" "0,1,2,3,4,5,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Minute (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 4.--6. ":,Current Second (tens)" "0,1,2,3,4,5,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Second (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 22. " ,Ante Meridiem Post Meridiem Indicator" "AM,PM"
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x01)==0x01)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RTC_TIMR,Time Register"
|
|
bitfld.long 0x00 20.--21. " TIME ,Current Hour (tens)" "0,1,?..."
|
|
bitfld.long 0x00 16.--19. ",Current Hour (units)" "0,1,2,?..."
|
|
bitfld.long 0x00 12.--14. ":,Current Minute (tens)" "0,1,2,3,4,5,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Minute (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 4.--6. ":,Current Second (tens)" "0,1,2,3,4,5,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Second (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 22. " ,Ante Meridiem Post Meridiem Indicator" "AM,PM"
|
|
elif (((d.l(ad:0x400E1460+0x08))&0x000000)==0x200000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RTC_TIMR,Time Register"
|
|
bitfld.long 0x00 20.--21. " TIME ,Current Hour (tens)" "0,1,2,?..."
|
|
bitfld.long 0x00 16.--19. ",Current Hour (units)" "0,1,2,3,?..."
|
|
bitfld.long 0x00 12.--14. ":,Current Minute (tens)" "0,1,2,3,4,5,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Minute (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 4.--6. ":,Current Second (tens)" "0,1,2,3,4,5,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Second (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RTC_TIMR,Time Register"
|
|
bitfld.long 0x00 20.--21. " TIME ,Current Hour (tens)" "0,1,2,?..."
|
|
bitfld.long 0x00 16.--19. ",Current Hour (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--14. ":,Current Minute (tens)" "0,1,2,3,4,5,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Minute (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 4.--6. ":,Current Second (tens)" "0,1,2,3,4,5,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Second (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
endif
|
|
if (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x0C))&0x001F0000)==(0x00010000||0x00030000||0x00050000||0x00070000||0x00080000||0x00100000||0x00120000))&&(((d.l(ad:0x400E1460+0x0C))&0x100000)==0x000000)&&(((d.l(ad:0x400E1460+0x0C))&0x70)==0x10)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" "0,1,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,2,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" ",9,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x0C))&0x001F0000)==(0x00010000||0x00030000||0x00050000||0x00070000||0x00080000||0x00100000||0x00120000))&&(((d.l(ad:0x400E1460+0x0C))&0x100000)==0x000000)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" "0,1,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,2,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" "0,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x0C))&0x001F0000)==(0x00010000||0x00030000||0x00050000||0x00070000||0x00080000||0x00100000||0x00120000))&&(((d.l(ad:0x400E1460+0x0C))&0x100000)==0x100000)&&(((d.l(ad:0x400E1460+0x0C))&0x70)==0x10)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" "0,1,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" "0,1,2,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,2,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" ",9,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x0C))&0x001F0000)==(0x00010000||0x00030000||0x00050000||0x00070000||0x00080000||0x00100000||0x00120000))&&(((d.l(ad:0x400E1460+0x0C))&0x100000)==0x100000)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" "0,1,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" "0,1,2,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,2,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" "0,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x0C))&0x001F0000)==(0x00010000||0x00030000||0x00050000||0x00070000||0x00080000||0x00100000||0x00120000))&&(((d.l(ad:0x400E1460+0x0C))&0x100000)==0x000000)&&(((d.l(ad:0x400E1460+0x0C))&0x70)==0x10)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,2,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" ",9,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x0C))&0x001F0000)==(0x00010000||0x00030000||0x00050000||0x00070000||0x00080000||0x00100000||0x00120000))&&(((d.l(ad:0x400E1460+0x0C))&0x100000)==0x000000)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,2,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" "0,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x0C))&0x001F0000)==(0x00010000||0x00030000||0x00050000||0x00070000||0x00080000||0x00100000||0x00120000))&&(((d.l(ad:0x400E1460+0x0C))&0x100000)==0x100000)&&(((d.l(ad:0x400E1460+0x0C))&0x70)==0x10)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" "0,1,2,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,2,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" ",9,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x0C))&0x001F0000)==(0x00010000||0x00030000||0x00050000||0x00070000||0x00080000||0x00100000||0x00120000))&&(((d.l(ad:0x400E1460+0x0C))&0x100000)==0x100000)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" "0,1,2,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,2,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" "0,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x0C))&0x1F0000)==(0x010000||0x030000||0x050000||0x070000||0x080000||0x100000||0x120000))&&(((d.l(ad:0x400E1460+0x0C))&0x100000)==0x000000)&&(((d.l(ad:0x400E1460+0x0C))&0x70)==0x10)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,2,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" ",9,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x0C))&0x1F0000)==(0x010000||0x030000||0x050000||0x070000||0x080000||0x100000||0x120000))&&(((d.l(ad:0x400E1460+0x0C))&0x100000)==0x000000)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,2,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" "0,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x0C))&0x1F0000)==(0x010000||0x030000||0x050000||0x070000||0x080000||0x100000||0x120000))&&(((d.l(ad:0x400E1460+0x0C))&0x100000)==0x100000)&&(((d.l(ad:0x400E1460+0x0C))&0x70)==0x10)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" "0,1,2,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,2,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" ",9,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x0C))&0x1F0000)==(0x010000||0x030000||0x050000||0x070000||0x080000||0x100000||0x120000))&&(((d.l(ad:0x400E1460+0x0C))&0x100000)==0x100000)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" "0,1,2,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,2,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" "0,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x0C))&0x001F0000)==(0x00040000||0x00060000||0x00090000||0x00110000||0x00120000))&&(((d.l(ad:0x400E1460+0x0C))&0x100000)==0x000000)&&(((d.l(ad:0x400E1460+0x0C))&0x70)==0x10)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" "0,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,2,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" ",9,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x0C))&0x001F0000)==(0x00040000||0x00060000||0x00090000||0x00110000||0x00120000))&&(((d.l(ad:0x400E1460+0x0C))&0x100000)==0x000000)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" "0,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,2,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" "0,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x0C))&0x001F0000)==(0x00040000||0x00060000||0x00090000||0x00110000||0x00120000))&&(((d.l(ad:0x400E1460+0x0C))&0x100000)==0x100000)&&(((d.l(ad:0x400E1460+0x0C))&0x70)==0x10)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" "0,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" "0,1,2,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,2,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" ",9,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x0C))&0x001F0000)==(0x00040000||0x00060000||0x00090000||0x00110000||0x00120000))&&(((d.l(ad:0x400E1460+0x0C))&0x100000)==0x100000)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" "0,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" "0,1,2,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,2,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" "0,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x0C))&0x001F0000)==(0x00040000||0x00060000||0x00090000||0x00110000))&&(((d.l(ad:0x400E1460+0x0C))&0x100000)==0x000000)&&(((d.l(ad:0x400E1460+0x0C))&0x70)==0x10)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,2,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" ",9,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x0C))&0x001F0000)==(0x00040000||0x00060000||0x00090000||0x00110000))&&(((d.l(ad:0x400E1460+0x0C))&0x100000)==0x000000)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,2,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" "0,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x0C))&0x001F0000)==(0x00040000||0x00060000||0x00090000||0x00110000))&&(((d.l(ad:0x400E1460+0x0C))&0x100000)==0x100000)&&(((d.l(ad:0x400E1460+0x0C))&0x70)==0x10)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" "0,1,2,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,2,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" ",9,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x0C))&0x001F0000)==(0x00040000||0x00060000||0x00090000||0x00110000))&&(((d.l(ad:0x400E1460+0x0C))&0x100000)==0x100000)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" "0,1,2,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,2,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" "0,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x0C))&0x1F0000)==(0x040000||0x060000||0x090000||0x110000))&&(((d.l(ad:0x400E1460+0x0C))&0x100000)==0x000000)&&(((d.l(ad:0x400E1460+0x0C))&0x70)==0x10)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,2,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" ",9,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x0C))&0x1F0000)==(0x040000||0x060000||0x090000||0x110000))&&(((d.l(ad:0x400E1460+0x0C))&0x100000)==0x000000)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,2,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" "0,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x0C))&0x1F0000)==(0x040000||0x060000||0x090000||0x110000))&&(((d.l(ad:0x400E1460+0x0C))&0x100000)==0x100000)&&(((d.l(ad:0x400E1460+0x0C))&0x70)==0x10)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" "0,1,2,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,2,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" ",9,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x0C))&0x1F0000)==(0x040000||0x060000||0x090000||0x110000))&&(((d.l(ad:0x400E1460+0x0C))&0x100000)==0x100000)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" "0,1,2,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,2,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" "0,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x0C))&0x1F0000)==0x020000)&&(((d.l(ad:0x400E1460+0x0C))&0x00000000)==0x00000000)&&(((d.l(ad:0x400E1460+0x0C))&0x70)==0x10)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,?..."
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,2,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" ",9,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x0C))&0x1F0000)==0x020000)&&(((d.l(ad:0x400E1460+0x0C))&0x00000000)==0x00000000)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,?..."
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,2,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" "0,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x0C))&0x1F0000)==0x020000)&&(((d.l(ad:0x400E1460+0x0C))&0x70)==0x10)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,?..."
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,2,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" ",9,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x0C))&0x1F0000)==0x020000)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,?..."
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,2,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" "0,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x0C))&0x1F0000)==0x000000)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,2,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" "0,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x02)&&(((d.l(ad:0x400E1460+0x0C))&0x301F0000)==(0x30010000||0x30020000||0x30030000||0x30040000||0x30050000||0x30060000))
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" "0,1,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Saturday,Sunday,Monday,Tuesday,Wednesday,Thursday,Friday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" ",3,4,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x02)&&(((d.l(ad:0x400E1460+0x0C))&0x301F0000)==(0x00010000||0x00020000||0x00030000||0x00040000||0x00050000||0x00060000))
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Saturday,Sunday,Monday,Tuesday,Wednesday,Thursday,Friday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" ",3,4,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x02)&&(((d.l(ad:0x400E1460+0x0C))&0x1F0000)==(0x010000||0x020000||0x030000||0x040000||0x050000||0x060000))
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Saturday,Sunday,Monday,Tuesday,Wednesday,Thursday,Friday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" ",3,4,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x02)&&(((d.l(ad:0x400E1460+0x0C))&0x301F0000)==(0x30070000||0x30080000||0x30090000||0x30100000||0x30110000||0x30120000))&&(((d.l(ad:0x400E1460+0x0C))&0x100000)==0x000000)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" "0,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Saturday,Sunday,Monday,Tuesday,Wednesday,Thursday,Friday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" ",3,4,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x02)&&(((d.l(ad:0x400E1460+0x0C))&0x301F0000)==(0x30070000||0x30080000||0x30090000||0x30100000||0x30110000||0x30120000))&&(((d.l(ad:0x400E1460+0x0C))&0x100000)==0x100000)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" "0,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Saturday,Sunday,Monday,Tuesday,Wednesday,Thursday,Friday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" "0,1,2,,,,,,,,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" ",3,4,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x02)&&(((d.l(ad:0x400E1460+0x0C))&0x001F0000)==(0x00070000||0x00080000||0x00090000||0x00100000||0x00110000||0x00120000))&&(((d.l(ad:0x400E1460+0x0C))&0x100000)==0x000000)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Saturday,Sunday,Monday,Tuesday,Wednesday,Thursday,Friday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" ",3,4,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x02)&&(((d.l(ad:0x400E1460+0x0C))&0x001F0000)==(0x00070000||0x00080000||0x00090000||0x00100000||0x00110000||0x00120000))&&(((d.l(ad:0x400E1460+0x0C))&0x100000)==0x100000)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Saturday,Sunday,Monday,Tuesday,Wednesday,Thursday,Friday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" "0,1,2,,,,,,,,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" ",3,4,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x02)&&(((d.l(ad:0x400E1460+0x0C))&0x1F0000)==(0x070000||0x080000||0x090000||0x100000||0x110000||0x120000))&&(((d.l(ad:0x400E1460+0x0C))&0x100000)==0x000000)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Saturday,Sunday,Monday,Tuesday,Wednesday,Thursday,Friday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" ",3,4,?..."
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x02)&&(((d.l(ad:0x400E1460+0x0C))&0x1F0000)==(0x070000||0x080000||0x090000||0x100000||0x110000||0x120000))&&(((d.l(ad:0x400E1460+0x0C))&0x100000)==0x100000)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" ",Saturday,Sunday,Monday,Tuesday,Wednesday,Thursday,Friday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" "0,1,2,,,,,,,,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" ",1,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" ",3,4,?..."
|
|
elif (((d.l(ad:0x400E1460+0x0C))&0x00100000)==0x00100000)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" "0,1,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" "-,-,-,-,-,-,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" "0,1,2,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
elif (((d.l(ad:0x400E1460+0x0C))&0x00100000)==0x00100000)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" "-,-,-,-,-,-,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" "0,1,2,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
elif (((d.l(ad:0x400E1460+0x0C))&0x00100000)==0x00000000)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" "0,1,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" "-,-,-,-,-,-,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
elif (((d.l(ad:0x400E1460+0x0C))&0x00100000)==0x00000000)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" "-,-,-,-,-,-,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
elif (((d.l(ad:0x400E1460+0x0C))&0x100000)==0x00100000)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" "-,-,-,-,-,-,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" "0,1,2,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
else
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current Date (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" "-,-,-,-,-,-,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current Month (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year (tens)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Year (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century (tens)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. ",Current Century (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
endif
|
|
if ((((d.l(ad:0x400E1460+0x04))&0x01)==0x01)&&(((d.l(ad:0x400E1460+0x10))&0x000000)==0x000000))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RTC_TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 20.--21. " TIME ,Current Hour (tens)" "0,1,?..."
|
|
bitfld.long 0x00 16.--19. ",Current Hour (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--14. ":,Current Minute (tens)" "0,1,2,3,4,5,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Minute (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 4.--6. ":,Current Second (tens)" "0,1,2,3,4,5,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Second (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 22. " ,Ante Meridiem Post Meridiem Indicator" "AM,PM"
|
|
textline " "
|
|
bitfld.long 0x00 23. " HOUREN ,Hour Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " MINEN ,Minute Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SECEN ,Second Alarm Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x01)==0x01)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RTC_TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 20.--21. " TIME ,Current Hour (tens)" "0,1,?..."
|
|
bitfld.long 0x00 16.--19. ",Current Hour (units)" "0,1,2,?..."
|
|
bitfld.long 0x00 12.--14. ":,Current Minute (tens)" "0,1,2,3,4,5,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Minute (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 4.--6. ":,Current Second (tens)" "0,1,2,3,4,5,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Second (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 22. " ,Ante Meridiem Post Meridiem Indicator" "AM,PM"
|
|
textline " "
|
|
bitfld.long 0x00 23. " HOUREN ,Hour Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " MINEN ,Minute Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SECEN ,Second Alarm Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x400E1460+0x10))&0x000000)==0x200000)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RTC_TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 20.--21. " TIME ,Current Hour (tens)" "0,1,2,?..."
|
|
bitfld.long 0x00 16.--19. ",Current Hour (units)" "0,1,2,3,?..."
|
|
bitfld.long 0x00 12.--14. ":,Current Minute (tens)" "0,1,2,3,4,5,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Minute (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 4.--6. ":,Current Second (tens)" "0,1,2,3,4,5,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Second (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " HOUREN ,Hour Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " MINEN ,Minute Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SECEN ,Second Alarm Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RTC_TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 20.--21. " TIME ,Current Hour (tens)" "0,1,2,?..."
|
|
bitfld.long 0x00 16.--19. ",Current Hour (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--14. ":,Current Minute (tens)" "0,1,2,3,4,5,?..."
|
|
bitfld.long 0x00 8.--11. ",Current Minute (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 4.--6. ":,Current Second (tens)" "0,1,2,3,4,5,?..."
|
|
bitfld.long 0x00 0.--3. ",Current Second (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " HOUREN ,Hour Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " MINEN ,Minute Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SECEN ,Second Alarm Enable" "Disabled,Enabled"
|
|
endif
|
|
width 12.
|
|
if (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x14))&0x301F0000)==(0x30010000||0x30030000||0x30050000||0x30070000||0x30080000||0x30100000||0x30120000))&&(((d.l(ad:0x400E1460+0x14))&0x100000)==0x000000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date Alarm (units)" "0,1,?..."
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month Alarm (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x14))&0x301F0000)==(0x00010000||0x00030000||0x00050000||0x00070000||0x00080000||0x00100000||0x00120000))&&(((d.l(ad:0x400E1460+0x14))&0x100000)==0x000000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date Alarm (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month Alarm (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x14))&0x1F0000)==(0x010000||0x030000||0x050000||0x070000||0x080000||0x100000||0x120000))&&(((d.l(ad:0x400E1460+0x14))&0x100000)==0x000000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date Alarm (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month Alarm (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x14))&0x301F0000)==(0x30010000||0x30030000||0x30050000||0x30070000||0x30080000||0x30100000||0x30120000))&&(((d.l(ad:0x400E1460+0x14))&0x100000)==0x100000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date Alarm (units)" "0,1,?..."
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month Alarm (units)" "0,1,2,?..."
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x14))&0x301F0000)==(0x00010000||0x00030000||0x00050000||0x00070000||0x00080000||0x00100000||0x00120000))&&(((d.l(ad:0x400E1460+0x14))&0x100000)==0x100000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date Alarm (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month Alarm (units)" "0,1,2,?..."
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x14))&0x1F0000)==(0x010000||0x030000||0x050000||0x070000||0x080000||0x100000||0x120000))&&(((d.l(ad:0x400E1460+0x14))&0x100000)==0x100000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date Alarm (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month Alarm (units)" "0,1,2,?..."
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x14))&0x301F0000)==(0x30040000||0x00060000||0x30090000||0x30110000))&&(((d.l(ad:0x400E1460+0x14))&0x100000)==0x000000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date Alarm (units)" "0,?..."
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month Alarm (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x14))&0x301F0000)==(0x00040000||0x00060000||0x00090000||0x00110000))&&(((d.l(ad:0x400E1460+0x14))&0x100000)==0x000000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date Alarm (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month Alarm (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x14))&0x1F0000)==(0x040000||0x060000||0x090000||0x110000))&&(((d.l(ad:0x400E1460+0x14))&0x100000)==0x000000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date Alarm (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month Alarm (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x14))&0x301F0000)==(0x30040000||0x30060000||0x30090000||0x30110000||0x30120000))&&(((d.l(ad:0x400E1460+0x14))&0x100000)==0x100000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date Alarm (units)" "0,?..."
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month Alarm (units)" "0,1,2,?..."
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x14))&0x301F0000)==(0x00040000||0x00060000||0x00090000||0x00110000))&&(((d.l(ad:0x400E1460+0x14))&0x100000)==0x100000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date Alarm (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month Alarm (units)" "0,1,2,?..."
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x14))&0x1F0000)==(0x040000||0x060000||0x090000||0x110000))&&(((d.l(ad:0x400E1460+0x14))&0x100000)==0x100000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date Alarm (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month Alarm (units)" "0,1,2,?..."
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x14))&0x301F0000)==(0x00020000))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date Alarm (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month Alarm (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)&&(((d.l(ad:0x400E1460+0x14))&0x1F0000)==(0x00020000))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date Alarm (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month Alarm (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x02)&&(((d.l(ad:0x400E1460+0x14))&0x301F0000)==(0x30010000||0x30020000||0x30030000||0x30040000||0x30050000||0x00060000))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date Alarm (units)" "0,1,?..."
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month Alarm (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x02)&&(((d.l(ad:0x400E1460+0x14))&0x301F0000)==(0x00010000||0x00020000||0x00030000||0x00040000||0x00050000||0x00060000))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date Alarm (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month Alarm (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x02)&&(((d.l(ad:0x400E1460+0x14))&0x1F0000)==(0x010000||0x020000||0x030000||0x040000||0x050000||0x060000))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date Alarm (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month Alarm (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x02)&&(((d.l(ad:0x400E1460+0x14))&0x301F0000)==(0x30070000||0x30080000||0x30090000||0x30100000||0x30110000||0x30120000))&&(((d.l(ad:0x400E1460+0x14))&0x100000)==0x000000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date Alarm (units)" "0,?..."
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month Alarm (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x02)&&(((d.l(ad:0x400E1460+0x14))&0x301F0000)==(0x00070000||0x00080000||0x00090000||0x00100000||0x00110000||0x00120000))&&(((d.l(ad:0x400E1460+0x14))&0x100000)==0x000000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date Alarm (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month Alarm (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x02)&&(((d.l(ad:0x400E1460+0x14))&0x1F0000)==(0x070000||0x080000||0x090000||0x100000||0x110000||0x120000))&&(((d.l(ad:0x400E1460+0x14))&0x100000)==0x000000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date Alarm (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month Alarm (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x02)&&(((d.l(ad:0x400E1460+0x14))&0x301F0000)==(0x30070000||0x30080000||0x30090000||0x30100000||0x30110000||0x30120000))&&(((d.l(ad:0x400E1460+0x14))&0x100000)==0x100000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date Alarm (units)" "0,?..."
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month Alarm (units)" "0,1,2,?..."
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x02)&&(((d.l(ad:0x400E1460+0x14))&0x301F0000)==(0x00070000||0x00080000||0x00090000||0x00100000||0x00110000||0x00120000))&&(((d.l(ad:0x400E1460+0x14))&0x100000)==0x100000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date Alarm (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month Alarm (units)" "0,1,2,?..."
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x400E1460+0x04))&0x02)==0x02)&&(((d.l(ad:0x400E1460+0x14))&0x1F0000)==(0x070000||0x080000||0x090000||0x100000||0x110000||0x120000))&&(((d.l(ad:0x400E1460+0x14))&0x100000)==0x100000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date Alarm (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month Alarm (units)" "0,1,2,?..."
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x400E1460+0x14))&0x00100000)==0x00100000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm (tens)" "0,1,2,3,?..."
|
|
bitfld.long 0x00 24.--27. ",Date Alarm (units)" "0,1,?..."
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month Alarm (units)" "0,1,2,?..."
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x400E1460+0x14))&0x00100000)==0x00100000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm (tens)" "0,1,2,3,?..."
|
|
bitfld.long 0x00 24.--27. ",Date Alarm (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month Alarm (units)" "0,1,2,?..."
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x400E1460+0x14))&0x00100000)==0x00000000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm (tens)" "0,1,2,3,?..."
|
|
bitfld.long 0x00 24.--27. ",Date Alarm (units)" "0,1,?..."
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month Alarm (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x400E1460+0x14))&0x00100000)==0x00000000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm (tens)" "0,1,2,3,?..."
|
|
bitfld.long 0x00 24.--27. ",Date Alarm (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month Alarm (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x400E1460+0x14))&0x100000)==0x00100000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm (tens)" "0,1,2,3,?..."
|
|
bitfld.long 0x00 24.--27. ",Date Alarm (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month Alarm (units)" "0,1,2,?..."
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm (tens)" "0,1,2,3,?..."
|
|
bitfld.long 0x00 24.--27. ",Date Alarm (units)" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month Alarm (units)" ",1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
endif
|
|
width 12.
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "RTC_SR,Status Register"
|
|
bitfld.long 0x00 5. " TDERR ,Time and/or Date Free Running Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CALEV ,Calendar Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " TIMEV ,Time Event" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEC ,Second Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " ALARM ,Alarm Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACKUPD ,Acknowledge for Update" "No,Yes"
|
|
wgroup.long 0x1C++0x0B
|
|
line.long 0x00 "RTC_SCCR,Status Clear Register"
|
|
bitfld.long 0x00 5. " TDERRCLR ,Time and/or Date Free Running Error Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CALCLR ,Calendar Event Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 3. " TIMCLR ,Time Event Interrupt Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SECCLR ,Second Event Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " ALRCLR ,Alarm Flag Interrupt Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACKCLR ,Acknowledge for Update Interrupt Clear" "No effect,Clear"
|
|
line.long 0x04 "RTC_IER,Interrupt Enable Register"
|
|
bitfld.long 0x04 5. " TDERREN ,Time and/or Date Free Running Error Interrupt Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 4. " CALEN ,Calendar Event Interrupt Enable" "No effect,Enable"
|
|
bitfld.long 0x04 3. " TIMEN ,Time Event Interrupt Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 2. " SECEN ,Second Event Interrupt Enable" "No effect,Enable"
|
|
bitfld.long 0x04 1. " ALREN ,Alarm Flag Interrupt Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ACKEN ,Acknowledge for Update Interrupt Enable" "No effect,Enable"
|
|
line.long 0x08 "RTC_IDR,Interrupt Disable Register"
|
|
bitfld.long 0x08 5. " TDERRDIS ,Time and/or Date Free Running Error Interrupt Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x08 4. " CALDIS ,Calendar Event Interrupt Disable" "No effect,Disable"
|
|
bitfld.long 0x08 3. " TIMDIS ,Time Event Interrupt Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SECDIS ,Second Event Interrupt Disable" "No effect,Disable"
|
|
bitfld.long 0x08 1. " ALRDIS ,Alarm Flag Interrupt Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x08 0. " ACKDIS ,Acknowledge for Update Interrupt Disable" "No effect,Disable"
|
|
rgroup.long 0x28++0x7
|
|
line.long 0x00 "RTC_IMR,Interrupt Mask Register"
|
|
bitfld.long 0x00 4. " CAL ,Calendar Event Interrupt Mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TIM ,Time Event Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEC ,Second Event Interrupt Mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ALR ,Alarm Flag Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACK ,Acknowledge for Update Interrupt Mask" "Disabled,Enabled"
|
|
line.long 0x04 "RTC_VER,Valid Entry Register"
|
|
bitfld.long 0x04 3. " NVCAL ,Non-Valid Calendar Alarm" "Valid,Invalid"
|
|
bitfld.long 0x04 2. " NVTAL ,Non-Valid Time Alarm" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x04 1. " NVC ,Non-Valid Calendar" "Valid,Invalid"
|
|
bitfld.long 0x04 0. " NVT ,Non-Valid Time" "Valid,Invalid"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "RTC_TSTR0,RTC TimeStamp Time Register 0"
|
|
bitfld.long 0x00 31. " BACKUP ,System Mode of the Tamper" "Not backup mode,Backup mode"
|
|
bitfld.long 0x00 24.--27. " TEVCNT ,Tamper Events Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 22. " AMPM ,Indicator of the Tamper" "AM,PM"
|
|
bitfld.long 0x00 16.--21. " HOUR ,HOURs of the Tamper" "0,1,2,3,4,%d..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " MIN ,MINutes of the Tamper"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SEC ,SEConds of the Tamper"
|
|
rgroup.long 0xBC++0x03
|
|
line.long 0x00 "RTC_TSTR1,RTC TimeStamp Time Register 1"
|
|
bitfld.long 0x00 31. " BACKUP ,System Mode of the Tamper" "Not backup mode,Backup mode"
|
|
textline " "
|
|
bitfld.long 0x00 22. " AMPM ,Indicator of the Tamper" "AM,PM"
|
|
bitfld.long 0x00 16.--21. " HOUR ,HOURs of the Tamper" "0,1,2,3,4,%d..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " MIN ,MINutes of the Tamper"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SEC ,SEConds of the Tamper"
|
|
if (((d.l(ad:0x400E1460+0x04))&0x02)==0x00)
|
|
rgroup.long 0xB4++0x03
|
|
line.long 0x00 "RTC_TSDR0,TimeStamp Date Register 0"
|
|
hexmask.long.byte 0x00 24.--29. 1. " DATE ,Date of the Tamper"
|
|
bitfld.long 0x00 21.--23. " DAY ,Day of the Tamper" ",Mon,Tue,Wen,Thu,Fri,Sat,Sun"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " MONTH ,Month of the Tamper" ",Jan,Fab,Mar,Apr,May,Jun,Jul,Aug,Sep,Oct,Nov,Dec,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " YEAR ,Year of the Tamper"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " CENT ,Century of the Tamper"
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "RTC_TSDR1,TImeStamp Date Register1"
|
|
bitfld.long 0x00 24.--29. " DATE ,Date of the Tamper" "0,1,2,3,4,%d..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Day of the Tamper" ",Mon,Tue,Wen,Thu,Fri,Sat,Sun"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " MONTH ,Month of the Tamper" ",Jan,Fab,Mar,Apr,May,Jun,Jul,Aug,Sep,Oct,Nov,Dec,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " YEAR ,Year of the Tamper"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " CENT ,Century of the Tamper"
|
|
else
|
|
rgroup.long 0xB4++0x03
|
|
line.long 0x00 "RTC_TSDR0,TimeStamp Date Register 0"
|
|
hexmask.long.byte 0x00 24.--29. 1. " DATE ,Date of the Tamper"
|
|
bitfld.long 0x00 21.--23. " DAY ,Day of the Tamper" ",Sat,Sun,Mon,Tue,Wen,Thu,Fri"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " MONTH ,Month of the Tamper" ",Jan,Fab,Mar,Apr,May,Jun,Jul,Aug,Sep,Oct,Nov,Dec,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " YEAR ,Year of the Tamper"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " CENT ,Century of the Tamper"
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "RTC_TSDR1,TImeStamp Date Register1"
|
|
bitfld.long 0x00 24.--29. " DATE ,Date of the Tamper" "0,1,2,3,4,%d..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Day of the Tamper" ",Sat,Sun,Mon,Tue,Wen,Thu,Fri"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " MONTH ,Month of the Tamper" ",Jan,Fab,Mar,Apr,May,Jun,Jul,Aug,Sep,Oct,Nov,Dec,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " YEAR ,Year of the Tamper"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " CENT ,Century of the Tamper"
|
|
endif
|
|
hgroup.long 0xB8++0x03
|
|
hide.long 0x00 "RTC_TSSR0,RTC TimeStamp Source Register 0"
|
|
textfld " "
|
|
in
|
|
hgroup.long 0xC4++0x03
|
|
hide.long 0x00 "RTC_TSSR1,RTC TimeStamp Source Register 1"
|
|
textfld " "
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
tree "WDT (Watchdog Timer)"
|
|
base ad:0x400E1450
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "WDT_CR,Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password"
|
|
bitfld.long 0x00 0. " WDRSTT ,Watchdog Restart" "No effect,Restart"
|
|
if ((d.l(ad:0x400E1450+0x04)&0x00002000)==0x00002000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "WDT_MR,Mode Register"
|
|
bitfld.long 0x00 29. " WDIDLEHLT ,Watchdog Idle Halt" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " WDDBGHLT ,Watchdog Debug Halt" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 16.--27. 1. " WDD ,Watchdog Delta Value"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WDDIS ,Watchdog Disable" "No,Yes"
|
|
bitfld.long 0x00 14. " WDRPROC ,Watchdog Reset Processor" "All resets,Processor reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " WDRSTEN ,Watchdog Reset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WDFIEN ,Watchdog Fault Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " WDV ,Watchdog Counter Value"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "WDT_MR,Mode Register"
|
|
bitfld.long 0x00 29. " WDIDLEHLT ,Watchdog Idle Halt" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " WDDBGHLT ,Watchdog Debug Halt" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 16.--27. 1. " WDD ,Watchdog Delta Value"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WDDIS ,Watchdog Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 13. " WDRSTEN ,Watchdog Reset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WDFIEN ,Watchdog Fault Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " WDV ,Watchdog Counter Value"
|
|
endif
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "WDT_SR,Status Register"
|
|
bitfld.long 0x00 1. " WDUNF ,Watchdog Underflow" "No underflow,Underflow"
|
|
bitfld.long 0x00 0. " WDERR ,Watchdog Error" "No error,Error"
|
|
width 0xB
|
|
tree.end
|
|
tree "RSWDT (Reinforced Safety Watchdog Timer)"
|
|
base ad:0x400E1500
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "RSWDT_CR,Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password"
|
|
bitfld.long 0x00 0. " WDRSTT ,Watchdog Restart" "No effect,Restart"
|
|
if ((d.l(ad:0x400E1500+0x04)&0x00002000)==0x00002000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RSWDT_MR,Mode Register"
|
|
bitfld.long 0x00 29. " WDIDLEHLT ,Watchdog Idle Halt" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " WDDBGHLT ,Watchdog Debug Halt" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 16.--27. 1. " WDD ,Watchdog Delta Value"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WDDIS ,Watchdog Disable" "No,Yes"
|
|
bitfld.long 0x00 14. " WDRPROC ,Watchdog Reset Processor" "All resets,Processor reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " WDRSTEN ,Watchdog Reset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WDFIEN ,Watchdog Fault Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " WDV ,Watchdog Counter Value"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RSWDT_MR,Mode Register"
|
|
bitfld.long 0x00 29. " WDIDLEHLT ,Watchdog Idle Halt" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " WDDBGHLT ,Watchdog Debug Halt" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 16.--27. 1. " WDD ,Watchdog Delta Value"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WDDIS ,Watchdog Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 13. " WDRSTEN ,Watchdog Reset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WDFIEN ,Watchdog Fault Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " WDV ,Watchdog Counter Value"
|
|
endif
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "RSWDT_SR,Status Register"
|
|
bitfld.long 0x00 1. " WDUNF ,Watchdog Underflow" "No underflow,Underflow"
|
|
bitfld.long 0x00 0. " WDERR ,Watchdog Error" "No error,Error"
|
|
width 0xB
|
|
tree.end
|
|
tree "SUPC (Supply Controller)"
|
|
base ad:0x400E1410
|
|
width 12.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SUPC_CR,Supply Controller Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password Key"
|
|
bitfld.long 0x00 3. " XTALSEL ,Crystal Oscillator Select " "No effect,Oscillator output"
|
|
textline " "
|
|
bitfld.long 0x00 2. " VROFF ,Voltage Regulator Off" "No effect,Off"
|
|
group.long 0x04++0x0f
|
|
line.long 0x00 "SUPC_SMMR,Supply Controller Supply Monitor Mode Register"
|
|
bitfld.long 0x00 13. " SMIEN ,Supply Monitor Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SMRSTEN ,Supply Monitor Reset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " SMSMPL ,Supply Monitor Sampling Period" "Disabled,Continuous,32 SLCK,256 SLCK,2048 SLCK,,,"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " SMTH ,Supply Monitor Threshold " "1.9 V,2.0 V,2.1 V,2.2 V,2.3 V,2.4 V,2.5 V,2.6 V,2.7 V,2.8 V,2.9 V,3.0 V,3.1 V,3.2 V,3.3 V,3.4 V"
|
|
line.long 0x04 "SUPC_MR,Supply Controller Mode Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " KEY ,Password Key"
|
|
bitfld.long 0x04 20. " OSCBYPASS ,Oscillator Bypass" "No effect,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x04 15. " BUPPOREN ,Backup Area Power-On Reset Enable" "No,Yes"
|
|
bitfld.long 0x04 14. " ONREG ,Voltage Regulator Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " BODDIS ,Brownout Detector Disable" "No,Yes"
|
|
bitfld.long 0x04 12. " BODRSTEN ,Brownout Detector Reset Enable" "Disabled,Enabled"
|
|
line.long 0x08 "SUPC_WUMR,Supply Controller Wake-up Mode Register"
|
|
bitfld.long 0x08 30. " DISTSTMP3 ,Disable Timestamp Command from WKUP15/TMP3 Pin" "No,Yes"
|
|
bitfld.long 0x08 29. " DISTSTMP2 ,Disable Timestamp Command from WKUP14/TMP2 Pin" "No,Yes"
|
|
bitfld.long 0x08 28. " DISTSTMP1 ,Disable Timestamp Command from WKUP10/TMP1 Pin" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 26. " DISTMPCLR3 ,Disable GPBR Command from WKUP15/TMP3 Pin" "No,Yes"
|
|
bitfld.long 0x08 25. " DISTMPCLR2 ,Disable GPBR Command from WKUP14/TMP2 Pin" "No,Yes"
|
|
bitfld.long 0x08 24. " DISTMPCLR1 ,Disable GPBR Command from WKUP10/TMP1 Pin" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 21. " LPDBCEN3 ,Low Power Debouncer Enable WKUP15/TMP3" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " LPDBCEN2 ,Low Power Debouncer Enable WKUP14/TMP2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " LPDBC ,Low Power DeBounCer Period" "Disabled,2_RTCOUT0,3_RTCOUT0,4_RTCOUT0,5_RTCOUT0,6_RTCOUT0,7_RTCOUT0,8_RTCOUT0"
|
|
bitfld.long 0x08 12.--14. " WKUPDBC ,Wake-up Inputs Debouncer" "Immediate,3 SLCK,32 SLCK,512 SLCK,4096 SLCK,32768 SLCK,,"
|
|
bitfld.long 0x08 8.--10. " FWUPDBC ,Force Wake-up Debouncer" "Immediate,3 SLCK,32 SLCK,512 SLCK,4096 SLCK,32768 SLCK,,"
|
|
textline " "
|
|
bitfld.long 0x08 7. " LPDBCCLR ,Low power Debouncer Clear" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " LPDBCEN1 ,Low power Debouncer Enable WKUP10/TMP1" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " LPDBCEN0 ,Low power Debouncer Enable WKUP0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " RTCEN ,Real-time Clock Wake-up Enable " "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RTTEN ,Real-time Timer Wake-up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " SMEN ,Supply Monitor Wake-up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " FWUPEN ,Force Wake-up Enable" "Disabled,Enabled"
|
|
line.long 0x0c "SUPC_WUIR,System Controller Wake-up Inputs Register"
|
|
bitfld.long 0x0c 31. " WKUPT15 ,Wake-up 15 Input Type" "Low,High"
|
|
bitfld.long 0x0c 30. " WKUPT14 ,Wake-up 14 Input Type" "Low,High"
|
|
bitfld.long 0x0c 29. " WKUPT13 ,Wake-up 13 Input Type" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0c 28. " WKUPT12 ,Wake-up 12 Input Type" "Low,High"
|
|
bitfld.long 0x0c 27. " WKUPT11 ,Wake-up 11 Input Type" "Low,High"
|
|
bitfld.long 0x0c 26. " WKUPT10 ,Wake-up 10 Input Type" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " WKUPT9 ,Wake-up 9 Input Type" "Low,High"
|
|
bitfld.long 0x0c 24. " WKUPT8 ,Wake-up 8 Input Type" "Low,High"
|
|
bitfld.long 0x0c 23. " WKUPT7 ,Wake-up 7 Input Type" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0c 22. " WKUPT6 ,Wake-up 6 Input Type" "Low,High"
|
|
bitfld.long 0x0c 21. " WKUPT5 ,Wake-up 5 Input Type" "Low,High"
|
|
bitfld.long 0x0c 20. " WKUPT4 ,Wake-up 4 Input Type" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " WKUPT3 ,Wake-up 3 Input Type" "Low,High"
|
|
bitfld.long 0x0c 18. " WKUPT2 ,Wake-up 2 Input Type" "Low,High"
|
|
bitfld.long 0x0c 17. " WKUPT1 ,Wake-up 1 Input Type" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0c 16. " WKUPT0 ,Wake-up 0 Input Type" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0c 31. " WKUPEN15 ,Wake-up 15 Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 30. " WKUPEN14 ,Wake-up 14 Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 29. " WKUPEN13 ,Wake-up 13 Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 28. " WKUPEN12 ,Wake-up 12 Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 27. " WKUPEN11 ,Wake-up 11 Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 26. " WKUPEN10 ,Wake-up 10 Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " WKUPEN9 ,Wake-up 9 Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 24. " WKUPEN8 ,Wake-up 8 Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 23. " WKUPEN7 ,Wake-up 7 Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 22. " WKUPEN6 ,Wake-up 6 Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 21. " WKUPEN5 ,Wake-up 5 Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 20. " WKUPEN4 ,Wake-up 4 Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " WKUPEN3 ,Wake-up 3 Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 18. " WKUPEN2 ,Wake-up 2 Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 17. " WKUPEN1 ,Wake-up 1 Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 16. " WKUPEN0 ,Wake-up 0 Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "SUPC_SR,Supply Controller Status Register"
|
|
bitfld.long 0x00 31. " WKUPIS15 ,WKUP15 Input Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " WKUPIS14 ,WKUP14 Input Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " WKUPIS13 ,WKUP13 Input Status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WKUPIS12 ,WKUP12 Input Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " WKUPIS11 ,WKUP11 Input Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WKUPIS10 ,WKUP10 Input Status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WKUPIS9 ,WKUP9 Input Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " WKUPIS8 ,WKUP8 Input Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " WKUPIS7 ,WKUP7 Input Status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " WKUPIS6 ,WKUP6 Input Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WKUPIS5 ,WKUP5 Input Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " WKUPIS4 ,WKUP4 Input Status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " WKUPIS3 ,WKUP3 Input Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " WKUPIS2 ,WKUP2 Input Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " WKUPIS1 ,WKUP1 Input Status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " WKUPIS0 ,WKUP0 Input Status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BUPPORS ,Backup Area Power-On Reset Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LPDBCS1 ,Low Power Debouncer Wake-up Status on WKUP10/TMP1" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LPDBCS0 ,Low Power Debouncer Wake-up Status on WKUP0/TMP0" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " FWUPIS ,FWUP Input Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LPDBCS3 ,Low Power Debouncer Tamper Status on WKUP15/TMP3" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " LPDBCS2 ,Low Power Debouncer Tamper Status on WKUP14/TMP2" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LCDS ,LCD Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " OSCSEL ,32 kHz Oscillator Selection Status" "RC,Crystal"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SMOS ,Supply Monitor Output Status" "High,Low"
|
|
bitfld.long 0x00 5. " SMS ,Supply Monitor Status" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SMRSTS ,Supply Monitor Reset Status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " BODRSTS ,Brownout Detector Reset Status" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SMWS ,Supply Monitor Detection Wake-up Status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " WKUPS ,WKUP Wake-up Status" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FWUPS ,FWUP Wake-up Status" "Not occurred,Occurred"
|
|
line.long 0x04 "SYSC_WPMR,System Controller Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. " WPKEY ,Write Protection Key"
|
|
bitfld.long 0x04 0. " WPEN ,WPEN" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "GPBR (General Purpose Backup Registers)"
|
|
base ad:0x400E1490
|
|
width 11.
|
|
sif (cpuis("AT91SAM3S8*")||cpuis("AT91SAM3N*")||cpuis("ATSAM4N*")||cpuis("ATSAM4S*"))
|
|
group.long 0x00++0x1F
|
|
line.long 0x0 "SYS_GPBR0,General Purpose Backup Register 0"
|
|
line.long 0x4 "SYS_GPBR1,General Purpose Backup Register 1"
|
|
line.long 0x8 "SYS_GPBR2,General Purpose Backup Register 2"
|
|
line.long 0xC "SYS_GPBR3,General Purpose Backup Register 3"
|
|
line.long 0x10 "SYS_GPBR4,General Purpose Backup Register 4"
|
|
line.long 0x14 "SYS_GPBR5,General Purpose Backup Register 5"
|
|
line.long 0x18 "SYS_GPBR6,General Purpose Backup Register 6"
|
|
line.long 0x1C "SYS_GPBR7,General Purpose Backup Register 7"
|
|
elif (cpuis("ATSAM4E*"))
|
|
group.long 0x00++0x67
|
|
line.long 0x0 "SYS_GPBR0,General Purpose Backup Register 0"
|
|
line.long 0x4 "SYS_GPBR1,General Purpose Backup Register 1"
|
|
line.long 0x8 "SYS_GPBR2,General Purpose Backup Register 2"
|
|
line.long 0xC "SYS_GPBR3,General Purpose Backup Register 3"
|
|
line.long 0x10 "SYS_GPBR4,General Purpose Backup Register 4"
|
|
line.long 0x14 "SYS_GPBR5,General Purpose Backup Register 5"
|
|
line.long 0x18 "SYS_GPBR6,General Purpose Backup Register 6"
|
|
line.long 0x1C "SYS_GPBR7,General Purpose Backup Register 7"
|
|
line.long 0x20 "SYS_GPBR8,General Purpose Backup Register 8"
|
|
line.long 0x24 "SYS_GPBR9,General Purpose Backup Register 9"
|
|
line.long 0x28 "SYS_GPBR10,General Purpose Backup Register 10"
|
|
line.long 0x2C "SYS_GPBR11,General Purpose Backup Register 11"
|
|
line.long 0x30 "SYS_GPBR12,General Purpose Backup Register 12"
|
|
line.long 0x34 "SYS_GPBR13,General Purpose Backup Register 13"
|
|
line.long 0x38 "SYS_GPBR14,General Purpose Backup Register 14"
|
|
line.long 0x3C "SYS_GPBR15,General Purpose Backup Register 15"
|
|
line.long 0x40 "SYS_GPBR16,General Purpose Backup Register 16"
|
|
line.long 0x44 "SYS_GPBR17,General Purpose Backup Register 17"
|
|
line.long 0x48 "SYS_GPBR18,General Purpose Backup Register 18"
|
|
line.long 0x4C "SYS_GPBR19,General Purpose Backup Register 19"
|
|
elif ((cpu()=="ATSAM4C16C-CORE0")||(cpu()=="ATSAM4C8C-CORE0")||(cpu()=="ATSAM4CMP16C-CORE0")||(cpu()=="ATSAM4CMP8C-CORE0")||(cpu()=="ATSAM4CMS8C-CORE0")||(cpu()=="ATSAM4CMS16C-CORE0")||(cpu()=="ATSAM4C16C-CORE1")||(cpu()=="ATSAM4C8C-CORE1")||(cpu()=="ATSAM4CMP16C-CORE1")||(cpu()=="ATSAM4CMP8C-CORE1")||(cpu()=="ATSAM4CMS8C-CORE1")||(cpu()=="ATSAM4CMS16C-CORE1"))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SYS_GPBR0,General Purpose Backup Register 0"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "SYS_GPBR1,General Purpose Backup Register 1"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "SYS_GPBR2,General Purpose Backup Register 2"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "SYS_GPBR3,General Purpose Backup Register 3"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SYS_GPBR4,General Purpose Backup Register 4"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SYS_GPBR5,General Purpose Backup Register 5"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SYS_GPBR6,General Purpose Backup Register 6"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SYS_GPBR7,General Purpose Backup Register 7"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SYS_GPBR8,General Purpose Backup Register 8"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SYS_GPBR9,General Purpose Backup Register 9"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SYS_GPBR10,General Purpose Backup Register 10"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SYS_GPBR11,General Purpose Backup Register 11"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SYS_GPBR12,General Purpose Backup Register 12"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SYS_GPBR13,General Purpose Backup Register 13"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SYS_GPBR14,General Purpose Backup Register 14"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SYS_GPBR15,General Purpose Backup Register 15"
|
|
else
|
|
group.long 0x00++0x0F
|
|
line.long 0x0 "SYS_GPBR0,General Purpose Backup Register 0"
|
|
line.long 0x4 "SYS_GPBR1,General Purpose Backup Register 1"
|
|
line.long 0x8 "SYS_GPBR2,General Purpose Backup Register 2"
|
|
line.long 0xC "SYS_GPBR3,General Purpose Backup Register 3"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "EEFC (Enhanced Embedded Flash Controller)"
|
|
base ad:0x400E0A00
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EEFC_FMR,EEFC Flash Mode Register"
|
|
bitfld.long 0x00 26. " CLOE ,Code Loops Optimization Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " FAM ,Flash Access Mode" "128-bit,64-bit"
|
|
bitfld.long 0x00 16. " SCOD ,Sequential Code Optimization Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " FWS ,Flash Wait State" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 0. " FRDY ,Ready Interrupt Enable" "Disabled,Enabled"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "EEFC_FCR,EEFC Flash Command Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " FKEY ,Flash Writing Protection Key"
|
|
hexmask.long.word 0x00 8.--23. 1. " FARG ,Flash Command Argument"
|
|
bitfld.long 0x00 0.--4. " FCMD ,Flash Command" "GETD,WP,WPL,EWP,EWPL,EA,,EPA,SLB,CLB,GLB,SGPB,CGPB,GGPB,STUI,SPUI,GCALB,ES,WUS,EUS,STUS,SPUS,,,,,,,,,,"
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "EEFC_FSR,EEFC Flash Status Register"
|
|
textfld " "
|
|
in
|
|
hgroup.long 0x0c++0x03
|
|
hide.long 0x00 "EEFC_FRR,EEFC Flash Result Register"
|
|
textfld " "
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
tree "CMCC (Cortex M Cache Controller)"
|
|
sif ((cpu()=="ATSAM4C16C-CORE0")||(cpu()=="ATSAM4C8C-CORE0")||(cpu()=="ATSAM4CMP16C-CORE0")||(cpu()=="ATSAM4CMP8C-CORE0")||(cpu()=="ATSAM4CMS8C-CORE0")||(cpu()=="ATSAM4CMS16C-CORE0"))
|
|
base ad:0x4007C000
|
|
else
|
|
base ad:0x48018000
|
|
endif
|
|
width 13.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "CMCC_TYPE,Cache Controller Type Register"
|
|
bitfld.long 0x00 11.--13. " CLSIZE ,Cache Size" "1 KB,2 KB,4 KB,8 KB,?..."
|
|
bitfld.long 0x00 8.--10. " CSIZE ,Cache Size" "1 KB,2 KB,4 KB,8 KB,?..."
|
|
bitfld.long 0x00 7. " LCKDOWN ,Lock Down Supported" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " WAYNUM ,Number of Way" "Direct,2-WAY,4-WAY,8-WAY"
|
|
bitfld.long 0x00 4. " RRP ,Random Selection Policy Supported" "Not supported,Supported"
|
|
bitfld.long 0x00 3. " LRUP ,Least Recently Used Policy Supported" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RANDP ,Random Selection Policy Supported" "Not supported,Supported"
|
|
wgroup.long 0x08++0x3
|
|
line.long 0x00 "CMCC_CTRL,Cache Controller Control Register"
|
|
bitfld.long 0x00 0. " CEN ,Cache Controller Enable" "Disable,Enable"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CMCC_SR,Cache Controller Status Register"
|
|
bitfld.long 0x00 0. " CSTS ,Cache Controller Status" "Disabled,Enabled"
|
|
wgroup.long 0x20++0x13
|
|
line.long 0x00 "CMCC_MAINT0,Cache Controller Maintenance Register 0"
|
|
bitfld.long 0x00 0. " INVALL ,Cache Controller Invalidate All" "No effect,Invalidate"
|
|
line.long 0x04 "CMCC_MAINT1,Cache Controller Maintenance Register 1"
|
|
bitfld.long 0x04 30.--31. " WAY ,Invalidate Way" "Way 0,Way 1,Way 2,Way 3"
|
|
bitfld.long 0x04 4.--8. " INDEX ,Invalidate Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "CMCC_MCFG,Cache Controller Monitor Configuration Register"
|
|
bitfld.long 0x08 0.--1. " MODE ,Cache Controller Monitor Counter Mode" "Cycle counter,Instruction hit,Data hit,"
|
|
line.long 0x0c "CMCC_MEN,Cache Controller Monitor Enable Register"
|
|
bitfld.long 0x0c 0. " MENABLE ,Cache Controller Monitor Enable" "Disable,Enable"
|
|
line.long 0x10 "CMCC_MCTRL,Cache Controller Monitor Control Register"
|
|
bitfld.long 0x10 0. " SWRST ,Monitor (software reset)" "No effect,Reset"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "CMCC_MSR,Cache Controller Monitor Status Register"
|
|
width 0xb
|
|
tree.end
|
|
tree "IPC (Inter-processor Communication Interface)"
|
|
sif ((cpu()=="ATSAM4C16C-CORE0")||(cpu()=="ATSAM4C8C-CORE0")||(cpu()=="ATSAM4CMP16C-CORE0")||(cpu()=="ATSAM4CMP8C-CORE0")||(cpu()=="ATSAM4CMS8C-CORE0")||(cpu()=="ATSAM4CMS16C-CORE0"))
|
|
base ad:0x4004C000
|
|
else
|
|
base ad:0x48014000
|
|
endif
|
|
width 17.
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IPC_ISR_set/clr,IPC Interrupt Status Register"
|
|
setclrfld.long 0x00 31. -0x18 31. -0x14 31. " IRQ31 ,Current Interrupt 31 Identifier" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. -0x18 30. -0x14 30. " IRQ30 ,Current Interrupt 30 Identifier" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. -0x18 29. -0x14 29. " IRQ29 ,Current Interrupt 29 Identifier" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 28. -0x18 28. -0x14 28. " IRQ28 ,Current Interrupt 28 Identifier" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x18 27. -0x14 27. " IRQ27 ,Current Interrupt 27 Identifier" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. -0x18 26. -0x14 26. " IRQ26 ,Current Interrupt 26 Identifier" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 25. -0x18 25. -0x14 25. " IRQ25 ,Current Interrupt 25 Identifier" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. -0x18 24. -0x14 24. " IRQ24 ,Current Interrupt 24 Identifier" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x18 23. -0x14 23. " IRQ23 ,Current Interrupt 23 Identifier" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 22. -0x18 22. -0x14 22. " IRQ22 ,Current Interrupt 22 Identifier" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. -0x18 21. -0x14 21. " IRQ21 ,Current Interrupt 21 Identifier" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. -0x18 20. -0x14 20. " IRQ20 ,Current Interrupt 20 Identifier" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x18 19. -0x14 19. " IRQ19 ,Current Interrupt 19 Identifier" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. -0x18 18. -0x14 18. " IRQ18 ,Current Interrupt 18 Identifier" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. -0x18 17. -0x14 17. " IRQ17 ,Current Interrupt 17 Identifier" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. -0x18 16. -0x14 16. " IRQ16 ,Current Interrupt 16 Identifier" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x18 15. -0x14 15. " IRQ15 ,Current Interrupt 15 Identifier" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. -0x18 14. -0x14 14. " IRQ14 ,Current Interrupt 14 Identifier" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. -0x18 13. -0x14 13. " IRQ13 ,Current Interrupt 13 Identifier" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. -0x18 12. -0x14 12. " IRQ12 ,Current Interrupt 12 Identifier" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x18 11. -0x14 11. " IRQ11 ,Current Interrupt 11 Identifier" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 10. -0x18 10. -0x14 10. " IRQ10 ,Current Interrupt 10 Identifier" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. -0x18 9. -0x14 9. " IRQ9 ,Current Interrupt 9 Identifier" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. -0x18 8. -0x14 8. " IRQ8 ,Current Interrupt 8 Identifier" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x18 7. -0x14 7. " IRQ7 ,Current Interrupt 7 Identifier" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. -0x18 6. -0x14 6. " IRQ6 ,Current Interrupt 6 Identifier" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. -0x18 5. -0x14 5. " IRQ5 ,Current Interrupt 5 Identifier" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. -0x18 4. -0x14 4. " IRQ4 ,Current Interrupt 4 Identifier" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x18 3. -0x14 3. " IRQ3 ,Current Interrupt 3 Identifier" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. -0x18 2. -0x14 2. " IRQ2 ,Current Interrupt 2 Identifier" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. -0x18 1. -0x14 1. " IRQ1 ,Current Interrupt 1 Identifier" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. -0x18 0. -0x14 0. " IRQ0 ,Current Interrupt 0 Identifier" "No interrupt,Interrupt"
|
|
textline " "
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "IPC_IMR_set/clr,IPC Interrupt Mask Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " IRQ31 ,Interrupt 31 Maskr" "Not masked,Masked"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " IRQ30 ,Interrupt 30 Maskr" "Not masked,Masked"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " IRQ29 ,Interrupt 29 Maskr" "Not masked,Masked"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " IRQ28 ,Interrupt 28 Maskr" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " IRQ27 ,Interrupt 27 Maskr" "Not masked,Masked"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " IRQ26 ,Interrupt 26 Maskr" "Not masked,Masked"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " IRQ25 ,Interrupt 25 Maskr" "Not masked,Masked"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " IRQ24 ,Interrupt 24 Maskr" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " IRQ23 ,Interrupt 23 Maskr" "Not masked,Masked"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " IRQ22 ,Interrupt 22 Maskr" "Not masked,Masked"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " IRQ21 ,Interrupt 21 Maskr" "Not masked,Masked"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " IRQ20 ,Interrupt 20 Maskr" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " IRQ19 ,Interrupt 19 Maskr" "Not masked,Masked"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " IRQ18 ,Interrupt 18 Maskr" "Not masked,Masked"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " IRQ17 ,Interrupt 17 Maskr" "Not masked,Masked"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " IRQ16 ,Interrupt 16 Maskr" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " IRQ15 ,Interrupt 15 Maskr" "Not masked,Masked"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " IRQ14 ,Interrupt 14 Maskr" "Not masked,Masked"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " IRQ13 ,Interrupt 13 Maskr" "Not masked,Masked"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " IRQ12 ,Interrupt 12 Maskr" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " IRQ11 ,Interrupt 11 Maskr" "Not masked,Masked"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " IRQ10 ,Interrupt 10 Maskr" "Not masked,Masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " IRQ9 ,Interrupt 9 Maskr" "Not masked,Masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " IRQ8 ,Interrupt 8 Maskr" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " IRQ7 ,Interrupt 7 Maskr" "Not masked,Masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " IRQ6 ,Interrupt 6 Maskr" "Not masked,Masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " IRQ5 ,Interrupt 5 Maskr" "Not masked,Masked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " IRQ4 ,Interrupt 4 Maskr" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " IRQ3 ,Interrupt 3 Maskr" "Not masked,Masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " IRQ2 ,Interrupt 2 Maskr" "Not masked,Masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " IRQ1 ,Interrupt 1 Maskr" "Not masked,Masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " IRQ0 ,Interrupt 0 Maskr" "Not masked,Masked"
|
|
textline " "
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "IPC_IPR,IPC Interrupt Pending Register"
|
|
bitfld.long 0x00 31. " IRQ31 ,Interrupt 31 Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " IRQ30 ,Interrupt 30 Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " IRQ29 ,Interrupt 29 Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " IRQ28 ,Interrupt 28 Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IRQ27 ,Interrupt 27 Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " IRQ26 ,Interrupt 26 Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 25. " IRQ25 ,Interrupt 25 Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " IRQ24 ,Interrupt 24 Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IRQ23 ,Interrupt 23 Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " IRQ22 ,Interrupt 22 Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " IRQ21 ,Interrupt 21 Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " IRQ20 ,Interrupt 20 Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQ19 ,Interrupt 19 Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " IRQ18 ,Interrupt 18 Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " IRQ17 ,Interrupt 17 Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " IRQ16 ,Interrupt 16 Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 15. " IRQ15 ,Interrupt 15 Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " IRQ14 ,Interrupt 14 Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " IRQ13 ,Interrupt 13 Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " IRQ12 ,Interrupt 12 Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IRQ11 ,Interrupt 11 Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " IRQ10 ,Interrupt 10 Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " IRQ9 ,Interrupt 9 Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " IRQ8 ,Interrupt 8 Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQ7 ,Interrupt 7 Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " IRQ6 ,Interrupt 6 Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " IRQ5 ,Interrupt 5 Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " IRQ4 ,Interrupt 4 Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IRQ3 ,Interrupt 3 Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " IRQ2 ,Interrupt 2 Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " IRQ1 ,Interrupt 1 Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " IRQ0 ,Interrupt 0 Pending" "Not pending,Pending"
|
|
width 0xB
|
|
tree.end
|
|
tree "MATRIX (AHB Bus Matrix User Interface)"
|
|
sif ((cpu()=="ATSAM4C16C-CORE0")||(cpu()=="ATSAM4C8C-CORE0")||(cpu()=="ATSAM4CMP16C-CORE0")||(cpu()=="ATSAM4CMP8C-CORE0")||(cpu()=="ATSAM4CMS8C-CORE0")||(cpu()=="ATSAM4CMS16C-CORE0"))
|
|
base ad:0x400E0200
|
|
tree "Bus Matrix Master Configuration Registers"
|
|
width 15.
|
|
if (((d.l(ad:0x400E0200+0x1E4))&0x01)==0x00)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "MATRIX_MCFG0,Bus Matrix Master Configuration 0 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "MATRIX_MCFG1,Bus Matrix Master Configuration 1 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "MATRIX_MCFG2,Bus Matrix Master Configuration 2 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "MATRIX_MCFG3,Bus Matrix Master Configuration 3 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MATRIX_MCFG4,Bus Matrix Master Configuration 4 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MATRIX_MCFG5,Bus Matrix Master Configuration 5 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MATRIX_MCFG6,Bus Matrix Master Configuration 6 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
else
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "MATRIX_MCFG0,Bus Matrix Master Configuration 0 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
rgroup.long 0x4++0x03
|
|
line.long 0x00 "MATRIX_MCFG1,Bus Matrix Master Configuration 1 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
rgroup.long 0x8++0x03
|
|
line.long 0x00 "MATRIX_MCFG2,Bus Matrix Master Configuration 2 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
rgroup.long 0xC++0x03
|
|
line.long 0x00 "MATRIX_MCFG3,Bus Matrix Master Configuration 3 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "MATRIX_MCFG4,Bus Matrix Master Configuration 4 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "MATRIX_MCFG5,Bus Matrix Master Configuration 5 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "MATRIX_MCFG6,Bus Matrix Master Configuration 6 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
endif
|
|
tree.end
|
|
tree "Bus Matrix Slave Configuration Registers"
|
|
width 17.
|
|
if (((d.l(ad:0x400E0200+0x40))&0x30000)==0x20000)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MATRIX_SCFG0,Bus Matrix Slave Configuration 0 Register"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MATRIX_SCFG0,Bus Matrix Slave Configuration 0 Register"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
endif
|
|
if (((d.l(ad:0x400E0200+0x44))&0x30000)==0x20000)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "MATRIX_SCFG1,Bus Matrix Slave Configuration 1 Register"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
else
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "MATRIX_SCFG1,Bus Matrix Slave Configuration 1 Register"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
endif
|
|
if (((d.l(ad:0x400E0200+0x48))&0x30000)==0x20000)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "MATRIX_SCFG2,Bus Matrix Slave Configuration 2 Register"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
else
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "MATRIX_SCFG2,Bus Matrix Slave Configuration 2 Register"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
endif
|
|
if (((d.l(ad:0x400E0200+0x4C))&0x30000)==0x20000)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "MATRIX_SCFG3,Bus Matrix Slave Configuration 3 Register"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
else
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "MATRIX_SCFG3,Bus Matrix Slave Configuration 3 Register"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
endif
|
|
if (((d.l(ad:0x400E0200+0x50))&0x30000)==0x20000)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "MATRIX_SCFG4,Bus Matrix Slave Configuration 4 Register"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
else
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "MATRIX_SCFG4,Bus Matrix Slave Configuration 4 Register"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
endif
|
|
if (((d.l(ad:0x400E0200+0x54))&0x30000)==0x20000)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "MATRIX_SCFG5,Bus Matrix Slave Configuration 5 Register"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "MATRIX_SCFG5,Bus Matrix Slave Configuration 5 Register"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
endif
|
|
if (((d.l(ad:0x400E0200+0x58))&0x30000)==0x20000)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MATRIX_SCFG6,Bus Matrix Slave Configuration 6 Register"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MATRIX_SCFG6,Bus Matrix Slave Configuration 6 Register"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
endif
|
|
if (((d.l(ad:0x400E0200+0x5C))&0x30000)==0x20000)
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "MATRIX_SCFG7,Bus Matrix Slave Configuration 7 Register"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
else
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "MATRIX_SCFG7,Bus Matrix Slave Configuration 7 Register"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
endif
|
|
tree.end
|
|
width 15.
|
|
tree "Bus Matrix Priority Registers A-B For Slaves"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "MATRIX_PRAS0,Bus Matrix Priority Register 0 A For Slaves"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "MATRIX_PRBS0,Bus Matrix Priority Register 0 B For Slaves"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M12PR ,Master 12 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "MATRIX_PRAS1,Bus Matrix Priority Register 1 A For Slaves"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
group.long (0x88+0x04)++0x03
|
|
line.long 0x00 "MATRIX_PRBS1,Bus Matrix Priority Register 1 B For Slaves"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M12PR ,Master 12 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "MATRIX_PRAS2,Bus Matrix Priority Register 2 A For Slaves"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
group.long (0x90+0x04)++0x03
|
|
line.long 0x00 "MATRIX_PRBS2,Bus Matrix Priority Register 2 B For Slaves"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M12PR ,Master 12 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "MATRIX_PRAS3,Bus Matrix Priority Register 3 A For Slaves"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
group.long (0x98+0x04)++0x03
|
|
line.long 0x00 "MATRIX_PRBS3,Bus Matrix Priority Register 3 B For Slaves"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M12PR ,Master 12 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "MATRIX_PRAS4,Bus Matrix Priority Register 4 A For Slaves"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
group.long (0xA0+0x04)++0x03
|
|
line.long 0x00 "MATRIX_PRBS4,Bus Matrix Priority Register 4 B For Slaves"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M12PR ,Master 12 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "MATRIX_PRAS5,Bus Matrix Priority Register 5 A For Slaves"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
group.long (0xA8+0x04)++0x03
|
|
line.long 0x00 "MATRIX_PRBS5,Bus Matrix Priority Register 5 B For Slaves"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M12PR ,Master 12 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "MATRIX_PRAS6,Bus Matrix Priority Register 6 A For Slaves"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
group.long (0xB0+0x04)++0x03
|
|
line.long 0x00 "MATRIX_PRBS6,Bus Matrix Priority Register 6 B For Slaves"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M12PR ,Master 12 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "MATRIX_PRAS7,Bus Matrix Priority Register 7 A For Slaves"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
group.long (0xB8+0x04)++0x03
|
|
line.long 0x00 "MATRIX_PRBS7,Bus Matrix Priority Register 7 B For Slaves"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M12PR ,Master 12 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
tree.end
|
|
textline " "
|
|
width 19.
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "CCFG_SYSIO,System I/O Configuration Register"
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1")
|
|
bitfld.long 0x00 9. " SYSIO9 ,PC9 or ERASE Assignment" "ERASE,PC9"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " SYSIO3 , PB3 or TCK/SWCLK Assignment" "TCK/SWCLK,PB3"
|
|
bitfld.long 0x00 2. " SYSIO2 , PB2 or TMS/SWDIO Assignment" "TMS/SWDIO,PB2"
|
|
bitfld.long 0x00 1. " SYSIO1 ,PB1 or TDO/TRACESWO Assignment" "TDOTRACESWO,PB1"
|
|
bitfld.long 0x00 0. " SYSIO0 ,PB0 or TDI Assignment" "TDI,PB0"
|
|
group.long 0x124++0x07
|
|
line.long 0x00 "CCFG_SMCNFCS,SMC NAND Flash Chip select Configuration Register"
|
|
bitfld.long 0x00 31. " SMC_SEL ,SMC Selection for EBI pins" "SMC0,SMC1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SMC_NFCS3 ,SMC NAND Flash Chip Select 3 Assignment" "Not assigned,Assigned"
|
|
bitfld.long 0x00 2. " SMC_NFCS2 ,SMC NAND Flash Chip Select 2 Assignment" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SMC_NFCS1 ,SMC NAND Flash Chip Select 1 Assignment" "Not assigned,Assigned"
|
|
bitfld.long 0x00 0. " SMC_NFCS0 ,SMC NAND Flash Chip Select 0 Assignment" "Not assigned,Assigned"
|
|
line.long 0x04 "MATRIX_CORE_DEBUG,Core Debug Configuration Register"
|
|
bitfld.long 0x04 2. " CROSS_TRG0 ,Core 0 --> Core 1 Cross Triggering" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CROSS_TRG1 ,Core 1 --> Core 0 Cross Triggering" "Disabled,Enabled"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "MATRIX_WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
rgroup.long 0x1E8++0x03
|
|
line.long 0x00 "MATRIX_WPSR,Write Protect Status Register"
|
|
hexmask.long.word 0x00 8.--23. 1. " WPVSRC ,Write Protect Violation Source"
|
|
bitfld.long 0x00 0. " WPVS ,Write Protect Violation Status" "Not violated,Violated"
|
|
width 0xB
|
|
else
|
|
base ad:0x48010000
|
|
tree "Bus Matrix Master Configuration Registers"
|
|
width 15.
|
|
if (((d.l(ad:0x48010000+0x1E4))&0x01)==0x00)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "MATRIX_MCFG0,Bus Matrix Master Configuration 0 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "MATRIX_MCFG1,Bus Matrix Master Configuration 1 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "MATRIX_MCFG2,Bus Matrix Master Configuration 2 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "MATRIX_MCFG3,Bus Matrix Master Configuration 3 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MATRIX_MCFG4,Bus Matrix Master Configuration 4 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MATRIX_MCFG5,Bus Matrix Master Configuration 5 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MATRIX_MCFG6,Bus Matrix Master Configuration 6 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
else
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "MATRIX_MCFG0,Bus Matrix Master Configuration 0 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
rgroup.long 0x4++0x03
|
|
line.long 0x00 "MATRIX_MCFG1,Bus Matrix Master Configuration 1 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
rgroup.long 0x8++0x03
|
|
line.long 0x00 "MATRIX_MCFG2,Bus Matrix Master Configuration 2 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
rgroup.long 0xC++0x03
|
|
line.long 0x00 "MATRIX_MCFG3,Bus Matrix Master Configuration 3 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "MATRIX_MCFG4,Bus Matrix Master Configuration 4 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "MATRIX_MCFG5,Bus Matrix Master Configuration 5 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "MATRIX_MCFG6,Bus Matrix Master Configuration 6 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
endif
|
|
tree.end
|
|
tree "Bus Matrix Slave Configuration Registers"
|
|
width 17.
|
|
if (((d.l(ad:0x48010000+0x40))&0x30000)==0x20000)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MATRIX_SCFG0,Bus Matrix Slave Configuration 0 Register"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MATRIX_SCFG0,Bus Matrix Slave Configuration 0 Register"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
endif
|
|
if (((d.l(ad:0x48010000+0x44))&0x30000)==0x20000)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "MATRIX_SCFG1,Bus Matrix Slave Configuration 1 Register"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
else
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "MATRIX_SCFG1,Bus Matrix Slave Configuration 1 Register"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
endif
|
|
if (((d.l(ad:0x48010000+0x48))&0x30000)==0x20000)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "MATRIX_SCFG2,Bus Matrix Slave Configuration 2 Register"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
else
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "MATRIX_SCFG2,Bus Matrix Slave Configuration 2 Register"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
endif
|
|
if (((d.l(ad:0x48010000+0x4C))&0x30000)==0x20000)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "MATRIX_SCFG3,Bus Matrix Slave Configuration 3 Register"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
else
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "MATRIX_SCFG3,Bus Matrix Slave Configuration 3 Register"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
endif
|
|
if (((d.l(ad:0x48010000+0x50))&0x30000)==0x20000)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "MATRIX_SCFG4,Bus Matrix Slave Configuration 4 Register"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
else
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "MATRIX_SCFG4,Bus Matrix Slave Configuration 4 Register"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
endif
|
|
if (((d.l(ad:0x48010000+0x54))&0x30000)==0x20000)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "MATRIX_SCFG5,Bus Matrix Slave Configuration 5 Register"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "MATRIX_SCFG5,Bus Matrix Slave Configuration 5 Register"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
endif
|
|
if (((d.l(ad:0x48010000+0x58))&0x30000)==0x20000)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MATRIX_SCFG6,Bus Matrix Slave Configuration 6 Register"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MATRIX_SCFG6,Bus Matrix Slave Configuration 6 Register"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
endif
|
|
if (((d.l(ad:0x48010000+0x5C))&0x30000)==0x20000)
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "MATRIX_SCFG7,Bus Matrix Slave Configuration 7 Register"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
else
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "MATRIX_SCFG7,Bus Matrix Slave Configuration 7 Register"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
endif
|
|
tree.end
|
|
width 15.
|
|
tree "Bus Matrix Priority Registers A-B For Slaves"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "MATRIX_PRAS0,Bus Matrix Priority Register 0 A For Slaves"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "MATRIX_PRBS0,Bus Matrix Priority Register 0 B For Slaves"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M12PR ,Master 12 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "MATRIX_PRAS1,Bus Matrix Priority Register 1 A For Slaves"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
group.long (0x88+0x04)++0x03
|
|
line.long 0x00 "MATRIX_PRBS1,Bus Matrix Priority Register 1 B For Slaves"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M12PR ,Master 12 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "MATRIX_PRAS2,Bus Matrix Priority Register 2 A For Slaves"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
group.long (0x90+0x04)++0x03
|
|
line.long 0x00 "MATRIX_PRBS2,Bus Matrix Priority Register 2 B For Slaves"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M12PR ,Master 12 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "MATRIX_PRAS3,Bus Matrix Priority Register 3 A For Slaves"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
group.long (0x98+0x04)++0x03
|
|
line.long 0x00 "MATRIX_PRBS3,Bus Matrix Priority Register 3 B For Slaves"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M12PR ,Master 12 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "MATRIX_PRAS4,Bus Matrix Priority Register 4 A For Slaves"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
group.long (0xA0+0x04)++0x03
|
|
line.long 0x00 "MATRIX_PRBS4,Bus Matrix Priority Register 4 B For Slaves"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M12PR ,Master 12 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "MATRIX_PRAS5,Bus Matrix Priority Register 5 A For Slaves"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
group.long (0xA8+0x04)++0x03
|
|
line.long 0x00 "MATRIX_PRBS5,Bus Matrix Priority Register 5 B For Slaves"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M12PR ,Master 12 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "MATRIX_PRAS6,Bus Matrix Priority Register 6 A For Slaves"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
group.long (0xB0+0x04)++0x03
|
|
line.long 0x00 "MATRIX_PRBS6,Bus Matrix Priority Register 6 B For Slaves"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M12PR ,Master 12 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "MATRIX_PRAS7,Bus Matrix Priority Register 7 A For Slaves"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
group.long (0xB8+0x04)++0x03
|
|
line.long 0x00 "MATRIX_PRBS7,Bus Matrix Priority Register 7 B For Slaves"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M12PR ,Master 12 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
tree.end
|
|
textline " "
|
|
width 19.
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "CCFG_SYSIO,System I/O Configuration Register"
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1")
|
|
bitfld.long 0x00 9. " SYSIO9 ,PC9 or ERASE Assignment" "ERASE,PC9"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " SYSIO3 , PB3 or TCK/SWCLK Assignment" "TCK/SWCLK,PB3"
|
|
bitfld.long 0x00 2. " SYSIO2 , PB2 or TMS/SWDIO Assignment" "TMS/SWDIO,PB2"
|
|
bitfld.long 0x00 1. " SYSIO1 ,PB1 or TDO/TRACESWO Assignment" "TDOTRACESWO,PB1"
|
|
bitfld.long 0x00 0. " SYSIO0 ,PB0 or TDI Assignment" "TDI,PB0"
|
|
group.long 0x124++0x07
|
|
line.long 0x00 "CCFG_SMCNFCS,SMC NAND Flash Chip select Configuration Register"
|
|
bitfld.long 0x00 31. " SMC_SEL ,SMC Selection for EBI pins" "SMC0,SMC1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SMC_NFCS3 ,SMC NAND Flash Chip Select 3 Assignment" "Not assigned,Assigned"
|
|
bitfld.long 0x00 2. " SMC_NFCS2 ,SMC NAND Flash Chip Select 2 Assignment" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SMC_NFCS1 ,SMC NAND Flash Chip Select 1 Assignment" "Not assigned,Assigned"
|
|
bitfld.long 0x00 0. " SMC_NFCS0 ,SMC NAND Flash Chip Select 0 Assignment" "Not assigned,Assigned"
|
|
line.long 0x04 "MATRIX_CORE_DEBUG,Core Debug Configuration Register"
|
|
bitfld.long 0x04 2. " CROSS_TRG0 ,Core 0 --> Core 1 Cross Triggering" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CROSS_TRG1 ,Core 1 --> Core 0 Cross Triggering" "Disabled,Enabled"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "MATRIX_WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
rgroup.long 0x1E8++0x03
|
|
line.long 0x00 "MATRIX_WPSR,Write Protect Status Register"
|
|
hexmask.long.word 0x00 8.--23. 1. " WPVSRC ,Write Protect Violation Source"
|
|
bitfld.long 0x00 0. " WPVS ,Write Protect Violation Status" "Not violated,Violated"
|
|
width 0xB
|
|
endif
|
|
tree.end
|
|
sif ((cpu()=="ATSAM4C16C-CORE0")||(cpu()=="ATSAM4C8C-CORE0")||(cpu()=="ATSAM4CMP16C-CORE0")||(cpu()=="ATSAM4CMP8C-CORE0")||(cpu()=="ATSAM4CMS8C-CORE0")||(cpu()=="ATSAM4CMS16C-CORE0"))
|
|
tree "SMC 0 (Static Memory Controller 0)"
|
|
base ad:0x400E0000
|
|
width 13.
|
|
tree "CS 0"
|
|
group.long 0x0++0x0F
|
|
line.long 0x00 "SMC_SETUP0,SMC Setup Register"
|
|
bitfld.long 0x00 24.--29. " NCS_RD_SETUP ,NCS Setup Length in Read Access" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,128 cycles,129 cycles,130 cycles,131 cycles,132 cycles,133 cycles,134 cycles,135 cycles,136 cycles,137 cycles,138 cycles,139 cycles,140 cycles,141 cycles,142 cycles,143 cycles,144 cycles,145 cycles,146 cycles,147 cycles,148 cycles,149 cycles,150 cycles,151 cycles,152 cycles,153 cycles,154 cycles,155 cycles,156 cycles,157 cycles,158 cycles,159"
|
|
bitfld.long 0x00 16.--21. " NRD_SETUP ,NRD Setup Length" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,128 cycles,129 cycles,130 cycles,131 cycles,132 cycles,133 cycles,134 cycles,135 cycles,136 cycles,137 cycles,138 cycles,139 cycles,140 cycles,141 cycles,142 cycles,143 cycles,144 cycles,145 cycles,146 cycles,147 cycles,148 cycles,149 cycles,150 cycles,151 cycles,152 cycles,153 cycles,154 cycles,155 cycles,156 cycles,157 cycles,158 cycles,159"
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " NCS_WR_SETUP ,NCS Setup Length in Write Access" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,128 cycles,129 cycles,130 cycles,131 cycles,132 cycles,133 cycles,134 cycles,135 cycles,136 cycles,137 cycles,138 cycles,139 cycles,140 cycles,141 cycles,142 cycles,143 cycles,144 cycles,145 cycles,146 cycles,147 cycles,148 cycles,149 cycles,150 cycles,151 cycles,152 cycles,153 cycles,154 cycles,155 cycles,156 cycles,157 cycles,158 cycles,159"
|
|
bitfld.long 0x00 0.--5. " NWE_SETUP ,NWE Setup Length" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,128 cycles,129 cycles,130 cycles,131 cycles,132 cycles,133 cycles,134 cycles,135 cycles,136 cycles,137 cycles,138 cycles,139 cycles,140 cycles,141 cycles,142 cycles,143 cycles,144 cycles,145 cycles,146 cycles,147 cycles,148 cycles,149 cycles,150 cycles,151 cycles,152 cycles,153 cycles,154 cycles,155 cycles,156 cycles,157 cycles,158 cycles,159"
|
|
line.long 0x04 "SMC_PULSE0,SMC Pulse Register"
|
|
hexmask.long.byte 0x04 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in READ Access"
|
|
hexmask.long.byte 0x04 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in WRITE Access"
|
|
hexmask.long.byte 0x04 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x08 "SMC_CYCLE0,SMC Cycle Register"
|
|
hexmask.long.word 0x08 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x08 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
line.long 0x0C "SMC_MODE0,SMC MODE Register"
|
|
bitfld.long 0x0C 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x0C 24. " PMEN ,Page Mode Enabled" "Standard,Asynchronous burst"
|
|
bitfld.long 0x0C 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 16.--19. " TDF_CYCLES ,Data Float Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 12. " DBF ,Data Bus Width" "8-bit,16-bit"
|
|
bitfld.long 0x0C 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " WRITE_MODE ,States will be inserted after the setup of NWE/NCS" "NCS,NWE"
|
|
bitfld.long 0x0C 0. " READ_MODE ,Read operation is controlled by the NRD/NCS signal" "NCS,NRD"
|
|
tree.end
|
|
tree "CS 1"
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "SMC_SETUP1,SMC Setup Register"
|
|
bitfld.long 0x00 24.--29. " NCS_RD_SETUP ,NCS Setup Length in Read Access" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,128 cycles,129 cycles,130 cycles,131 cycles,132 cycles,133 cycles,134 cycles,135 cycles,136 cycles,137 cycles,138 cycles,139 cycles,140 cycles,141 cycles,142 cycles,143 cycles,144 cycles,145 cycles,146 cycles,147 cycles,148 cycles,149 cycles,150 cycles,151 cycles,152 cycles,153 cycles,154 cycles,155 cycles,156 cycles,157 cycles,158 cycles,159"
|
|
bitfld.long 0x00 16.--21. " NRD_SETUP ,NRD Setup Length" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,128 cycles,129 cycles,130 cycles,131 cycles,132 cycles,133 cycles,134 cycles,135 cycles,136 cycles,137 cycles,138 cycles,139 cycles,140 cycles,141 cycles,142 cycles,143 cycles,144 cycles,145 cycles,146 cycles,147 cycles,148 cycles,149 cycles,150 cycles,151 cycles,152 cycles,153 cycles,154 cycles,155 cycles,156 cycles,157 cycles,158 cycles,159"
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " NCS_WR_SETUP ,NCS Setup Length in Write Access" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,128 cycles,129 cycles,130 cycles,131 cycles,132 cycles,133 cycles,134 cycles,135 cycles,136 cycles,137 cycles,138 cycles,139 cycles,140 cycles,141 cycles,142 cycles,143 cycles,144 cycles,145 cycles,146 cycles,147 cycles,148 cycles,149 cycles,150 cycles,151 cycles,152 cycles,153 cycles,154 cycles,155 cycles,156 cycles,157 cycles,158 cycles,159"
|
|
bitfld.long 0x00 0.--5. " NWE_SETUP ,NWE Setup Length" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,128 cycles,129 cycles,130 cycles,131 cycles,132 cycles,133 cycles,134 cycles,135 cycles,136 cycles,137 cycles,138 cycles,139 cycles,140 cycles,141 cycles,142 cycles,143 cycles,144 cycles,145 cycles,146 cycles,147 cycles,148 cycles,149 cycles,150 cycles,151 cycles,152 cycles,153 cycles,154 cycles,155 cycles,156 cycles,157 cycles,158 cycles,159"
|
|
line.long 0x04 "SMC_PULSE1,SMC Pulse Register"
|
|
hexmask.long.byte 0x04 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in READ Access"
|
|
hexmask.long.byte 0x04 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in WRITE Access"
|
|
hexmask.long.byte 0x04 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x08 "SMC_CYCLE1,SMC Cycle Register"
|
|
hexmask.long.word 0x08 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x08 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
line.long 0x0C "SMC_MODE1,SMC MODE Register"
|
|
bitfld.long 0x0C 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x0C 24. " PMEN ,Page Mode Enabled" "Standard,Asynchronous burst"
|
|
bitfld.long 0x0C 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 16.--19. " TDF_CYCLES ,Data Float Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 12. " DBF ,Data Bus Width" "8-bit,16-bit"
|
|
bitfld.long 0x0C 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " WRITE_MODE ,States will be inserted after the setup of NWE/NCS" "NCS,NWE"
|
|
bitfld.long 0x0C 0. " READ_MODE ,Read operation is controlled by the NRD/NCS signal" "NCS,NRD"
|
|
tree.end
|
|
tree "CS 2"
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "SMC_SETUP2,SMC Setup Register"
|
|
bitfld.long 0x00 24.--29. " NCS_RD_SETUP ,NCS Setup Length in Read Access" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,128 cycles,129 cycles,130 cycles,131 cycles,132 cycles,133 cycles,134 cycles,135 cycles,136 cycles,137 cycles,138 cycles,139 cycles,140 cycles,141 cycles,142 cycles,143 cycles,144 cycles,145 cycles,146 cycles,147 cycles,148 cycles,149 cycles,150 cycles,151 cycles,152 cycles,153 cycles,154 cycles,155 cycles,156 cycles,157 cycles,158 cycles,159"
|
|
bitfld.long 0x00 16.--21. " NRD_SETUP ,NRD Setup Length" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,128 cycles,129 cycles,130 cycles,131 cycles,132 cycles,133 cycles,134 cycles,135 cycles,136 cycles,137 cycles,138 cycles,139 cycles,140 cycles,141 cycles,142 cycles,143 cycles,144 cycles,145 cycles,146 cycles,147 cycles,148 cycles,149 cycles,150 cycles,151 cycles,152 cycles,153 cycles,154 cycles,155 cycles,156 cycles,157 cycles,158 cycles,159"
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " NCS_WR_SETUP ,NCS Setup Length in Write Access" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,128 cycles,129 cycles,130 cycles,131 cycles,132 cycles,133 cycles,134 cycles,135 cycles,136 cycles,137 cycles,138 cycles,139 cycles,140 cycles,141 cycles,142 cycles,143 cycles,144 cycles,145 cycles,146 cycles,147 cycles,148 cycles,149 cycles,150 cycles,151 cycles,152 cycles,153 cycles,154 cycles,155 cycles,156 cycles,157 cycles,158 cycles,159"
|
|
bitfld.long 0x00 0.--5. " NWE_SETUP ,NWE Setup Length" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,128 cycles,129 cycles,130 cycles,131 cycles,132 cycles,133 cycles,134 cycles,135 cycles,136 cycles,137 cycles,138 cycles,139 cycles,140 cycles,141 cycles,142 cycles,143 cycles,144 cycles,145 cycles,146 cycles,147 cycles,148 cycles,149 cycles,150 cycles,151 cycles,152 cycles,153 cycles,154 cycles,155 cycles,156 cycles,157 cycles,158 cycles,159"
|
|
line.long 0x04 "SMC_PULSE2,SMC Pulse Register"
|
|
hexmask.long.byte 0x04 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in READ Access"
|
|
hexmask.long.byte 0x04 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in WRITE Access"
|
|
hexmask.long.byte 0x04 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x08 "SMC_CYCLE2,SMC Cycle Register"
|
|
hexmask.long.word 0x08 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x08 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
line.long 0x0C "SMC_MODE2,SMC MODE Register"
|
|
bitfld.long 0x0C 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x0C 24. " PMEN ,Page Mode Enabled" "Standard,Asynchronous burst"
|
|
bitfld.long 0x0C 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 16.--19. " TDF_CYCLES ,Data Float Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 12. " DBF ,Data Bus Width" "8-bit,16-bit"
|
|
bitfld.long 0x0C 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " WRITE_MODE ,States will be inserted after the setup of NWE/NCS" "NCS,NWE"
|
|
bitfld.long 0x0C 0. " READ_MODE ,Read operation is controlled by the NRD/NCS signal" "NCS,NRD"
|
|
tree.end
|
|
tree "CS 3"
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "SMC_SETUP3,SMC Setup Register"
|
|
bitfld.long 0x00 24.--29. " NCS_RD_SETUP ,NCS Setup Length in Read Access" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,128 cycles,129 cycles,130 cycles,131 cycles,132 cycles,133 cycles,134 cycles,135 cycles,136 cycles,137 cycles,138 cycles,139 cycles,140 cycles,141 cycles,142 cycles,143 cycles,144 cycles,145 cycles,146 cycles,147 cycles,148 cycles,149 cycles,150 cycles,151 cycles,152 cycles,153 cycles,154 cycles,155 cycles,156 cycles,157 cycles,158 cycles,159"
|
|
bitfld.long 0x00 16.--21. " NRD_SETUP ,NRD Setup Length" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,128 cycles,129 cycles,130 cycles,131 cycles,132 cycles,133 cycles,134 cycles,135 cycles,136 cycles,137 cycles,138 cycles,139 cycles,140 cycles,141 cycles,142 cycles,143 cycles,144 cycles,145 cycles,146 cycles,147 cycles,148 cycles,149 cycles,150 cycles,151 cycles,152 cycles,153 cycles,154 cycles,155 cycles,156 cycles,157 cycles,158 cycles,159"
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " NCS_WR_SETUP ,NCS Setup Length in Write Access" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,128 cycles,129 cycles,130 cycles,131 cycles,132 cycles,133 cycles,134 cycles,135 cycles,136 cycles,137 cycles,138 cycles,139 cycles,140 cycles,141 cycles,142 cycles,143 cycles,144 cycles,145 cycles,146 cycles,147 cycles,148 cycles,149 cycles,150 cycles,151 cycles,152 cycles,153 cycles,154 cycles,155 cycles,156 cycles,157 cycles,158 cycles,159"
|
|
bitfld.long 0x00 0.--5. " NWE_SETUP ,NWE Setup Length" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,128 cycles,129 cycles,130 cycles,131 cycles,132 cycles,133 cycles,134 cycles,135 cycles,136 cycles,137 cycles,138 cycles,139 cycles,140 cycles,141 cycles,142 cycles,143 cycles,144 cycles,145 cycles,146 cycles,147 cycles,148 cycles,149 cycles,150 cycles,151 cycles,152 cycles,153 cycles,154 cycles,155 cycles,156 cycles,157 cycles,158 cycles,159"
|
|
line.long 0x04 "SMC_PULSE3,SMC Pulse Register"
|
|
hexmask.long.byte 0x04 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in READ Access"
|
|
hexmask.long.byte 0x04 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in WRITE Access"
|
|
hexmask.long.byte 0x04 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x08 "SMC_CYCLE3,SMC Cycle Register"
|
|
hexmask.long.word 0x08 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x08 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
line.long 0x0C "SMC_MODE3,SMC MODE Register"
|
|
bitfld.long 0x0C 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x0C 24. " PMEN ,Page Mode Enabled" "Standard,Asynchronous burst"
|
|
bitfld.long 0x0C 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 16.--19. " TDF_CYCLES ,Data Float Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 12. " DBF ,Data Bus Width" "8-bit,16-bit"
|
|
bitfld.long 0x0C 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " WRITE_MODE ,States will be inserted after the setup of NWE/NCS" "NCS,NWE"
|
|
bitfld.long 0x0C 0. " READ_MODE ,Read operation is controlled by the NRD/NCS signal" "NCS,NRD"
|
|
tree.end
|
|
textline ""
|
|
width 10.
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SMC_OCMS,SMC OCMS Mode Register"
|
|
bitfld.long 0x00 19. " CS3SE ,Chip Select 3 Scrambling Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CS2SE ,Chip Select 2 Scrambling Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CS1SE ,Chip Select 1 Scrambling Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CS0SE ,Chip Select 0 Scrambling Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SMSE ,Static Memory Controller Scrambling Enable" "Disabled,Enabled"
|
|
wgroup.long 0x84++0x07
|
|
line.long 0x00 "SMC_KEY1,SMC OCMS Key1 Register"
|
|
line.long 0x04 "SMC_KEY2,SMC OCMS Key2 Register"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "SMC_WPCR,SMC Write Protection Control"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WP_KEY ,Write Protection KEY password"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "SMC_WPSR,SMC Write Protection Status"
|
|
textfld " "
|
|
in
|
|
width 0xB
|
|
tree.end
|
|
else
|
|
tree "SMC 1 (Static Memory Controller 1)"
|
|
base ad:0x4801C000
|
|
width 13.
|
|
tree "CS 0"
|
|
group.long 0x0++0x0F
|
|
line.long 0x00 "SMC_SETUP0,SMC Setup Register"
|
|
bitfld.long 0x00 24.--29. " NCS_RD_SETUP ,NCS Setup Length in Read Access" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,128 cycles,129 cycles,130 cycles,131 cycles,132 cycles,133 cycles,134 cycles,135 cycles,136 cycles,137 cycles,138 cycles,139 cycles,140 cycles,141 cycles,142 cycles,143 cycles,144 cycles,145 cycles,146 cycles,147 cycles,148 cycles,149 cycles,150 cycles,151 cycles,152 cycles,153 cycles,154 cycles,155 cycles,156 cycles,157 cycles,158 cycles,159"
|
|
bitfld.long 0x00 16.--21. " NRD_SETUP ,NRD Setup Length" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,128 cycles,129 cycles,130 cycles,131 cycles,132 cycles,133 cycles,134 cycles,135 cycles,136 cycles,137 cycles,138 cycles,139 cycles,140 cycles,141 cycles,142 cycles,143 cycles,144 cycles,145 cycles,146 cycles,147 cycles,148 cycles,149 cycles,150 cycles,151 cycles,152 cycles,153 cycles,154 cycles,155 cycles,156 cycles,157 cycles,158 cycles,159"
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " NCS_WR_SETUP ,NCS Setup Length in Write Access" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,128 cycles,129 cycles,130 cycles,131 cycles,132 cycles,133 cycles,134 cycles,135 cycles,136 cycles,137 cycles,138 cycles,139 cycles,140 cycles,141 cycles,142 cycles,143 cycles,144 cycles,145 cycles,146 cycles,147 cycles,148 cycles,149 cycles,150 cycles,151 cycles,152 cycles,153 cycles,154 cycles,155 cycles,156 cycles,157 cycles,158 cycles,159"
|
|
bitfld.long 0x00 0.--5. " NWE_SETUP ,NWE Setup Length" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,128 cycles,129 cycles,130 cycles,131 cycles,132 cycles,133 cycles,134 cycles,135 cycles,136 cycles,137 cycles,138 cycles,139 cycles,140 cycles,141 cycles,142 cycles,143 cycles,144 cycles,145 cycles,146 cycles,147 cycles,148 cycles,149 cycles,150 cycles,151 cycles,152 cycles,153 cycles,154 cycles,155 cycles,156 cycles,157 cycles,158 cycles,159"
|
|
line.long 0x04 "SMC_PULSE0,SMC Pulse Register"
|
|
hexmask.long.byte 0x04 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in READ Access"
|
|
hexmask.long.byte 0x04 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in WRITE Access"
|
|
hexmask.long.byte 0x04 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x08 "SMC_CYCLE0,SMC Cycle Register"
|
|
hexmask.long.word 0x08 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x08 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
line.long 0x0C "SMC_MODE0,SMC MODE Register"
|
|
bitfld.long 0x0C 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x0C 24. " PMEN ,Page Mode Enabled" "Standard,Asynchronous burst"
|
|
bitfld.long 0x0C 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 16.--19. " TDF_CYCLES ,Data Float Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 12. " DBF ,Data Bus Width" "8-bit,16-bit"
|
|
bitfld.long 0x0C 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " WRITE_MODE ,States will be inserted after the setup of NWE/NCS" "NCS,NWE"
|
|
bitfld.long 0x0C 0. " READ_MODE ,Read operation is controlled by the NRD/NCS signal" "NCS,NRD"
|
|
tree.end
|
|
tree "CS 1"
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "SMC_SETUP1,SMC Setup Register"
|
|
bitfld.long 0x00 24.--29. " NCS_RD_SETUP ,NCS Setup Length in Read Access" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,128 cycles,129 cycles,130 cycles,131 cycles,132 cycles,133 cycles,134 cycles,135 cycles,136 cycles,137 cycles,138 cycles,139 cycles,140 cycles,141 cycles,142 cycles,143 cycles,144 cycles,145 cycles,146 cycles,147 cycles,148 cycles,149 cycles,150 cycles,151 cycles,152 cycles,153 cycles,154 cycles,155 cycles,156 cycles,157 cycles,158 cycles,159"
|
|
bitfld.long 0x00 16.--21. " NRD_SETUP ,NRD Setup Length" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,128 cycles,129 cycles,130 cycles,131 cycles,132 cycles,133 cycles,134 cycles,135 cycles,136 cycles,137 cycles,138 cycles,139 cycles,140 cycles,141 cycles,142 cycles,143 cycles,144 cycles,145 cycles,146 cycles,147 cycles,148 cycles,149 cycles,150 cycles,151 cycles,152 cycles,153 cycles,154 cycles,155 cycles,156 cycles,157 cycles,158 cycles,159"
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " NCS_WR_SETUP ,NCS Setup Length in Write Access" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,128 cycles,129 cycles,130 cycles,131 cycles,132 cycles,133 cycles,134 cycles,135 cycles,136 cycles,137 cycles,138 cycles,139 cycles,140 cycles,141 cycles,142 cycles,143 cycles,144 cycles,145 cycles,146 cycles,147 cycles,148 cycles,149 cycles,150 cycles,151 cycles,152 cycles,153 cycles,154 cycles,155 cycles,156 cycles,157 cycles,158 cycles,159"
|
|
bitfld.long 0x00 0.--5. " NWE_SETUP ,NWE Setup Length" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,128 cycles,129 cycles,130 cycles,131 cycles,132 cycles,133 cycles,134 cycles,135 cycles,136 cycles,137 cycles,138 cycles,139 cycles,140 cycles,141 cycles,142 cycles,143 cycles,144 cycles,145 cycles,146 cycles,147 cycles,148 cycles,149 cycles,150 cycles,151 cycles,152 cycles,153 cycles,154 cycles,155 cycles,156 cycles,157 cycles,158 cycles,159"
|
|
line.long 0x04 "SMC_PULSE1,SMC Pulse Register"
|
|
hexmask.long.byte 0x04 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in READ Access"
|
|
hexmask.long.byte 0x04 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in WRITE Access"
|
|
hexmask.long.byte 0x04 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x08 "SMC_CYCLE1,SMC Cycle Register"
|
|
hexmask.long.word 0x08 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x08 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
line.long 0x0C "SMC_MODE1,SMC MODE Register"
|
|
bitfld.long 0x0C 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x0C 24. " PMEN ,Page Mode Enabled" "Standard,Asynchronous burst"
|
|
bitfld.long 0x0C 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 16.--19. " TDF_CYCLES ,Data Float Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 12. " DBF ,Data Bus Width" "8-bit,16-bit"
|
|
bitfld.long 0x0C 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " WRITE_MODE ,States will be inserted after the setup of NWE/NCS" "NCS,NWE"
|
|
bitfld.long 0x0C 0. " READ_MODE ,Read operation is controlled by the NRD/NCS signal" "NCS,NRD"
|
|
tree.end
|
|
tree "CS 2"
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "SMC_SETUP2,SMC Setup Register"
|
|
bitfld.long 0x00 24.--29. " NCS_RD_SETUP ,NCS Setup Length in Read Access" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,128 cycles,129 cycles,130 cycles,131 cycles,132 cycles,133 cycles,134 cycles,135 cycles,136 cycles,137 cycles,138 cycles,139 cycles,140 cycles,141 cycles,142 cycles,143 cycles,144 cycles,145 cycles,146 cycles,147 cycles,148 cycles,149 cycles,150 cycles,151 cycles,152 cycles,153 cycles,154 cycles,155 cycles,156 cycles,157 cycles,158 cycles,159"
|
|
bitfld.long 0x00 16.--21. " NRD_SETUP ,NRD Setup Length" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,128 cycles,129 cycles,130 cycles,131 cycles,132 cycles,133 cycles,134 cycles,135 cycles,136 cycles,137 cycles,138 cycles,139 cycles,140 cycles,141 cycles,142 cycles,143 cycles,144 cycles,145 cycles,146 cycles,147 cycles,148 cycles,149 cycles,150 cycles,151 cycles,152 cycles,153 cycles,154 cycles,155 cycles,156 cycles,157 cycles,158 cycles,159"
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " NCS_WR_SETUP ,NCS Setup Length in Write Access" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,128 cycles,129 cycles,130 cycles,131 cycles,132 cycles,133 cycles,134 cycles,135 cycles,136 cycles,137 cycles,138 cycles,139 cycles,140 cycles,141 cycles,142 cycles,143 cycles,144 cycles,145 cycles,146 cycles,147 cycles,148 cycles,149 cycles,150 cycles,151 cycles,152 cycles,153 cycles,154 cycles,155 cycles,156 cycles,157 cycles,158 cycles,159"
|
|
bitfld.long 0x00 0.--5. " NWE_SETUP ,NWE Setup Length" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,128 cycles,129 cycles,130 cycles,131 cycles,132 cycles,133 cycles,134 cycles,135 cycles,136 cycles,137 cycles,138 cycles,139 cycles,140 cycles,141 cycles,142 cycles,143 cycles,144 cycles,145 cycles,146 cycles,147 cycles,148 cycles,149 cycles,150 cycles,151 cycles,152 cycles,153 cycles,154 cycles,155 cycles,156 cycles,157 cycles,158 cycles,159"
|
|
line.long 0x04 "SMC_PULSE2,SMC Pulse Register"
|
|
hexmask.long.byte 0x04 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in READ Access"
|
|
hexmask.long.byte 0x04 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in WRITE Access"
|
|
hexmask.long.byte 0x04 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x08 "SMC_CYCLE2,SMC Cycle Register"
|
|
hexmask.long.word 0x08 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x08 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
line.long 0x0C "SMC_MODE2,SMC MODE Register"
|
|
bitfld.long 0x0C 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x0C 24. " PMEN ,Page Mode Enabled" "Standard,Asynchronous burst"
|
|
bitfld.long 0x0C 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 16.--19. " TDF_CYCLES ,Data Float Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 12. " DBF ,Data Bus Width" "8-bit,16-bit"
|
|
bitfld.long 0x0C 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " WRITE_MODE ,States will be inserted after the setup of NWE/NCS" "NCS,NWE"
|
|
bitfld.long 0x0C 0. " READ_MODE ,Read operation is controlled by the NRD/NCS signal" "NCS,NRD"
|
|
tree.end
|
|
tree "CS 3"
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "SMC_SETUP3,SMC Setup Register"
|
|
bitfld.long 0x00 24.--29. " NCS_RD_SETUP ,NCS Setup Length in Read Access" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,128 cycles,129 cycles,130 cycles,131 cycles,132 cycles,133 cycles,134 cycles,135 cycles,136 cycles,137 cycles,138 cycles,139 cycles,140 cycles,141 cycles,142 cycles,143 cycles,144 cycles,145 cycles,146 cycles,147 cycles,148 cycles,149 cycles,150 cycles,151 cycles,152 cycles,153 cycles,154 cycles,155 cycles,156 cycles,157 cycles,158 cycles,159"
|
|
bitfld.long 0x00 16.--21. " NRD_SETUP ,NRD Setup Length" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,128 cycles,129 cycles,130 cycles,131 cycles,132 cycles,133 cycles,134 cycles,135 cycles,136 cycles,137 cycles,138 cycles,139 cycles,140 cycles,141 cycles,142 cycles,143 cycles,144 cycles,145 cycles,146 cycles,147 cycles,148 cycles,149 cycles,150 cycles,151 cycles,152 cycles,153 cycles,154 cycles,155 cycles,156 cycles,157 cycles,158 cycles,159"
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " NCS_WR_SETUP ,NCS Setup Length in Write Access" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,128 cycles,129 cycles,130 cycles,131 cycles,132 cycles,133 cycles,134 cycles,135 cycles,136 cycles,137 cycles,138 cycles,139 cycles,140 cycles,141 cycles,142 cycles,143 cycles,144 cycles,145 cycles,146 cycles,147 cycles,148 cycles,149 cycles,150 cycles,151 cycles,152 cycles,153 cycles,154 cycles,155 cycles,156 cycles,157 cycles,158 cycles,159"
|
|
bitfld.long 0x00 0.--5. " NWE_SETUP ,NWE Setup Length" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,128 cycles,129 cycles,130 cycles,131 cycles,132 cycles,133 cycles,134 cycles,135 cycles,136 cycles,137 cycles,138 cycles,139 cycles,140 cycles,141 cycles,142 cycles,143 cycles,144 cycles,145 cycles,146 cycles,147 cycles,148 cycles,149 cycles,150 cycles,151 cycles,152 cycles,153 cycles,154 cycles,155 cycles,156 cycles,157 cycles,158 cycles,159"
|
|
line.long 0x04 "SMC_PULSE3,SMC Pulse Register"
|
|
hexmask.long.byte 0x04 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in READ Access"
|
|
hexmask.long.byte 0x04 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in WRITE Access"
|
|
hexmask.long.byte 0x04 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x08 "SMC_CYCLE3,SMC Cycle Register"
|
|
hexmask.long.word 0x08 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x08 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
line.long 0x0C "SMC_MODE3,SMC MODE Register"
|
|
bitfld.long 0x0C 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x0C 24. " PMEN ,Page Mode Enabled" "Standard,Asynchronous burst"
|
|
bitfld.long 0x0C 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 16.--19. " TDF_CYCLES ,Data Float Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 12. " DBF ,Data Bus Width" "8-bit,16-bit"
|
|
bitfld.long 0x0C 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " WRITE_MODE ,States will be inserted after the setup of NWE/NCS" "NCS,NWE"
|
|
bitfld.long 0x0C 0. " READ_MODE ,Read operation is controlled by the NRD/NCS signal" "NCS,NRD"
|
|
tree.end
|
|
textline ""
|
|
width 10.
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SMC_OCMS,SMC OCMS Mode Register"
|
|
bitfld.long 0x00 19. " CS3SE ,Chip Select 3 Scrambling Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CS2SE ,Chip Select 2 Scrambling Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CS1SE ,Chip Select 1 Scrambling Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CS0SE ,Chip Select 0 Scrambling Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SMSE ,Static Memory Controller Scrambling Enable" "Disabled,Enabled"
|
|
wgroup.long 0x84++0x07
|
|
line.long 0x00 "SMC_KEY1,SMC OCMS Key1 Register"
|
|
line.long 0x04 "SMC_KEY2,SMC OCMS Key2 Register"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "SMC_WPCR,SMC Write Protection Control"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WP_KEY ,Write Protection KEY password"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "SMC_WPSR,SMC Write Protection Status"
|
|
textfld " "
|
|
in
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree "PMC (Power Management Controller)"
|
|
base ad:0x400E0400
|
|
width 19.
|
|
if ((d.l(ad:0x400E0400+0xE4)&0x01)==0x00)
|
|
wgroup.long 0x00++0x07
|
|
line.long 0x00 "PMC_SCER,PMC System Clock Enable Register"
|
|
bitfld.long 0x00 20.--23. " CPKEY ,Coprocessor Clocks Enable Key" ",,,,,,,,,,Enable,?..."
|
|
line.long 0x04 "PMC_SCDR,PMC System Clock Disable Register"
|
|
bitfld.long 0x04 20.--23. " CPKEY ,Coprocessor Clocks Disable Key" ",,,,,,,,,,Disable,?..."
|
|
group.long 0x08++0x03
|
|
line.long 0x0 "PMC_SCSR,PMC System Clock Status Register"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " CPBMCK ,Coprocessor Bus Master Clocks Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " CPCK ,Coprocessor Clocks Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " PCK2 ,Programmable Clock 2 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " PCK1 ,Programmable Clock 1 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " PCK0 ,Programmable Clock 0 Output Status" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x0 "PMC_PCSR0_set/clr,PMC Peripheral Clock Status Register 0"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " IPC0 ,Interprocessor communication 0 (Peripheral ID 31) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " ADC ,Analog To Digital Converter (Peripheral ID 29) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " TC5 ,Timer/Counter 5 (Peripheral ID 28) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " TC4 ,Timer/Counter 4 (Peripheral ID 27) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " TC3 ,Timer/Counter 3 (Peripheral ID 26) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " TC2 ,Timer/Counter 2 (Peripheral ID 25) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " TC1 ,Timer/Counter 1 (Peripheral ID 24) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " TC0 ,Timer/Counter 0 (Peripheral ID 23) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 21. " SPI0 ,Serial Peripheral Interface 0 (Peripheral ID 21) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " TWI1 ,Two Wire Interface 1 (Peripheral ID 20) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " TWI0 ,Two Wire Interface 0 (Peripheral ID 19) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
sif ((cpu()=="ATSAM4CMS8C-CORE0")||(cpu()=="ATSAM4CMS16C-CORE0")||(cpu()=="ATSAM4CMS8C-CORE1")||(cpu()=="ATSAM4CMS16C-CORE1"))
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " USART3 ,USART 3 (Peripheral ID 17) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " USART2 ,USART 2 (Peripheral ID 16) Controller Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " USART1 ,USART 1(Peripheral ID 15) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " USART0 ,USART 0 (Peripheral ID 14) Clock Status" "Disabled,Enabled"
|
|
elif ((cpu()=="ATSAM4CMP16C-CORE0")||(cpu()=="ATSAM4CMP8C-CORE0")||(cpu()=="ATSAM4CMP16C-CORE1")||(cpu()=="ATSAM4CMP8C-CORE1"))
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " USART2 ,USART 2 (Peripheral ID 16) Controller Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " USART1 ,USART 1(Peripheral ID 15) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " USART0 ,USART 0 (Peripheral ID 14) Clock Status" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " USART4 ,USART 4 (Peripheral ID 18) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " USART3 ,USART 3 (Peripheral ID 17) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " USART2 ,USART 2 (Peripheral ID 16) Controller Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " USART1 ,USART 1(Peripheral ID 15) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " USART0 ,USART 0 (Peripheral ID 14) Clock Status" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " PIOB ,Parallel I/O Controller B (Peripheral ID 12) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " PIOA ,Parallel I/O Controller A (Peripheral ID 11) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " SMC0 ,Static Memory Controller 0 (Peripheral ID 10) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " UART0 ,UART 0 (Peripheral ID 8) Clock Status" "Disabled,Enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CKGR_MOR,PMC Clock Generator Main Oscillator Register"
|
|
bitfld.long 0x00 26. " XT32KFME ,Slow Crystal Oscillator Frequency Monitoring Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " CFDEN ,Clock Failure Detector Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " MOSCSEL ,Main Oscillator Selection" "On-Chip RC,Crystal"
|
|
hexmask.long.byte 0x00 16.--23. 1. " KEY ,Write Access Password"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " MOSCXTST ,Main Crystal Oscillator Start-up Time"
|
|
bitfld.long 0x00 4.--6. " MOSCRCF ,Main On-Chip RC Oscillator Frequency Selection" "4 MHz,8 MHz,12 MHz,?..."
|
|
bitfld.long 0x00 3. " MOSCRCEN ,Main On-Chip RC Oscillator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " WAITMODE ,Wait Mode Command" "No effect,Wait Mode"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MOSCXTBY ,Main Crystal Oscillator Bypass" "No effect,Bypassed"
|
|
bitfld.long 0x00 0. " MOSCXTEN ,Main Crystal Oscillator Enable" "Disabled,Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CKGR_MCFR,PMC Clock Generator Main Clock Frequency Register"
|
|
bitfld.long 0x00 20. " RCMEAS ,RC Oscillator Frequency Measure" "No effect,Restart"
|
|
bitfld.long 0x00 16. " MAINFRDY ,Main Clock Ready" "Not ready,Ready"
|
|
hexmask.long.word 0x00 0.--15. 1. " MAINF ,Main Clock Frequency"
|
|
group.long 0x28++0x7
|
|
line.long 0x00 "CKGR_PLLAR,PMC Clock Generator PLLA Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " MULA ,PLLA Multiplier"
|
|
bitfld.long 0x00 8.--13. " PLLACOUNT ,PLLA Counter" "0,1,2,3,4,5,%d..."
|
|
bitfld.long 0x00 0. " PLLAEN ,PLLA Control" "Disabled,Enabled"
|
|
line.long 0x04 "CKGR_PLLBR,PMC Clock Generator PLLB Register"
|
|
bitfld.long 0x04 29. " SRCB ,Source for PLLB" "Main Clock,PLLA"
|
|
hexmask.long.word 0x04 16.--26. 1. " MULB ,PLLB Multiplier"
|
|
bitfld.long 0x04 8.--13. " PLLBCOUNT ,PLLB Counter" "0,1,2,3,4,5,%d..."
|
|
hexmask.long.byte 0x04 0.--7. 1. " DIVB ,PLLB Front-End Divider"
|
|
group.long 0x30++0x03
|
|
line.long 0x0 "PMC_MCKR,PMC Master Clock Register"
|
|
bitfld.long 0x00 20.--23. " CPPRES ,AHB 32-bit Matrix Divisor (Matrix frequency)" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 16.--18. " CPCSS ,Coprocessor Master Clock Source Selection" "Slow,Main,PLLA,PLLB,Master,?..."
|
|
bitfld.long 0x00 13. " PLLBDIV2 ,PLLB Divisor by 2" "/1,/2"
|
|
bitfld.long 0x00 12. " PLLADIV2 ,PLLA Divisor by 2" "/1,/2"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PRES ,Master/Processor Clock Prescaler" "/1,/2,/4,/8,/16,/32,/64,/3"
|
|
bitfld.long 0x00 0.--1. " CSS ,Master/Processor Clock Source Selection" "Slow,Main,PLLA,PLLB"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PMC_PCK0,PMC Programmable Clock 0 Register"
|
|
bitfld.long 0x00 4.--6. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0x00 0.--2. " CSS ,Master Clock Selection" "Slow,Main,PLLACK2,UPLL,Master,?..."
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PMC_PCK1,PMC Programmable Clock 1 Register"
|
|
bitfld.long 0x00 4.--6. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0x00 0.--2. " CSS ,Master Clock Selection" "Slow,Main,PLLACK2,UPLL,Master,?..."
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PMC_PCK2,PMC Programmable Clock 2 Register"
|
|
bitfld.long 0x00 4.--6. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0x00 0.--2. " CSS ,Master Clock Selection" "Slow,Main,PLLACK2,UPLL,Master,?..."
|
|
else
|
|
hgroup.long 0x00++0x07
|
|
hide.long 0x00 "PMC_SCER,PMC System Clock Enable Register"
|
|
hide.long 0x04 "PMC_SCDR,PMC System Clock Disable Register"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "PMC_SCSR,PMC System Clock Status Register"
|
|
bitfld.long 0x00 17. " CPBMCK ,Coprocessor Bus Master Clocks Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CPCK ,Coprocessor Clocks Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PCK2 ,Programmable Clock 2 Output Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PCK1 ,Programmable Clock 1 Output Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PCK0 ,Programmable Clock 0 Output Status" "Disabled,Enabled"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "PMC_PCSR0,PMC Peripheral Clock Status Register 0"
|
|
bitfld.long 0x00 31. " IPC0 ,Interprocessor communication 0 (Peripheral ID 31) Clock Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ADC ,Analog To Digital Converter (Peripheral ID 29) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TC5 ,Timer/Counter 5 (Peripheral ID 28) Clock Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " TC4 ,Timer/Counter 4 (Peripheral ID 27) Clock Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " TC3 ,Timer/Counter 3 (Peripheral ID 26) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TC2 ,Timer/Counter 2 (Peripheral ID 25) Clock Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " TC1 ,Timer/Counter 1 (Peripheral ID 24) Clock Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TC0 ,Timer/Counter 0 (Peripheral ID 23) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPI0 ,Serial Peripheral Interface 0 (Peripheral ID 21) Clock Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TWI1 ,Two Wire Interface 1 (Peripheral ID 20) Clock Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " TWI0 ,Two Wire Interface 0 (Peripheral ID 19) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
sif ((cpu()=="ATSAM4CMS8C-CORE0")||(cpu()=="ATSAM4CMS16C-CORE0")||(cpu()=="ATSAM4CMS8C-CORE1")||(cpu()=="ATSAM4CMS16C-CORE1"))
|
|
bitfld.long 0x00 17. " USART3 ,USART 3 (Peripheral ID 17) Clock Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " USART2 ,USART 2 (Peripheral ID 16) Controller Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USART1 ,USART 1(Peripheral ID 15) Clock Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " USART0 ,USART 0 (Peripheral ID 14) Clock Status" "Disabled,Enabled"
|
|
elif ((cpu()=="ATSAM4CMP16C-CORE0")||(cpu()=="ATSAM4CMP8C-CORE0")||(cpu()=="ATSAM4CMP16C-CORE1")||(cpu()=="ATSAM4CMP8C-CORE1"))
|
|
bitfld.long 0x00 16. " USART2 ,USART 2 (Peripheral ID 16) Controller Clock Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " USART1 ,USART 1(Peripheral ID 15) Clock Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " USART0 ,USART 0 (Peripheral ID 14) Clock Status" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 18. " USART4 ,USART 4 (Peripheral ID 18) Clock Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " USART3 ,USART 3 (Peripheral ID 17) Clock Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " USART2 ,USART 2 (Peripheral ID 16) Controller Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USART1 ,USART 1(Peripheral ID 15) Clock Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " USART0 ,USART 0 (Peripheral ID 14) Clock Status" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " PIOB ,Parallel I/O Controller B (Peripheral ID 12) Clock Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PIOA ,Parallel I/O Controller A (Peripheral ID 11) Clock Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SMC0 ,Static Memory Controller 0 (Peripheral ID 10) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " UART0 ,UART 0 (Peripheral ID 8) Clock Status" "Disabled,Enabled"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "CKGR_MOR,PMC Clock Generator Main Oscillator Register"
|
|
bitfld.long 0x00 26. " XT32KFME ,Slow Crystal Oscillator Frequency Monitoring Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " CFDEN ,Clock Failure Detector Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " MOSCSEL ,Main Oscillator Selection" "On-Chip RC,Crystal"
|
|
hexmask.long.byte 0x00 16.--23. 1. " KEY ,Write Access Password"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " MOSCXTST ,Main Crystal Oscillator Start-up Time"
|
|
bitfld.long 0x00 4.--6. " MOSCRCF ,Main On-Chip RC Oscillator Frequency Selection" "4 MHz,8 MHz,12 MHz,?..."
|
|
bitfld.long 0x00 3. " MOSCRCEN ,Main On-Chip RC Oscillator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " WAITMODE ,Wait Mode Command" "No effect,Wait Mode"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MOSCXTBY ,Main Crystal Oscillator Bypass" "No effect,Bypassed"
|
|
bitfld.long 0x00 0. " MOSCXTEN ,Main Crystal Oscillator Enable" "Disabled,Enabled"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "CKGR_MCFR,PMC Clock Generator Main Clock Frequency Register"
|
|
bitfld.long 0x00 20. " RCMEAS ,RC Oscillator Frequency Measure" "No effect,Restart"
|
|
bitfld.long 0x00 16. " MAINFRDY ,Main Clock Ready" "Not ready,Ready"
|
|
hexmask.long.word 0x00 0.--15. 1. " MAINF ,Main Clock Frequency"
|
|
rgroup.long 0x28++0x07
|
|
line.long 0x00 "CKGR_PLLAR,PMC Clock Generator PLLA Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " MULA ,PLLA Multiplier"
|
|
bitfld.long 0x00 8.--13. " PLLACOUNT ,PLLA Counter" "0,1,2,3,4,5,%d..."
|
|
bitfld.long 0x00 0. " PLLAEN ,PLLA Control" "Disabled,Enabled"
|
|
line.long 0x04 "CKGR_PLLBR,PMC Clock Generator PLLB Register"
|
|
bitfld.long 0x04 29. " SRCB ,Source for PLLB" "Main Clock,PLLA"
|
|
hexmask.long.word 0x04 16.--26. 1. " MULB ,PLLB Multiplier"
|
|
bitfld.long 0x04 8.--13. " PLLBCOUNT ,PLLB Counter" "0,1,2,3,4,5,%d..."
|
|
hexmask.long.byte 0x04 0.--7. 1. " DIVB ,PLLB Front-End Divider"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x0 "PMC_MCKR,PMC Master Clock Register"
|
|
bitfld.long 0x00 20.--23. " CPPRES ,AHB 32-bit Matrix Divisor (Matrix frequency)" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 16.--18. " CPCSS ,Coprocessor Master Clock Source Selection" "Slow,Main,PLLA,PLLB,Master,?..."
|
|
bitfld.long 0x00 13. " PLLBDIV2 ,PLLB Divisor by 2" "/1,/2"
|
|
bitfld.long 0x00 12. " PLLADIV2 ,PLLA Divisor by 2" "/1,/2"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PRES ,Master/Processor Clock Prescaler" "/1,/2,/4,/8,/16,/32,/64,/3"
|
|
bitfld.long 0x00 0.--1. " CSS ,Master/Processor Clock Source Selection" "Slow,Main,PLLA,PLLB"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "PMC_PCK0,PMC Programmable Clock 0 Register"
|
|
bitfld.long 0x00 4.--6. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0x00 0.--2. " CSS ,Master Clock Selection" "Slow,Main,PLLACK2,UPLL,Master,?..."
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "PMC_PCK1,PMC Programmable Clock 1 Register"
|
|
bitfld.long 0x00 4.--6. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0x00 0.--2. " CSS ,Master Clock Selection" "Slow,Main,PLLACK2,UPLL,Master,?..."
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "PMC_PCK2,PMC Programmable Clock 2 Register"
|
|
bitfld.long 0x00 4.--6. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0x00 0.--2. " CSS ,Master Clock Selection" "Slow,Main,PLLACK2,UPLL,Master,?..."
|
|
endif
|
|
hgroup.long 0x68++0x03
|
|
hide.long 0x00 "PMC_SR,PMC Status Register"
|
|
textfld " "
|
|
in
|
|
group.long 0x6c++0x03
|
|
line.long 0x00 "PMC_IMR_set/clr,PMC Interrupt Mask Register"
|
|
setclrfld.long 0x00 21. -0x0c 21. -0x08 21. " XT32KERR ,Main Crystal Oscillator Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x0c 18. -0x08 18. " CFDEV ,Clock Failure Detector Event Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x0c 17. -0x08 17. " MOSCRCS ,Main On-Chip RC Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x0c 16. -0x08 16. " MOSCSELS ,Main Oscillator Selection Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x0c 10. -0x08 10. " PCKRDY2 ,Programmable Clock Ready 2 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x0c 9. -0x08 9. " PCKRDY1 ,Programmable Clock Ready 1 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x0c 8. -0x08 8. " PCKRDY0 ,Programmable Clock Ready 0 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x0c 3. -0x08 3. " MCKRDY ,Master Clock Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x0c 2. -0x08 2. " LOCKB ,PLLB Lock Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x0c 1. -0x08 1. " LOCKA ,PLLA Lock Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x0c 0. -0x08 0. " MOSCXTS ,Main Crystal Oscillator Interrupt Mask" "Disabled,Enabled"
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "PMC_FSMR,PMC Fast Start-up Mode Register"
|
|
bitfld.long 0x00 21.--22. " FLPM ,Flash Low Power Mode" "Standby,Deep power down,Idle,"
|
|
bitfld.long 0x00 20. " LPM ,Low Power Mode" "WFI/WFE -> Sleep Mode,WFE -> Wait Mode"
|
|
bitfld.long 0x00 17. " RTCAL ,RTC Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RTTAL ,RTT Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FSTT15 ,Fast Start-up Input 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FSTT14 ,Fast Start-up Input 14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " FSTT13 ,Fast Start-up Input 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " FSTT12 ,Fast Start-up Input 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSTT11 ,Fast Start-up Input 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " FSTT10 ,Fast Start-up Input 10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " FSTT9 ,Fast Start-up Input 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FSTT8 ,Fast Start-up Input 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FSTT7 ,Fast Start-up Input 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FSTT6 ,Fast Start-up Input 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FSTT5 ,Fast Start-up Input 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FSTT4 ,Fast Start-up Input 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FSTT3 ,Fast Start-up Input 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FSTT2 ,Fast Start-up Input 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FSTT1 ,Fast Start-up Input 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FSTT0 ,Fast Start-up Input 0 Enable" "Disabled,Enabled"
|
|
line.long 0x04 "PMC_FSPR,PMC Fast Start-up Polarity Register"
|
|
bitfld.long 0x04 15. " FSTP15 ,Fast Start-up Input 15 Polarity" "Low,High"
|
|
bitfld.long 0x04 14. " FSTP14 ,Fast Start-up Input 14 Polarity" "Low,High"
|
|
bitfld.long 0x04 13. " FSTP13 ,Fast Start-up Input 13 Polarity" "Low,High"
|
|
bitfld.long 0x04 12. " FSTP12 ,Fast Start-up Input 12 Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FSTP11 ,Fast Start-up Input 11 Polarity" "Low,High"
|
|
bitfld.long 0x04 10. " FSTP10 ,Fast Start-up Input 10 Polarity" "Low,High"
|
|
bitfld.long 0x04 9. " FSTP9 ,Fast Start-up Input 9 Polarity" "Low,High"
|
|
bitfld.long 0x04 8. " FSTP8 ,Fast Start-up Input 8 Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FSTP7 ,Fast Start-up Input 7 Polarity" "Low,High"
|
|
bitfld.long 0x04 6. " FSTP6 ,Fast Start-up Input 6 Polarity" "Low,High"
|
|
bitfld.long 0x04 5. " FSTP5 ,Fast Start-up Input 5 Polarity" "Low,High"
|
|
bitfld.long 0x04 4. " FSTP4 ,Fast Start-up Input 4 Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FSTP3 ,Fast Start-up Input 3 Polarity" "Low,High"
|
|
bitfld.long 0x04 2. " FSTP2 ,Fast Start-up Input 2 Polarity" "Low,High"
|
|
bitfld.long 0x04 1. " FSTP1 ,Fast Start-up Input 1 Polarity" "Low,High"
|
|
bitfld.long 0x04 0. " FSTP0 ,Fast Start-up Input 0 Polarity" "Low,High"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "PMC_CPFSMR,PMC Coprocessor Fast Start-up Mode Register"
|
|
bitfld.long 0x00 17. " RTCAL ,RTC Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RTTAL ,RTT Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FSTT15 ,Fast Start-up Input 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FSTT14 ,Fast Start-up Input 14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " FSTT13 ,Fast Start-up Input 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " FSTT12 ,Fast Start-up Input 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSTT11 ,Fast Start-up Input 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " FSTT10 ,Fast Start-up Input 10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " FSTT9 ,Fast Start-up Input 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FSTT8 ,Fast Start-up Input 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FSTT7 ,Fast Start-up Input 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FSTT6 ,Fast Start-up Input 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FSTT5 ,Fast Start-up Input 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FSTT4 ,Fast Start-up Input 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FSTT3 ,Fast Start-up Input 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FSTT2 ,Fast Start-up Input 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FSTT1 ,Fast Start-up Input 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FSTT0 ,Fast Start-up Input 0 Enable" "Disabled,Enabled"
|
|
wgroup.long 0x78++0x03
|
|
line.long 0x00 "PMC_FOCR,PMC Fault Output Clear Register"
|
|
bitfld.long 0x00 0. " FOCLR ,Fault Output Clear" "No effect,Clear"
|
|
group.long 0xe4++0x03
|
|
line.long 0x00 "PMC_WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
rgroup.long 0xe8++0x03
|
|
line.long 0x00 "PMC_WPSR,Write Protect Status Register"
|
|
hexmask.long.word 0x00 8.--23. 1. " WPVSRC ,Write Protection Violation Source"
|
|
bitfld.long 0x00 0. " WPVS ,Write Protection Violation Status" "No violation,Violation"
|
|
if ((d.l(ad:0x400E0400+0xE4)&0x01)==0x00)
|
|
group.long 0x108++0x03
|
|
line.long 0x0 "PMC_PCSR1_set/clr,PMC Peripheral Clock Status Register 1"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " SMC1 ,Static Memory Controller 1 (Peripheral ID 43) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " SRAM ,SRAM (Peripheral ID 42) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " PWM ,Pulse Width Modulation (Peripheral ID 41) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " SPI1 ,Serial Peripheral Interface 1 (Peripheral ID 40) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " IPC1 ,Interprocessor communication 1 (Peripheral ID 39) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " UART1 ,UART 1 (Peripheral ID 38) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " PIOC ,Parallel I/O Controller C (Peripheral ID 37) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " AES ,Advanced Enhanced Standard (Peripheral ID 36) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPKCC ,Classical Public Key Cryptography Controller (Peripheral ID 35) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " ICM ,Integrity Check Module" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TRNG ,True Random Generator (Peripheral ID 33) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " SLCDC ,Segment LCD Controller (Peripheral ID 32) Clock Status" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "PMC_PCSR1,PMC Peripheral Clock Status Register 1"
|
|
bitfld.long 0x00 11. " SMC1 ,Static Memory Controller 1 (Peripheral ID 43) Clock Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SRAM ,SRAM (Peripheral ID 42) Clock Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PWM ,Pulse Width Modulation (Peripheral ID 41) Clock Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SPI1 ,Serial Peripheral Interface 1 (Peripheral ID 40) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IPC1 ,Interprocessor communication 1 (Peripheral ID 39) Clock Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " UART1 ,UART 1 (Peripheral ID 38) Clock Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PIOC ,Parallel I/O Controller C (Peripheral ID 37) Clock Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " AES ,Advanced Enhanced Standard (Peripheral ID 36) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPKCC ,Classical Public Key Cryptography Controller (Peripheral ID 35) Clock Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ICM ,Integrity Check Module" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TRNG ,True Random Generator (Peripheral ID 33) Clock Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SLCDC ,Segment LCD Controller (Peripheral ID 32) Clock Status" "Disabled,Enabled"
|
|
endif
|
|
if ((d.l(ad:0x400E0400+0xE4)&0x01)==0x00)&&(((d.l(ad:0x400E0400+0x110))&0x808080)==0x808080)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "PMC_OCR,PMC Oscillator Calibration Register"
|
|
bitfld.long 0x00 23. " SEL12 ,RC Oscillator Calibration bits for 12 MHz" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CAL12 ,Selection of RC Oscillator Calibration bits for 12 MHz"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SEL8 ,RC Oscillator Calibration bits for 8 MHz" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CAL8 ,Selection of RC Oscillator Calibration bits for 8 MHz"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SEL4 ,RC Oscillator Calibration bits for 4 MHz" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CAL4 ,Selection of RC Oscillator Calibration bits for 4 MHz"
|
|
elif ((d.l(ad:0x400E0400+0xE4)&0x01)==0x00)&&(((d.l(ad:0x400E0400+0x110))&0x808080)==0x808000)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "PMC_OCR,PMC Oscillator Calibration Register"
|
|
bitfld.long 0x00 23. " SEL12 ,RC Oscillator Calibration bits for 12 MHz" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CAL12 ,Selection of RC Oscillator Calibration bits for 12 MHz"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SEL8 ,RC Oscillator Calibration bits for 8 MHz" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CAL8 ,Selection of RC Oscillator Calibration bits for 8 MHz"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SEL4 ,RC Oscillator Calibration bits for 4 MHz" "Disabled,Enabled"
|
|
elif ((d.l(ad:0x400E0400+0xE4)&0x01)==0x00)&&(((d.l(ad:0x400E0400+0x110))&0x808080)==0x800080)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "PMC_OCR,PMC Oscillator Calibration Register"
|
|
bitfld.long 0x00 23. " SEL12 ,RC Oscillator Calibration bits for 12 MHz" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CAL12 ,Selection of RC Oscillator Calibration bits for 12 MHz"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SEL8 ,RC Oscillator Calibration bits for 8 MHz" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SEL4 ,RC Oscillator Calibration bits for 4 MHz" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CAL4 ,Selection of RC Oscillator Calibration bits for 4 MHz"
|
|
elif ((d.l(ad:0x400E0400+0xE4)&0x01)==0x00)&&(((d.l(ad:0x400E0400+0x110))&0x808080)==0x800000)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "PMC_OCR,PMC Oscillator Calibration Register"
|
|
bitfld.long 0x00 23. " SEL12 ,RC Oscillator Calibration bits for 12 MHz" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CAL12 ,Selection of RC Oscillator Calibration bits for 12 MHz"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SEL8 ,RC Oscillator Calibration bits for 8 MHz" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SEL4 ,RC Oscillator Calibration bits for 4 MHz" "Disabled,Enabled"
|
|
elif ((d.l(ad:0x400E0400+0xE4)&0x01)==0x00)&&(((d.l(ad:0x400E0400+0x110))&0x808080)==0x008080)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "PMC_OCR,PMC Oscillator Calibration Register"
|
|
bitfld.long 0x00 23. " SEL12 ,RC Oscillator Calibration bits for 12 MHz" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SEL8 ,RC Oscillator Calibration bits for 8 MHz" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CAL8 ,Selection of RC Oscillator Calibration bits for 8 MHz"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SEL4 ,RC Oscillator Calibration bits for 4 MHz" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CAL4 ,Selection of RC Oscillator Calibration bits for 4 MHz"
|
|
elif ((d.l(ad:0x400E0400+0xE4)&0x01)==0x00)&&(((d.l(ad:0x400E0400+0x110))&0x808080)==0x008000)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "PMC_OCR,PMC Oscillator Calibration Register"
|
|
bitfld.long 0x00 23. " SEL12 ,RC Oscillator Calibration bits for 12 MHz" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SEL8 ,RC Oscillator Calibration bits for 8 MHz" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CAL8 ,Selection of RC Oscillator Calibration bits for 8 MHz"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SEL4 ,RC Oscillator Calibration bits for 4 MHz" "Disabled,Enabled"
|
|
elif ((d.l(ad:0x400E0400+0xE4)&0x01)==0x00)&&(((d.l(ad:0x400E0400+0x110))&0x808080)==0x000080)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "PMC_OCR,PMC Oscillator Calibration Register"
|
|
bitfld.long 0x00 23. " SEL12 ,RC Oscillator Calibration bits for 12 MHz" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SEL8 ,RC Oscillator Calibration bits for 8 MHz" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SEL4 ,RC Oscillator Calibration bits for 4 MHz" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CAL4 ,Selection of RC Oscillator Calibration bits for 4 MHz"
|
|
elif ((d.l(ad:0x400E0400+0xE4)&0x01)==0x00)&&(((d.l(ad:0x400E0400+0x110))&0x808080)==0x000000)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "PMC_OCR,PMC Oscillator Calibration Register"
|
|
bitfld.long 0x00 23. " SEL12 ,RC Oscillator Calibration bits for 12 MHz" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SEL8 ,RC Oscillator Calibration bits for 8 MHz" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SEL4 ,RC Oscillator Calibration bits for 4 MHz" "Disabled,Enabled"
|
|
elif ((d.l(ad:0x400E0400+0xE4)&0x01)==0x00)&&(((d.l(ad:0x400E0400+0x110))&0x808080)==0x808080)
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "PMC_OCR,PMC Oscillator Calibration Register"
|
|
bitfld.long 0x00 23. " SEL12 ,RC Oscillator Calibration bits for 12 MHz" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CAL12 ,Selection of RC Oscillator Calibration bits for 12 MHz"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SEL8 ,RC Oscillator Calibration bits for 8 MHz" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CAL8 ,Selection of RC Oscillator Calibration bits for 8 MHz"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SEL4 ,RC Oscillator Calibration bits for 4 MHz" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CAL4 ,Selection of RC Oscillator Calibration bits for 4 MHz"
|
|
elif ((d.l(ad:0x400E0400+0xE4)&0x01)==0x01)&&(((d.l(ad:0x400E0400+0x110))&0x808080)==0x808000)
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "PMC_OCR,PMC Oscillator Calibration Register"
|
|
bitfld.long 0x00 23. " SEL12 ,RC Oscillator Calibration bits for 12 MHz" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CAL12 ,Selection of RC Oscillator Calibration bits for 12 MHz"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SEL8 ,RC Oscillator Calibration bits for 8 MHz" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CAL8 ,Selection of RC Oscillator Calibration bits for 8 MHz"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SEL4 ,RC Oscillator Calibration bits for 4 MHz" "Disabled,Enabled"
|
|
elif ((d.l(ad:0x400E0400+0xE4)&0x01)==0x01)&&(((d.l(ad:0x400E0400+0x110))&0x808080)==0x800080)
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "PMC_OCR,PMC Oscillator Calibration Register"
|
|
bitfld.long 0x00 23. " SEL12 ,RC Oscillator Calibration bits for 12 MHz" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CAL12 ,Selection of RC Oscillator Calibration bits for 12 MHz"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SEL8 ,RC Oscillator Calibration bits for 8 MHz" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SEL4 ,RC Oscillator Calibration bits for 4 MHz" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CAL4 ,Selection of RC Oscillator Calibration bits for 4 MHz"
|
|
elif ((d.l(ad:0x400E0400+0xE4)&0x01)==0x01)&&(((d.l(ad:0x400E0400+0x110))&0x808080)==0x800000)
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "PMC_OCR,PMC Oscillator Calibration Register"
|
|
bitfld.long 0x00 23. " SEL12 ,RC Oscillator Calibration bits for 12 MHz" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CAL12 ,Selection of RC Oscillator Calibration bits for 12 MHz"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SEL8 ,RC Oscillator Calibration bits for 8 MHz" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SEL4 ,RC Oscillator Calibration bits for 4 MHz" "Disabled,Enabled"
|
|
elif ((d.l(ad:0x400E0400+0xE4)&0x01)==0x01)&&(((d.l(ad:0x400E0400+0x110))&0x808080)==0x008080)
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "PMC_OCR,PMC Oscillator Calibration Register"
|
|
bitfld.long 0x00 23. " SEL12 ,RC Oscillator Calibration bits for 12 MHz" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SEL8 ,RC Oscillator Calibration bits for 8 MHz" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CAL8 ,Selection of RC Oscillator Calibration bits for 8 MHz"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SEL4 ,RC Oscillator Calibration bits for 4 MHz" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CAL4 ,Selection of RC Oscillator Calibration bits for 4 MHz"
|
|
elif ((d.l(ad:0x400E0400+0xE4)&0x01)==0x01)&&(((d.l(ad:0x400E0400+0x110))&0x808080)==0x008000)
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "PMC_OCR,PMC Oscillator Calibration Register"
|
|
bitfld.long 0x00 23. " SEL12 ,RC Oscillator Calibration bits for 12 MHz" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SEL8 ,RC Oscillator Calibration bits for 8 MHz" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CAL8 ,Selection of RC Oscillator Calibration bits for 8 MHz"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SEL4 ,RC Oscillator Calibration bits for 4 MHz" "Disabled,Enabled"
|
|
elif ((d.l(ad:0x400E0400+0xE4)&0x01)==0x01)&&(((d.l(ad:0x400E0400+0x110))&0x808080)==0x000080)
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "PMC_OCR,PMC Oscillator Calibration Register"
|
|
bitfld.long 0x00 23. " SEL12 ,RC Oscillator Calibration bits for 12 MHz" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SEL8 ,RC Oscillator Calibration bits for 8 MHz" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SEL4 ,RC Oscillator Calibration bits for 4 MHz" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CAL4 ,Selection of RC Oscillator Calibration bits for 4 MHz"
|
|
else
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "PMC_OCR,PMC Oscillator Calibration Register"
|
|
bitfld.long 0x00 23. " SEL12 ,RC Oscillator Calibration bits for 12 MHz" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SEL8 ,RC Oscillator Calibration bits for 8 MHz" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SEL4 ,RC Oscillator Calibration bits for 4 MHz" "Disabled,Enabled"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "CHIPID (Chip Identifier)"
|
|
base ad:0x400E0740
|
|
width 13.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CHIPID_CIDR,Chip ID Register"
|
|
bitfld.long 0x00 31. " EXT ,Extension Flag" "Not extended,Extended"
|
|
bitfld.long 0x00 28.--30. " NVPTYP ,Nonvolatile Program Memory Type" "ROM,ROMLESS,FLASH,ROM_FLASH,SRAM,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 20.--27. 1. " ARCH ,Architecture Identifier"
|
|
bitfld.long 0x00 16.--19. " SRAMSIZ ,Internal SRAM Size" "48K,192K,2K,6K,24K,4K,80K,160K,8K,16K,32K,64K,128K,256K,96K,512K"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " NVPSIZ2 ,Second Nonvolatile Program Memory Size " "NONE,8K,16K,32K,,64K,,128K,,256K,512K,,1024K,,2048K,"
|
|
bitfld.long 0x00 8.--11. " NVPSIZ , Nonvolatile Program Memory Size" "NONE,8K,16K,32K,,64K,,128K,,256K,512K,,1024K,,2048K,"
|
|
textline " "
|
|
bitfld.long 0x00 5.--7. " EPROC , Embedded Processor" ",ARM946ES,ARM7TDMI,Cortex-M3,ARM920T,ARM926EJS,Cortex-A5,Cortex-M4"
|
|
bitfld.long 0x00 0.--4. " VERSION , Current Version of the Device" "0,1,2,3,%d..."
|
|
if (((d.l(ad:0x400E0740))&0x80000000)==0x80000000)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CHIPID_EXID,Chip ID Extension Register"
|
|
else
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "CHIPID_EXID,Chip ID Extension Register"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree.open "PIO (Parallel Input/Output)"
|
|
sif ((cpu()=="ATSAM4C16C-CORE0")||(cpu()=="ATSAM4C8C-CORE0")||(cpu()=="ATSAM4CMP16C-CORE0")||(cpu()=="ATSAM4CMP8C-CORE0")||(cpu()=="ATSAM4CMS8C-CORE0")||(cpu()=="ATSAM4CMS16C-CORE0"))
|
|
tree "PIO A"
|
|
base ad:0x400E0E00
|
|
width 19.
|
|
wgroup.long 0x00++0x07
|
|
line.long 0x00 "PIO_PER,PIO Enable Register"
|
|
bitfld.long 0x00 31. " P31 ,PIO31 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " P30 ,PIO30 Enable" "No effect,Enable"
|
|
textline " "
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
bitfld.long 0x00 29. " P29 ,PIO29 Enable" "No effect,Enable"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " P28 ,PIO28 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 27. " P27 ,PIO27 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 26. " P26 ,PIO26 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 25. " P25 ,PIO25 Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,PIO24 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 23. " P23 ,PIO23 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 22. " P22 ,PIO22 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 21. " P21 ,PIO21 Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,PIO20 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 19. " P19 ,PIO19 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 18. " P18 ,PIO18 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 17. " P17 ,PIO17 Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,PIO16 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 15. " P15 ,PIO15 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 14. " P14 ,PIO14 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 13. " P13 ,PIO13 Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,PIO12 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 11. " P11 ,PIO11 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 10. " P10 ,PIO10 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 9. " P9 ,PIO9 Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,PIO8 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 7. " P7 ,PIO7 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 6. " P6 ,PIO6 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 5. " P5 ,PIO5 Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,PIO4 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " P3 ,PIO3 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 2. " P2 ,PIO2 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " P1 ,PIO1 Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,PIO0 Enable" "No effect,Enable"
|
|
textline " "
|
|
line.long 0x04 "PIO_PDR,PIO Disable Register"
|
|
bitfld.long 0x04 31. " P31 ,PIO31 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 30. " P30 ,PIO30 Disable" "No effect,Disable"
|
|
textline " "
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
bitfld.long 0x04 29. " P29 ,PIO29 Disable" "No effect,Disable"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 28. " P28 ,PIO28 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 27. " P27 ,PIO27 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 26. " P26 ,PIO26 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 25. " P25 ,PIO25 Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x04 24. " P24 ,PIO24 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 23. " P23 ,PIO23 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 22. " P22 ,PIO22 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 21. " P21 ,PIO21 Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x04 20. " P20 ,PIO20 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 19. " P19 ,PIO19 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 18. " P18 ,PIO18 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 17. " P17 ,PIO17 Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x04 16. " P16 ,PIO16 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 15. " P15 ,PIO15 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 14. " P14 ,PIO14 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 13. " P13 ,PIO13 Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x04 12. " P12 ,PIO12 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 11. " P11 ,PIO11 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 10. " P10 ,PIO10 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 9. " P9 ,PIO9 Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x04 8. " P8 ,PIO8 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 7. " P7 ,PIO7 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 6. " P6 ,PIO6 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 5. " P5 ,PIO5 Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x04 4. " P4 ,PIO4 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 3. " P3 ,PIO3 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 2. " P2 ,PIO2 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 1. " P1 ,PIO1 Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x04 0. " P0 ,PIO0 Disable" "No effect,Disable"
|
|
textline " "
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "PIO_PSR,PIO Status Register"
|
|
bitfld.long 0x00 31. " P31 ,PIO31 Status" "Inactive,Active"
|
|
bitfld.long 0x00 30. " P30 ,PIO30 Status" "Inactive,Active"
|
|
textline " "
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
bitfld.long 0x00 29. " P29 ,PIO29 Status" "Inactive,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " P28 ,PIO28 Status" "Inactive,Active"
|
|
bitfld.long 0x00 27. " P27 ,PIO27 Status" "Inactive,Active"
|
|
bitfld.long 0x00 26. " P26 ,PIO26 Status" "Inactive,Active"
|
|
bitfld.long 0x00 25. " P25 ,PIO25 Status" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,PIO24 Status" "Inactive,Active"
|
|
bitfld.long 0x00 23. " P23 ,PIO23 Status" "Inactive,Active"
|
|
bitfld.long 0x00 22. " P22 ,PIO22 Status" "Inactive,Active"
|
|
bitfld.long 0x00 21. " P21 ,PIO21 Status" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,PIO20 Status" "Inactive,Active"
|
|
bitfld.long 0x00 19. " P19 ,PIO19 Status" "Inactive,Active"
|
|
bitfld.long 0x00 18. " P18 ,PIO18 Status" "Inactive,Active"
|
|
bitfld.long 0x00 17. " P17 ,PIO17 Status" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,PIO16 Status" "Inactive,Active"
|
|
bitfld.long 0x00 15. " P15 ,PIO15 Status" "Inactive,Active"
|
|
bitfld.long 0x00 14. " P14 ,PIO14 Status" "Inactive,Active"
|
|
bitfld.long 0x00 13. " P13 ,PIO13 Status" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,PIO12 Status" "Inactive,Active"
|
|
bitfld.long 0x00 11. " P11 ,PIO11 Status" "Inactive,Active"
|
|
bitfld.long 0x00 10. " P10 ,PIO10 Status" "Inactive,Active"
|
|
bitfld.long 0x00 9. " P9 ,PIO9 Status" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,PIO8 Status" "Inactive,Active"
|
|
bitfld.long 0x00 7. " P7 ,PIO7 Status" "Inactive,Active"
|
|
bitfld.long 0x00 6. " P6 ,PIO6 Status" "Inactive,Active"
|
|
bitfld.long 0x00 5. " P5 ,PIO5 Status" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,PIO4 Status" "Inactive,Active"
|
|
bitfld.long 0x00 3. " P3 ,PIO3 Status" "Inactive,Active"
|
|
bitfld.long 0x00 2. " P2 ,PIO2 Status" "Inactive,Active"
|
|
bitfld.long 0x00 1. " P1 ,PIO1 Status" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,PIO0 Status" "Inactive,Active"
|
|
textline " "
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PIO_OSR_set/clr,PIO Output Status Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31 ,PIO31 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30 ,PIO30 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29 ,PIO29 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28 ,PIO28 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27 ,PIO27 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26 ,PIO26 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25 ,PIO25 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24 ,PIO24 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23 ,PIO23 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22 ,PIO22 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21 ,PIO21 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20 ,PIO20 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19 ,PIO19 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18 ,PIO18 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17 ,PIO17 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16 ,PIO16 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15 ,PIO15 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14 ,PIO14 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13 ,PIO13 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12 ,PIO12 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11 ,PIO11 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10 ,PIO10 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9 ,PIO9 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8 ,PIO8 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7 ,PIO7 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6 ,PIO6 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5 ,PIO5 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4 ,PIO4 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3 ,PIO3 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2 ,PIO2 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1 ,PIO1 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0 ,PIO0 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PIO_IFSR_set/clr,PIO Input Filter Status Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31 ,PIO31 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30 ,PIO30 Input Filter Status" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29 ,PIO29 Input Filter Status" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28 ,PIO28 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27 ,PIO27 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26 ,PIO26 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25 ,PIO25 Input Filter Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24 ,PIO24 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23 ,PIO23 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22 ,PIO22 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21 ,PIO21 Input Filter Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20 ,PIO20 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19 ,PIO19 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18 ,PIO18 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17 ,PIO17 Input Filter Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16 ,PIO16 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15 ,PIO15 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14 ,PIO14 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13 ,PIO13 Input Filter Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12 ,PIO12 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11 ,PIO11 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10 ,PIO10 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9 ,PIO9 Input Filter Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8 ,PIO8 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7 ,PIO7 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6 ,PIO6 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5 ,PIO5 Input Filter Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4 ,PIO4 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3 ,PIO3 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2 ,PIO2 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1 ,PIO1 Input Filter Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0 ,PIO0 Input Filter Status" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PIO_PDSR_set/clr,PIO Pin Data Status Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31 ,PIO31 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30 ,PIO30 Output Data Status" "0,1"
|
|
textline " "
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29 ,PIO29 Output Data Status" "0,1"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28 ,PIO28 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27 ,PIO27 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26 ,PIO26 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25 ,PIO25 Output Data Status" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24 ,PIO24 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23 ,PIO23 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22 ,PIO22 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21 ,PIO21 Output Data Status" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20 ,PIO20 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19 ,PIO19 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18 ,PIO18 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17 ,PIO17 Output Data Status" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16 ,PIO16 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15 ,PIO15 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14 ,PIO14 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13 ,PIO13 Output Data Status" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12 ,PIO12 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11 ,PIO11 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10 ,PIO10 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9 ,PIO9 Output Data Status" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8 ,PIO8 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7 ,PIO7 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6 ,PIO6 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5 ,PIO5 Output Data Status" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4 ,PIO4 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3 ,PIO3 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2 ,PIO2 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1 ,PIO1 Output Data Status" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0 ,PIO0 Output Data Status" "0,1"
|
|
textline " "
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "PIO_PDSR,PIO Pin Data Status Register"
|
|
bitfld.long 0x00 31. " P31 ,PIO31 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,PIO30 Pin Data Status" "0,1"
|
|
textline " "
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
bitfld.long 0x00 29. " P29 ,PIO29 Pin Data Status" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " P28 ,PIO28 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 27. " P27 ,PIO27 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,PIO26 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 25. " P25 ,PIO25 Pin Data Status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,PIO24 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 23. " P23 ,PIO23 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,PIO22 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 21. " P21 ,PIO21 Pin Data Status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,PIO20 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 19. " P19 ,PIO19 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,PIO18 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 17. " P17 ,PIO17 Pin Data Status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,PIO16 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 15. " P15 ,PIO15 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,PIO14 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 13. " P13 ,PIO13 Pin Data Status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,PIO12 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 11. " P11 ,PIO11 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,PIO10 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 9. " P9 ,PIO9 Pin Data Status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,PIO8 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 7. " P7 ,PIO7 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,PIO6 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 5. " P5 ,PIO5 Pin Data Status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,PIO4 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 3. " P3 ,PIO3 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,PIO2 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 1. " P1 ,PIO1 Pin Data Status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,PIO0 Pin Data Status" "0,1"
|
|
textline " "
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PIO_IMR_set/clr,PIO Interrupt Mask Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31 ,PIO31 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30 ,PIO30 Input Change Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29 ,PIO29 Input Change Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28 ,PIO28 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27 ,PIO27 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26 ,PIO26 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25 ,PIO25 Input Change Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24 ,PIO24 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23 ,PIO23 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22 ,PIO22 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21 ,PIO21 Input Change Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20 ,PIO20 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19 ,PIO19 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18 ,PIO18 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17 ,PIO17 Input Change Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16 ,PIO16 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15 ,PIO15 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14 ,PIO14 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13 ,PIO13 Input Change Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12 ,PIO12 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11 ,PIO11 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10 ,PIO10 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9 ,PIO9 Input Change Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8 ,PIO8 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7 ,PIO7 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6 ,PIO6 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5 ,PIO5 Input Change Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4 ,PIO4 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3 ,PIO3 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2 ,PIO2 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1 ,PIO1 Input Change Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0 ,PIO0 Input Change Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x04 "PIO_ISR,PIO Interrupt Status Register"
|
|
textfld " "
|
|
in
|
|
textline " "
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PIO_MDSR_set/clr,PIO Multi-driver Status Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31 ,PIO31 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30 ,PIO30 Multi-driver Status" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29 ,PIO29 Multi-driver Status" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28 ,PIO28 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27 ,PIO27 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26 ,PIO26 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25 ,PIO25 Multi-driver Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24 ,PIO24 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23 ,PIO23 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22 ,PIO22 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21 ,PIO21 Multi-driver Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20 ,PIO20 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19 ,PIO19 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18 ,PIO18 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17 ,PIO17 Multi-driver Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16 ,PIO16 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15 ,PIO15 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14 ,PIO14 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13 ,PIO13 Multi-driver Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12 ,PIO12 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11 ,PIO11 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10 ,PIO10 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9 ,PIO9 Multi-driver Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8 ,PIO8 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7 ,PIO7 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6 ,PIO6 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5 ,PIO5 Multi-driver Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4 ,PIO4 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3 ,PIO3 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2 ,PIO2 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1 ,PIO1 Multi-driver Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0 ,PIO0 Multi-driver Status" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PIO_PUSR_set/clr,PIO Pull-Up Status Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31 ,PIO31 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30 ,PIO30 Pull-up Status" "Enabled,Disabled"
|
|
textline " "
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29 ,PIO29 Pull-up Status" "Enabled,Disabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28 ,PIO28 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27 ,PIO27 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26 ,PIO26 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25 ,PIO25 Pull-up Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24 ,PIO24 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23 ,PIO23 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22 ,PIO22 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21 ,PIO21 Pull-up Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20 ,PIO20 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19 ,PIO19 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18 ,PIO18 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17 ,PIO17 Pull-up Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16 ,PIO16 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15 ,PIO15 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14 ,PIO14 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13 ,PIO13 Pull-up Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12 ,PIO12 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11 ,PIO11 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10 ,PIO10 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9 ,PIO9 Pull-up Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8 ,PIO8 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7 ,PIO7 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6 ,PIO6 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5 ,PIO5 Pull-up Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4 ,PIO4 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3 ,PIO3 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2 ,PIO2 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1 ,PIO1 Pull-up Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0 ,PIO0 Pull-up Status" "Enabled,Disabled"
|
|
textline " "
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "PIO_ABCDSR1,PIO Peripheral ABCD Select Register 1"
|
|
bitfld.long 0x00 31. " P31 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 30. " P30 , Peripheral Select" "A/C,B/D"
|
|
textline " "
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
bitfld.long 0x00 29. " P29 , Peripheral Select" "A/C,B/D"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " P28 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 27. " P27 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 26. " P26 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 25. " P25 , Peripheral Select" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 23. " P23 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 22. " P22 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 21. " P21 , Peripheral Select" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 19. " P19 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 18. " P18 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 17. " P17 , Peripheral Select" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 15. " P15 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 14. " P14 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 13. " P13 , Peripheral Select" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 11. " P11 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 10. " P10 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 9. " P9 , Peripheral Select" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 7. " P7 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 6. " P6 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 5. " P5 , Peripheral Select" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 3. " P3 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 2. " P2 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 1. " P1 , Peripheral Select" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 , Peripheral Select" "A/C,B/D"
|
|
textline " "
|
|
line.long 0x04 "PIO_ABCDSR2,PIO Peripheral ABCD Select Register 2"
|
|
bitfld.long 0x04 31. " P31 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 30. " P30 , Peripheral Select" "A/B,C/D"
|
|
textline " "
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
bitfld.long 0x04 29. " P29 , Peripheral Select" "A/B,C/D"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 28. " P28 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 27. " P27 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 26. " P26 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 25. " P25 , Peripheral Select" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 24. " P24 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 23. " P23 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 22. " P22 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 21. " P21 , Peripheral Select" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 20. " P20 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 19. " P19 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 18. " P18 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 17. " P17 , Peripheral Select" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 16. " P16 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 15. " P15 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 14. " P14 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 13. " P13 , Peripheral Select" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 12. " P12 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 11. " P11 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 10. " P10 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 9. " P9 , Peripheral Select" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 8. " P8 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 7. " P7 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 6. " P6 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 5. " P5 , Peripheral Select" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 4. " P4 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 3. " P3 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 2. " P2 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 1. " P1 , Peripheral Select" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 0. " P0 , Peripheral Select" "A/B,C/D"
|
|
textline " "
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PIO_IFSCSR_set/clr,PIO Input Filter Slow Clock Status Register"
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P31 ,PIO31 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " P30 ,PIO30 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
textline " "
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29 ,PIO29 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28 ,PIO28 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27 ,PIO27 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26 ,PIO26 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25 ,PIO25 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24 ,PIO24 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23 ,PIO23 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22 ,PIO22 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21 ,PIO21 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20 ,PIO20 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19 ,PIO19 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18 ,PIO18 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17 ,PIO17 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16 ,PIO16 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15 ,PIO15 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14 ,PIO14 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13 ,PIO13 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12 ,PIO12 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11 ,PIO11 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10 ,PIO10 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9 ,PIO9 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7 ,PIO7 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6 ,PIO6 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8 ,PIO8 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5 ,PIO5 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4 ,PIO4 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3 ,PIO3 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2 ,PIO2 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1 ,PIO1 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0 ,PIO0 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
textline " "
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PIO_SCDR,PIO Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow Clock Divider Selection for Debouncing"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PIO_PPDSR_set/clr,PIO Pad Pull-Down Status Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31 ,PIO31 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30 ,PIO30 Pull-down Status" "Enabled,Disabled"
|
|
textline " "
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29 ,PIO29 Pull-down Status" "Enabled,Disabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28 ,PIO28 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27 ,PIO27 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26 ,PIO26 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25 ,PIO25 Pull-down Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24 ,PIO24 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23 ,PIO23 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22 ,PIO22 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21 ,PIO21 Pull-down Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20 ,PIO20 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19 ,PIO19 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18 ,PIO18 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17 ,PIO17 Pull-down Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16 ,PIO16 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15 ,PIO15 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14 ,PIO14 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13 ,PIO13 Pull-down Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12 ,PIO12 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11 ,PIO11 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10 ,PIO10 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9 ,PIO9 Pull-down Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8 ,PIO8 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7 ,PIO7 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6 ,PIO6 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5 ,PIO5 Pull-down Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4 ,PIO4 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3 ,PIO3 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2 ,PIO2 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1 ,PIO1 Pull-down Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0 ,PIO0 Pull-down Status" "Enabled,Disabled"
|
|
textline " "
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "PIO_OWSR_set/clr,PIO Output Write Status Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31 ,PIO31 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30 ,PIO30 Output Write Status" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29 ,PIO29 Output Write Status" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28 ,PIO28 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27 ,PIO27 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26 ,PIO26 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25 ,PIO25 Output Write Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24 ,PIO24 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23 ,PIO23 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22 ,PIO22 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21 ,PIO21 Output Write Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20 ,PIO20 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19 ,PIO19 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18 ,PIO18 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17 ,PIO17 Output Write Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16 ,PIO16 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15 ,PIO15 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14 ,PIO14 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13 ,PIO13 Output Write Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12 ,PIO12 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11 ,PIO11 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10 ,PIO10 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9 ,PIO9 Output Write Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8 ,PIO8 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7 ,PIO7 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6 ,PIO6 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5 ,PIO5 Output Write Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4 ,PIO4 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3 ,PIO3 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2 ,PIO2 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1 ,PIO1 Output Write Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0 ,PIO0 Output Write Status" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "PIO_AIMMR_set/clr,PIO Additional Interrupt Modes Mask Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31 ,PIO31 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30 ,PIO30 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
textline " "
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29 ,PIO29 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28 ,PIO28 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27 ,PIO27 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26 ,PIO26 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25 ,PIO25 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24 ,PIO24 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23 ,PIO23 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22 ,PIO22 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21 ,PIO21 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20 ,PIO20 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19 ,PIO19 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18 ,PIO18 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17 ,PIO17 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16 ,PIO16 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15 ,PIO15 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14 ,PIO14 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13 ,PIO13 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12 ,PIO12 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11 ,PIO11 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10 ,PIO10 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9 ,PIO9 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8 ,PIO8 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7 ,PIO7 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6 ,PIO6 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5 ,PIO5 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4 ,PIO4 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3 ,PIO3 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2 ,PIO2 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1 ,PIO1 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0 ,PIO0 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
textline " "
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "PIO_ELSR_set/clr,PIO Edge/Level Status Register"
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P31 ,PIO31 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " P30 ,PIO30 Input Filter Slow Clock Status" "Edge,Level"
|
|
textline " "
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29 ,PIO29 Input Filter Slow Clock Status" "Edge,Level"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28 ,PIO28 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27 ,PIO27 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26 ,PIO26 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25 ,PIO25 Input Filter Slow Clock Status" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24 ,PIO24 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23 ,PIO23 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22 ,PIO22 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21 ,PIO21 Input Filter Slow Clock Status" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20 ,PIO20 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19 ,PIO19 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18 ,PIO18 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17 ,PIO17 Input Filter Slow Clock Status" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16 ,PIO16 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15 ,PIO15 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14 ,PIO14 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13 ,PIO13 Input Filter Slow Clock Status" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12 ,PIO12 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11 ,PIO11 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10 ,PIO10 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9 ,PIO9 Input Filter Slow Clock Status" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8 ,PIO8 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7 ,PIO7 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6 ,PIO6 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5 ,PIO5 Input Filter Slow Clock Status" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4 ,PIO4 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3 ,PIO3 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2 ,PIO2 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1 ,PIO1 Input Filter Slow Clock Status" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0 ,PIO0 Input Filter Slow Clock Status" "Edge,Level"
|
|
textline " "
|
|
group.long 0xD8++0X03
|
|
line.long 0x00 "PIO_FRLHSR_set/clr,PIO Fall/Rise - Low/High Status Register"
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P31 ,PIO31 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " P30 ,PIO30 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29 ,PIO29 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28 ,PIO28 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27 ,PIO27 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26 ,PIO26 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25 ,PIO25 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24 ,PIO24 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23 ,PIO23 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22 ,PIO22 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21 ,PIO21 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20 ,PIO20 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19 ,PIO19 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18 ,PIO18 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17 ,PIO17 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16 ,PIO16 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15 ,PIO15 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14 ,PIO14 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13 ,PIO13 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12 ,PIO12 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11 ,PIO11 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10 ,PIO10 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9 ,PIO9 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8 ,PIO8 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7 ,PIO7 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6 ,PIO6 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5 ,PIO5 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4 ,PIO4 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3 ,PIO3 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2 ,PIO2 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1 ,PIO1 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0 ,PIO0 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protection Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0xE8++0x03
|
|
line.long 0x00 "PIO_WPSR,PIO Write Protection Status Register"
|
|
hexmask.long.word 0x00 8.--23. 1. " WPVSRC ,Write Protection Violation Status"
|
|
rbitfld.long 0x00 0. " WPVS ,Write Protection Violation Source" "No,Yes"
|
|
textline " "
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PIO_SCHMITT,PIO Schmitt Trigger Register"
|
|
bitfld.long 0x00 31. " P31 ,PIO31 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 30. " P30 ,PIO30 Schmitt Trigger Control" "Enabled,Disabled"
|
|
textline " "
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
bitfld.long 0x00 29. " P29 ,PIO29 Schmitt Trigger Control" "Enabled,Disabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " P28 ,PIO28 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 27. " P27 ,PIO27 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 26. " P26 ,PIO26 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 25. " P25 ,PIO25 Schmitt Trigger Control" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,PIO24 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 23. " P23 ,PIO23 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 22. " P22 ,PIO22 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 21. " P21 ,PIO21 Schmitt Trigger Control" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,PIO20 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 19. " P19 ,PIO19 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 18. " P18 ,PIO18 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 17. " P17 ,PIO17 Schmitt Trigger Control" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,PIO16 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " P15 ,PIO15 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 14. " P14 ,PIO14 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 13. " P13 ,PIO13 Schmitt Trigger Control" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,PIO12 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 11. " P11 ,PIO11 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " P10 ,PIO10 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 9. " P9 ,PIO9 Schmitt Trigger Control" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,PIO8 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 7. " P7 ,PIO7 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " P6 ,PIO6 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 5. " P5 ,PIO5 Schmitt Trigger Control" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,PIO4 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 3. " P3 ,PIO3 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " P2 ,PIO2 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 1. " P1 ,PIO1 Schmitt Trigger Control" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,PIO0 Schmitt Trigger Control" "Enabled,Disabled"
|
|
textline " "
|
|
group.long 0x118++0x07
|
|
line.long 0x00 "PIO_DRIVER1,PIO I/O Drive Register 1"
|
|
bitfld.long 0x00 30.--31. " P15 ,Drive of PIO Line 15" "High,Medium,Low,"
|
|
bitfld.long 0x00 28.--29. " P14 ,Drive of PIO Line 14" "High,Medium,Low,"
|
|
bitfld.long 0x00 26.--27. " P13 ,Drive of PIO Line 13" "High,Medium,Low,"
|
|
bitfld.long 0x00 24.--25. " P12 ,Drive of PIO Line 12" "High,Medium,Low,"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " P11 ,Drive of PIO Line 11" "High,Medium,Low,"
|
|
bitfld.long 0x00 20.--21. " P10 ,Drive of PIO Line 10" "High,Medium,Low,"
|
|
bitfld.long 0x00 18.--19. " P9 ,Drive of PIO Line 9" "High,Medium,Low,"
|
|
bitfld.long 0x00 16.--17. " P8 ,Drive of PIO Line 8" "High,Medium,Low,"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " P7 ,Drive of PIO Line 7" "High,Medium,Low,"
|
|
bitfld.long 0x00 12.--13. " P6 ,Drive of PIO Line 6" "High,Medium,Low,"
|
|
bitfld.long 0x00 10.--11. " P5 ,Drive of PIO Line 5" "High,Medium,Low,"
|
|
bitfld.long 0x00 8.--9. " P4 ,Drive of PIO Line 4" "High,Medium,Low,"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " P3 ,Drive of PIO Line 3" "High,Medium,Low,"
|
|
bitfld.long 0x00 4.--5. " P2 ,Drive of PIO Line 2" "High,Medium,Low,"
|
|
bitfld.long 0x00 2.--3. " P1 ,Drive of PIO Line 1" "High,Medium,Low,"
|
|
bitfld.long 0x00 0.--1. " P0 ,Drive of PIO Line 0" "High,Medium,Low,"
|
|
textline " "
|
|
line.long 0x04 "PIO_DRIVER2,PIO I/O Drive Register 2"
|
|
bitfld.long 0x04 30.--31. " P31 ,Drive of PIO Line 31" "High,Medium,Low,"
|
|
bitfld.long 0x04 28.--29. " P30 ,Drive of PIO Line 30" "High,Medium,Low,"
|
|
textline " "
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
bitfld.long 0x04 26.--27. " P29 ,Drive of PIO Line 29" "High,Medium,Low,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 24.--25. " P28 ,Drive of PIO Line 28" "High,Medium,Low,"
|
|
bitfld.long 0x04 22.--23. " P27 ,Drive of PIO Line 27" "High,Medium,Low,"
|
|
bitfld.long 0x04 20.--21. " P26 ,Drive of PIO Line 26" "High,Medium,Low,"
|
|
bitfld.long 0x04 18.--19. " P25 ,Drive of PIO Line 25" "High,Medium,Low,"
|
|
textline " "
|
|
bitfld.long 0x04 16.--17. " P24 ,Drive of PIO Line 24" "High,Medium,Low,"
|
|
bitfld.long 0x04 14.--15. " P23 ,Drive of PIO Line 23" "High,Medium,Low,"
|
|
bitfld.long 0x04 12.--13. " P22 ,Drive of PIO Line 22" "High,Medium,Low,"
|
|
bitfld.long 0x04 10.--11. " P21 ,Drive of PIO Line 21" "High,Medium,Low,"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " P20 ,Drive of PIO Line 20" "High,Medium,Low,"
|
|
bitfld.long 0x04 6.--7. " P19 ,Drive of PIO Line 19" "High,Medium,Low,"
|
|
bitfld.long 0x04 4.--5. " P18 ,Drive of PIO Line 18" "High,Medium,Low,"
|
|
bitfld.long 0x04 2.--3. " P17 ,Drive of PIO Line 17" "High,Medium,Low,"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " P16 ,Drive of PIO Line 16" "High,Medium,Low,"
|
|
textline " "
|
|
width 0xB
|
|
tree.end
|
|
tree "PIO B"
|
|
base ad:0x400E1000
|
|
width 19.
|
|
wgroup.long 0x00++0x07
|
|
line.long 0x00 "PIO_PER,PIO Enable Register"
|
|
sif (cpu()!=("ATSAM4CMP16C-CORE0")&&cpu()!=("ATSAM4CMP16C-CORE1")&&cpu()!=("ATSAM4CMP8C-CORE0")&&cpu()!=("ATSAM4CMP8C-CORE1")&&cpu()!=("ATSAM4CMS16C-CORE0")&&cpu()!=("ATSAM4CMS16C-CORE1")&&cpu()!=("ATSAM4CMS8C-CORE0")&&cpu()!=("ATSAM4CMS8C-CORE1"))
|
|
bitfld.long 0x00 31. " P31 ,PIO31 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " P30 ,PIO30 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 29. " P29 ,PIO29 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 28. " P28 ,PIO28 Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,PIO27 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 26. " P26 ,PIO26 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 25. " P25 ,PIO25 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 24. " P24 ,PIO24 Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,PIO23 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 22. " P22 ,PIO22 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 21. " P21 ,PIO21 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 20. " P20 ,PIO20 Enable" "No effect,Enable"
|
|
else
|
|
bitfld.long 0x00 21. " P21 ,PIO21 Enable" "No effect,Enable"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,PIO19 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 18. " P18 ,PIO18 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 17. " P17 ,PIO17 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 16. " P16 ,PIO16 Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,PIO15 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 14. " P14 ,PIO14 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 13. " P13 ,PIO13 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 12. " P12 ,PIO12 Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,PIO11 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 10. " P10 ,PIO10 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 9. " P9 ,PIO9 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 8. " P8 ,PIO8 Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,PIO7 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 6. " P6 ,PIO6 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 5. " P5 ,PIO5 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 4. " P4 ,PIO4 Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,PIO3 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 2. " P2 ,PIO2 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " P1 ,PIO1 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 0. " P0 ,PIO0 Enable" "No effect,Enable"
|
|
textline " "
|
|
line.long 0x04 "PIO_PDR,PIO Disable Register"
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
bitfld.long 0x04 31. " P31 ,PIO31 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 30. " P30 ,PIO30 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 29. " P29 ,PIO29 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 28. " P28 ,PIO28 Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x04 27. " P27 ,PIO27 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 26. " P26 ,PIO26 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 25. " P25 ,PIO25 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 24. " P24 ,PIO24 Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x04 23. " P23 ,PIO23 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 22. " P22 ,PIO22 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 21. " P21 ,PIO21 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 20. " P20 ,PIO20 Disable" "No effect,Disable"
|
|
else
|
|
bitfld.long 0x04 21. " P21 ,PIO21 Disable" "No effect,Disable"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 19. " P19 ,PIO19 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 18. " P18 ,PIO18 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 17. " P17 ,PIO17 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 16. " P16 ,PIO16 Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x04 15. " P15 ,PIO15 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 14. " P14 ,PIO14 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 13. " P13 ,PIO13 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 12. " P12 ,PIO12 Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x04 11. " P11 ,PIO11 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 10. " P10 ,PIO10 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 9. " P9 ,PIO9 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 8. " P8 ,PIO8 Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x04 7. " P7 ,PIO7 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 6. " P6 ,PIO6 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 5. " P5 ,PIO5 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 4. " P4 ,PIO4 Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P3 ,PIO3 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 2. " P2 ,PIO2 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 1. " P1 ,PIO1 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 0. " P0 ,PIO0 Disable" "No effect,Disable"
|
|
textline " "
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "PIO_PSR,PIO Status Register"
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
bitfld.long 0x00 31. " P31 ,PIO31 Status" "Inactive,Active"
|
|
bitfld.long 0x00 30. " P30 ,PIO30 Status" "Inactive,Active"
|
|
bitfld.long 0x00 29. " P29 ,PIO29 Status" "Inactive,Active"
|
|
bitfld.long 0x00 28. " P28 ,PIO28 Status" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,PIO27 Status" "Inactive,Active"
|
|
bitfld.long 0x00 26. " P26 ,PIO26 Status" "Inactive,Active"
|
|
bitfld.long 0x00 25. " P25 ,PIO25 Status" "Inactive,Active"
|
|
bitfld.long 0x00 24. " P24 ,PIO24 Status" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,PIO23 Status" "Inactive,Active"
|
|
bitfld.long 0x00 22. " P22 ,PIO22 Status" "Inactive,Active"
|
|
bitfld.long 0x00 21. " P21 ,PIO21 Status" "Inactive,Active"
|
|
bitfld.long 0x00 20. " P20 ,PIO20 Status" "Inactive,Active"
|
|
else
|
|
bitfld.long 0x00 21. " P21 ,PIO21 Status" "Inactive,Active"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,PIO19 Status" "Inactive,Active"
|
|
bitfld.long 0x00 18. " P18 ,PIO18 Status" "Inactive,Active"
|
|
bitfld.long 0x00 17. " P17 ,PIO17 Status" "Inactive,Active"
|
|
bitfld.long 0x00 16. " P16 ,PIO16 Status" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,PIO15 Status" "Inactive,Active"
|
|
bitfld.long 0x00 14. " P14 ,PIO14 Status" "Inactive,Active"
|
|
bitfld.long 0x00 13. " P13 ,PIO13 Status" "Inactive,Active"
|
|
bitfld.long 0x00 12. " P12 ,PIO12 Status" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,PIO11 Status" "Inactive,Active"
|
|
bitfld.long 0x00 10. " P10 ,PIO10 Status" "Inactive,Active"
|
|
bitfld.long 0x00 9. " P9 ,PIO9 Status" "Inactive,Active"
|
|
bitfld.long 0x00 8. " P8 ,PIO8 Status" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,PIO7 Status" "Inactive,Active"
|
|
bitfld.long 0x00 6. " P6 ,PIO6 Status" "Inactive,Active"
|
|
bitfld.long 0x00 5. " P5 ,PIO5 Status" "Inactive,Active"
|
|
bitfld.long 0x00 4. " P4 ,PIO4 Status" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,PIO3 Status" "Inactive,Active"
|
|
bitfld.long 0x00 2. " P2 ,PIO2 Status" "Inactive,Active"
|
|
bitfld.long 0x00 1. " P1 ,PIO1 Status" "Inactive,Active"
|
|
bitfld.long 0x00 0. " P0 ,PIO0 Status" "Inactive,Active"
|
|
textline " "
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PIO_OSR_set/clr,PIO Output Status Register"
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31 ,PIO31 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30 ,PIO30 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29 ,PIO29 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28 ,PIO28 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27 ,PIO27 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26 ,PIO26 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25 ,PIO25 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24 ,PIO24 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23 ,PIO23 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22 ,PIO22 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21 ,PIO21 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20 ,PIO20 Output Status" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21 ,PIO21 Output Status" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19 ,PIO19 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18 ,PIO18 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17 ,PIO17 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16 ,PIO16 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15 ,PIO15 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14 ,PIO14 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13 ,PIO13 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12 ,PIO12 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11 ,PIO11 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10 ,PIO10 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9 ,PIO9 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8 ,PIO8 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7 ,PIO7 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6 ,PIO6 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5 ,PIO5 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4 ,PIO4 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3 ,PIO3 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2 ,PIO2 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1 ,PIO1 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0 ,PIO0 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PIO_IFSR_set/clr,PIO Input Filter Status Register"
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31 ,PIO31 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30 ,PIO30 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29 ,PIO29 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28 ,PIO28 Input Filter Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27 ,PIO27 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26 ,PIO26 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25 ,PIO25 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24 ,PIO24 Input Filter Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23 ,PIO23 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22 ,PIO22 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21 ,PIO21 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20 ,PIO20 Input Filter Status" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21 ,PIO21 Input Filter Status" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19 ,PIO19 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18 ,PIO18 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17 ,PIO17 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16 ,PIO16 Input Filter Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15 ,PIO15 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14 ,PIO14 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13 ,PIO13 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12 ,PIO12 Input Filter Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11 ,PIO11 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10 ,PIO10 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9 ,PIO9 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8 ,PIO8 Input Filter Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7 ,PIO7 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6 ,PIO6 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5 ,PIO5 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4 ,PIO4 Input Filter Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3 ,PIO3 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2 ,PIO2 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1 ,PIO1 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0 ,PIO0 Input Filter Status" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PIO_PDSR_set/clr,PIO Pin Data Status Register"
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31 ,PIO31 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30 ,PIO30 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29 ,PIO29 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28 ,PIO28 Output Data Status" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27 ,PIO27 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26 ,PIO26 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25 ,PIO25 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24 ,PIO24 Output Data Status" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23 ,PIO23 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22 ,PIO22 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21 ,PIO21 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20 ,PIO20 Output Data Status" "0,1"
|
|
else
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21 ,PIO21 Output Data Status" "0,1"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19 ,PIO19 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18 ,PIO18 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17 ,PIO17 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16 ,PIO16 Output Data Status" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15 ,PIO15 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14 ,PIO14 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13 ,PIO13 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12 ,PIO12 Output Data Status" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11 ,PIO11 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10 ,PIO10 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9 ,PIO9 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8 ,PIO8 Output Data Status" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7 ,PIO7 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6 ,PIO6 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5 ,PIO5 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4 ,PIO4 Output Data Status" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3 ,PIO3 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2 ,PIO2 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1 ,PIO1 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0 ,PIO0 Output Data Status" "0,1"
|
|
textline " "
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "PIO_PDSR,PIO Pin Data Status Register"
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
bitfld.long 0x00 31. " P31 ,PIO31 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,PIO30 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 29. " P29 ,PIO29 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,PIO28 Pin Data Status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,PIO27 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,PIO26 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 25. " P25 ,PIO25 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,PIO24 Pin Data Status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,PIO23 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,PIO22 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 21. " P21 ,PIO21 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,PIO20 Pin Data Status" "0,1"
|
|
else
|
|
bitfld.long 0x00 21. " P21 ,PIO21 Pin Data Status" "0,1"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,PIO19 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,PIO18 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 17. " P17 ,PIO17 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,PIO16 Pin Data Status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,PIO15 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,PIO14 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 13. " P13 ,PIO13 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,PIO12 Pin Data Status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,PIO11 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,PIO10 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 9. " P9 ,PIO9 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,PIO8 Pin Data Status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,PIO7 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,PIO6 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 5. " P5 ,PIO5 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,PIO4 Pin Data Status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,PIO3 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,PIO2 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 1. " P1 ,PIO1 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,PIO0 Pin Data Status" "0,1"
|
|
textline " "
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PIO_IMR_set/clr,PIO Interrupt Mask Register"
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31 ,PIO31 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30 ,PIO30 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29 ,PIO29 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28 ,PIO28 Input Change Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27 ,PIO27 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26 ,PIO26 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25 ,PIO25 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24 ,PIO24 Input Change Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23 ,PIO23 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22 ,PIO22 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21 ,PIO21 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20 ,PIO20 Input Change Interrupt" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21 ,PIO21 Input Change Interrupt" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19 ,PIO19 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18 ,PIO18 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17 ,PIO17 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16 ,PIO16 Input Change Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15 ,PIO15 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14 ,PIO14 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13 ,PIO13 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12 ,PIO12 Input Change Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11 ,PIO11 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10 ,PIO10 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9 ,PIO9 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8 ,PIO8 Input Change Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7 ,PIO7 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6 ,PIO6 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5 ,PIO5 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4 ,PIO4 Input Change Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3 ,PIO3 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2 ,PIO2 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1 ,PIO1 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0 ,PIO0 Input Change Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x04 "PIO_ISR,PIO Interrupt Status Register"
|
|
textfld " "
|
|
in
|
|
textline " "
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PIO_MDSR_set/clr,PIO Multi-driver Status Register"
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31 ,PIO31 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30 ,PIO30 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29 ,PIO29 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28 ,PIO28 Multi-driver Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27 ,PIO27 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26 ,PIO26 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25 ,PIO25 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24 ,PIO24 Multi-driver Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23 ,PIO23 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22 ,PIO22 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21 ,PIO21 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20 ,PIO20 Multi-driver Status" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21 ,PIO21 Multi-driver Status" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19 ,PIO19 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18 ,PIO18 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17 ,PIO17 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16 ,PIO16 Multi-driver Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15 ,PIO15 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14 ,PIO14 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13 ,PIO13 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12 ,PIO12 Multi-driver Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11 ,PIO11 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10 ,PIO10 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9 ,PIO9 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8 ,PIO8 Multi-driver Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7 ,PIO7 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6 ,PIO6 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5 ,PIO5 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4 ,PIO4 Multi-driver Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3 ,PIO3 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2 ,PIO2 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1 ,PIO1 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0 ,PIO0 Multi-driver Status" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PIO_PUSR_set/clr,PIO Pull-Up Status Register"
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31 ,PIO31 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30 ,PIO30 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29 ,PIO29 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28 ,PIO28 Pull-up Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27 ,PIO27 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26 ,PIO26 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25 ,PIO25 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24 ,PIO24 Pull-up Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23 ,PIO23 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22 ,PIO22 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21 ,PIO21 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20 ,PIO20 Pull-up Status" "Enabled,Disabled"
|
|
else
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21 ,PIO21 Pull-up Status" "Enabled,Disabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19 ,PIO19 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18 ,PIO18 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17 ,PIO17 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16 ,PIO16 Pull-up Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15 ,PIO15 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14 ,PIO14 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13 ,PIO13 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12 ,PIO12 Pull-up Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11 ,PIO11 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10 ,PIO10 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9 ,PIO9 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8 ,PIO8 Pull-up Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7 ,PIO7 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6 ,PIO6 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5 ,PIO5 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4 ,PIO4 Pull-up Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3 ,PIO3 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2 ,PIO2 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1 ,PIO1 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0 ,PIO0 Pull-up Status" "Enabled,Disabled"
|
|
textline " "
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "PIO_ABCDSR1,PIO Peripheral ABCD Select Register 1"
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
bitfld.long 0x00 31. " P31 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 30. " P30 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 29. " P29 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 28. " P28 , Peripheral Select" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 26. " P26 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 25. " P25 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 24. " P24 , Peripheral Select" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 22. " P22 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 21. " P21 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 20. " P20 , Peripheral Select" "A/C,B/D"
|
|
else
|
|
bitfld.long 0x00 21. " P21 , Peripheral Select" "A/C,B/D"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 18. " P18 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 17. " P17 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 16. " P16 , Peripheral Select" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 14. " P14 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 13. " P13 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 12. " P12 , Peripheral Select" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 10. " P10 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 9. " P9 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 8. " P8 , Peripheral Select" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 6. " P6 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 5. " P5 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 4. " P4 , Peripheral Select" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 2. " P2 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 1. " P1 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 0. " P0 , Peripheral Select" "A/C,B/D"
|
|
textline " "
|
|
line.long 0x04 "PIO_ABCDSR2,PIO Peripheral ABCD Select Register 2"
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
bitfld.long 0x04 31. " P31 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 30. " P30 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 29. " P29 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 28. " P28 , Peripheral Select" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 27. " P27 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 26. " P26 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 25. " P25 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 24. " P24 , Peripheral Select" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 23. " P23 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 22. " P22 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 21. " P21 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 20. " P20 , Peripheral Select" "A/B,C/D"
|
|
else
|
|
bitfld.long 0x04 21. " P21 , Peripheral Select" "A/B,C/D"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 19. " P19 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 18. " P18 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 17. " P17 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 16. " P16 , Peripheral Select" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 15. " P15 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 14. " P14 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 13. " P13 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 12. " P12 , Peripheral Select" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 11. " P11 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 10. " P10 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 9. " P9 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 8. " P8 , Peripheral Select" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 7. " P7 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 6. " P6 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 5. " P5 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 4. " P4 , Peripheral Select" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P3 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 2. " P2 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 1. " P1 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 0. " P0 , Peripheral Select" "A/B,C/D"
|
|
textline " "
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PIO_IFSCSR_set/clr,PIO Input Filter Slow Clock Status Register"
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P31 ,PIO31 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " P30 ,PIO30 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29 ,PIO29 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28 ,PIO28 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27 ,PIO27 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26 ,PIO26 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25 ,PIO25 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24 ,PIO24 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23 ,PIO23 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22 ,PIO22 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21 ,PIO21 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20 ,PIO20 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
else
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21 ,PIO21 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19 ,PIO19 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18 ,PIO18 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17 ,PIO17 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16 ,PIO16 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15 ,PIO15 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14 ,PIO14 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13 ,PIO13 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12 ,PIO12 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11 ,PIO11 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10 ,PIO10 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9 ,PIO9 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8 ,PIO8 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7 ,PIO7 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6 ,PIO6 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5 ,PIO5 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4 ,PIO4 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3 ,PIO3 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2 ,PIO2 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1 ,PIO1 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0 ,PIO0 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
textline " "
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PIO_SCDR,PIO Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow Clock Divider Selection for Debouncing"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PIO_PPDSR_set/clr,PIO Pad Pull-Down Status Register"
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31 ,PIO31 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30 ,PIO30 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29 ,PIO29 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28 ,PIO28 Pull-down Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27 ,PIO27 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26 ,PIO26 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25 ,PIO25 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24 ,PIO24 Pull-down Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23 ,PIO23 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22 ,PIO22 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21 ,PIO21 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20 ,PIO20 Pull-down Status" "Enabled,Disabled"
|
|
else
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21 ,PIO21 Pull-down Status" "Enabled,Disabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19 ,PIO19 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18 ,PIO18 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17 ,PIO17 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16 ,PIO16 Pull-down Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15 ,PIO15 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14 ,PIO14 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13 ,PIO13 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12 ,PIO12 Pull-down Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11 ,PIO11 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10 ,PIO10 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9 ,PIO9 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8 ,PIO8 Pull-down Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7 ,PIO7 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6 ,PIO6 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5 ,PIO5 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4 ,PIO4 Pull-down Status" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3 ,PIO3 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2 ,PIO2 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1 ,PIO1 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0 ,PIO0 Pull-down Status" "Enabled,Disabled"
|
|
textline " "
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "PIO_OWSR_set/clr,PIO Output Write Status Register"
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31 ,PIO31 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30 ,PIO30 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29 ,PIO29 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28 ,PIO28 Output Write Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27 ,PIO27 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26 ,PIO26 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25 ,PIO25 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24 ,PIO24 Output Write Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23 ,PIO23 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22 ,PIO22 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21 ,PIO21 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20 ,PIO20 Output Write Status" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21 ,PIO21 Output Write Status" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19 ,PIO19 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18 ,PIO18 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17 ,PIO17 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16 ,PIO16 Output Write Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15 ,PIO15 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14 ,PIO14 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13 ,PIO13 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12 ,PIO12 Output Write Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11 ,PIO11 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10 ,PIO10 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9 ,PIO9 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8 ,PIO8 Output Write Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7 ,PIO7 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6 ,PIO6 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5 ,PIO5 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4 ,PIO4 Output Write Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3 ,PIO3 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2 ,PIO2 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1 ,PIO1 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0 ,PIO0 Output Write Status" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "PIO_AIMMR_set/clr,PIO Additional Interrupt Modes Mask Register"
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31 ,PIO31 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30 ,PIO30 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29 ,PIO29 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28 ,PIO28 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27 ,PIO27 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26 ,PIO26 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25 ,PIO25 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24 ,PIO24 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23 ,PIO23 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22 ,PIO22 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21 ,PIO21 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20 ,PIO20 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
else
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21 ,PIO21 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19 ,PIO19 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18 ,PIO18 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17 ,PIO17 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16 ,PIO16 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15 ,PIO15 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14 ,PIO14 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13 ,PIO13 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12 ,PIO12 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11 ,PIO11 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10 ,PIO10 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9 ,PIO9 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8 ,PIO8 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7 ,PIO7 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6 ,PIO6 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5 ,PIO5 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4 ,PIO4 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3 ,PIO3 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2 ,PIO2 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1 ,PIO1 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0 ,PIO0 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
textline " "
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "PIO_ELSR_set/clr,PIO Edge/Level Status Register"
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P31 ,PIO31 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " P30 ,PIO30 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29 ,PIO29 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28 ,PIO28 Input Filter Slow Clock Status" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27 ,PIO27 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26 ,PIO26 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25 ,PIO25 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24 ,PIO24 Input Filter Slow Clock Status" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23 ,PIO23 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22 ,PIO22 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21 ,PIO21 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20 ,PIO20 Input Filter Slow Clock Status" "Edge,Level"
|
|
else
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21 ,PIO21 Input Filter Slow Clock Status" "Edge,Level"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19 ,PIO19 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18 ,PIO18 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17 ,PIO17 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16 ,PIO16 Input Filter Slow Clock Status" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15 ,PIO15 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14 ,PIO14 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13 ,PIO13 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12 ,PIO12 Input Filter Slow Clock Status" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11 ,PIO11 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10 ,PIO10 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9 ,PIO9 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8 ,PIO8 Input Filter Slow Clock Status" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7 ,PIO7 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6 ,PIO6 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5 ,PIO5 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4 ,PIO4 Input Filter Slow Clock Status" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3 ,PIO3 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2 ,PIO2 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1 ,PIO1 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0 ,PIO0 Input Filter Slow Clock Status" "Edge,Level"
|
|
textline " "
|
|
group.long 0xD8++0X03
|
|
line.long 0x00 "PIO_FRLHSR_set/clr,PIO Fall/Rise - Low/High Status Register"
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P31 ,PIO31 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " P30 ,PIO30 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29 ,PIO29 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28 ,PIO28 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27 ,PIO27 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26 ,PIO26 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25 ,PIO25 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24 ,PIO24 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23 ,PIO23 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22 ,PIO22 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21 ,PIO21 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20 ,PIO20 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
else
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21 ,PIO21 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19 ,PIO19 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18 ,PIO18 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17 ,PIO17 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16 ,PIO16 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15 ,PIO15 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14 ,PIO14 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13 ,PIO13 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12 ,PIO12 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11 ,PIO11 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10 ,PIO10 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9 ,PIO9 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8 ,PIO8 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7 ,PIO7 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6 ,PIO6 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5 ,PIO5 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4 ,PIO4 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3 ,PIO3 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2 ,PIO2 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1 ,PIO1 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0 ,PIO0 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protection Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0xE8++0x03
|
|
line.long 0x00 "PIO_WPSR,PIO Write Protection Status Register"
|
|
hexmask.long.word 0x00 8.--23. 1. " WPVSRC ,Write Protection Violation Status"
|
|
rbitfld.long 0x00 0. " WPVS ,Write Protection Violation Source" "No,Yes"
|
|
textline " "
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PIO_SCHMITT,PIO Schmitt Trigger Register"
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
bitfld.long 0x00 31. " P31 ,PIO31 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 30. " P30 ,PIO30 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 29. " P29 ,PIO29 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 28. " P28 ,PIO28 Schmitt Trigger Control" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,PIO27 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 26. " P26 ,PIO26 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 25. " P25 ,PIO25 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 24. " P24 ,PIO24 Schmitt Trigger Control" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,PIO23 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 22. " P22 ,PIO22 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 21. " P21 ,PIO21 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " P20 ,PIO20 Schmitt Trigger Control" "Enabled,Disabled"
|
|
else
|
|
bitfld.long 0x00 21. " P21 ,PIO21 Schmitt Trigger Control" "Enabled,Disabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,PIO19 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 18. " P18 ,PIO18 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 17. " P17 ,PIO17 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 16. " P16 ,PIO16 Schmitt Trigger Control" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,PIO15 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 14. " P14 ,PIO14 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 13. " P13 ,PIO13 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 12. " P12 ,PIO12 Schmitt Trigger Control" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,PIO11 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " P10 ,PIO10 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 9. " P9 ,PIO9 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " P8 ,PIO8 Schmitt Trigger Control" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,PIO7 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " P6 ,PIO6 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 5. " P5 ,PIO5 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " P4 ,PIO4 Schmitt Trigger Control" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,PIO3 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " P2 ,PIO2 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 1. " P1 ,PIO1 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " P0 ,PIO0 Schmitt Trigger Control" "Enabled,Disabled"
|
|
textline " "
|
|
group.long 0x118++0x07
|
|
line.long 0x00 "PIO_DRIVER1,PIO I/O Drive Register 1"
|
|
bitfld.long 0x00 30.--31. " P15 ,Drive of PIO Line 15" "High,Medium,Low,"
|
|
bitfld.long 0x00 28.--29. " P14 ,Drive of PIO Line 14" "High,Medium,Low,"
|
|
bitfld.long 0x00 26.--27. " P13 ,Drive of PIO Line 13" "High,Medium,Low,"
|
|
bitfld.long 0x00 24.--25. " P12 ,Drive of PIO Line 12" "High,Medium,Low,"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " P11 ,Drive of PIO Line 11" "High,Medium,Low,"
|
|
bitfld.long 0x00 20.--21. " P10 ,Drive of PIO Line 10" "High,Medium,Low,"
|
|
bitfld.long 0x00 18.--19. " P9 ,Drive of PIO Line 9" "High,Medium,Low,"
|
|
bitfld.long 0x00 16.--17. " P8 ,Drive of PIO Line 8" "High,Medium,Low,"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " P7 ,Drive of PIO Line 7" "High,Medium,Low,"
|
|
bitfld.long 0x00 12.--13. " P6 ,Drive of PIO Line 6" "High,Medium,Low,"
|
|
bitfld.long 0x00 10.--11. " P5 ,Drive of PIO Line 5" "High,Medium,Low,"
|
|
bitfld.long 0x00 8.--9. " P4 ,Drive of PIO Line 4" "High,Medium,Low,"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " P3 ,Drive of PIO Line 3" "High,Medium,Low,"
|
|
bitfld.long 0x00 4.--5. " P2 ,Drive of PIO Line 2" "High,Medium,Low,"
|
|
bitfld.long 0x00 2.--3. " P1 ,Drive of PIO Line 1" "High,Medium,Low,"
|
|
bitfld.long 0x00 0.--1. " P0 ,Drive of PIO Line 0" "High,Medium,Low,"
|
|
textline " "
|
|
line.long 0x04 "PIO_DRIVER2,PIO I/O Drive Register 2"
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP16C-CORE1"&&cpu()!="ATSAM4CMP8C-CORE0"&&cpu()!="ATSAM4CMP8C-CORE1"&&cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE0"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
bitfld.long 0x04 30.--31. " P31 ,Drive of PIO Line 31" "High,Medium,Low,"
|
|
bitfld.long 0x04 28.--29. " P30 ,Drive of PIO Line 30" "High,Medium,Low,"
|
|
bitfld.long 0x04 26.--27. " P29 ,Drive of PIO Line 29" "High,Medium,Low,"
|
|
bitfld.long 0x04 24.--25. " P28 ,Drive of PIO Line 28" "High,Medium,Low,"
|
|
textline " "
|
|
bitfld.long 0x04 22.--23. " P27 ,Drive of PIO Line 27" "High,Medium,Low,"
|
|
bitfld.long 0x04 20.--21. " P26 ,Drive of PIO Line 26" "High,Medium,Low,"
|
|
bitfld.long 0x04 18.--19. " P25 ,Drive of PIO Line 25" "High,Medium,Low,"
|
|
bitfld.long 0x04 16.--17. " P24 ,Drive of PIO Line 24" "High,Medium,Low,"
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " P23 ,Drive of PIO Line 23" "High,Medium,Low,"
|
|
bitfld.long 0x04 12.--13. " P22 ,Drive of PIO Line 22" "High,Medium,Low,"
|
|
bitfld.long 0x04 10.--11. " P21 ,Drive of PIO Line 21" "High,Medium,Low,"
|
|
bitfld.long 0x04 8.--9. " P20 ,Drive of PIO Line 20" "High,Medium,Low,"
|
|
else
|
|
bitfld.long 0x04 10.--11. " P21 ,Drive of PIO Line 21" "High,Medium,Low,"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " P19 ,Drive of PIO Line 19" "High,Medium,Low,"
|
|
bitfld.long 0x04 4.--5. " P18 ,Drive of PIO Line 18" "High,Medium,Low,"
|
|
bitfld.long 0x04 2.--3. " P17 ,Drive of PIO Line 17" "High,Medium,Low,"
|
|
bitfld.long 0x04 0.--1. " P16 ,Drive of PIO Line 16" "High,Medium,Low,"
|
|
textline " "
|
|
width 0xB
|
|
tree.end
|
|
elif ((cpu()!="ATSAM4CMP16C-CORE1")&&(cpu()!="ATSAM4CMP8C-CORE1"))
|
|
tree "PIO C"
|
|
base ad:0x4800C000
|
|
width 19.
|
|
wgroup.long 0x00++0x07
|
|
line.long 0x00 "PIO_PER,PIO Enable Register"
|
|
bitfld.long 0x00 9. " P9 ,PIO9 Enable" "No effect,Enable"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
bitfld.long 0x00 8. " P8 ,PIO8 Enable" "No effect,Enable"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,PIO7 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 6. " P6 ,PIO6 Enable" "No effect,Enable"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,PIO5 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 4. " P4 ,PIO4 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " P3 ,PIO3 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 2. " P2 ,PIO2 Enable" "No effect,Enable"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,PIO1 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 0. " P0 ,PIO0 Enable" "No effect,Enable"
|
|
textline " "
|
|
line.long 0x04 "PIO_PDR,PIO Disable Register"
|
|
bitfld.long 0x04 9. " P9 ,PIO9 Disable" "No effect,Disable"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
bitfld.long 0x04 8. " P8 ,PIO8 Disable" "No effect,Disable"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 7. " P7 ,PIO7 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 6. " P6 ,PIO6 Disable" "No effect,Disable"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
textline " "
|
|
bitfld.long 0x04 5. " P5 ,PIO5 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 4. " P4 ,PIO4 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 3. " P3 ,PIO3 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 2. " P2 ,PIO2 Disable" "No effect,Disable"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 1. " P1 ,PIO1 Disable" "No effect,Disable"
|
|
bitfld.long 0x04 0. " P0 ,PIO0 Disable" "No effect,Disable"
|
|
textline " "
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "PIO_PSR,PIO Status Register"
|
|
bitfld.long 0x00 9. " P9 ,PIO9 Status" "Inactive,Active"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
bitfld.long 0x00 8. " P8 ,PIO8 Status" "Inactive,Active"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,PIO7 Status" "Inactive,Active"
|
|
bitfld.long 0x00 6. " P6 ,PIO6 Status" "Inactive,Active"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,PIO5 Status" "Inactive,Active"
|
|
bitfld.long 0x00 4. " P4 ,PIO4 Status" "Inactive,Active"
|
|
bitfld.long 0x00 3. " P3 ,PIO3 Status" "Inactive,Active"
|
|
bitfld.long 0x00 2. " P2 ,PIO2 Status" "Inactive,Active"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,PIO1 Status" "Inactive,Active"
|
|
bitfld.long 0x00 0. " P0 ,PIO0 Status" "Inactive,Active"
|
|
textline " "
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PIO_OSR_set/clr,PIO Output Status Register"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9 ,PIO9 Output Status" "Disabled,Enabled"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8 ,PIO8 Output Status" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7 ,PIO7 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6 ,PIO6 Output Status" "Disabled,Enabled"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5 ,PIO5 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4 ,PIO4 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3 ,PIO3 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2 ,PIO2 Output Status" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1 ,PIO1 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0 ,PIO0 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PIO_IFSR_set/clr,PIO Input Filter Status Register"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9 ,PIO9 Input Filter Status" "Disabled,Enabled"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8 ,PIO8 Input Filter Status" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7 ,PIO7 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6 ,PIO6 Input Filter Status" "Disabled,Enabled"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5 ,PIO5 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4 ,PIO4 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3 ,PIO3 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2 ,PIO2 Input Filter Status" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1 ,PIO1 Input Filter Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0 ,PIO0 Input Filter Status" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PIO_PDSR_set/clr,PIO Pin Data Status Register"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9 ,PIO9 Output Data Status" "0,1"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8 ,PIO8 Output Data Status" "0,1"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7 ,PIO7 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6 ,PIO6 Output Data Status" "0,1"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5 ,PIO5 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4 ,PIO4 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3 ,PIO3 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2 ,PIO2 Output Data Status" "0,1"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1 ,PIO1 Output Data Status" "0,1"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0 ,PIO0 Output Data Status" "0,1"
|
|
textline " "
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "PIO_PDSR,PIO Pin Data Status Register"
|
|
bitfld.long 0x00 9. " P9 ,PIO9 Pin Data Status" "0,1"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
bitfld.long 0x00 8. " P8 ,PIO8 Pin Data Status" "0,1"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,PIO7 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,PIO6 Pin Data Status" "0,1"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,PIO5 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,PIO4 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 3. " P3 ,PIO3 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,PIO2 Pin Data Status" "0,1"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,PIO1 Pin Data Status" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,PIO0 Pin Data Status" "0,1"
|
|
textline " "
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PIO_IMR_set/clr,PIO Interrupt Mask Register"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9 ,PIO9 Input Change Interrupt" "Disabled,Enabled"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8 ,PIO8 Input Change Interrupt" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7 ,PIO7 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6 ,PIO6 Input Change Interrupt" "Disabled,Enabled"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5 ,PIO5 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4 ,PIO4 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3 ,PIO3 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2 ,PIO2 Input Change Interrupt" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1 ,PIO1 Input Change Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0 ,PIO0 Input Change Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x04 "PIO_ISR,PIO Interrupt Status Register"
|
|
textfld " "
|
|
in
|
|
textline " "
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PIO_MDSR_set/clr,PIO Multi-driver Status Register"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9 ,PIO9 Multi-driver Status" "Disabled,Enabled"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8 ,PIO8 Multi-driver Status" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7 ,PIO7 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6 ,PIO6 Multi-driver Status" "Disabled,Enabled"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5 ,PIO5 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4 ,PIO4 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3 ,PIO3 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2 ,PIO2 Multi-driver Status" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1 ,PIO1 Multi-driver Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0 ,PIO0 Multi-driver Status" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PIO_PUSR_set/clr,PIO Pull-Up Status Register"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9 ,PIO9 Pull-up Status" "Enabled,Disabled"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8 ,PIO8 Pull-up Status" "Enabled,Disabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7 ,PIO7 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6 ,PIO6 Pull-up Status" "Enabled,Disabled"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5 ,PIO5 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4 ,PIO4 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3 ,PIO3 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2 ,PIO2 Pull-up Status" "Enabled,Disabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1 ,PIO1 Pull-up Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0 ,PIO0 Pull-up Status" "Enabled,Disabled"
|
|
textline " "
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "PIO_ABCDSR1,PIO Peripheral ABCD Select Register 1"
|
|
bitfld.long 0x00 9. " P9 , Peripheral Select" "A/C,B/D"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
bitfld.long 0x00 8. " P8 , Peripheral Select" "A/C,B/D"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 6. " P6 , Peripheral Select" "A/C,B/D"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 4. " P4 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 3. " P3 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 2. " P2 , Peripheral Select" "A/C,B/D"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 , Peripheral Select" "A/C,B/D"
|
|
bitfld.long 0x00 0. " P0 , Peripheral Select" "A/C,B/D"
|
|
textline " "
|
|
line.long 0x04 "PIO_ABCDSR2,PIO Peripheral ABCD Select Register 2"
|
|
bitfld.long 0x04 9. " P9 , Peripheral Select" "A/B,C/D"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
bitfld.long 0x04 8. " P8 , Peripheral Select" "A/B,C/D"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 7. " P7 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 6. " P6 , Peripheral Select" "A/B,C/D"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
textline " "
|
|
bitfld.long 0x04 5. " P5 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 4. " P4 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 3. " P3 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 2. " P2 , Peripheral Select" "A/B,C/D"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 1. " P1 , Peripheral Select" "A/B,C/D"
|
|
bitfld.long 0x04 0. " P0 , Peripheral Select" "A/B,C/D"
|
|
textline " "
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PIO_IFSCSR_set/clr,PIO Input Filter Slow Clock Status Register"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9 ,PIO9 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8 ,PIO8 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7 ,PIO7 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6 ,PIO6 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5 ,PIO5 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4 ,PIO4 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3 ,PIO3 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2 ,PIO2 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1 ,PIO1 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0 ,PIO0 Input Filter Slow Clock Status" "Glitch,Debouncing"
|
|
textline " "
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PIO_SCDR,PIO Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow Clock Divider Selection for Debouncing"
|
|
textline " "
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PIO_PPDSR_set/clr,PIO Pad Pull-Down Status Register"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9 ,PIO9 Pull-down Status" "Enabled,Disabled"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8 ,PIO8 Pull-down Status" "Enabled,Disabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7 ,PIO7 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6 ,PIO6 Pull-down Status" "Enabled,Disabled"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5 ,PIO5 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4 ,PIO4 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3 ,PIO3 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2 ,PIO2 Pull-down Status" "Enabled,Disabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1 ,PIO1 Pull-down Status" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0 ,PIO0 Pull-down Status" "Enabled,Disabled"
|
|
textline " "
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "PIO_OWSR_set/clr,PIO Output Write Status Register"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9 ,PIO9 Output Write Status" "Disabled,Enabled"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8 ,PIO8 Output Write Status" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7 ,PIO7 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6 ,PIO6 Output Write Status" "Disabled,Enabled"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5 ,PIO5 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4 ,PIO4 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3 ,PIO3 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2 ,PIO2 Output Write Status" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1 ,PIO1 Output Write Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0 ,PIO0 Output Write Status" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "PIO_AIMMR_set/clr,PIO Additional Interrupt Modes Mask Register"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9 ,PIO9 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8 ,PIO8 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7 ,PIO7 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6 ,PIO6 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5 ,PIO5 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4 ,PIO4 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3 ,PIO3 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2 ,PIO2 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1 ,PIO1 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0 ,PIO0 Additional Interrupt Modes Status" "Both-edge,ELSR/FRLHSR"
|
|
textline " "
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "PIO_ELSR_set/clr,PIO Edge/Level Status Register"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9 ,PIO9 Input Filter Slow Clock Status" "Edge,Level"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8 ,PIO8 Input Filter Slow Clock Status" "Edge,Level"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7 ,PIO7 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6 ,PIO6 Input Filter Slow Clock Status" "Edge,Level"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5 ,PIO5 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4 ,PIO4 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3 ,PIO3 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2 ,PIO2 Input Filter Slow Clock Status" "Edge,Level"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1 ,PIO1 Input Filter Slow Clock Status" "Edge,Level"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0 ,PIO0 Input Filter Slow Clock Status" "Edge,Level"
|
|
textline " "
|
|
group.long 0xD8++0X03
|
|
line.long 0x00 "PIO_FRLHSR_set/clr,PIO Fall/Rise - Low/High Status Register"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9 ,PIO9 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8 ,PIO8 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7 ,PIO7 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6 ,PIO6 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5 ,PIO5 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4 ,PIO4 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3 ,PIO3 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2 ,PIO2 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1 ,PIO1 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0 ,PIO0 Edge/Level Interrupt Source Selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protection Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0xE8++0x03
|
|
line.long 0x00 "PIO_WPSR,PIO Write Protection Status Register"
|
|
hexmask.long.word 0x00 8.--23. 1. " WPVSRC ,Write Protection Violation Status"
|
|
rbitfld.long 0x00 0. " WPVS ,Write Protection Violation Source" "No,Yes"
|
|
textline " "
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PIO_SCHMITT,PIO Schmitt Trigger Register"
|
|
bitfld.long 0x00 9. " P9 ,PIO9 Schmitt Trigger Control" "Enabled,Disabled"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
bitfld.long 0x00 8. " P8 ,PIO8 Schmitt Trigger Control" "Enabled,Disabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,PIO7 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " P6 ,PIO6 Schmitt Trigger Control" "Enabled,Disabled"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,PIO5 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " P4 ,PIO4 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 3. " P3 ,PIO3 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " P2 ,PIO2 Schmitt Trigger Control" "Enabled,Disabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,PIO1 Schmitt Trigger Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " P0 ,PIO0 Schmitt Trigger Control" "Enabled,Disabled"
|
|
textline " "
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "PIO_DRIVER1,PIO I/O Drive Register 1"
|
|
bitfld.long 0x00 18.--19. " P9 ,Drive of PIO Line 9" "High,Medium,Low,"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
bitfld.long 0x00 16.--17. " P8 ,Drive of PIO Line 8" "High,Medium,Low,"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " P7 ,Drive of PIO Line 7" "High,Medium,Low,"
|
|
bitfld.long 0x00 12.--13. " P6 ,Drive of PIO Line 6" "High,Medium,Low,"
|
|
sif (cpu()!="ATSAM4CMS16C-CORE1"&&cpu()!="ATSAM4CMS8C-CORE1")
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " P5 ,Drive of PIO Line 5" "High,Medium,Low,"
|
|
bitfld.long 0x00 8.--9. " P4 ,Drive of PIO Line 4" "High,Medium,Low,"
|
|
bitfld.long 0x00 6.--7. " P3 ,Drive of PIO Line 3" "High,Medium,Low,"
|
|
bitfld.long 0x00 4.--5. " P2 ,Drive of PIO Line 2" "High,Medium,Low,"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " P1 ,Drive of PIO Line 1" "High,Medium,Low,"
|
|
bitfld.long 0x00 0.--1. " P0 ,Drive of PIO Line 0" "High,Medium,Low,"
|
|
textline " "
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif (cpu()=="ATSAM4C16C-CORE0"||cpu()=="ATSAM4C8C-CORE0")
|
|
tree "SPI 0 (Serial Peripheral Interface 0)"
|
|
base ad:0x40008000
|
|
width 10.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SPI_CR,SPI Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enable"
|
|
if ((((d.l((ad:0x40008000+0x4)))&0x06)==0x00)&&(((d.l((ad:0x40008000+0x4)))&0x1)==0x1))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif ((((d.l((ad:0x40008000+0x4)))&0x06)==0x04)&&(((d.l((ad:0x40008000+0x4)))&0x1)==0x1))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40008000+0x4)))&0x07)==(0x02||0x07))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40008000+0x4)))&0x06)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40008000+0x4)))&0x06)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
endif
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "SPI_RDR,SPI Receive Data Register"
|
|
textfld " "
|
|
in
|
|
if (((d.l((ad:0x40008000+0x4)))&0x06)==0x02)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
elif (((d.l((ad:0x40008000+0x4)))&0x06)==0x06)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
else
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
endif
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SPI_SR,SPI Status Register"
|
|
textfld " "
|
|
in
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SPI_IMR,SPI Interrupt Mask Register"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNDES_set/clr ,Underrun Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,Transmission Registers Empty" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NSSR_set/clr ,NSS Rising Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " RXBUFF_set/clr ,Receive Buffer Full Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " ENDTX_set/clr ,End of Transmit Buffer Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDRX_set/clr ,End of Receive Buffer Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " OVRES_set/clr ,Overrun Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MODF_set/clr ,Mode Fault Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TDRE_set/clr ,SPI Transmit Data Register Empty Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RDRF_set/clr ,Receive Data Register Full Interrupt" "Disabled,Enabled"
|
|
if (((d.l(ad:0x40008000+0x30))&0x08)==0x08)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,,,,,,,"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Rise,Not rise"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Change/capture,Capture/change"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,,,,,,,"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Rise,Not rise"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not rise,Rise"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Change/capture,Capture/change"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
endif
|
|
if (((d.l(ad:0x40008000+0x34))&0x08)==0x08)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,,,,,,,"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Rise,Not rise"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Change/capture,Capture/change"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,,,,,,,"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Rise,Not rise"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not rise,Rise"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Change/capture,Capture/change"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
endif
|
|
if (((d.l(ad:0x40008000+0x38))&0x08)==0x08)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SPI_CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,,,,,,,"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Rise,Not rise"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Change/capture,Capture/change"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SPI_CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,,,,,,,"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Rise,Not rise"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not rise,Rise"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Change/capture,Capture/change"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
endif
|
|
if (((d.l(ad:0x40008000+0x3C))&0x08)==0x08)
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SPI_CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,,,,,,,"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Rise,Not rise"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Change/capture,Capture/change"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
else
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SPI_CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,,,,,,,"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Rise,Not rise"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not rise,Rise"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Change/capture,Capture/change"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
endif
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "SPI_WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,SPI Write Protection Key Password"
|
|
bitfld.long 0x00 0. " WPEN ,SPI Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "SPI_WPSR,SPI Write Protection Status Register"
|
|
textfld " "
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
elif (cpu()=="ATSAM4C16C-CORE1"||cpu()=="ATSAM4C8C-CORE1")
|
|
tree "SPI 1 (Serial Peripheral Interface 1)"
|
|
base ad:0x48000000
|
|
width 10.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SPI_CR,SPI Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enable"
|
|
if ((((d.l((ad:0x48000000+0x4)))&0x06)==0x00)&&(((d.l((ad:0x48000000+0x4)))&0x1)==0x1))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif ((((d.l((ad:0x48000000+0x4)))&0x06)==0x04)&&(((d.l((ad:0x48000000+0x4)))&0x1)==0x1))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x48000000+0x4)))&0x07)==(0x02||0x07))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x48000000+0x4)))&0x06)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x48000000+0x4)))&0x06)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
endif
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "SPI_RDR,SPI Receive Data Register"
|
|
textfld " "
|
|
in
|
|
if (((d.l((ad:0x48000000+0x4)))&0x06)==0x02)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
elif (((d.l((ad:0x48000000+0x4)))&0x06)==0x06)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
else
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
endif
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SPI_SR,SPI Status Register"
|
|
textfld " "
|
|
in
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SPI_IMR,SPI Interrupt Mask Register"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNDES_set/clr ,Underrun Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,Transmission Registers Empty" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NSSR_set/clr ,NSS Rising Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " RXBUFF_set/clr ,Receive Buffer Full Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " ENDTX_set/clr ,End of Transmit Buffer Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDRX_set/clr ,End of Receive Buffer Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " OVRES_set/clr ,Overrun Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MODF_set/clr ,Mode Fault Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TDRE_set/clr ,SPI Transmit Data Register Empty Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RDRF_set/clr ,Receive Data Register Full Interrupt" "Disabled,Enabled"
|
|
if (((d.l(ad:0x48000000+0x30))&0x08)==0x08)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,,,,,,,"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Rise,Not rise"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Change/capture,Capture/change"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,,,,,,,"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Rise,Not rise"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not rise,Rise"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Change/capture,Capture/change"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
endif
|
|
if (((d.l(ad:0x48000000+0x34))&0x08)==0x08)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,,,,,,,"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Rise,Not rise"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Change/capture,Capture/change"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,,,,,,,"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Rise,Not rise"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not rise,Rise"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Change/capture,Capture/change"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
endif
|
|
if (((d.l(ad:0x48000000+0x38))&0x08)==0x08)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SPI_CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,,,,,,,"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Rise,Not rise"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Change/capture,Capture/change"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SPI_CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,,,,,,,"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Rise,Not rise"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not rise,Rise"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Change/capture,Capture/change"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
endif
|
|
if (((d.l(ad:0x48000000+0x3C))&0x08)==0x08)
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SPI_CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,,,,,,,"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Rise,Not rise"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Change/capture,Capture/change"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
else
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SPI_CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,,,,,,,"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Rise,Not rise"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not rise,Rise"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Change/capture,Capture/change"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
endif
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "SPI_WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,SPI Write Protection Key Password"
|
|
bitfld.long 0x00 0. " WPEN ,SPI Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "SPI_WPSR,SPI Write Protection Status Register"
|
|
textfld " "
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
elif (cpu()=="ATSAM4CMP16C-CORE0"||cpu()=="ATSAM4CMP8C-CORE0"||cpu()=="ATSAM4CMS8C-CORE0"||cpu()=="ATSAM4CMS16C-CORE0")
|
|
tree "SPI (Serial Peripheral Interface)"
|
|
base ad:0x40008000
|
|
width 10.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SPI_CR,SPI Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enable"
|
|
if ((((d.l((ad:0x40008000+0x4)))&0x06)==0x00)&&(((d.l((ad:0x40008000+0x4)))&0x1)==0x1))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif ((((d.l((ad:0x40008000+0x4)))&0x06)==0x04)&&(((d.l((ad:0x40008000+0x4)))&0x1)==0x1))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40008000+0x4)))&0x07)==(0x02||0x07))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40008000+0x4)))&0x06)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40008000+0x4)))&0x06)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
endif
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "SPI_RDR,SPI Receive Data Register"
|
|
textfld " "
|
|
in
|
|
if (((d.l((ad:0x40008000+0x4)))&0x06)==0x02)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
elif (((d.l((ad:0x40008000+0x4)))&0x06)==0x06)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
else
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
endif
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SPI_SR,SPI Status Register"
|
|
textfld " "
|
|
in
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SPI_IMR,SPI Interrupt Mask Register"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNDES_set/clr ,Underrun Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,Transmission Registers Empty" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NSSR_set/clr ,NSS Rising Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " RXBUFF_set/clr ,Receive Buffer Full Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " ENDTX_set/clr ,End of Transmit Buffer Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDRX_set/clr ,End of Receive Buffer Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " OVRES_set/clr ,Overrun Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MODF_set/clr ,Mode Fault Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TDRE_set/clr ,SPI Transmit Data Register Empty Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RDRF_set/clr ,Receive Data Register Full Interrupt" "Disabled,Enabled"
|
|
if (((d.l(ad:0x40008000+0x30))&0x08)==0x08)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,,,,,,,"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Rise,Not rise"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Change/capture,Capture/change"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,,,,,,,"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Rise,Not rise"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not rise,Rise"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Change/capture,Capture/change"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
endif
|
|
if (((d.l(ad:0x40008000+0x34))&0x08)==0x08)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,,,,,,,"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Rise,Not rise"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Change/capture,Capture/change"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,,,,,,,"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Rise,Not rise"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not rise,Rise"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Change/capture,Capture/change"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
endif
|
|
if (((d.l(ad:0x40008000+0x38))&0x08)==0x08)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SPI_CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,,,,,,,"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Rise,Not rise"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Change/capture,Capture/change"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SPI_CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,,,,,,,"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Rise,Not rise"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not rise,Rise"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Change/capture,Capture/change"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
endif
|
|
if (((d.l(ad:0x40008000+0x3C))&0x08)==0x08)
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SPI_CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,,,,,,,"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Rise,Not rise"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Change/capture,Capture/change"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
else
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SPI_CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,,,,,,,"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Rise,Not rise"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not rise,Rise"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Change/capture,Capture/change"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
endif
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "SPI_WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,SPI Write Protection Key Password"
|
|
bitfld.long 0x00 0. " WPEN ,SPI Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "SPI_WPSR,SPI Write Protection Status Register"
|
|
textfld " "
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="ATSAM4C16C-CORE0"||cpu()=="ATSAM4C8C-CORE0"||cpu()=="ATSAM4CMP16C-CORE0"||cpu()=="ATSAM4CMP8C-CORE0"||cpu()=="ATSAM4CMS8C-CORE0"||cpu()=="ATSAM4CMS16C-CORE0")
|
|
tree "TWI (Two-Wire Interface)"
|
|
tree "TWI 0"
|
|
base ad:0x40018000
|
|
width 18.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TWI_CR,TWI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 6. " QUICK ,SMBUS Quick Command" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SVDIS ,TWI Slave Mode Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 4. " SVEN ,TWI Slave Mode Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSDIS ,TWI Master Transfer Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 2. " MSEN ,TWI Master Transfer Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP Condition" "No effect,Send"
|
|
bitfld.long 0x00 0. " START ,Send a START Condition" "No effect,Send"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "No address,One-byte,Two-byte,Three-byte"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SADR ,Slave Address"
|
|
if (((d.l((ad:0x40018000+0x4)))&0x300)==0x300)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x40018000+0x4)))&0x300)==0x200)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x40018000+0x4)))&0x300)==0x100)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IADR ,Internal Address"
|
|
else
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
endif
|
|
if (((d.l(ad:0x40018000+0xE4))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
bitfld.long 0x0 16.--18. " CKDIV ,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
bitfld.long 0x0 16.--18. " CKDIV ,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
endif
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TWI_SR,TWI Status Register"
|
|
textfld " "
|
|
in
|
|
group.long 0x2c++0x03
|
|
line.long 0x0 "TWI_IMR,TWI Interrupt Mask Register"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " RXBUFF_set/clr ,Receive Buffer Full Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " ENDTX_set/clr ,End of Transmit Buffer Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " ENDRX_set/clr ,End of Receive Buffer Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " EOSACC_set/clr ,End Of Slave Access Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " SCL_WS_set/clr ,Clock Wait State Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " ABRLST_set/clr ,Arbitration Lost Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NACK_set/clr ,Not Acknowledge Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " OVRE_set/clr ,Overrun Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " GACC_set/clr ,General Call Access Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " SVACC_set/clr ,Slave Access Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " TXRDY_set/clr ,Transmit Holding Register Ready Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " RXRDY_set/clr ,Receive Holding Register Ready Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " TXCOMP_set/clr ,Transmission Completed Interrupt" "Disabled,Enabled"
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x0 "TWI_RHR,TWI Receive Holding Register"
|
|
textfld " "
|
|
in
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TWI_WPROT_MODE,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
rgroup.long 0xE8++0x03
|
|
line.long 0x00 "TWI_WPROT_STATUS,TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPVSRC ,Write Protect Violation Source"
|
|
bitfld.long 0x00 0. " WPVS ,Write Protect Violation Status" "No error,Error"
|
|
width 0xB
|
|
tree.end
|
|
tree "TWI 1"
|
|
base ad:0x4001C000
|
|
width 18.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TWI_CR,TWI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 6. " QUICK ,SMBUS Quick Command" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SVDIS ,TWI Slave Mode Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 4. " SVEN ,TWI Slave Mode Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSDIS ,TWI Master Transfer Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 2. " MSEN ,TWI Master Transfer Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP Condition" "No effect,Send"
|
|
bitfld.long 0x00 0. " START ,Send a START Condition" "No effect,Send"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "No address,One-byte,Two-byte,Three-byte"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SADR ,Slave Address"
|
|
if (((d.l((ad:0x4001C000+0x4)))&0x300)==0x300)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x4001C000+0x4)))&0x300)==0x200)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x4001C000+0x4)))&0x300)==0x100)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IADR ,Internal Address"
|
|
else
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
endif
|
|
if (((d.l(ad:0x4001C000+0xE4))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
bitfld.long 0x0 16.--18. " CKDIV ,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
bitfld.long 0x0 16.--18. " CKDIV ,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
endif
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TWI_SR,TWI Status Register"
|
|
textfld " "
|
|
in
|
|
group.long 0x2c++0x03
|
|
line.long 0x0 "TWI_IMR,TWI Interrupt Mask Register"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " RXBUFF_set/clr ,Receive Buffer Full Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " ENDTX_set/clr ,End of Transmit Buffer Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " ENDRX_set/clr ,End of Receive Buffer Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " EOSACC_set/clr ,End Of Slave Access Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " SCL_WS_set/clr ,Clock Wait State Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " ABRLST_set/clr ,Arbitration Lost Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NACK_set/clr ,Not Acknowledge Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " OVRE_set/clr ,Overrun Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " GACC_set/clr ,General Call Access Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " SVACC_set/clr ,Slave Access Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " TXRDY_set/clr ,Transmit Holding Register Ready Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " RXRDY_set/clr ,Receive Holding Register Ready Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " TXCOMP_set/clr ,Transmission Completed Interrupt" "Disabled,Enabled"
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x0 "TWI_RHR,TWI Receive Holding Register"
|
|
textfld " "
|
|
in
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TWI_WPROT_MODE,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
rgroup.long 0xE8++0x03
|
|
line.long 0x00 "TWI_WPROT_STATUS,TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPVSRC ,Write Protect Violation Source"
|
|
bitfld.long 0x00 0. " WPVS ,Write Protect Violation Status" "No error,Error"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="ATSAM4C16C-CORE0"||cpu()=="ATSAM4C8C-CORE0"||cpu()=="ATSAM4CMP16C-CORE0"||cpu()=="ATSAM4CMP8C-CORE0"||cpu()=="ATSAM4CMS8C-CORE0"||cpu()=="ATSAM4CMS16C-CORE0")
|
|
tree "UART 0 (Universal Asynchronous Receiver Transmitter 0)"
|
|
base ad:0x400E0600
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "UART_CR,UART Control Register"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "UART_MR,UART Mode Register"
|
|
bitfld.long 0x00 28.--30. " OPT_CMPTH ,Receive Path Comparator Threshold" "VDDIO/2 Volts,VDDIO/2.5 Volts,VDDIO/3.3Volts,VDDIO/5 Volts,VDDIO/10 Volts,?..."
|
|
bitfld.long 0x00 24.--26. " OPT_DUTY ,Optical Link Modulation Clock Duty Cycle" "50%,43.75%,37.5%,31.75%,25%,18.75%,12.5%,6.25%"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " OPT_CLKDIV ,Optical Link Clock Divider" "0,1,2,3,4,%d..."
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,,"
|
|
bitfld.long 0x00 4. " FILTER ,Receiver Digital Filter" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OPT_MDINV ,UART Modulated Data Inverted" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " OPT_RXINV ,UART Receive Data Inverted" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OPT_EN ,UART Optical Interface Enable" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "UART_IMR,UART Interrupt Mask Register"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,Buffer Full Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,Buffer Empty Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE_set/clr ,Parity Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME_set/clr ,Framing Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDTX_set/clr ,End of Transmit Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
rgroup.long 0x14++0x03
|
|
hide.long 0x00 "UART_SR,UART Status Register"
|
|
bitfld.long 0x00 12. " RXBUFF ,Receive Buffer Full" "Not full,Full"
|
|
bitfld.long 0x00 11. " TXBUFE ,Transmission Buffer Empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 7. " PARE ,Parity Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FRAME ,Framing Error" "No error,Error"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDTX ,End of Transmitter Transfer" "Not ended,Ended"
|
|
bitfld.long 0x00 3. " ENDRX ,End of Receiver Transfer" "Not ended,Ended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver Ready" "Not ready,Ready"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "UART_RHR,UART Receiver Holding Register"
|
|
textfld " "
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US_THR,Transmitter Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "UART_BRGR,UART Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "UART_WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protection Key"
|
|
bitfld.long 0x00 0. " WPEN , Write Protection Enable" "Disabled,Enabled"
|
|
width 11.
|
|
base ad:0x400E0600+0x100
|
|
group.long 0x00++0x1F "Peripheral DMA Controller"
|
|
line.long 0x00 "PERIPH_RPR,Receive Pointer Register"
|
|
line.long 0x04 "PERIPH_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter"
|
|
line.long 0x08 "PERIPH_TPR,Transmit Pointer Register"
|
|
line.long 0x0C "PERIPH_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter"
|
|
line.long 0x10 "PERIPH_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "PERIPH_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter"
|
|
line.long 0x18 "PERIPH_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1C "PERIPH_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " RXNCTR ,Transmit Next Counter"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PERIPH_PTCR,Transfer Control Register"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x04 9. " TX_set/clr ,Transmitter Transfer" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x04 1. " TX_set/clr ,Transmitter Transfer" "Disabled,Enabled"
|
|
width 0xB
|
|
width 0xb
|
|
tree.end
|
|
else
|
|
tree "UART 1 (Universal Asynchronous Receiver Transmitter 1)"
|
|
base ad:0x48004000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "UART_CR,UART Control Register"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "UART_MR,UART Mode Register"
|
|
bitfld.long 0x00 28.--30. " OPT_CMPTH ,Receive Path Comparator Threshold" "VDDIO/2 Volts,VDDIO/2.5 Volts,VDDIO/3.3Volts,VDDIO/5 Volts,VDDIO/10 Volts,?..."
|
|
bitfld.long 0x00 24.--26. " OPT_DUTY ,Optical Link Modulation Clock Duty Cycle" "50%,43.75%,37.5%,31.75%,25%,18.75%,12.5%,6.25%"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " OPT_CLKDIV ,Optical Link Clock Divider" "0,1,2,3,4,%d..."
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,,"
|
|
bitfld.long 0x00 4. " FILTER ,Receiver Digital Filter" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OPT_MDINV ,UART Modulated Data Inverted" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " OPT_RXINV ,UART Receive Data Inverted" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OPT_EN ,UART Optical Interface Enable" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "UART_IMR,UART Interrupt Mask Register"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,Buffer Full Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,Buffer Empty Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE_set/clr ,Parity Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME_set/clr ,Framing Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDTX_set/clr ,End of Transmit Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
rgroup.long 0x14++0x03
|
|
hide.long 0x00 "UART_SR,UART Status Register"
|
|
bitfld.long 0x00 12. " RXBUFF ,Receive Buffer Full" "Not full,Full"
|
|
bitfld.long 0x00 11. " TXBUFE ,Transmission Buffer Empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 7. " PARE ,Parity Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FRAME ,Framing Error" "No error,Error"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDTX ,End of Transmitter Transfer" "Not ended,Ended"
|
|
bitfld.long 0x00 3. " ENDRX ,End of Receiver Transfer" "Not ended,Ended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver Ready" "Not ready,Ready"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "UART_RHR,UART Receiver Holding Register"
|
|
textfld " "
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US_THR,Transmitter Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "UART_BRGR,UART Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "UART_WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protection Key"
|
|
bitfld.long 0x00 0. " WPEN , Write Protection Enable" "Disabled,Enabled"
|
|
width 11.
|
|
base ad:0x48004000+0x100
|
|
group.long 0x00++0x1F "Peripheral DMA Controller"
|
|
line.long 0x00 "PERIPH_RPR,Receive Pointer Register"
|
|
line.long 0x04 "PERIPH_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter"
|
|
line.long 0x08 "PERIPH_TPR,Transmit Pointer Register"
|
|
line.long 0x0C "PERIPH_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter"
|
|
line.long 0x10 "PERIPH_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "PERIPH_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter"
|
|
line.long 0x18 "PERIPH_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1C "PERIPH_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " RXNCTR ,Transmit Next Counter"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PERIPH_PTCR,Transfer Control Register"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x04 9. " TX_set/clr ,Transmitter Transfer" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x04 1. " TX_set/clr ,Transmitter Transfer" "Disabled,Enabled"
|
|
width 0xB
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="ATSAM4C16C-CORE0"||cpu()=="ATSAM4C8C-CORE0"||cpu()=="ATSAM4CMP16C-CORE0"||cpu()=="ATSAM4CMP8C-CORE0"||cpu()=="ATSAM4CMS8C-CORE0"||cpu()=="ATSAM4CMS16C-CORE0")
|
|
tree.open "USART (Universal Synchronous Asynchronous Receiver Transmitter)"
|
|
tree "USART 0"
|
|
base ad:0x40024000
|
|
width 10.
|
|
if (((d.l(ad:0x40024000+0x4))&0x0F)==(0x0E||0x0F))
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select" "No effect,Force 0"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif (((d.l(ad:0x40024000+0x4))&0x0F)==(0x04||0x06))
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,Disable"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,Disable"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
if ((d.l((ad:0x40024000+0x04))&0x0f)==(0x0e||0x0f))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-low,Inactive-high"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SLK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
elif (((d.l(ad:0x40024000+0x04))&0x10F)==0x104)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "CMD/DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,,2 bits,"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (((d.l(ad:0x40024000+0x04))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "CMD/DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,,2 bits,"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "CMD/DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bit,2 bits,"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
if (((d.l((ad:0x40024000+0x4)))&0x0F)==(0x0E||0x0F))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Enable/Mask Register"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,Buffer Full Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,Buffer Empty Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNRE_set/clr ,SPI Underrun Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDTX_set/clr ,End of Transmit Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Enable/Mask Register"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " MANE_set/clr ,Manchester Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " NACK_set/clr ,Non Acknowledge Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,Buffer Full Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,Buffer Empty Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " ITER_set/clr ,Max number of Repetitions Reached Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " TIMEOUT_set/clr ,Time-out Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE_set/clr ,Parity Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME_set/clr ,Framing Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDTX_set/clr ,End of Transmit Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " RXBRK_set/clr ,Receiver Break Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x0 "US_CSR,Channel Status Register"
|
|
textfld " "
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "US_RHR,Receiver Holding Register"
|
|
textfld " "
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US_THR,Transmitter Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20--0x2b
|
|
line.long 0x00 "US_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,1/4,3/8,1/2,5/8,3/4,7/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US_RTOR,Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US_TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US_FIDI,FI DI Ratio Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
if (((d.l((ad:0x40024000+0x4)))&0x0F)==(0x04||0x06))
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "US_NER,Number of Errors Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NB_ERRORS ,Number of Errors"
|
|
else
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US_NER,Number of Errors Register"
|
|
endif
|
|
if (((d.l((ad:0x40024000+0x4)))&0x0F)==(0x08))
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
else
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
endif
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern Detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "US_WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "US_WPSR,USART Write Protect Status Register"
|
|
textfld " "
|
|
in
|
|
width 11.
|
|
base ad:0x40024000+0x100
|
|
group.long 0x00++0x1F "Peripheral DMA Controller"
|
|
line.long 0x00 "PERIPH_RPR,Receive Pointer Register"
|
|
line.long 0x04 "PERIPH_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter"
|
|
line.long 0x08 "PERIPH_TPR,Transmit Pointer Register"
|
|
line.long 0x0C "PERIPH_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter"
|
|
line.long 0x10 "PERIPH_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "PERIPH_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter"
|
|
line.long 0x18 "PERIPH_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1C "PERIPH_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " RXNCTR ,Transmit Next Counter"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PERIPH_PTCR,Transfer Control Register"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x04 9. " TX_set/clr ,Transmitter Transfer" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x04 1. " TX_set/clr ,Transmitter Transfer" "Disabled,Enabled"
|
|
width 0xB
|
|
width 0xB
|
|
tree.end
|
|
tree "USART 1"
|
|
base ad:0x40028000
|
|
width 10.
|
|
if (((d.l(ad:0x40028000+0x4))&0x0F)==(0x0E||0x0F))
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select" "No effect,Force 0"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif (((d.l(ad:0x40028000+0x4))&0x0F)==(0x04||0x06))
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,Disable"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,Disable"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
if ((d.l((ad:0x40028000+0x04))&0x0f)==(0x0e||0x0f))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-low,Inactive-high"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SLK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
elif (((d.l(ad:0x40028000+0x04))&0x10F)==0x104)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "CMD/DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,,2 bits,"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (((d.l(ad:0x40028000+0x04))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "CMD/DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,,2 bits,"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "CMD/DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bit,2 bits,"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
if (((d.l((ad:0x40028000+0x4)))&0x0F)==(0x0E||0x0F))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Enable/Mask Register"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,Buffer Full Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,Buffer Empty Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNRE_set/clr ,SPI Underrun Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDTX_set/clr ,End of Transmit Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Enable/Mask Register"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " MANE_set/clr ,Manchester Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " NACK_set/clr ,Non Acknowledge Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,Buffer Full Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,Buffer Empty Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " ITER_set/clr ,Max number of Repetitions Reached Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " TIMEOUT_set/clr ,Time-out Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE_set/clr ,Parity Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME_set/clr ,Framing Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDTX_set/clr ,End of Transmit Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " RXBRK_set/clr ,Receiver Break Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x0 "US_CSR,Channel Status Register"
|
|
textfld " "
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "US_RHR,Receiver Holding Register"
|
|
textfld " "
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US_THR,Transmitter Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20--0x2b
|
|
line.long 0x00 "US_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,1/4,3/8,1/2,5/8,3/4,7/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US_RTOR,Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US_TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US_FIDI,FI DI Ratio Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
if (((d.l((ad:0x40028000+0x4)))&0x0F)==(0x04||0x06))
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "US_NER,Number of Errors Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NB_ERRORS ,Number of Errors"
|
|
else
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US_NER,Number of Errors Register"
|
|
endif
|
|
if (((d.l((ad:0x40028000+0x4)))&0x0F)==(0x08))
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
else
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
endif
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern Detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "US_WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "US_WPSR,USART Write Protect Status Register"
|
|
textfld " "
|
|
in
|
|
width 11.
|
|
base ad:0x40028000+0x100
|
|
group.long 0x00++0x1F "Peripheral DMA Controller"
|
|
line.long 0x00 "PERIPH_RPR,Receive Pointer Register"
|
|
line.long 0x04 "PERIPH_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter"
|
|
line.long 0x08 "PERIPH_TPR,Transmit Pointer Register"
|
|
line.long 0x0C "PERIPH_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter"
|
|
line.long 0x10 "PERIPH_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "PERIPH_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter"
|
|
line.long 0x18 "PERIPH_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1C "PERIPH_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " RXNCTR ,Transmit Next Counter"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PERIPH_PTCR,Transfer Control Register"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x04 9. " TX_set/clr ,Transmitter Transfer" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x04 1. " TX_set/clr ,Transmitter Transfer" "Disabled,Enabled"
|
|
width 0xB
|
|
width 0xB
|
|
tree.end
|
|
tree "USART 2"
|
|
base ad:0x4002C000
|
|
width 10.
|
|
if (((d.l(ad:0x4002C000+0x4))&0x0F)==(0x0E||0x0F))
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select" "No effect,Force 0"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif (((d.l(ad:0x4002C000+0x4))&0x0F)==(0x04||0x06))
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,Disable"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,Disable"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
if ((d.l((ad:0x4002C000+0x04))&0x0f)==(0x0e||0x0f))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-low,Inactive-high"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SLK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
elif (((d.l(ad:0x4002C000+0x04))&0x10F)==0x104)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "CMD/DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,,2 bits,"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (((d.l(ad:0x4002C000+0x04))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "CMD/DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,,2 bits,"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "CMD/DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bit,2 bits,"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
if (((d.l((ad:0x4002C000+0x4)))&0x0F)==(0x0E||0x0F))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Enable/Mask Register"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,Buffer Full Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,Buffer Empty Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNRE_set/clr ,SPI Underrun Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDTX_set/clr ,End of Transmit Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Enable/Mask Register"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " MANE_set/clr ,Manchester Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " NACK_set/clr ,Non Acknowledge Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,Buffer Full Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,Buffer Empty Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " ITER_set/clr ,Max number of Repetitions Reached Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " TIMEOUT_set/clr ,Time-out Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE_set/clr ,Parity Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME_set/clr ,Framing Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDTX_set/clr ,End of Transmit Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " RXBRK_set/clr ,Receiver Break Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x0 "US_CSR,Channel Status Register"
|
|
textfld " "
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "US_RHR,Receiver Holding Register"
|
|
textfld " "
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US_THR,Transmitter Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20--0x2b
|
|
line.long 0x00 "US_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,1/4,3/8,1/2,5/8,3/4,7/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US_RTOR,Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US_TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US_FIDI,FI DI Ratio Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
if (((d.l((ad:0x4002C000+0x4)))&0x0F)==(0x04||0x06))
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "US_NER,Number of Errors Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NB_ERRORS ,Number of Errors"
|
|
else
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US_NER,Number of Errors Register"
|
|
endif
|
|
if (((d.l((ad:0x4002C000+0x4)))&0x0F)==(0x08))
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
else
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
endif
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern Detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "US_WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "US_WPSR,USART Write Protect Status Register"
|
|
textfld " "
|
|
in
|
|
width 11.
|
|
base ad:0x4002C000+0x100
|
|
group.long 0x00++0x1F "Peripheral DMA Controller"
|
|
line.long 0x00 "PERIPH_RPR,Receive Pointer Register"
|
|
line.long 0x04 "PERIPH_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter"
|
|
line.long 0x08 "PERIPH_TPR,Transmit Pointer Register"
|
|
line.long 0x0C "PERIPH_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter"
|
|
line.long 0x10 "PERIPH_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "PERIPH_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter"
|
|
line.long 0x18 "PERIPH_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1C "PERIPH_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " RXNCTR ,Transmit Next Counter"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PERIPH_PTCR,Transfer Control Register"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x04 9. " TX_set/clr ,Transmitter Transfer" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x04 1. " TX_set/clr ,Transmitter Transfer" "Disabled,Enabled"
|
|
width 0xB
|
|
width 0xB
|
|
tree.end
|
|
sif ((cpu()!="ATSAM4CMP16C-CORE0")&&(cpu()!="ATSAM4CMP8C-CORE0"))
|
|
tree "USART 3"
|
|
base ad:0x40030000
|
|
width 10.
|
|
if (((d.l(ad:0x40030000+0x4))&0x0F)==(0x0E||0x0F))
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select" "No effect,Force 0"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif (((d.l(ad:0x40030000+0x4))&0x0F)==(0x04||0x06))
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,Disable"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,Disable"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
if ((d.l((ad:0x40030000+0x04))&0x0f)==(0x0e||0x0f))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-low,Inactive-high"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SLK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
elif (((d.l(ad:0x40030000+0x04))&0x10F)==0x104)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "CMD/DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,,2 bits,"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (((d.l(ad:0x40030000+0x04))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "CMD/DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,,2 bits,"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "CMD/DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bit,2 bits,"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
if (((d.l((ad:0x40030000+0x4)))&0x0F)==(0x0E||0x0F))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Enable/Mask Register"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,Buffer Full Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,Buffer Empty Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNRE_set/clr ,SPI Underrun Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDTX_set/clr ,End of Transmit Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Enable/Mask Register"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " MANE_set/clr ,Manchester Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " NACK_set/clr ,Non Acknowledge Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,Buffer Full Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,Buffer Empty Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " ITER_set/clr ,Max number of Repetitions Reached Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " TIMEOUT_set/clr ,Time-out Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE_set/clr ,Parity Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME_set/clr ,Framing Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDTX_set/clr ,End of Transmit Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " RXBRK_set/clr ,Receiver Break Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x0 "US_CSR,Channel Status Register"
|
|
textfld " "
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "US_RHR,Receiver Holding Register"
|
|
textfld " "
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US_THR,Transmitter Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20--0x2b
|
|
line.long 0x00 "US_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,1/4,3/8,1/2,5/8,3/4,7/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US_RTOR,Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US_TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US_FIDI,FI DI Ratio Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
if (((d.l((ad:0x40030000+0x4)))&0x0F)==(0x04||0x06))
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "US_NER,Number of Errors Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NB_ERRORS ,Number of Errors"
|
|
else
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US_NER,Number of Errors Register"
|
|
endif
|
|
if (((d.l((ad:0x40030000+0x4)))&0x0F)==(0x08))
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
else
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
endif
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern Detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "US_WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "US_WPSR,USART Write Protect Status Register"
|
|
textfld " "
|
|
in
|
|
width 11.
|
|
base ad:0x40030000+0x100
|
|
group.long 0x00++0x1F "Peripheral DMA Controller"
|
|
line.long 0x00 "PERIPH_RPR,Receive Pointer Register"
|
|
line.long 0x04 "PERIPH_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter"
|
|
line.long 0x08 "PERIPH_TPR,Transmit Pointer Register"
|
|
line.long 0x0C "PERIPH_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter"
|
|
line.long 0x10 "PERIPH_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "PERIPH_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter"
|
|
line.long 0x18 "PERIPH_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1C "PERIPH_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " RXNCTR ,Transmit Next Counter"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PERIPH_PTCR,Transfer Control Register"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x04 9. " TX_set/clr ,Transmitter Transfer" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x04 1. " TX_set/clr ,Transmitter Transfer" "Disabled,Enabled"
|
|
width 0xB
|
|
width 0xB
|
|
tree.end
|
|
sif ((cpu()!="ATSAM4CMS16C-CORE0")&&(cpu()!="ATSAM4CMS8C-CORE0"))
|
|
tree "USART 4"
|
|
base ad:0x40034000
|
|
width 10.
|
|
if (((d.l(ad:0x40034000+0x4))&0x0F)==(0x0E||0x0F))
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select" "No effect,Force 0"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif (((d.l(ad:0x40034000+0x4))&0x0F)==(0x04||0x06))
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,Disable"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,Disable"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
if ((d.l((ad:0x40034000+0x04))&0x0f)==(0x0e||0x0f))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-low,Inactive-high"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SLK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
elif (((d.l(ad:0x40034000+0x04))&0x10F)==0x104)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "CMD/DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,,2 bits,"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (((d.l(ad:0x40034000+0x04))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "CMD/DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,,2 bits,"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "CMD/DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bit,2 bits,"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
if (((d.l((ad:0x40034000+0x4)))&0x0F)==(0x0E||0x0F))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Enable/Mask Register"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,Buffer Full Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,Buffer Empty Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNRE_set/clr ,SPI Underrun Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDTX_set/clr ,End of Transmit Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Enable/Mask Register"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " MANE_set/clr ,Manchester Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " NACK_set/clr ,Non Acknowledge Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,Buffer Full Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,Buffer Empty Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " ITER_set/clr ,Max number of Repetitions Reached Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " TIMEOUT_set/clr ,Time-out Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE_set/clr ,Parity Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME_set/clr ,Framing Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDTX_set/clr ,End of Transmit Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " RXBRK_set/clr ,Receiver Break Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x0 "US_CSR,Channel Status Register"
|
|
textfld " "
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "US_RHR,Receiver Holding Register"
|
|
textfld " "
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US_THR,Transmitter Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20--0x2b
|
|
line.long 0x00 "US_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,1/4,3/8,1/2,5/8,3/4,7/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US_RTOR,Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US_TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US_FIDI,FI DI Ratio Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
if (((d.l((ad:0x40034000+0x4)))&0x0F)==(0x04||0x06))
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "US_NER,Number of Errors Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NB_ERRORS ,Number of Errors"
|
|
else
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US_NER,Number of Errors Register"
|
|
endif
|
|
if (((d.l((ad:0x40034000+0x4)))&0x0F)==(0x08))
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
else
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
endif
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern Detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "US_WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "US_WPSR,USART Write Protect Status Register"
|
|
textfld " "
|
|
in
|
|
width 11.
|
|
base ad:0x40034000+0x100
|
|
group.long 0x00++0x1F "Peripheral DMA Controller"
|
|
line.long 0x00 "PERIPH_RPR,Receive Pointer Register"
|
|
line.long 0x04 "PERIPH_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter"
|
|
line.long 0x08 "PERIPH_TPR,Transmit Pointer Register"
|
|
line.long 0x0C "PERIPH_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter"
|
|
line.long 0x10 "PERIPH_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "PERIPH_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter"
|
|
line.long 0x18 "PERIPH_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1C "PERIPH_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " RXNCTR ,Transmit Next Counter"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PERIPH_PTCR,Transfer Control Register"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x04 9. " TX_set/clr ,Transmitter Transfer" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x04 1. " TX_set/clr ,Transmitter Transfer" "Disabled,Enabled"
|
|
width 0xB
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="ATSAM4C16C-CORE0"||cpu()=="ATSAM4C8C-CORE0"||cpu()=="ATSAM4CMP16C-CORE0"||cpu()=="ATSAM4CMP8C-CORE0"||cpu()=="ATSAM4CMS8C-CORE0"||cpu()=="ATSAM4CMS16C-CORE0")
|
|
tree.open "TC (Timer Counter)"
|
|
tree "Block A"
|
|
base ad:0x40010000
|
|
width 0x8
|
|
wgroup.long 0xc0++0x03
|
|
line.long 0x00 "TC_BCR,TC Block Control Register"
|
|
bitfld.long 0x00 0. " SYNC , Synchro Command" "No effect,Assert"
|
|
group.long 0xc4++0x03
|
|
line.long 0x00 "TC_BMR,TC Block Mode Register"
|
|
bitfld.long 0x00 20.--25. " MAXFILT ,Maximum Filter" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
bitfld.long 0x00 19. " FILTER ,Glitch Filter - IDX/PHA/PHB input pins filter" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " IDXPHB ,Index pin is PHB pin" "TIOA1,TIOB0"
|
|
bitfld.long 0x00 16. " SWAP ,SWAP PHA and PHB" "Not swapped,Swapped"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INVIDX ,Inverted Index" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " INVB ,Inverted PHB" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INVA ,Inverted PHA" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " EDGPHA ,Edge on PHA count mode" "PHA and PHB,PHA only"
|
|
textline " "
|
|
bitfld.long 0x00 11. " QDTRANS ,Quadrature Decoding Transparent" "Full,Transparent"
|
|
bitfld.long 0x00 10. " SPEEDEN ,Speed Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " POSEN ,Position Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " QDEN ,Quadrature Decoder Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External Clock Signal 2 Selection" "TCLK2,,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External Clock Signal 1 Selection" "TCLK1,,TIOA0,TIOA2"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External Clock Signal 0 Selection" "TCLK0,,TIOA1,TIOA2"
|
|
group.long 0xd0++0x3
|
|
line.long 0x00 "TC_QIMR,TC QDEC Interrupt Mask Register"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " IDX_set/clr ,Index" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " DIRCHG_set/clr ,Direction Change" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " QERR_set/clr ,Quadrature Error" "Disabled,Enabled"
|
|
hgroup.long 0xd4++0x3
|
|
hide.long 0x00 "TC_QISR,TC QDEC Interrupt Status Register"
|
|
textfld " "
|
|
in
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "TC_WPMR,TC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
width 0x9
|
|
tree "TC Channel 0"
|
|
wgroup.long 0x0++0x03
|
|
line.long 0x00 "TC0_CCR,TC0 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Perform"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (((d.l((ad:0x40010000+0x0+0x4))&0x8000))==0x8000)
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "No,Yes"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register 0"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
rgroup.long (0x0+0x10)++0x03
|
|
line.long 0x00 "TC0_CV,TC0 Counter Value Register"
|
|
if (((d.l((ad:0x40010000+0x0+0x4)))&0x8000)==0x8000)
|
|
group.long (0x0+0x14)++0x7
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
else
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
endif
|
|
group.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "TC0_RC,TC0 Register C"
|
|
hgroup.long (0x0+0x20)++0x03
|
|
hide.long 0x00 "TC0_SR,TC0 Status Register"
|
|
textfld " "
|
|
in
|
|
group.long (0x0+0x2C)++0x03
|
|
line.long 0x00 "TC0_IMR,TC0 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TC Channel 1"
|
|
wgroup.long 0x40++0x03
|
|
line.long 0x00 "TC1_CCR,TC1 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Perform"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (((d.l((ad:0x40010000+0x40+0x4))&0x8000))==0x8000)
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "No,Yes"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "TC_SMMR1,TC Stepper Motor Mode Register 1"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
rgroup.long (0x40+0x10)++0x03
|
|
line.long 0x00 "TC1_CV,TC1 Counter Value Register"
|
|
if (((d.l((ad:0x40010000+0x40+0x4)))&0x8000)==0x8000)
|
|
group.long (0x40+0x14)++0x7
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
else
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
endif
|
|
group.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "TC1_RC,TC1 Register C"
|
|
hgroup.long (0x40+0x20)++0x03
|
|
hide.long 0x00 "TC1_SR,TC1 Status Register"
|
|
textfld " "
|
|
in
|
|
group.long (0x40+0x2C)++0x03
|
|
line.long 0x00 "TC1_IMR,TC1 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TC Channel 2"
|
|
wgroup.long 0x80++0x03
|
|
line.long 0x00 "TC2_CCR,TC2 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Perform"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (((d.l((ad:0x40010000+0x80+0x4))&0x8000))==0x8000)
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "No,Yes"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "TC_SMMR2,TC Stepper Motor Mode Register 2"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
rgroup.long (0x80+0x10)++0x03
|
|
line.long 0x00 "TC2_CV,TC2 Counter Value Register"
|
|
if (((d.l((ad:0x40010000+0x80+0x4)))&0x8000)==0x8000)
|
|
group.long (0x80+0x14)++0x7
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
else
|
|
rgroup.long (0x80+0x14)++0x07
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
endif
|
|
group.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "TC2_RC,TC2 Register C"
|
|
hgroup.long (0x80+0x20)++0x03
|
|
hide.long 0x00 "TC2_SR,TC2 Status Register"
|
|
textfld " "
|
|
in
|
|
group.long (0x80+0x2C)++0x03
|
|
line.long 0x00 "TC2_IMR,TC2 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Block B"
|
|
base ad:0x40014000
|
|
width 0x8
|
|
wgroup.long 0xc0++0x03
|
|
line.long 0x00 "TC_BCR,TC Block Control Register"
|
|
bitfld.long 0x00 0. " SYNC , Synchro Command" "No effect,Assert"
|
|
group.long 0xc4++0x03
|
|
line.long 0x00 "TC_BMR,TC Block Mode Register"
|
|
bitfld.long 0x00 20.--25. " MAXFILT ,Maximum Filter" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
bitfld.long 0x00 19. " FILTER ,Glitch Filter - IDX/PHA/PHB input pins filter" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " IDXPHB ,Index pin is PHB pin" "TIOA1,TIOB0"
|
|
bitfld.long 0x00 16. " SWAP ,SWAP PHA and PHB" "Not swapped,Swapped"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INVIDX ,Inverted Index" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " INVB ,Inverted PHB" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INVA ,Inverted PHA" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " EDGPHA ,Edge on PHA count mode" "PHA and PHB,PHA only"
|
|
textline " "
|
|
bitfld.long 0x00 11. " QDTRANS ,Quadrature Decoding Transparent" "Full,Transparent"
|
|
bitfld.long 0x00 10. " SPEEDEN ,Speed Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " POSEN ,Position Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " QDEN ,Quadrature Decoder Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External Clock Signal 2 Selection" "TCLK2,,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External Clock Signal 1 Selection" "TCLK1,,TIOA0,TIOA2"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External Clock Signal 0 Selection" "TCLK0,,TIOA1,TIOA2"
|
|
group.long 0xd0++0x3
|
|
line.long 0x00 "TC_QIMR,TC QDEC Interrupt Mask Register"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " IDX_set/clr ,Index" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " DIRCHG_set/clr ,Direction Change" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " QERR_set/clr ,Quadrature Error" "Disabled,Enabled"
|
|
hgroup.long 0xd4++0x3
|
|
hide.long 0x00 "TC_QISR,TC QDEC Interrupt Status Register"
|
|
textfld " "
|
|
in
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "TC_WPMR,TC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
width 0x9
|
|
tree "TC Channel 3"
|
|
wgroup.long 0x0++0x03
|
|
line.long 0x00 "TC3_CCR,TC3 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Perform"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (((d.l((ad:0x40014000+0x0+0x4))&0x8000))==0x8000)
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC3_CMR,TC3 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "No,Yes"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC3_CMR,TC3 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "TC_SMMR3,TC Stepper Motor Mode Register 3"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
rgroup.long (0x0+0x10)++0x03
|
|
line.long 0x00 "TC3_CV,TC3 Counter Value Register"
|
|
if (((d.l((ad:0x40014000+0x0+0x4)))&0x8000)==0x8000)
|
|
group.long (0x0+0x14)++0x7
|
|
line.long 0x00 "TC3_RA,TC3 Register A"
|
|
line.long 0x04 "TC3_RB,TC3 Register B"
|
|
else
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "TC3_RA,TC3 Register A"
|
|
line.long 0x04 "TC3_RB,TC3 Register B"
|
|
endif
|
|
group.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "TC3_RC,TC3 Register C"
|
|
hgroup.long (0x0+0x20)++0x03
|
|
hide.long 0x00 "TC3_SR,TC3 Status Register"
|
|
textfld " "
|
|
in
|
|
group.long (0x0+0x2C)++0x03
|
|
line.long 0x00 "TC3_IMR,TC3 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TC Channel 4"
|
|
wgroup.long 0x40++0x03
|
|
line.long 0x00 "TC4_CCR,TC4 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Perform"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (((d.l((ad:0x40014000+0x40+0x4))&0x8000))==0x8000)
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC4_CMR,TC4 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "No,Yes"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC4_CMR,TC4 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "TC_SMMR4,TC Stepper Motor Mode Register 4"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
rgroup.long (0x40+0x10)++0x03
|
|
line.long 0x00 "TC4_CV,TC4 Counter Value Register"
|
|
if (((d.l((ad:0x40014000+0x40+0x4)))&0x8000)==0x8000)
|
|
group.long (0x40+0x14)++0x7
|
|
line.long 0x00 "TC4_RA,TC4 Register A"
|
|
line.long 0x04 "TC4_RB,TC4 Register B"
|
|
else
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "TC4_RA,TC4 Register A"
|
|
line.long 0x04 "TC4_RB,TC4 Register B"
|
|
endif
|
|
group.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "TC4_RC,TC4 Register C"
|
|
hgroup.long (0x40+0x20)++0x03
|
|
hide.long 0x00 "TC4_SR,TC4 Status Register"
|
|
textfld " "
|
|
in
|
|
group.long (0x40+0x2C)++0x03
|
|
line.long 0x00 "TC4_IMR,TC4 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TC Channel 5"
|
|
wgroup.long 0x80++0x03
|
|
line.long 0x00 "TC5_CCR,TC5 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Perform"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (((d.l((ad:0x40014000+0x80+0x4))&0x8000))==0x8000)
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "TC5_CMR,TC5 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "No,Yes"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "TC5_CMR,TC5 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "TC_SMMR5,TC Stepper Motor Mode Register 5"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
rgroup.long (0x80+0x10)++0x03
|
|
line.long 0x00 "TC5_CV,TC5 Counter Value Register"
|
|
if (((d.l((ad:0x40014000+0x80+0x4)))&0x8000)==0x8000)
|
|
group.long (0x80+0x14)++0x7
|
|
line.long 0x00 "TC5_RA,TC5 Register A"
|
|
line.long 0x04 "TC5_RB,TC5 Register B"
|
|
else
|
|
rgroup.long (0x80+0x14)++0x07
|
|
line.long 0x00 "TC5_RA,TC5 Register A"
|
|
line.long 0x04 "TC5_RB,TC5 Register B"
|
|
endif
|
|
group.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "TC5_RC,TC5 Register C"
|
|
hgroup.long (0x80+0x20)++0x03
|
|
hide.long 0x00 "TC5_SR,TC5 Status Register"
|
|
textfld " "
|
|
in
|
|
group.long (0x80+0x2C)++0x03
|
|
line.long 0x00 "TC5_IMR,TC5 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="ATSAM4C16C-CORE1"||cpu()=="ATSAM4C8C-CORE1"||cpu()=="ATSAM4CMP16C-CORE1"||cpu()=="ATSAM4CMP8C-CORE1"||cpu()=="ATSAM4CMS8C-CORE1"||cpu()=="ATSAM4CMS16C-CORE1")
|
|
tree "PWM (Pulse Width Modulation Controller)"
|
|
base ad:0x48008000
|
|
width 10.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "PWM_MR,PWM Mode Register"
|
|
bitfld.long 0x00 24.--27. " PREB ,Master clock selection for CLKB" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,?..."
|
|
hexmask.long.byte 0x00 16.--23. 1. " DIVB ,CLKB Divide Factor"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " PREA ,Master clock selection for CLKA" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIVA ,CLKA Divide Factor"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PWM_SR,PWM Status Register"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CHID3_set/clr ,PWM output for channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CHID2_set/clr ,PWM output for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " CHID1_set/clr ,PWM output for channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " CHID0_set/clr ,PWM output for channel 0" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PWM_IMR,PWM Interrupt Mask Register"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CHID3_set/clr ,Interrupt for PWM channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CHID2_set/clr ,Interrupt for PWM channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " CHID1_set/clr ,Interrupt for PWM channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " CHID0_set/clr ,Interrupt for PWM channel 0" "Disabled,Enabled"
|
|
hgroup.long 0x1c++0x03
|
|
hide.long 0x0 "PWM_ISR1,PWM Interrupt Status Register 1"
|
|
textfld " "
|
|
in
|
|
group.long 0x200++0xB "Channel 0"
|
|
line.long 0x00 "PWM_CMR0,Channel 0 Mode Register"
|
|
bitfld.long 0x00 10. " CPD ,Channel Update Period" "Duty cycle,Period"
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
line.long 0x04 "PWM_CDTY0,PWM Channel 0 Duty Cycle Register"
|
|
line.long 0x08 "PWM_CPRD0,PWM Channel 0 Duty Cycle Update Register"
|
|
rgroup.long (0x200+0x0C)++0x03
|
|
line.long 0x00 "PWM_CCNT0,PWM Channel 0 Counter Register"
|
|
wgroup.long (0x200+0x10)++0x03
|
|
line.long 0x00 "PWM_CUPD0,PWM Channel Update Register"
|
|
group.long 0x220++0xB "Channel 1"
|
|
line.long 0x00 "PWM_CMR1,Channel 1 Mode Register"
|
|
bitfld.long 0x00 10. " CPD ,Channel Update Period" "Duty cycle,Period"
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
line.long 0x04 "PWM_CDTY1,PWM Channel 1 Duty Cycle Register"
|
|
line.long 0x08 "PWM_CPRD1,PWM Channel 1 Duty Cycle Update Register"
|
|
rgroup.long (0x220+0x0C)++0x03
|
|
line.long 0x00 "PWM_CCNT1,PWM Channel 1 Counter Register"
|
|
wgroup.long (0x220+0x10)++0x03
|
|
line.long 0x00 "PWM_CUPD1,PWM Channel Update Register"
|
|
group.long 0x240++0xB "Channel 2"
|
|
line.long 0x00 "PWM_CMR2,Channel 2 Mode Register"
|
|
bitfld.long 0x00 10. " CPD ,Channel Update Period" "Duty cycle,Period"
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
line.long 0x04 "PWM_CDTY2,PWM Channel 2 Duty Cycle Register"
|
|
line.long 0x08 "PWM_CPRD2,PWM Channel 2 Duty Cycle Update Register"
|
|
rgroup.long (0x240+0x0C)++0x03
|
|
line.long 0x00 "PWM_CCNT2,PWM Channel 2 Counter Register"
|
|
wgroup.long (0x240+0x10)++0x03
|
|
line.long 0x00 "PWM_CUPD2,PWM Channel Update Register"
|
|
group.long 0x260++0xB "Channel 3"
|
|
line.long 0x00 "PWM_CMR3,Channel 3 Mode Register"
|
|
bitfld.long 0x00 10. " CPD ,Channel Update Period" "Duty cycle,Period"
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
line.long 0x04 "PWM_CDTY3,PWM Channel 3 Duty Cycle Register"
|
|
line.long 0x08 "PWM_CPRD3,PWM Channel 3 Duty Cycle Update Register"
|
|
rgroup.long (0x260+0x0C)++0x03
|
|
line.long 0x00 "PWM_CCNT3,PWM Channel 3 Counter Register"
|
|
wgroup.long (0x260+0x10)++0x03
|
|
line.long 0x00 "PWM_CUPD3,PWM Channel Update Register"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="ATSAM4C16C-CORE0"||cpu()=="ATSAM4C8C-CORE0"||cpu()=="ATSAM4CMP16C-CORE0"||cpu()=="ATSAM4CMP8C-CORE0"||cpu()=="ATSAM4CMS8C-CORE0"||cpu()=="ATSAM4CMS16C-CORE0")
|
|
tree "SLCDC (Segment Liquid Crystal Display Controller Interface)"
|
|
base ad:0x4003C000
|
|
width 13.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SLCDC_CR ,SLCDC Control Register"
|
|
bitfld.long 0x00 3. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 1. " LCDDIS ,Disable LCDC" "No effect,Disable"
|
|
bitfld.long 0x00 0. " LCDEN ,Enable LCDC" "No effect,Enable"
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "SLCDC_MR ,SLCDC Mode Register"
|
|
bitfld.long 0x00 24. " LPMODE ,Low Power Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " BIAS ,LCD Display Configuration" "Static,Bias 1/2,Bias 1/3,"
|
|
bitfld.long 0x00 16.--19. " BUFTIME ,Buffer On-Time" "Off,2 periods,4 periods,8 periods,16 periods,32 periods,64 periods,128 periods,50% of period,100% of period,?..."
|
|
sif (cpu()=="ATSAM4CMP16C-CORE0"||cpu()=="ATSAM4CMP8-CORE0")
|
|
bitfld.long 0x00 8.--13. " SEGSEL ,Selection of the Number of Segments" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
elif (cpu()=="ATSAM4CMS16C-CORE0"||cpu()=="ATSAM4CMS8-CORE0")
|
|
bitfld.long 0x00 8.--13. " SEGSEL ,Selection of the Number of Segments" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,?..."
|
|
else
|
|
bitfld.long 0x00 8.--13. " SEGSEL ,Selection of the Number of Segments" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,?..."
|
|
endif
|
|
bitfld.long 0x00 0.--2. " COMSEL ,Selection of the Number of Commons" "COM 0,COM 0:1,COM 0:2,COM 0:3,COM 0:4,COM 0:5,,"
|
|
line.long 0x04 "SLCDC_FRR,SLCDC Frame Rate Register"
|
|
bitfld.long 0x04 8.--10. " DIV ,Clock Division" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
bitfld.long 0x04 0.--2. " PRESC ,Clock Prescaler" "/8,/16,/32,/64,/128,/256,/512,/1024"
|
|
textline " "
|
|
line.long 0x08 "SLCDC_DR,SLCDC Display Register"
|
|
hexmask.long.byte 0x08 8.--15. 1. " LCDBLKFREQ ,LCD Blinking Frequency Selection"
|
|
bitfld.long 0x08 0.--2. " DISPMODE ,Display Mode Register" "Normal,Force Off,Force On,Blinking,Inverted,Inverted Blinking,User Buffer Only Load,Buffer Swap"
|
|
textline " "
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "SLCDC_SR,SLCDC Status Register"
|
|
bitfld.long 0x00 0. " ENA ,Enable Status" "Disabled,Enabled"
|
|
wgroup.long 0x20++0x0B
|
|
line.long 0x00 "SLCDC_IER,SLCDC Interrupt Enable Register"
|
|
bitfld.long 0x00 2. " DIS ,Disable Interrupt Enable" "No effect,Enable"
|
|
bitfld.long 0x00 0. " ENDFRAME ,End of Frame Interrupt Mask" "No effect,Enable"
|
|
line.long 0x04 "SLCDC_IDR,SLCDC Interrupt Disable Register"
|
|
bitfld.long 0x04 2. " DIS ,Disable Interrupt Disable" "No effect,Disable"
|
|
bitfld.long 0x04 0. " ENDFRAME ,End of Frame Interrupt Mask" "No effect,Disable"
|
|
line.long 0x08 "SLCDC_IMR,SLCDC Interrupt Mask Register"
|
|
bitfld.long 0x08 2. " DIS ,Disable Interrupt Mask" "No,Yes"
|
|
bitfld.long 0x08 0. " ENDFRAME ,End of Frame Interrupt Mask" "No,Yes"
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "SLCDC_ISR,SLCDC Interrupt Status Register"
|
|
textfld " "
|
|
in
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "SLCDC_SMR0,SLCDC Segment Map Register 0"
|
|
bitfld.long 0x00 31. " LCD31 ,LCD Segment Mapped on SEG31 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x00 30. " LCD30 ,LCD Segment Mapped on SEG30 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x00 29. " LCD29 ,LCD Segment Mapped on SEG29 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x00 28. " LCD28 ,LCD Segment Mapped on SEG28 I/O pin" "SEGSEL,I/O pin"
|
|
textline " "
|
|
bitfld.long 0x00 27. " LCD27 ,LCD Segment Mapped on SEG27 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x00 26. " LCD26 ,LCD Segment Mapped on SEG26 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x00 25. " LCD25 ,LCD Segment Mapped on SEG25 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x00 24. " LCD24 ,LCD Segment Mapped on SEG24 I/O pin" "SEGSEL,I/O pin"
|
|
textline " "
|
|
bitfld.long 0x00 23. " LCD23 ,LCD Segment Mapped on SEG23 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x00 22. " LCD22 ,LCD Segment Mapped on SEG22 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x00 21. " LCD21 ,LCD Segment Mapped on SEG21 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x00 20. " LCD20 ,LCD Segment Mapped on SEG20 I/O pin" "SEGSEL,I/O pin"
|
|
textline " "
|
|
bitfld.long 0x00 19. " LCD19 ,LCD Segment Mapped on SEG19 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x00 18. " LCD18 ,LCD Segment Mapped on SEG18 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x00 17. " LCD17 ,LCD Segment Mapped on SEG17 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x00 16. " LCD16 ,LCD Segment Mapped on SEG16 I/O pin" "SEGSEL,I/O pin"
|
|
textline " "
|
|
bitfld.long 0x00 15. " LCD15 ,LCD Segment Mapped on SEG15 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x00 14. " LCD14 ,LCD Segment Mapped on SEG14 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x00 13. " LCD13 ,LCD Segment Mapped on SEG13 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x00 12. " LCD12 ,LCD Segment Mapped on SEG12 I/O pin" "SEGSEL,I/O pin"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LCD11 ,LCD Segment Mapped on SEG11 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x00 10. " LCD10 ,LCD Segment Mapped on SEG10 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x00 9. " LCD9 ,LCD Segment Mapped on SEG9 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x00 8. " LCD8 ,LCD Segment Mapped on SEG8 I/O pin" "SEGSEL,I/O pin"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LCD7 ,LCD Segment Mapped on SEG7 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x00 6. " LCD6 ,LCD Segment Mapped on SEG6 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x00 5. " LCD5 ,LCD Segment Mapped on SEG5 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x00 4. " LCD4 ,LCD Segment Mapped on SEG4 I/O pin" "SEGSEL,I/O pin"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LCD3 ,LCD Segment Mapped on SEG3 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x00 2. " LCD2 ,LCD Segment Mapped on SEG2 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x00 1. " LCD1 ,LCD Segment Mapped on SEG1 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x00 0. " LCD0 ,LCD Segment Mapped on SEG0 I/O pin" "SEGSEL,I/O pin"
|
|
line.long 0x04 "SLCDC_SMR1,SLCDC Segment Map Register 1"
|
|
sif (cpu()!="ATSAM4CMP16C-CORE0"&&cpu()!="ATSAM4CMP8-CORE0")
|
|
sif (cpu()!="ATSAM4CMS16C-CORE0"&&cpu()!="ATSAM4CMS8-CORE0")
|
|
bitfld.long 0x04 17. " LCD49 ,LCD Segment Mapped on SEG49 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x04 16. " LCD48 ,LCD Segment Mapped on SEG48 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x04 15. " LCD47 ,LCD Segment Mapped on SEG47 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x04 14. " LCD46 ,LCD Segment Mapped on SEG46 I/O pin" "SEGSEL,I/O pin"
|
|
textline " "
|
|
bitfld.long 0x04 13. " LCD45 ,LCD Segment Mapped on SEG45 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x04 12. " LCD44 ,LCD Segment Mapped on SEG44 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x04 11. " LCD43 ,LCD Segment Mapped on SEG43 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x04 10. " LCD42 ,LCD Segment Mapped on SEG42 I/O pin" "SEGSEL,I/O pin"
|
|
textline " "
|
|
bitfld.long 0x04 9. " LCD41 ,LCD Segment Mapped on SEG41 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x04 8. " LCD40 ,LCD Segment Mapped on SEG40 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x04 7. " LCD39 ,LCD Segment Mapped on SEG39 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x04 6. " LCD38 ,LCD Segment Mapped on SEG38 I/O pin" "SEGSEL,I/O pin"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 5. " LCD37 ,LCD Segment Mapped on SEG37 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x04 4. " LCD36 ,LCD Segment Mapped on SEG36 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x04 3. " LCD35 ,LCD Segment Mapped on SEG35 I/O pin" "SEGSEL,I/O pin"
|
|
bitfld.long 0x04 2. " LCD34 ,LCD Segment Mapped on SEG34 I/O pin" "SEGSEL,I/O pin"
|
|
textline " "
|
|
bitfld.long 0x04 1. " LCD33 ,LCD Segment Mapped on SEG33 I/O pin" "SEGSEL,I/O pin"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 0. " LCD32 ,LCD Segment Mapped on SEG32 I/O pin" "SEGSEL,I/O pin"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "SLCDC_WPMR,SLCDC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0xE8++0x03
|
|
line.long 0x00 "SLCDC_WPSR ,SLCDC Write Protect Status Register"
|
|
hexmask.long.word 0x00 8.--16. 1. " WPVSRC ,Write Protect Violation Source"
|
|
bitfld.long 0x00 0. " WPVS ,Write Protect Violation Status" "No violation,Violation"
|
|
textline " "
|
|
group.long 0x200++0x2F
|
|
line.long 0x00 "SLCDC_LMEMR0,SLCDC LSB Memory Register"
|
|
line.long 0x04 "SLCDC_MMEMR0,SLCDC MSB Memory Register"
|
|
line.long 0x08 "SLCDC_LMEMR1,SLCDC LSB Memory Register"
|
|
line.long 0x0C "SLCDC_MMEMR1,SLCDC MSB Memory Register"
|
|
line.long 0x10 "SLCDC_LMEMR2,SLCDC LSB Memory Register"
|
|
line.long 0x14 "SLCDC_MMEMR2,SLCDC MSB Memory Register"
|
|
line.long 0x18 "SLCDC_LMEMR3,SLCDC LSB Memory Register"
|
|
line.long 0x1C "SLCDC_MMEMR3,SLCDC MSB Memory Register"
|
|
line.long 0x20 "SLCDC_LMEMR4,SLCDC LSB Memory Register"
|
|
line.long 0x24 "SLCDC_MMEMR4,SLCDC MSB Memory Register"
|
|
line.long 0x28 "SLCDC_LMEMR5,SLCDC LSB Memory Register"
|
|
line.long 0x2C "SLCDC_MMEMR5,SLCDC MSB Memory Register"
|
|
width 0xB
|
|
tree.end
|
|
tree "ADC (Analog to Digital Converter)"
|
|
base ad:0x40038000
|
|
width 0x13
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "ADC_CR,ADC Control Register"
|
|
bitfld.long 0x00 1. " START ,Conversion Start" "No effect,Start"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "No effect,Reset"
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "ADC_MR,ADC Mode Register"
|
|
bitfld.long 0x00 31. " USEQ ,User Sequence Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " TRACKTIM ,Tracking Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--22. 1. " STARTUP ,Start Up Time"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCAL ,Prescaler Rate Selection"
|
|
bitfld.long 0x00 7. " FREERUN ,Free Run Mode" "Normal,Free run"
|
|
bitfld.long 0x00 5. " SLEEP ,Sleep Mode" "Normal,Sleep"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LOWRES ,Resolution" "10-bit,8-bit"
|
|
bitfld.long 0x00 1.--3. " TRGSEL , Trigger Selection" "External,TC0,TC1,TC2,TC3,TC4,TC5,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " TRGEN , Trigger Enable" "Disabled,Enabled"
|
|
line.long 0x04 "ADC_SEQR1,ADC Channel Sequence 1 Register"
|
|
sif (cpu()=="ATSAM4C16C-CORE0"||cpu()=="ATSAM4C16C-CORE1"||cpu()=="ATSAM4C8C-CORE0"||cpu()=="ATSAM4C8C-CORE1")
|
|
bitfld.long 0x04 28.--31. " USCH8 ,User Sequence Number 8" "0,1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x04 24.--27. " USCH7 ,User Sequence Number 7" "0,1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x04 20.--23. " USCH6 ,User Sequence Number 6" "0,1,2,3,4,5,6,7,?..."
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " USCH5 ,User Sequence Number 5" "0,1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x04 12.--15. " USCH4 ,User Sequence Number 4" "0,1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x04 8.--11. " USCH3 ,User Sequence Number 3" "0,1,2,3,4,5,6,7,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " USCH2 ,User Sequence Number 2" "0,1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x04 0.--3. " USCH1 ,User Sequence Number 1" "0,1,2,3,4,5,6,7,?..."
|
|
else
|
|
bitfld.long 0x04 16.--19. " USCH6 ,User Sequence Number 6" "0,1,2,3,,,6,7,?..."
|
|
bitfld.long 0x04 16.--19. " USCH5 ,User Sequence Number 5" "0,1,2,3,,,6,7,?..."
|
|
bitfld.long 0x04 12.--15. " USCH4 ,User Sequence Number 4" "0,1,2,3,,,6,7,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " USCH3 ,User Sequence Number 3" "0,1,2,3,,,6,7,?..."
|
|
bitfld.long 0x04 4.--7. " USCH2 ,User Sequence Number 2" "0,1,2,3,,,6,7,?..."
|
|
bitfld.long 0x04 0.--3. " USCH1 ,User Sequence Number 1" "0,1,2,3,,,6,7,?..."
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ADC_CHSR,ADC Channel Status Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " CH7_set/clr ,Channel 7 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " CH6_set/clr ,Channel 6 Status" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="ATSAM4C16C-CORE0"||cpu()=="ATSAM4C16C-CORE1"||cpu()=="ATSAM4C8C-CORE0"||cpu()=="ATSAM4C8C-CORE1")
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " CH5_set/clr ,Channel 5 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CH4_set/clr ,Channel 4 Status" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CH3_set/clr ,Channel 3 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CH2_set/clr ,Channel 2 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " CH1_set/clr ,Channel 1 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " CH0_set/clr ,Channel 0 Status" "Disabled,Enabled"
|
|
hgroup.long 0x20++0x3
|
|
hide.long 0x00 "ADC_LCDR,ADC Last Data Converted"
|
|
textfld " "
|
|
in
|
|
group.long 0x2c++0x03
|
|
line.long 0x00 "ADC_IMR,ADC Interrupt Mask Register"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " RXBUFF_set/clr ,Comparison Event Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " ENDRX_set/clr ,Receive Buffer End Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " COMPE_set/clr ,Comparison Event Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " GOVRE_set/clr ,General Overrun Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " DRDY_set/clr ,Data Ready Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " TEMPCHG_set/clr ,Temperature Change Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " EOC7_set/clr ,Conversion End Interrupt 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " EOC6_set/clr ,Conversion End Interrupt 6" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="ATSAM4C16C-CORE0"||cpu()=="ATSAM4C16C-CORE1"||cpu()=="ATSAM4C8C-CORE0"||cpu()=="ATSAM4C8C-CORE1")
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " EOC5_set/clr ,Conversion End Interrupt 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " EOC4_set/clr ,Conversion End Interrupt 4" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " EOC3_set/clr ,Conversion End Interrupt 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " EOC2_set/clr ,Conversion End Interrupt 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " EOC1_set/clr ,Conversion End Interrupt 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EOC0_set/clr ,Conversion End Interrupt 0" "Disabled,Enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "ADC_ISR,ADC Interrupt Status Register"
|
|
bitfld.long 0x00 28. " RXBUFF ,Comparison Event Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 27. " ENDRX ,Receive Buffer End Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 26. " COMPE ,Comparison Event Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " GOVRE ,General Overrun Error Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DRDY ,Data Ready Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " TEMPCHG ,Temperature Change Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EOC7 ,Conversion End Interrupt 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " EOC6 ,Conversion End Interrupt 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpu()=="ATSAM4C16C-CORE0"||cpu()=="ATSAM4C16C-CORE1"||cpu()=="ATSAM4C8C-CORE0"||cpu()=="ATSAM4C8C-CORE1")
|
|
bitfld.long 0x00 5. " EOC5 ,Conversion End Interrupt 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " EOC4 ,Conversion End Interrupt 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " EOC3 ,Conversion End Interrupt 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " EOC2 ,Conversion End Interrupt 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EOC1 ,Conversion End Interrupt 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " EOC0 ,Conversion End Interrupt 0" "No interrupt,Interrupt"
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "ADC_TEMPMR,ADC Temperature Sensor Mode Register"
|
|
bitfld.long 0x00 4.--5. " TEMPCMPMOD ,Temperature Comparison Mode" "Low,High,In,Out"
|
|
bitfld.long 0x00 0. " TEMPON ,Temperature Sensor ON" "Disabled,Enabled"
|
|
line.long 0x04 "ADC_TEMPCWR,ADC Temperature Compare Window Register"
|
|
hexmask.long.word 0x04 16.--27. 1. " THIGHTHRES ,Temperature High Threshold"
|
|
hexmask.long.word 0x04 0.--11. 1. " TLOWTHRES ,Temperature Low Threshold"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "ADC_OVER,ADC Overrun Status Register"
|
|
bitfld.long 0x00 7. " OVRE7 ,Overrun Error 7" "No error,Error"
|
|
bitfld.long 0x00 6. " OVRE6 ,Overrun Error 6" "No error,Error"
|
|
textline " "
|
|
sif (cpu()=="ATSAM4C16C-CORE0"||cpu()=="ATSAM4C16C-CORE1"||cpu()=="ATSAM4C8C-CORE0"||cpu()=="ATSAM4C8C-CORE1")
|
|
bitfld.long 0x00 5. " OVRE5 ,Overrun Error 5" "No error,Error"
|
|
bitfld.long 0x00 4. " OVRE4 ,Overrun Error 4" "No error,Error"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " OVRE3 ,Overrun Error 3" "No error,Error"
|
|
bitfld.long 0x00 2. " OVRE2 ,Overrun Error 2" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OVRE1 ,Overrun Error 1" "No error,Error"
|
|
bitfld.long 0x00 0. " OVRE0 ,Overrun Error 0" "No error,Error"
|
|
if (((d.l(ad:0x40038000+0x40))&0x200)==0x000)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "ADC_EMR,ADC Extended Mode Register"
|
|
bitfld.long 0x00 24. " TAG ,TAG of the ADC_LDCR register" "0,Channel"
|
|
bitfld.long 0x00 20. " ASTE ,Averaging on Single Trigger Event" "Several,Single"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " OSR ,Over Sampling Rate" "Disabled,1-bit,2-bit,"
|
|
bitfld.long 0x00 12.--13. " CMPFILTER ,Compare Event Filtering" "1,2,3,4"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CMPALL ,Compare All Channels" "CMPSEL,All channels"
|
|
sif (cpu()=="ATSAM4C16C-CORE0"||cpu()=="ATSAM4C16C-CORE1"||cpu()=="ATSAM4C8C-CORE0"||cpu()=="ATSAM4C8C-CORE1")
|
|
bitfld.long 0x00 4.--7. " CMPSEL ,Comparison Selected Channel" "0,1,2,3,4,5,6,7,?..."
|
|
else
|
|
bitfld.long 0x00 4.--7. " CMPSEL ,Comparison Selected Channel" "0,1,2,3,,,6,7,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CMPMODE ,Comparison Mode" "LOW,HIGH,IN,OUT"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "ADC_EMR,ADC Extended Mode Register"
|
|
bitfld.long 0x00 24. " TAG ,TAG of the ADC_LDCR register" "0,Channel"
|
|
bitfld.long 0x00 20. " ASTE ,Averaging on Single Trigger Event" "Several,Single"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " OSR ,Over Sampling Rate" "Disabled,1-bit,2-bit,"
|
|
bitfld.long 0x00 12.--13. " CMPFILTER ,Compare Event Filtering" "1,2,3,4"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CMPALL ,Compare All Channels" "CMPSEL,All channels"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CMPMODE ,Comparison Mode" "LOW,HIGH,IN,OUT"
|
|
endif
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "ADC_CWR,ADC Compare Window Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " HIGHTHRES ,High Threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWTHRES ,Low Threshold"
|
|
textline " "
|
|
sif (cpu()=="ATSAM4C16C-CORE0"||cpu()=="ATSAM4C16C-CORE1"||cpu()=="ATSAM4C8C-CORE0"||cpu()=="ATSAM4C8C-CORE1")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "ADC_CDR0,ADC Channel 0 Data Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DATA ,Converted Data"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "ADC_CDR1,ADC Channel 1 Data Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DATA ,Converted Data"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "ADC_CDR2,ADC Channel 2 Data Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DATA ,Converted Data"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "ADC_CDR3,ADC Channel 3 Data Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DATA ,Converted Data"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "ADC_CDR4,ADC Channel 4 Data Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DATA ,Converted Data"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "ADC_CDR5,ADC Channel 5 Data Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DATA ,Converted Data"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "ADC_CDR6,ADC Channel 6 Data Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DATA ,Converted Data"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "ADC_CDR7,ADC Channel 7 Data Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DATA ,Converted Data"
|
|
else
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "ADC_CDR0,ADC Channel 0 Data Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DATA ,Converted Data"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "ADC_CDR1,ADC Channel 1 Data Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DATA ,Converted Data"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "ADC_CDR2,ADC Channel 2 Data Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DATA ,Converted Data"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "ADC_CDR3,ADC Channel 3 Data Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DATA ,Converted Data"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "ADC_CDR6,ADC Channel 6 Data Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DATA ,Converted Data"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "ADC_CDR7,ADC Channel 7 Data Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DATA ,Converted Data"
|
|
endif
|
|
if (((d.l(ad:0x40038000+0x94))&0x04)==0x04)
|
|
group.long 0x94++0x07
|
|
line.long 0x00 "ADC_ACR,ADC Analog Control Register"
|
|
bitfld.long 0x00 20. " ONREF ,Internal Voltage Reference ON" "External,Internal"
|
|
bitfld.long 0x00 19. " FORCEREF ,Force Internal Reference Voltage" "Define,VDDIO"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IRVCE , Internal Reference Voltage Change Enable" "Default 2.40V,IRVS"
|
|
bitfld.long 0x00 3.--6. " IRVS ,Internal Reference Voltage Selection" "2.40V,2.28V,2.16V,2.04V,1.92V,1.80V,1.68V,1.55V,3.38V,3.25V,3.13V,3.01V,2.89V,2.77V,2.65V,2.53V"
|
|
textline " "
|
|
else
|
|
group.long 0x94++0x07
|
|
line.long 0x00 "ADC_ACR,ADC Analog Control Register"
|
|
bitfld.long 0x00 20. " ONREF ,Internal Voltage Reference ON" "External,Internal"
|
|
bitfld.long 0x00 19. " FORCEREF ,Force Internal Reference Voltage" "Define,VDDIO"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IRVCE , Internal Reference Voltage Change Enable" "Default 2.40V,IRVS"
|
|
textline " "
|
|
endif
|
|
group.long 0x0E4++0x03
|
|
line.long 0x00 "ADC_WPMR,ADC Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0x0E8++0x03
|
|
line.long 0x00 "ADC_WPSR,ADC Write Protection Status Register"
|
|
hexmask.long.word 0x00 8.--23. 1. " WPVSRC , Write Protection Violation Source"
|
|
bitfld.long 0x00 0. " WPVS , Write Protection Violation Status" "No violation,Violation"
|
|
textline " "
|
|
width 11.
|
|
base ad:0x40038000+0x100
|
|
group.long 0x00++0x1F "Peripheral DMA Controller"
|
|
line.long 0x00 "PERIPH_RPR,Receive Pointer Register"
|
|
line.long 0x04 "PERIPH_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter"
|
|
line.long 0x08 "PERIPH_TPR,Transmit Pointer Register"
|
|
line.long 0x0C "PERIPH_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter"
|
|
line.long 0x10 "PERIPH_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "PERIPH_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter"
|
|
line.long 0x18 "PERIPH_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1C "PERIPH_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " RXNCTR ,Transmit Next Counter"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PERIPH_PTCR,Transfer Control Register"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x04 9. " TX_set/clr ,Transmitter Transfer" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x04 1. " TX_set/clr ,Transmitter Transfer" "Disabled,Enabled"
|
|
width 0xB
|
|
width 0x0B
|
|
tree.end
|
|
tree "AES (Advanced Encryption Standard)"
|
|
base ad:0x40000000
|
|
width 14.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "AES_CR,AES Control Register"
|
|
bitfld.long 0x00 8. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " START ,Start Processing" "No effect,Start"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "AES_MR,AES Mode Register"
|
|
bitfld.long 0x00 20.--23. " CKEY ,Key" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--18. " CFBS ,Cipher Feedback Data Size" "128-bit,64-bit,32-bit,16-bit,8-bit,,,"
|
|
textline " "
|
|
bitfld.long 0x00 15. " LOD ,Last Output Data Mode" "No effect,Set"
|
|
bitfld.long 0x00 12.--14. " OPMOD ,Operation Mode" "ECB,CBC,OFB,CFB,CTR,GCM,,"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " KEYSIZE ,Key Size" "128 bits,192 bits,256 bits,"
|
|
bitfld.long 0x00 8.--9. " SMOD ,Start Mode" "Manual,Auto,AES_IDATAR0 access only,"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PROCDLY ,Processing Delay" "12 cycles,24 cycles,36 cycles,48 cycles,60 cycles,72 cycles,84 cycles,96 cycles,108 cycles,120 cycles,132 cycles,144 cycles,156 cycles,168 cycles,180 cycles,192 cycles"
|
|
bitfld.long 0x00 3. " DUALBUFF ,Dual Input Buffer" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GTAGEN ,GCM Automatic Tag Generation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CIPHER ,Processing Mode" "Decrypt,Encrypt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "AES_IMR,AES Interrupt Mask Register"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " URAD_set/clr ,Unspecified Register Access Detection Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " RXBUFF_set/clr ,Receive Buffer Full Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " ENDTX_set/clr ,End of Transmit Buffer Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " ENDRX_set/clr ,End of Receive Buffer Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DATRDY_set/clr ,Data Ready Interrupt" "Disabled,Enabled"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "AES_ISR,AES Interrupt Status Register"
|
|
bitfld.long 0x00 16. " TAGRDY ,GCM Tag Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 12.--15. " URAT ,Unspecified Register Access" "IDR_WR_PROCESSING,ODR_RD_PROCESSING,MR_WR_PROCESSING,ODR_RD_SUBKGEN,MR_WR_SUBKGEN,WOR_RD_ACCESS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " URAD ,Unspecified Register Access Detection Status" "Not detected,Detected"
|
|
bitfld.long 0x00 4. " TXBUFE ,TX Buffer Empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RXBUFF ,RX Buffer Full" "Not full,Full"
|
|
bitfld.long 0x00 2. " ENDTX ,End of TX Buffer" "Not ended,Ended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENDRX ,End of RX Buffer" "Not ended,Ended"
|
|
bitfld.long 0x00 0. " DATRDY ,Data Ready" "Not ready,Ready"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "AES_KEYWR0,Key Word Register 0"
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "AES_KEYWR1,Key Word Register 1"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "AES_KEYWR2,Key Word Register 2"
|
|
wgroup.long 0x2C++0x03
|
|
line.long 0x00 "AES_KEYWR3,Key Word Register 3"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "AES_KEYWR4,Key Word Register 4"
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "AES_KEYWR5,Key Word Register 5"
|
|
wgroup.long 0x38++0x03
|
|
line.long 0x00 "AES_KEYWR6,Key Word Register 6"
|
|
wgroup.long 0x3C++0x03
|
|
line.long 0x00 "AES_KEYWR7,Key Word Register 7"
|
|
wgroup.long 0x40++0x03
|
|
line.long 0x00 "AES_IDATAR0,AES Input Data Register 0"
|
|
wgroup.long 0x44++0x03
|
|
line.long 0x00 "AES_IDATAR1,AES Input Data Register 1"
|
|
wgroup.long 0x48++0x03
|
|
line.long 0x00 "AES_IDATAR2,AES Input Data Register 2"
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "AES_IDATAR3,AES Input Data Register 3"
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "AES_ODATAR0,AES Output Data Register 0"
|
|
textfld " "
|
|
in
|
|
hgroup.long 0x54++0x03
|
|
hide.long 0x00 "AES_ODATAR1,AES Output Data Register 1"
|
|
textfld " "
|
|
in
|
|
hgroup.long 0x58++0x03
|
|
hide.long 0x00 "AES_ODATAR2,AES Output Data Register 2"
|
|
textfld " "
|
|
in
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "AES_ODATAR3,AES Output Data Register 3"
|
|
textfld " "
|
|
in
|
|
wgroup.long 0x60++0x03
|
|
line.long 0x00 "AES_IVR0,AES Initialization Vector Register 0"
|
|
wgroup.long 0x64++0x03
|
|
line.long 0x00 "AES_IVR1,AES Initialization Vector Register 1"
|
|
wgroup.long 0x68++0x03
|
|
line.long 0x00 "AES_IVR2,AES Initialization Vector Register 2"
|
|
wgroup.long 0x6C++0x03
|
|
line.long 0x00 "AES_IVR3,AES Initialization Vector Register 3"
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "AES_AADLENR,AES Additional Authenticated DataLength Register"
|
|
line.long 0x04 "AES_CLENR,AES Plaintext/Ciphertext Length Register"
|
|
group.long 0x78++0x0F
|
|
line.long 0x00 "AES_GHASHR0,AES GCM Intermediate Hash Word Register 0"
|
|
group.long 0x7C++0x0F
|
|
line.long 0x00 "AES_GHASHR1,AES GCM Intermediate Hash Word Register 1"
|
|
group.long 0x80++0x0F
|
|
line.long 0x00 "AES_GHASHR2,AES GCM Intermediate Hash Word Register 2"
|
|
group.long 0x84++0x0F
|
|
line.long 0x00 "AES_GHASHR3,AES GCM Intermediate Hash Word Register 3"
|
|
rgroup.long 0x88++0x0F
|
|
line.long 0x00 "AES_TAGR0,AES GCM Authentication Tag Word Register 0"
|
|
rgroup.long 0x8C++0x0F
|
|
line.long 0x00 "AES_TAGR1,AES GCM Authentication Tag Word Register 1"
|
|
rgroup.long 0x90++0x0F
|
|
line.long 0x00 "AES_TAGR2,AES GCM Authentication Tag Word Register 2"
|
|
rgroup.long 0x94++0x0F
|
|
line.long 0x00 "AES_TAGR3,AES GCM Authentication Tag Word Register 3"
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "AES_CTRR,AES GCM Encryption Counter Value Register"
|
|
group.long 0x9C++0x0F
|
|
line.long 0x00 "AES_GCMHR0,AES GCM H Word Register 0"
|
|
group.long 0xA0++0x0F
|
|
line.long 0x00 "AES_GCMHR1,AES GCM H Word Register 1"
|
|
group.long 0xA4++0x0F
|
|
line.long 0x00 "AES_GCMHR2,AES GCM H Word Register 2"
|
|
group.long 0xA8++0x0F
|
|
line.long 0x00 "AES_GCMHR3,AES GCM H Word Register 3"
|
|
width 11.
|
|
base ad:0x40000000+0x100
|
|
group.long 0x00++0x1F "Peripheral DMA Controller"
|
|
line.long 0x00 "PERIPH_RPR,Receive Pointer Register"
|
|
line.long 0x04 "PERIPH_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter"
|
|
line.long 0x08 "PERIPH_TPR,Transmit Pointer Register"
|
|
line.long 0x0C "PERIPH_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter"
|
|
line.long 0x10 "PERIPH_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "PERIPH_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter"
|
|
line.long 0x18 "PERIPH_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1C "PERIPH_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " RXNCTR ,Transmit Next Counter"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PERIPH_PTCR,Transfer Control Register"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x04 9. " TX_set/clr ,Transmitter Transfer" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x04 1. " TX_set/clr ,Transmitter Transfer" "Disabled,Enabled"
|
|
width 0xB
|
|
width 0x0b
|
|
tree.end
|
|
tree "ICM (Integrity Check Monitor)"
|
|
base ad:0x40044000
|
|
width 17.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "ICM_CFG,Configuration Register"
|
|
bitfld.long 0x00 24.--29. " DAPROT ,Region Descriptor Area Protection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " HAPROT ,Region Hash Area Protection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. " UALGO ,User SHA Algorithm" "SHA1,SHA256,,,SHA224,?..."
|
|
bitfld.long 0x00 12. " UIHASH ,User Initial Hash Value" "Standard,Programmable"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DUALBUFF ,Dual Input Buffer" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ASCD ,Automatic Switch To Compare Digest" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " BBC ,Bus Burden Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2. " SLBDIS ,Secondary List Branching Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EOMDIS ,End of Monitoring Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " WBDIS ,Write Back Disable" "No,Yes"
|
|
textline " "
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "ICM_CTRL,ICM Control Register"
|
|
bitfld.long 0x00 7. " REHASH3 ,Recompute Internal Hash 3" "No effect,Recompute"
|
|
bitfld.long 0x00 6. " REHASH2 ,Recompute Internal Hash 2" "No effect,Recompute"
|
|
bitfld.long 0x00 5. " REHASH1 ,Recompute Internal Hash 1" "No effect,Recompute"
|
|
bitfld.long 0x00 4. " REHASH0 ,Recompute Internal Hash 0" "No effect,Recompute"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SWRESET ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 1. " DISABLE ,ICM Disable Register" "No effect,Disable"
|
|
bitfld.long 0x00 0. " ENABLE ,ICM Enable" "No effect,Enable"
|
|
textline " "
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ICM_SR,ICM Status Register"
|
|
setclrfld.long 0x00 15. -0x04 11. -0x04 15. " RMDIS3 ,Region 3 Monitoring Disable" "No,Yes"
|
|
setclrfld.long 0x00 14. -0x04 10. -0x04 14. " RMDIS2 ,Region 2 Monitoring Disable" "No,Yes"
|
|
setclrfld.long 0x00 13. -0x04 9. -0x04 13. " RMDIS1 ,Region 1 Monitoring Disable" "No,Yes"
|
|
setclrfld.long 0x00 12. -0x04 8. -0x04 12. " RMDIS0 ,Region 0 Monitoring Disable" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " RAWRMDIS3 ,RAW Region 3 Monitoring Disabled Status" "No,Yes"
|
|
rbitfld.long 0x00 10. " RAWRMDIS2 ,RAW Region 2 Monitoring Disabled Status" "No,Yes"
|
|
rbitfld.long 0x00 9. " RAWRMDIS1 ,RAW Region 1 Monitoring Disabled Status" "No,Yes"
|
|
rbitfld.long 0x00 8. " RAWRMDIS0 ,RAW Region 0 Monitoring Disabled Status" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x04 0. -0x04 1. " ENABLE , ICM Controller Enable" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ICM_IMR_set/clr,ICM Interrupt Mask Register"
|
|
textline " "
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " URAD ,Undefined Register Access Detection Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " RSU3 ,Region 3 Status Updated Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " RSU2 ,Region 2 Status Updated Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " RSU1 ,Region 1 Status Updated Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " RSU0 ,Region 0 Status Updated Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " REC3 ,Region $2 End bit Condition Detected Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " REC2 ,Region $2 End bit Condition Detected Interrupt" "Disabled,Enabled"
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setclrfld.long 0x00 17. -0x08 17. -0x04 17. " REC1 ,Region $2 End bit Condition Detected Interrupt" "Disabled,Enabled"
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setclrfld.long 0x00 16. -0x08 16. -0x04 16. " REC0 ,Region $2 End bit Condition Detected Interrupt" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 15. -0x08 15. -0x04 15. " RWC3 ,Region 3 Wrap Condition Detected Interrupt" "Disabled,Enabled"
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setclrfld.long 0x00 14. -0x08 14. -0x04 14. " RWC2 ,Region 2 Wrap Condition Detected Interrupt" "Disabled,Enabled"
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setclrfld.long 0x00 13. -0x08 13. -0x04 13. " RWC1 ,Region 1 Wrap Condition Detected Interrupt" "Disabled,Enabled"
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setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RWC0 ,Region 0 Wrap Condition Detected Interrupt" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 11. -0x08 11. -0x04 11. " RBE3 ,Region 3 Bus Error Interrupt" "Disabled,Enabled"
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setclrfld.long 0x00 10. -0x08 10. -0x04 10. " RBE2 ,Region 2 Bus Error Interrupt" "Disabled,Enabled"
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setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RBE1 ,Region 1 Bus Error Interrupt" "Disabled,Enabled"
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|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " RBE0 ,Region 0 Bus Error Interrupt" "Disabled,Enabled"
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|
textline " "
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setclrfld.long 0x00 7. -0x08 7. -0x04 7. " RDM3 ,Region 3 Digest Mismatch Interrupt" "Disabled,Enabled"
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|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " RDM2 ,Region 2 Digest Mismatch Interrupt" "Disabled,Enabled"
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setclrfld.long 0x00 5. -0x08 5. -0x04 5. " RDM1 ,Region 1 Digest Mismatch Interrupt" "Disabled,Enabled"
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|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RDM0 ,Region 0 Digest Mismatch Interrupt" "Disabled,Enabled"
|
|
textline " "
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setclrfld.long 0x00 3. -0x08 3. -0x04 3. " RHC3 ,Region 3 Hash Completed Interrupt" "Disabled,Enabled"
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|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " RHC2 ,Region 2 Hash Completed Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " RHC1 ,Region 1 Hash Completed Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RHC0 ,Region 0 Hash Completed Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0x1C++0x07
|
|
line.long 0x00 "ICM_ISR,ICM Interrupt Status Register"
|
|
bitfld.long 0x00 24. " URAD ,Undefined Register Access Detection Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " RSU3 ,Region 3 Status Updated Detected" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " RSU2 ,Region 2 Status Updated Detected" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " RSU1 ,Region 1 Status Updated Detected" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " RSU0 ,Region 0 Status Updated Detected" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " REC3 ,Region 3 End bit Condition Detected" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " REC2 ,Region 2 End bit Condition Detected" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " REC1 ,Region 1 End bit Condition Detected" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " REC0 ,Region 0 End bit Condition Detected" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RWC3 ,Region 3 Wrap Condition Detected" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " RWC2 ,Region 2 Wrap Condition Detected" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " RWC1 ,Region 1 Wrap Condition Detected" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " RWC0 ,Region 0 Wrap Condition Detected" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RBE3 ,Region 3 Bus Error" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " RBE2 ,Region 2 Bus Error" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " RBE1 ,Region 1 Bus Error" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " RBE0 ,Region 0 Bus Error" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RDM3 ,Region 3 Digest Mismatch" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " RDM2 ,Region 2 Digest Mismatch" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " RDM1 ,Region 1 Digest Mismatch" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " RDM0 ,Region 0 Digest Mismatch" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RHC3 ,Region 3 Hash Completed" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RHC2 ,Region 2 Hash Completed" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " RHC1 ,Region 1 Hash Completed" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RHC0 ,Region 0 Hash Completed" "No interrupt,Interrupt"
|
|
line.long 0x04 "ICM_UASR,ICM Undefined Access Status Register"
|
|
bitfld.long 0x04 0.--2. " URAT ,Undefined Register Access Trace" "UNSPEC_STRUCT_MEMBER,ICM_CFG_MODIFIED,ICM_DSCR_MODIFIED,ICM_HASH_MODIFIED,READ_ACCESS,,,"
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "ICM_DSCR,ICM Descriptor Area Start Address Register"
|
|
hexmask.long 0x00 6.--31. 0x40 " DASA ,Descriptor Area Start Address"
|
|
line.long 0x04 "ICM_HASH,ICM Hash Area Start Address Register"
|
|
hexmask.long 0x04 7.--31. 0x80 " HASA ,Hash Area Start Address"
|
|
wgroup.long 0x38++0x03
|
|
line.long 0x00 "ICM_UIHVAL0,ICM User Initial Hash Value Register 0"
|
|
wgroup.long 0x3C++0x03
|
|
line.long 0x00 "ICM_UIHVAL1,ICM User Initial Hash Value Register 1"
|
|
wgroup.long 0x40++0x03
|
|
line.long 0x00 "ICM_UIHVAL2,ICM User Initial Hash Value Register 2"
|
|
wgroup.long 0x44++0x03
|
|
line.long 0x00 "ICM_UIHVAL3,ICM User Initial Hash Value Register 3"
|
|
wgroup.long 0x48++0x03
|
|
line.long 0x00 "ICM_UIHVAL4,ICM User Initial Hash Value Register 4"
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "ICM_UIHVAL5,ICM User Initial Hash Value Register 5"
|
|
wgroup.long 0x50++0x03
|
|
line.long 0x00 "ICM_UIHVAL6,ICM User Initial Hash Value Register 6"
|
|
wgroup.long 0x54++0x03
|
|
line.long 0x00 "ICM_UIHVAL7,ICM User Initial Hash Value Register 7"
|
|
width 0x0B
|
|
tree.end
|
|
tree "TRNG (True Random Number Generator)"
|
|
base ad:0x40048000
|
|
width 12.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TRNG_CR,TRNG Control Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " TRNG_CR ,TRNG Control Register"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the TRNG to provide random values" "Disable,Enable"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TRNG_IMR,TRNG Interrupt Mask Register"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DATRDY_set/clr ,Data Ready Interrupt" "Disabled,Enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TRNG_ISR,TRNG Interrupt Status Register"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " DATRDY ,Data Ready" "Not ready,Ready"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "TRNG_ODATA,TRNG Output Data Register"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
textline ""
|