32605 lines
2.7 MiB
32605 lines
2.7 MiB
; --------------------------------------------------------------------------------
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; @Title: Apollo 4 On-Chip Peripherals
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; @Props: Released
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; @Author: KWI, NEJ, ADR, JDU
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; @Changelog: 2020-06-17 KWI
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; 2020-06-24 KWI
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; 2021-01-14 KWI
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; 2021-12-07 NEJ
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; 2022-01-20 ADR
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; 2023-02-23 JDU
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; 2023-11-03 NEJ
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; 2023-11-16 NEJ
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; @Manufacturer: AMBIQ - Ambiq Micro, Inc.
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; @Doc: Generated (TRACE32, build: 164363.), based on:
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; apollo4b.svd (Ver. 1.0), apollo4p.svd (Ver. 1.0)
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; apollo4l.svd (Ver. 1.0)
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; @Core: Cortex-M4F
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; @Chip: AMA4B2KK, AMAP42KK, AMA4B2KP, AMAP42KP, AMAP42KL, AMA4B2KL
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; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perapollo4.per 17037 2023-11-20 17:12:05Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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tree.close "Core Registers (Cortex-M4F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes"
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bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes"
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bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes"
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group.long 0x10++0x0B
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending"
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bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x07
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line.long 0x00 "HFSR,Hard Fault Status Register"
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bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
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bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
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bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested"
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group.long 0xD34++0x0B
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line.long 0x00 "MMFAR,MemManage Fault Address Register"
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line.long 0x04 "BFAR,BusFault Address Register"
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line.long 0x08 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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width 10.
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tree "Feature Registers"
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
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bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
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bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
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textline " "
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bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
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line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
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bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
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bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
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bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
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textline " "
|
|
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
|
|
bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM4F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x07
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline ""
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
|
|
hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "ADC (Analog-to-Digital Converter)"
|
|
base ad:0x40038000
|
|
group.long 0x0++0x43
|
|
line.long 0x0 "CFG,The ADC Configuration Register contains the software control for selecting the clock frequency used for the SAR conversions. the trigger polarity. the trigger select. the reference voltage select. the low power mode. the operating mode (single scan.."
|
|
bitfld.long 0x0 24.--25. "CLKSEL,Select the source and frequency for the general purpose ADC clock. HFRC_24MHZ is the only valid GP ADC clock selection and must be configured for proper operation." "0: This setting must not be used for CLKSEL for the..,1: This setting must not be used for CLKSEL for the..,2: HFRC clock at 24 MHz. This setting is the only..,3: This setting must not be used for CLKSEL for the.."
|
|
bitfld.long 0x0 20. "RPTTRIGSEL,This bit selects which periodic trigger to use with RPTEN = 1." "0: Trigger from on-chip timer.,1: Trigger from ADC-internal timer."
|
|
newline
|
|
bitfld.long 0x0 19. "TRIGPOL,This bit selects the ADC trigger polarity for external off chip triggers." "0: Trigger on rising edge.,1: Trigger on falling edge."
|
|
bitfld.long 0x0 16.--18. "TRIGSEL,Select the ADC trigger source." "0: Off chip External Trigger0 (ADC_ET0),1: Off chip External Trigger1 (ADC_ET1),2: Off chip External Trigger2 (ADC_ET2),3: Off chip External Trigger3 (ADC_ET3),4: Voltage Comparator Output,?,?,7: Software Trigger"
|
|
newline
|
|
bitfld.long 0x0 12. "DFIFORDEN,Destructive FIFO Read Enable. Setting this will enable FIFO pop upon reading the FIFOPR register." "0: Destructive Reads are prevented. Reads to the..,1: Reads to the FIFOPR registger will automatically.."
|
|
bitfld.long 0x0 4. "CKMODE,Clock mode register" "0: Disable the clock between scans for LPMODE0. Set..,1: Low Latency Clock Mode. When set HFRC and the.."
|
|
newline
|
|
bitfld.long 0x0 3. "LPMODE,Select power mode to enter between active scans." "0: Low Power Mode 0. Leaves the ADC fully powered..,1: Low Power Mode 1. Powers down all circuity and.."
|
|
bitfld.long 0x0 2. "RPTEN,This bit enables Repeating Scan Mode." "0: In Single Scan Mode the ADC will complete a..,1: In Repeating Scan Mode the ADC will complete its.."
|
|
newline
|
|
bitfld.long 0x0 0. "ADCEN,This bit enables the ADC module. While the ADC is enabled the ADCCFG and SLOT Configuration regsiter settings must remain stable and unchanged. All configuration register settings slot configuration settings and window comparison settings should.." "0: Disable the ADC module.,1: Enable the ADC module."
|
|
line.long 0x4 "STAT,This register indicates the basic power status for the ADC. For detailed power status. see the power control power status register. ADC power mode 0 indicates the ADC is in its full power state and is ready to process scans. ADC Power mode 1.."
|
|
bitfld.long 0x4 0. "PWDSTAT,Indicates the power-status of the ADC." "0: Powered on.,1: ADC Low Power Mode 1."
|
|
line.long 0x8 "SWT,This register enables initiating an ADC scan through software."
|
|
hexmask.long.byte 0x8 0.--7. 1. "SWT,Writing 0x37 to this register generates a software trigger."
|
|
line.long 0xC "SL0CFG,Slot 0 Configuration"
|
|
bitfld.long 0xC 24.--26. "ADSEL0,Select the number of measurements to average in the accumulate divide module for this slot." "0: Average in 1 measurement in the accumulate..,1: Average in 2 measurements in the accumulate..,2: Average in 4 measurements in the accumulate..,3: Average in 8 measurements in the accumulate..,4: Average in 16 measurements in the accumulate..,5: Average in 32 measurements in the accumulate..,6: Average in 64 measurements in the accumulate..,7: Average in 128 measurements in the accumulate.."
|
|
hexmask.long.byte 0xC 18.--23. 1. "TRKCYC0,Set additional input signal sampling/tracking time to the specified number of ADC clock cycles. (Note that a value of 0 in this register specifies the minimum required 5 cycles. A maximum of 64 specifies 69 cycles.)"
|
|
newline
|
|
bitfld.long 0xC 16.--17. "PRMODE0,Set the Precision Mode For Slot 0." "0: 12-bit precision mode,1: 12-bit precision mode,2: 10-bit precision mode,3: 8-bit precision mode"
|
|
hexmask.long.byte 0xC 8.--11. 1. "CHSEL0,Select one of the 14 channel inputs for this slot."
|
|
newline
|
|
bitfld.long 0xC 1. "WCEN0,This bit enables the window compare function for slot 0." "0: Disable the window compare for slot 0.,1: Enable the window compare for slot 0."
|
|
bitfld.long 0xC 0. "SLEN0,This bit enables slot 0 for ADC conversions." "0: Disable slot 0 for ADC conversions.,1: Enable slot 0 for ADC conversions."
|
|
line.long 0x10 "SL1CFG,Slot 1 Configuration"
|
|
bitfld.long 0x10 24.--26. "ADSEL1,Select the number of measurements to average in the accumulate divide module for this slot." "0: Average in 1 measurement in the accumulate..,1: Average in 2 measurements in the accumulate..,2: Average in 4 measurements in the accumulate..,3: Average in 8 measurements in the accumulate..,4: Average in 16 measurements in the accumulate..,5: Average in 32 measurements in the accumulate..,6: Average in 64 measurements in the accumulate..,7: Average in 128 measurements in the accumulate.."
|
|
hexmask.long.byte 0x10 18.--23. 1. "TRKCYC1,Set additional input signal sampling/tracking time to the specified number of ADC clock cycles. (Note that a value of 0 in this register specifies the minimum required 5 cycles. A maximum of 64 specifies 69 cycles.)"
|
|
newline
|
|
bitfld.long 0x10 16.--17. "PRMODE1,Set the Precision Mode For Slot 1." "0: 12-bit precision mode,1: 12-bit precision mode,2: 10-bit precision mode,3: 8-bit precision mode"
|
|
hexmask.long.byte 0x10 8.--11. 1. "CHSEL1,Select one of the 14 channel inputs for this slot."
|
|
newline
|
|
bitfld.long 0x10 1. "WCEN1,This bit enables the window compare function for slot 1." "0: Disable the window compare for slot 1.,1: Enable the window compare for slot 1."
|
|
bitfld.long 0x10 0. "SLEN1,This bit enables slot 1 for ADC conversions." "0: Disable slot 1 for ADC conversions.,1: Enable slot 1 for ADC conversions."
|
|
line.long 0x14 "SL2CFG,Slot 2 Configuration"
|
|
bitfld.long 0x14 24.--26. "ADSEL2,Select the number of measurements to average in the accumulate divide module for this slot." "0: Average in 1 measurement in the accumulate..,1: Average in 2 measurements in the accumulate..,2: Average in 4 measurements in the accumulate..,3: Average in 8 measurements in the accumulate..,4: Average in 16 measurements in the accumulate..,5: Average in 32 measurements in the accumulate..,6: Average in 64 measurements in the accumulate..,7: Average in 128 measurements in the accumulate.."
|
|
hexmask.long.byte 0x14 18.--23. 1. "TRKCYC2,Set additional input signal sampling/tracking time to the specified number of ADC clock cycles. (Note that a value of 0 in this register specifies the minimum required 5 cycles. A maximum of 64 specifies 69 cycles.)"
|
|
newline
|
|
bitfld.long 0x14 16.--17. "PRMODE2,Set the Precision Mode For Slot 2." "0: 12-bit precision mode,1: 12-bit precision mode,2: 10-bit precision mode,3: 8-bit precision mode"
|
|
hexmask.long.byte 0x14 8.--11. 1. "CHSEL2,Select one of the 14 channel inputs for this slot."
|
|
newline
|
|
bitfld.long 0x14 1. "WCEN2,This bit enables the window compare function for slot 2." "0: Disable the window compare for slot 2.,1: Enable the window compare for slot 2."
|
|
bitfld.long 0x14 0. "SLEN2,This bit enables slot 2 for ADC conversions." "0: Disable slot 2 for ADC conversions.,1: Enable slot 2 for ADC conversions."
|
|
line.long 0x18 "SL3CFG,Slot 3 Configuration"
|
|
bitfld.long 0x18 24.--26. "ADSEL3,Select the number of measurements to average in the accumulate divide module for this slot." "0: Average in 1 measurement in the accumulate..,1: Average in 2 measurements in the accumulate..,2: Average in 4 measurements in the accumulate..,3: Average in 8 measurements in the accumulate..,4: Average in 16 measurements in the accumulate..,5: Average in 32 measurements in the accumulate..,6: Average in 64 measurements in the accumulate..,7: Average in 128 measurements in the accumulate.."
|
|
hexmask.long.byte 0x18 18.--23. 1. "TRKCYC3,Set additional input signal sampling/tracking time to the specified number of ADC clock cycles. (Note that a value of 0 in this register specifies the minimum required 5 cycles. A maximum of 64 specifies 69 cycles.)"
|
|
newline
|
|
bitfld.long 0x18 16.--17. "PRMODE3,Set the Precision Mode For Slot 3." "0: 12-bit precision mode,1: 12-bit precision mode,2: 10-bit precision mode,3: 8-bit precision mode"
|
|
hexmask.long.byte 0x18 8.--11. 1. "CHSEL3,Select one of the 14 channel inputs for this slot."
|
|
newline
|
|
bitfld.long 0x18 1. "WCEN3,This bit enables the window compare function for slot 3." "0: Disable the window compare for slot 3.,1: Enable the window compare for slot 3."
|
|
bitfld.long 0x18 0. "SLEN3,This bit enables slot 3 for ADC conversions." "0: Disable slot 3 for ADC conversions.,1: Enable slot 3 for ADC conversions."
|
|
line.long 0x1C "SL4CFG,Slot 4 Configuration"
|
|
bitfld.long 0x1C 24.--26. "ADSEL4,Select the number of measurements to average in the accumulate divide module for this slot." "0: Average in 1 measurement in the accumulate..,1: Average in 2 measurements in the accumulate..,2: Average in 4 measurements in the accumulate..,3: Average in 8 measurements in the accumulate..,4: Average in 16 measurements in the accumulate..,5: Average in 32 measurements in the accumulate..,6: Average in 64 measurements in the accumulate..,7: Average in 128 measurements in the accumulate.."
|
|
hexmask.long.byte 0x1C 18.--23. 1. "TRKCYC4,Set additional input signal sampling/tracking time to the specified number of ADC clock cycles. (Note that a value of 0 in this register specifies the minimum required 5 cycles. A maximum of 64 specifies 69 cycles.)"
|
|
newline
|
|
bitfld.long 0x1C 16.--17. "PRMODE4,Set the Precision Mode For Slot 4." "0: 12-bit precision mode,1: 12-bit precision mode,2: 10-bit precision mode,3: 8-bit precision mode"
|
|
hexmask.long.byte 0x1C 8.--11. 1. "CHSEL4,Select one of the 14 channel inputs for this slot."
|
|
newline
|
|
bitfld.long 0x1C 1. "WCEN4,This bit enables the window compare function for slot 4." "0: Disable the window compare for slot 4.,1: Enable the window compare for slot 4."
|
|
bitfld.long 0x1C 0. "SLEN4,This bit enables slot 4 for ADC conversions." "0: Disable slot 4 for ADC conversions.,1: Enable slot 4 for ADC conversions."
|
|
line.long 0x20 "SL5CFG,Slot 5 Configuration"
|
|
bitfld.long 0x20 24.--26. "ADSEL5,Select the number of measurements to average in the accumulate divide module for this slot." "0: Average in 1 measurement in the accumulate..,1: Average in 2 measurements in the accumulate..,2: Average in 4 measurements in the accumulate..,3: Average in 8 measurements in the accumulate..,4: Average in 16 measurements in the accumulate..,5: Average in 32 measurements in the accumulate..,6: Average in 64 measurements in the accumulate..,7: Average in 128 measurements in the accumulate.."
|
|
hexmask.long.byte 0x20 18.--23. 1. "TRKCYC5,Set additional input signal sampling/tracking time to the specified number of ADC clock cycles. (Note that a value of 0 in this register specifies the minimum required 5 cycles. A maximum of 64 specifies 69 cycles.)"
|
|
newline
|
|
bitfld.long 0x20 16.--17. "PRMODE5,Set the Precision Mode For Slot 5." "0: 12-bit precision mode,1: 12-bit precision mode,2: 10-bit precision mode,3: 8-bit precision mode"
|
|
hexmask.long.byte 0x20 8.--11. 1. "CHSEL5,Select one of the 14 channel inputs for this slot."
|
|
newline
|
|
bitfld.long 0x20 1. "WCEN5,This bit enables the window compare function for slot 5." "0: Disable the window compare for slot 5.,1: Enable the window compare for slot 5."
|
|
bitfld.long 0x20 0. "SLEN5,This bit enables slot 5 for ADC conversions." "0: Disable slot 5 for ADC conversions.,1: Enable slot 5 for ADC conversions."
|
|
line.long 0x24 "SL6CFG,Slot 6 Configuration"
|
|
bitfld.long 0x24 24.--26. "ADSEL6,Select the number of measurements to average in the accumulate divide module for this slot." "0: Average in 1 measurement in the accumulate..,1: Average in 2 measurements in the accumulate..,2: Average in 4 measurements in the accumulate..,3: Average in 8 measurements in the accumulate..,4: Average in 16 measurements in the accumulate..,5: Average in 32 measurements in the accumulate..,6: Average in 64 measurements in the accumulate..,7: Average in 128 measurements in the accumulate.."
|
|
hexmask.long.byte 0x24 18.--23. 1. "TRKCYC6,Set additional input signal sampling/tracking time to the specified number of ADC clock cycles. (Note that a value of 0 in this register specifies the minimum required 5 cycles. A maximum of 64 specifies 69 cycles.)"
|
|
newline
|
|
bitfld.long 0x24 16.--17. "PRMODE6,Set the Precision Mode For Slot 6." "0: 12-bit precision mode,1: 12-bit precision mode,2: 10-bit precision mode,3: 8-bit precision mode"
|
|
hexmask.long.byte 0x24 8.--11. 1. "CHSEL6,Select one of the 14 channel inputs for this slot."
|
|
newline
|
|
bitfld.long 0x24 1. "WCEN6,This bit enables the window compare function for slot 6." "0: Disable the window compare for slot 6.,1: Enable the window compare for slot 6."
|
|
bitfld.long 0x24 0. "SLEN6,This bit enables slot 6 for ADC conversions." "0: Disable slot 6 for ADC conversions.,1: Enable slot 6 for ADC conversions."
|
|
line.long 0x28 "SL7CFG,Slot 7 Configuration"
|
|
bitfld.long 0x28 24.--26. "ADSEL7,Select the number of measurements to average in the accumulate divide module for this slot." "0: Average in 1 measurement in the accumulate..,1: Average in 2 measurements in the accumulate..,2: Average in 4 measurements in the accumulate..,3: Average in 8 measurements in the accumulate..,4: Average in 16 measurements in the accumulate..,5: Average in 32 measurements in the accumulate..,6: Average in 64 measurements in the accumulate..,7: Average in 128 measurements in the accumulate.."
|
|
hexmask.long.byte 0x28 18.--23. 1. "TRKCYC7,Set additional input signal sampling/tracking time to the specified number of ADC clock cycles. (Note that a value of 0 in this register specifies the minimum required 5 cycles. A maximum of 64 specifies 69 cycles.)"
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|
newline
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bitfld.long 0x28 16.--17. "PRMODE7,Set the Precision Mode For Slot 7." "0: 12-bit precision mode,1: 12-bit precision mode,2: 10-bit precision mode,3: 8-bit precision mode"
|
|
hexmask.long.byte 0x28 8.--11. 1. "CHSEL7,Select one of the 14 channel inputs for this slot."
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|
newline
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|
bitfld.long 0x28 1. "WCEN7,This bit enables the window compare function for slot 7." "0: Disable the window compare for slot 7.,1: Enable the window compare for slot 7."
|
|
bitfld.long 0x28 0. "SLEN7,This bit enables slot 7 for ADC conversions." "0: Disable slot 7 for ADC conversions.,1: Enable slot 7 for ADC conversions."
|
|
line.long 0x2C "WULIM,Window Comparator Upper Limits"
|
|
hexmask.long.tbyte 0x2C 0.--19. 1. "ULIM,Sets the upper limit for the window comparator."
|
|
line.long 0x30 "WLLIM,Window Comparator Lower Limits"
|
|
hexmask.long.tbyte 0x30 0.--19. 1. "LLIM,Sets the lower limit for the window comparator."
|
|
line.long 0x34 "SCWLIM,Scale Window Comparator Limits"
|
|
bitfld.long 0x34 0. "SCWLIMEN,Scale the window limits compare values per precision mode. When set to 0x0 (default) the values in the 20-bit limits registers will compare directly with the FIFO values regardless of the precision mode the slot is configured to. When set to.." "0,1"
|
|
line.long 0x38 "FIFO,The ADC FIFO Register contains the slot number and fifo data for the oldest conversion data in the FIFO. The COUNT field indicates the total number of valid entries in the FIFO. A write to this register will pop one of the FIFO entries off the FIFO.."
|
|
bitfld.long 0x38 31. "RSVD,RESERVED." "0,1"
|
|
bitfld.long 0x38 28.--30. "SLOTNUM,Slot number associated with this FIFO data." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x38 20.--27. 1. "COUNT,Number of valid entries in the ADC FIFO."
|
|
hexmask.long.tbyte 0x38 0.--19. 1. "DATA,Oldest data in the FIFO."
|
|
line.long 0x3C "FIFOPR,This is a Pop Read mirrored copy of the ADCFIFO register with the only difference being that reading this register will result in a simultaneous FIFO POP which is also achieved by writing to the ADCFIFO Register. Note: The DFIFORDEN bit must be.."
|
|
bitfld.long 0x3C 31. "RSVDPR,RESERVED." "0,1"
|
|
bitfld.long 0x3C 28.--30. "SLOTNUMPR,Slot number associated with this FIFO data." "0,1,2,3,4,5,6,7"
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|
newline
|
|
hexmask.long.byte 0x3C 20.--27. 1. "COUNT,Number of valid entries in the ADC FIFO."
|
|
hexmask.long.tbyte 0x3C 0.--19. 1. "DATA,Oldest data in the FIFO."
|
|
line.long 0x40 "INTTRIGTIMER,ADC-Internal Repeating Trigger Timer Configuration"
|
|
bitfld.long 0x40 31. "TIMEREN,ADC-internal trigger timer enable." "0: Disable the ADC-internal trigger timer.,1: Enable the ADC-internal trigger timer."
|
|
bitfld.long 0x40 16.--18. "CLKDIV,Configure number of divide-by-2 of clock source as input to trigger counter. (Max value of 5.) A value of 0 in this register would not divide down the ADC input clock. A value of 1 would divide the ADC input clock frequency by 2. A value of 5.." "0,1,2,3,4,5,6,7"
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|
newline
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hexmask.long.word 0x40 0.--9. 1. "TIMERMAX,Trigger counter count max used as initial condition to trigger. Also used repeatedly each time counter reaches it to restart trigger timer at zero. To update this value first disable the INTTRIGTIMER by setting TIMEREN to DIS change TIMERMAX .."
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|
group.long 0x60++0xF
|
|
line.long 0x0 "ZXCFG,Zero Crossing Comparator Configuration"
|
|
bitfld.long 0x0 4. "ZXCHANSEL,Select which slots to use for zero crossing measurement. 0 enables zero crossing detection on slots 0 and 2. 1 enables zero crossing detection on slots 1 and 3." "0,1"
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|
bitfld.long 0x0 0. "ZXEN,Enable the ZX comparator" "0,1"
|
|
line.long 0x4 "ZXLIM,Zero Crossing Comparator Limits"
|
|
hexmask.long.word 0x4 16.--27. 1. "UZXC,Sets the upper integer sample limit for the ZX comparator. Note that these values are raw ADC values whose bounds are specified by PRMODE but not maniupulated by accumulate/divide logic. Therefore there is no oversampling and no binary point in.."
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|
hexmask.long.word 0x4 0.--11. 1. "LZXC,Sets the lower integer sample limit for the ZX comparator. Note that these values are raw ADC values whose bounds are specified by PRMODE but not maniupulated by accumulate/divide logic. Therefore there is no oversampling and no binary point in.."
|
|
line.long 0x8 "GAINCFG,PGA Gain Configuration"
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|
bitfld.long 0x8 4. "UPDATEMODE,PGA update mode" "0: Immediate update mode. Once gain is written it..,1: Update gain only at detected zero crossing as.."
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|
bitfld.long 0x8 0. "PGACTRLEN,Enable PGA gain updates." "0,1"
|
|
line.long 0xC "GAIN,PGA Gain Codes"
|
|
hexmask.long.byte 0xC 24.--30. 1. "HGBDELTA,Specifies the high gain code as an delta from the LGB field for channel B (slot 3)."
|
|
hexmask.long.byte 0xC 16.--22. 1. "LGB,Specifies the low gain code (0 to 102 decimal specifies -6.0 dB to 45.0 dB in half-dB increments) for channel B (slot 2)."
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|
newline
|
|
hexmask.long.byte 0xC 8.--14. 1. "HGADELTA,Specifies the high gain code as an delta from the LGA field for channel A (slot 1)."
|
|
hexmask.long.byte 0xC 0.--6. 1. "LGA,Specifies the low gain code (0 to 102 decimal specifies -6.0 dB to 45.0 dB in half-dB increments) for channel A (slot 0)."
|
|
group.long 0xA4++0xF
|
|
line.long 0x0 "SATCFG,Saturation Comparator Configuration"
|
|
bitfld.long 0x0 4. "SATCHANSEL,Select which slots to use for saturation measurement. 0 enables saturation on slots 0 and 2. 1 enables saturation on slots 1 and 3." "0,1"
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|
bitfld.long 0x0 0. "SATEN,Enable the saturation comparator" "0,1"
|
|
line.long 0x4 "SATLIM,Saturation Comparator Limits"
|
|
hexmask.long.word 0x4 16.--27. 1. "USATC,Sets the upper integer sample limit for the saturation comparator. Note that these values are raw ADC values whose bounds are specified by PRMODE but not manipulated by accumulate/divide logic. Therefore there is no oversampling and no binary.."
|
|
hexmask.long.word 0x4 0.--11. 1. "LSATC,Sets the lower integer sample limit for the saturation comparator. Note that these values are raw ADC values whose bounds are specified by PRMODE but not manipulated by accumulate/divide logic. Therefore there is no oversampling and no binary.."
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|
line.long 0x8 "SATMAX,Saturation Comparator Event Counter Limits"
|
|
hexmask.long.word 0x8 16.--27. 1. "SATCBMAX,Sets the number of saturation events that may occur before a SATCB interrupt occurs. Once this interrupt occurs the saturation event counter must be cleared by writing the SATCLR register. A value of 0 is invalid and will cause the saturation.."
|
|
hexmask.long.word 0x8 0.--11. 1. "SATCAMAX,Sets the number of saturation events that may occur before a SATCA interrupt occurs. Once this interrupt occurs the saturation event counter must be cleared by writing the SATCLR register. A value of 0 is invalid and will cause the saturation.."
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|
line.long 0xC "SATCLR,Clears the saturation event counter registers"
|
|
bitfld.long 0xC 1. "SATCBCLR,Clear saturation event counter register for channel B (slots 2 or 3 depending on SATCHANSEL)" "0,1"
|
|
bitfld.long 0xC 0. "SATCACLR,Clear saturation event counter register for channel A (slots 0 or 1 depending on SATCHANSEL)" "0,1"
|
|
group.long 0x200++0xF
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 11. "SATCB,Saturation - Channel B (Slots 2 or 3)" "0: No-Saturation,1: Saturation as specified by SAT configuration.."
|
|
bitfld.long 0x0 10. "SATCA,Saturation - Channel A (Slots 0 or 1)" "0: No Saturation,1: Saturation as specified by SAT configuration.."
|
|
newline
|
|
bitfld.long 0x0 9. "ZXCB,Zero Crossing - Channel B (Slots 2 or 3)" "0: Non Zero Crossing,1: Zero Crossing as specified by ZX configuration.."
|
|
bitfld.long 0x0 8. "ZXCA,Zero Crossing - Channel A (Slots 0 or 1)" "0: Non Zero Crossing,1: Zero Crossing as specified by ZX configuration.."
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|
newline
|
|
bitfld.long 0x0 7. "DERR,DMA Error Condition" "0: DMA Error Condition did not Occurred,1: DMA Error Condition Occurred"
|
|
bitfld.long 0x0 6. "DCMP,DMA Transfer Complete" "0: DMA completion is pending or not triggered.,1: DMA Completed a transfer"
|
|
newline
|
|
bitfld.long 0x0 5. "WCINC,Window comparator voltage incursion interrupt." "0: Not a Window comparator voltage incursion..,1: Window comparator voltage incursion interrupt."
|
|
bitfld.long 0x0 4. "WCEXC,Window comparator voltage excursion interrupt." "0: Not a Window comparator voltage excursion..,1: Window comparator voltage excursion interrupt."
|
|
newline
|
|
bitfld.long 0x0 3. "FIFOOVR2,FIFO 100 percent full interrupt." "0: Not a FIFO 100 percent full interrupt.,1: FIFO 100 percent full interrupt."
|
|
bitfld.long 0x0 2. "FIFOOVR1,FIFO 75 percent full interrupt." "0: Not FIFO 75 percent full interrupt.,1: FIFO 75 percent full interrupt."
|
|
newline
|
|
bitfld.long 0x0 1. "SCNCMP,ADC scan complete interrupt." "0: No ADC scan complete interrupt.,1: ADC scan complete interrupt."
|
|
bitfld.long 0x0 0. "CNVCMP,ADC conversion complete interrupt." "0: No ADC conversion complete interrupt.,1: ADC conversion complete interrupt."
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 11. "SATCB,Saturation - Channel B (Slots 2 or 3)" "0: No-Saturation,1: Saturation as specified by SAT configuration.."
|
|
bitfld.long 0x4 10. "SATCA,Saturation - Channel A (Slots 0 or 1)" "0: No Saturation,1: Saturation as specified by SAT configuration.."
|
|
newline
|
|
bitfld.long 0x4 9. "ZXCB,Zero Crossing - Channel B (Slots 2 or 3)" "0: Non Zero Crossing,1: Zero Crossing as specified by ZX configuration.."
|
|
bitfld.long 0x4 8. "ZXCA,Zero Crossing - Channel A (Slots 0 or 1)" "0: Non Zero Crossing,1: Zero Crossing as specified by ZX configuration.."
|
|
newline
|
|
bitfld.long 0x4 7. "DERR,DMA Error Condition" "0: DMA Error Condition did not Occurred,1: DMA Error Condition Occurred"
|
|
bitfld.long 0x4 6. "DCMP,DMA Transfer Complete" "0: DMA completion is pending or not triggered.,1: DMA Completed a transfer"
|
|
newline
|
|
bitfld.long 0x4 5. "WCINC,Window comparator voltage incursion interrupt." "0: Not a Window comparator voltage incursion..,1: Window comparator voltage incursion interrupt."
|
|
bitfld.long 0x4 4. "WCEXC,Window comparator voltage excursion interrupt." "0: Not a Window comparator voltage excursion..,1: Window comparator voltage excursion interrupt."
|
|
newline
|
|
bitfld.long 0x4 3. "FIFOOVR2,FIFO 100 percent full interrupt." "0: Not a FIFO 100 percent full interrupt.,1: FIFO 100 percent full interrupt."
|
|
bitfld.long 0x4 2. "FIFOOVR1,FIFO 75 percent full interrupt." "0: Not FIFO 75 percent full interrupt.,1: FIFO 75 percent full interrupt."
|
|
newline
|
|
bitfld.long 0x4 1. "SCNCMP,ADC scan complete interrupt." "0: No ADC scan complete interrupt.,1: ADC scan complete interrupt."
|
|
bitfld.long 0x4 0. "CNVCMP,ADC conversion complete interrupt." "0: No ADC conversion complete interrupt.,1: ADC conversion complete interrupt."
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 11. "SATCB,Saturation - Channel B (Slots 2 or 3)" "0: No-Saturation,1: Saturation as specified by SAT configuration.."
|
|
bitfld.long 0x8 10. "SATCA,Saturation - Channel A (Slots 0 or 1)" "0: No Saturation,1: Saturation as specified by SAT configuration.."
|
|
newline
|
|
bitfld.long 0x8 9. "ZXCB,Zero Crossing - Channel B (Slots 2 or 3)" "0: Non Zero Crossing,1: Zero Crossing as specified by ZX configuration.."
|
|
bitfld.long 0x8 8. "ZXCA,Zero Crossing - Channel A (Slots 0 or 1)" "0: Non Zero Crossing,1: Zero Crossing as specified by ZX configuration.."
|
|
newline
|
|
bitfld.long 0x8 7. "DERR,DMA Error Condition" "0: DMA Error Condition did not Occurred,1: DMA Error Condition Occurred"
|
|
bitfld.long 0x8 6. "DCMP,DMA Transfer Complete" "0: DMA completion is pending or not triggered.,1: DMA Completed a transfer"
|
|
newline
|
|
bitfld.long 0x8 5. "WCINC,Window comparator voltage incursion interrupt." "0: Not a Window comparator voltage incursion..,1: Window comparator voltage incursion interrupt."
|
|
bitfld.long 0x8 4. "WCEXC,Window comparator voltage excursion interrupt." "0: Not a Window comparator voltage excursion..,1: Window comparator voltage excursion interrupt."
|
|
newline
|
|
bitfld.long 0x8 3. "FIFOOVR2,FIFO 100 percent full interrupt." "0: Not a FIFO 100 percent full interrupt.,1: FIFO 100 percent full interrupt."
|
|
bitfld.long 0x8 2. "FIFOOVR1,FIFO 75 percent full interrupt." "0: Not FIFO 75 percent full interrupt.,1: FIFO 75 percent full interrupt."
|
|
newline
|
|
bitfld.long 0x8 1. "SCNCMP,ADC scan complete interrupt." "0: No ADC scan complete interrupt.,1: ADC scan complete interrupt."
|
|
bitfld.long 0x8 0. "CNVCMP,ADC conversion complete interrupt." "0: No ADC conversion complete interrupt.,1: ADC conversion complete interrupt."
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 11. "SATCB,Saturation - Channel B (Slots 2 or 3)" "0: No-Saturation,1: Saturation as specified by SAT configuration.."
|
|
bitfld.long 0xC 10. "SATCA,Saturation - Channel A (Slots 0 or 1)" "0: No Saturation,1: Saturation as specified by SAT configuration.."
|
|
newline
|
|
bitfld.long 0xC 9. "ZXCB,Zero Crossing - Channel B (Slots 2 or 3)" "0: Non Zero Crossing,1: Zero Crossing as specified by ZX configuration.."
|
|
bitfld.long 0xC 8. "ZXCA,Zero Crossing - Channel A (Slots 0 or 1)" "0: Non Zero Crossing,1: Zero Crossing as specified by ZX configuration.."
|
|
newline
|
|
bitfld.long 0xC 7. "DERR,DMA Error Condition" "0: DMA Error Condition did not Occurred,1: DMA Error Condition Occurred"
|
|
bitfld.long 0xC 6. "DCMP,DMA Transfer Complete" "0: DMA completion is pending or not triggered.,1: DMA Completed a transfer"
|
|
newline
|
|
bitfld.long 0xC 5. "WCINC,Window comparator voltage incursion interrupt." "0: Not a Window comparator voltage incursion..,1: Window comparator voltage incursion interrupt."
|
|
bitfld.long 0xC 4. "WCEXC,Window comparator voltage excursion interrupt." "0: Not a Window comparator voltage excursion..,1: Window comparator voltage excursion interrupt."
|
|
newline
|
|
bitfld.long 0xC 3. "FIFOOVR2,FIFO 100 percent full interrupt." "0: Not a FIFO 100 percent full interrupt.,1: FIFO 100 percent full interrupt."
|
|
bitfld.long 0xC 2. "FIFOOVR1,FIFO 75 percent full interrupt." "0: Not FIFO 75 percent full interrupt.,1: FIFO 75 percent full interrupt."
|
|
newline
|
|
bitfld.long 0xC 1. "SCNCMP,ADC scan complete interrupt." "0: No ADC scan complete interrupt.,1: ADC scan complete interrupt."
|
|
bitfld.long 0xC 0. "CNVCMP,ADC conversion complete interrupt." "0: No ADC conversion complete interrupt.,1: ADC conversion complete interrupt."
|
|
group.long 0x240++0x7
|
|
line.long 0x0 "DMATRIGEN,DMA Trigger Enable"
|
|
bitfld.long 0x0 1. "DFIFOFULL,Trigger DMA upon FIFO 100 percent Full" "0,1"
|
|
bitfld.long 0x0 0. "DFIFO75,Trigger DMA upon FIFO 75 percent Full" "0,1"
|
|
line.long 0x4 "DMATRIGSTAT,DMA Trigger Status"
|
|
bitfld.long 0x4 1. "DFULLSTAT,Triggered DMA from FIFO 100 percent Full" "0,1"
|
|
bitfld.long 0x4 0. "D75STAT,Triggered DMA from FIFO 75 percent Full" "0,1"
|
|
group.long 0x280++0x3
|
|
line.long 0x0 "DMACFG,DMA Configuration"
|
|
bitfld.long 0x0 18. "DPWROFF,Power Off the ADC System upon DMACPL." "0,1"
|
|
bitfld.long 0x0 17. "DMAMSK,Mask the FIFOCNT and SLOTNUM when transferring FIFO contents to memory" "0: FIFO Contents are copied directly to memory..,1: Only the FIFODATA contents are copied to memory.."
|
|
newline
|
|
bitfld.long 0x0 9. "DMADYNPRI,Enables dynamic priority based on FIFO fullness. When FIFO is full priority is automatically set to HIGH. Otherwise DMAPRI is used." "0: Disable dynamic priority (use DMAPRI setting only),1: Enable dynamic priority"
|
|
bitfld.long 0x0 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
|
|
newline
|
|
bitfld.long 0x0 2. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction,1: Memory to Peripheral transaction"
|
|
bitfld.long 0x0 0. "DMAEN,DMA Enable" "0: Disable DMA Function,1: Enable DMA Function"
|
|
group.long 0x288++0xB
|
|
line.long 0x0 "DMATOTCOUNT,DMA Total Transfer Count"
|
|
hexmask.long.word 0x0 2.--17. 1. "TOTCOUNT,Total Transfer Count"
|
|
line.long 0x4 "DMATARGADDR,DMA Target Address"
|
|
hexmask.long.byte 0x4 28.--31. 1. "UTARGADDR,SRAM Target"
|
|
hexmask.long 0x4 0.--27. 1. "LTARGADDR,DMA Target Address"
|
|
line.long 0x8 "DMASTAT,DMA Status"
|
|
bitfld.long 0x8 2. "DMAERR,DMA Error" "0,1"
|
|
bitfld.long 0x8 1. "DMACPL,DMA Transfer Complete" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "DMATIP,DMA Transfer In Progress" "0,1"
|
|
tree.end
|
|
tree "APBDMA (APB DMA Register Interfaces)"
|
|
base ad:0x40011000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "BBVALUE,Control"
|
|
hexmask.long.byte 0x0 16.--23. 1. "PIN,PIO values"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATAOUT,Data Output Values"
|
|
line.long 0x4 "BBSETCLEAR,Set/Clear"
|
|
hexmask.long.byte 0x4 16.--23. 1. "CLEAR,Write 1 to Clear PIO value"
|
|
hexmask.long.byte 0x4 0.--7. 1. "SET,Write 1 to Set PIO value (set hier priority than clear if both bit set)"
|
|
line.long 0x8 "BBINPUT,PIO Input Values"
|
|
hexmask.long.byte 0x8 0.--7. 1. "DATAIN,PIO values"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "DEBUGDATA,PIO Input Values"
|
|
hexmask.long 0x0 0.--31. 1. "DEBUGDATA,Debug Data"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "DEBUG,PIO Input Values"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DEBUGEN,Debug Enable"
|
|
tree.end
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMA4B2KP")||cpuis("AMAP42KK")||cpuis("AMAP42KP"))
|
|
tree "AUDADC (Audio Analog-to-Digital Converter)"
|
|
base ad:0x40210000
|
|
group.long 0x0++0x4B
|
|
line.long 0x0 "CFG,The Audio ADC Configuration Register contains the software control for selecting the clock frequency used for the SAR conversions. the trigger polarity. the trigger select. the reference voltage select. the low power mode. the operating mode (single.."
|
|
bitfld.long 0x0 24.--25. "CLKSEL,Select the source and frequency for the AUDADC clock. All values not enumerated below are undefined.Whenever changing the clock source to HFRC2 the MISC_HFRC2FRC bit in the CLKGEN module must first be set. The sequence for changing the clock.." "0: Off mode. The HFRC HFRC2 or high frequency XTAL..,1: HFRC Clock,2: High frequency XTAL (nominally 24.567 MHz but..,3: HFRC2 Clock"
|
|
bitfld.long 0x0 20. "RPTTRIGSEL,This bit selects which periodic trigger to use with RPTEN = 1." "0: Trigger from on-chip timer.,1: Trigger from AUDADC-internal timer."
|
|
newline
|
|
bitfld.long 0x0 19. "TRIGPOL,This bit selects the AUDADC trigger polarity for external off chip triggers." "0: Trigger on rising edge.,1: Trigger on falling edge."
|
|
bitfld.long 0x0 16.--18. "TRIGSEL,Select the AUDADC trigger source." "0: Off chip External Trigger0 (ADC_ET0),1: Off chip External Trigger1 (ADC_ET1),2: Off chip External Trigger2 (ADC_ET2),3: Off chip External Trigger3 (ADC_ET3),4: Voltage Comparator Output,?,?,7: Software Trigger"
|
|
newline
|
|
bitfld.long 0x0 13. "SAMPMODE,Audio ADC sampling mode. Changes to this control bit are applied when the audio ADC is not performing conversions. This is the only control bit which is properly synchronized to AUDADC operation." "0: Max of 2 low-gain PGA channels configured on..,1: Max of 2 low-gain and 2 high-gain PGA channels."
|
|
bitfld.long 0x0 12. "DFIFORDEN,Destructive FIFO Read Enable. Setting this will enable FIFO pop upon reading the FIFOPR register." "0: Destructive Reads are prevented. Reads to the..,1: Reads to the FIFOPR registger will automatically.."
|
|
newline
|
|
bitfld.long 0x0 4. "CKMODE,Clock mode register" "0: Disable the clock between scans for LPMODE0. Set..,1: Low Latency Clock Mode. When set HFRC and the.."
|
|
bitfld.long 0x0 3. "LPMODE,Select power mode to enter between active scans." "0: Low Power Mode 0. Leaves the AUDADC fully..,1: Low Power Mode 1. Powers down all circuity and.."
|
|
newline
|
|
bitfld.long 0x0 2. "RPTEN,This bit enables Repeating Scan Mode." "0: In Single Scan Mode the AUDADC will complete a..,1: In Repeating Scan Mode the AUDADC will complete.."
|
|
bitfld.long 0x0 0. "ADCEN,This bit enables the AUDADC module. While the AUDADC is enabled the ADCCFG and SLOT Configuration regsiter settings must remain stable and unchanged. All configuration register settings slot configuration settings and window comparison settings.." "0: Disable the AUDADC module.,1: Enable the AUDADC module."
|
|
line.long 0x4 "STAT,This register indicates the basic power status for the AUDADC. For detailed power status. see the power control power status register. AUDADC power mode 0 indicates the AUDADC is in its full power state and is ready to process scans. AUDADC Power.."
|
|
bitfld.long 0x4 0. "PWDSTAT,Indicates the power-status of the AUDADC." "0: Powered on.,1: AUDADC Low Power Mode 1."
|
|
line.long 0x8 "SWT,This register enables initiating an AUDADC scan through software."
|
|
hexmask.long.byte 0x8 0.--7. 1. "SWT,Writing 0x37 to this register generates a software trigger."
|
|
line.long 0xC "SL0CFG,Slot 0 Configuration"
|
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bitfld.long 0xC 24.--26. "ADSEL0,Select the number of measurements to average in the accumulate divide module for this slot." "0: Average in 1 measurement in the accumulate..,1: Average in 2 measurements in the accumulate..,2: Average in 4 measurements in the accumulate..,3: Average in 8 measurements in the accumulate..,4: Average in 16 measurements in the accumulate..,5: Average in 32 measurements in the accumulate..,6: Average in 64 measurements in the accumulate..,7: Average in 128 measurements in the accumulate.."
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hexmask.long.byte 0xC 18.--23. 1. "TRKCYC0,Set additional input signal sampling/tracking time to the specified number of AUDADC clock cycles. (Note that a value of 0 in this register specifies the minimum required 5 cycles. A maximum of 64 specifies 69 cycles.)"
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newline
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bitfld.long 0xC 16.--17. "PRMODE0,Set the Precision Mode For Slot 0." "0: 12-bit precision mode,1: 12-bit precision mode,2: 10-bit precision mode,3: 8-bit precision mode"
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hexmask.long.byte 0xC 8.--11. 1. "CHSEL0,Select one of the 14 channel inputs for this slot."
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newline
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bitfld.long 0xC 1. "WCEN0,This bit enables the window compare function for slot 0." "0: Disable the window compare for slot 0.,1: Enable the window compare for slot 0."
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bitfld.long 0xC 0. "SLEN0,This bit enables slot 0 for AUDADC conversions." "0: Disable slot 0 for AUDADC conversions.,1: Enable slot 0 for AUDADC conversions."
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line.long 0x10 "SL1CFG,Slot 1 Configuration"
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bitfld.long 0x10 24.--26. "ADSEL1,Select the number of measurements to average in the accumulate divide module for this slot." "0: Average in 1 measurement in the accumulate..,1: Average in 2 measurements in the accumulate..,2: Average in 4 measurements in the accumulate..,3: Average in 8 measurements in the accumulate..,4: Average in 16 measurements in the accumulate..,5: Average in 32 measurements in the accumulate..,6: Average in 64 measurements in the accumulate..,7: Average in 128 measurements in the accumulate.."
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hexmask.long.byte 0x10 18.--23. 1. "TRKCYC1,Set additional input signal sampling/tracking time to the specified number of AUDADC clock cycles. (Note that a value of 0 in this register specifies the minimum required 5 cycles. A maximum of 64 specifies 69 cycles.)"
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newline
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bitfld.long 0x10 16.--17. "PRMODE1,Set the Precision Mode For Slot 1." "0: 12-bit precision mode,1: 12-bit precision mode,2: 10-bit precision mode,3: 8-bit precision mode"
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hexmask.long.byte 0x10 8.--11. 1. "CHSEL1,Select one of the 14 channel inputs for this slot."
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newline
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bitfld.long 0x10 1. "WCEN1,This bit enables the window compare function for slot 1." "0: Disable the window compare for slot 1.,1: Enable the window compare for slot 1."
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bitfld.long 0x10 0. "SLEN1,This bit enables slot 1 for AUDADC conversions." "0: Disable slot 1 for AUDADC conversions.,1: Enable slot 1 for AUDADC conversions."
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line.long 0x14 "SL2CFG,Slot 2 Configuration"
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bitfld.long 0x14 24.--26. "ADSEL2,Select the number of measurements to average in the accumulate divide module for this slot." "0: Average in 1 measurement in the accumulate..,1: Average in 2 measurements in the accumulate..,2: Average in 4 measurements in the accumulate..,3: Average in 8 measurements in the accumulate..,4: Average in 16 measurements in the accumulate..,5: Average in 32 measurements in the accumulate..,6: Average in 64 measurements in the accumulate..,7: Average in 128 measurements in the accumulate.."
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hexmask.long.byte 0x14 18.--23. 1. "TRKCYC2,Set additional input signal sampling/tracking time to the specified number of AUDADC clock cycles. (Note that a value of 0 in this register specifies the minimum required 5 cycles. A maximum of 64 specifies 69 cycles.)"
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newline
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bitfld.long 0x14 16.--17. "PRMODE2,Set the Precision Mode For Slot 2." "0: 12-bit precision mode,1: 12-bit precision mode,2: 10-bit precision mode,3: 8-bit precision mode"
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hexmask.long.byte 0x14 8.--11. 1. "CHSEL2,Select one of the 14 channel inputs for this slot."
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newline
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bitfld.long 0x14 1. "WCEN2,This bit enables the window compare function for slot 2." "0: Disable the window compare for slot 2.,1: Enable the window compare for slot 2."
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bitfld.long 0x14 0. "SLEN2,This bit enables slot 2 for AUDADC conversions." "0: Disable slot 2 for AUDADC conversions.,1: Enable slot 2 for AUDADC conversions."
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line.long 0x18 "SL3CFG,Slot 3 Configuration"
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bitfld.long 0x18 24.--26. "ADSEL3,Select the number of measurements to average in the accumulate divide module for this slot." "0: Average in 1 measurement in the accumulate..,1: Average in 2 measurements in the accumulate..,2: Average in 4 measurements in the accumulate..,3: Average in 8 measurements in the accumulate..,4: Average in 16 measurements in the accumulate..,5: Average in 32 measurements in the accumulate..,6: Average in 64 measurements in the accumulate..,7: Average in 128 measurements in the accumulate.."
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hexmask.long.byte 0x18 18.--23. 1. "TRKCYC3,Set additional input signal sampling/tracking time to the specified number of AUDADC clock cycles. (Note that a value of 0 in this register specifies the minimum required 5 cycles. A maximum of 64 specifies 69 cycles.)"
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newline
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bitfld.long 0x18 16.--17. "PRMODE3,Set the Precision Mode For Slot 3." "0: 12-bit precision mode,1: 12-bit precision mode,2: 10-bit precision mode,3: 8-bit precision mode"
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hexmask.long.byte 0x18 8.--11. 1. "CHSEL3,Select one of the 14 channel inputs for this slot."
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newline
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bitfld.long 0x18 1. "WCEN3,This bit enables the window compare function for slot 3." "0: Disable the window compare for slot 3.,1: Enable the window compare for slot 3."
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bitfld.long 0x18 0. "SLEN3,This bit enables slot 3 for AUDADC conversions." "0: Disable slot 3 for AUDADC conversions.,1: Enable slot 3 for AUDADC conversions."
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line.long 0x1C "SL4CFG,Slot 4 Configuration"
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bitfld.long 0x1C 24.--26. "ADSEL4,Select the number of measurements to average in the accumulate divide module for this slot." "0: Average in 1 measurement in the accumulate..,1: Average in 2 measurements in the accumulate..,2: Average in 4 measurements in the accumulate..,3: Average in 8 measurements in the accumulate..,4: Average in 16 measurements in the accumulate..,5: Average in 32 measurements in the accumulate..,6: Average in 64 measurements in the accumulate..,7: Average in 128 measurements in the accumulate.."
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hexmask.long.byte 0x1C 18.--23. 1. "TRKCYC4,Set additional input signal sampling/tracking time to the specified number of AUDADC clock cycles. (Note that a value of 0 in this register specifies the minimum required 5 cycles. A maximum of 64 specifies 69 cycles.)"
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newline
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bitfld.long 0x1C 16.--17. "PRMODE4,Set the Precision Mode For Slot 4." "0: 12-bit precision mode,1: 12-bit precision mode,2: 10-bit precision mode,3: 8-bit precision mode"
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hexmask.long.byte 0x1C 8.--11. 1. "CHSEL4,Select one of the 14 channel inputs for this slot."
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newline
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bitfld.long 0x1C 1. "WCEN4,This bit enables the window compare function for slot 4." "0: Disable the window compare for slot 4.,1: Enable the window compare for slot 4."
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bitfld.long 0x1C 0. "SLEN4,This bit enables slot 4 for AUDADC conversions." "0: Disable slot 4 for AUDADC conversions.,1: Enable slot 4 for AUDADC conversions."
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line.long 0x20 "SL5CFG,Slot 5 Configuration"
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bitfld.long 0x20 24.--26. "ADSEL5,Select the number of measurements to average in the accumulate divide module for this slot." "0: Average in 1 measurement in the accumulate..,1: Average in 2 measurements in the accumulate..,2: Average in 4 measurements in the accumulate..,3: Average in 8 measurements in the accumulate..,4: Average in 16 measurements in the accumulate..,5: Average in 32 measurements in the accumulate..,6: Average in 64 measurements in the accumulate..,7: Average in 128 measurements in the accumulate.."
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hexmask.long.byte 0x20 18.--23. 1. "TRKCYC5,Set additional input signal sampling/tracking time to the specified number of AUDADC clock cycles. (Note that a value of 0 in this register specifies the minimum required 5 cycles. A maximum of 64 specifies 69 cycles.)"
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newline
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bitfld.long 0x20 16.--17. "PRMODE5,Set the Precision Mode For Slot 5." "0: 12-bit precision mode,1: 12-bit precision mode,2: 10-bit precision mode,3: 8-bit precision mode"
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hexmask.long.byte 0x20 8.--11. 1. "CHSEL5,Select one of the 14 channel inputs for this slot."
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newline
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bitfld.long 0x20 1. "WCEN5,This bit enables the window compare function for slot 5." "0: Disable the window compare for slot 5.,1: Enable the window compare for slot 5."
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bitfld.long 0x20 0. "SLEN5,This bit enables slot 5 for AUDADC conversions." "0: Disable slot 5 for AUDADC conversions.,1: Enable slot 5 for AUDADC conversions."
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line.long 0x24 "SL6CFG,Slot 6 Configuration"
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bitfld.long 0x24 24.--26. "ADSEL6,Select the number of measurements to average in the accumulate divide module for this slot." "0: Average in 1 measurement in the accumulate..,1: Average in 2 measurements in the accumulate..,2: Average in 4 measurements in the accumulate..,3: Average in 8 measurements in the accumulate..,4: Average in 16 measurements in the accumulate..,5: Average in 32 measurements in the accumulate..,6: Average in 64 measurements in the accumulate..,7: Average in 128 measurements in the accumulate.."
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hexmask.long.byte 0x24 18.--23. 1. "TRKCYC6,Set additional input signal sampling/tracking time to the specified number of AUDADC clock cycles. (Note that a value of 0 in this register specifies the minimum required 5 cycles. A maximum of 64 specifies 69 cycles.)"
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newline
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bitfld.long 0x24 16.--17. "PRMODE6,Set the Precision Mode For Slot 6." "0: 12-bit precision mode,1: 12-bit precision mode,2: 10-bit precision mode,3: 8-bit precision mode"
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hexmask.long.byte 0x24 8.--11. 1. "CHSEL6,Select one of the 14 channel inputs for this slot."
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newline
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bitfld.long 0x24 1. "WCEN6,This bit enables the window compare function for slot 6." "0: Disable the window compare for slot 6.,1: Enable the window compare for slot 6."
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bitfld.long 0x24 0. "SLEN6,This bit enables slot 6 for AUDADC conversions." "0: Disable slot 6 for AUDADC conversions.,1: Enable slot 6 for AUDADC conversions."
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line.long 0x28 "SL7CFG,Slot 7 Configuration"
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bitfld.long 0x28 24.--26. "ADSEL7,Select the number of measurements to average in the accumulate divide module for this slot." "0: Average in 1 measurement in the accumulate..,1: Average in 2 measurements in the accumulate..,2: Average in 4 measurements in the accumulate..,3: Average in 8 measurements in the accumulate..,4: Average in 16 measurements in the accumulate..,5: Average in 32 measurements in the accumulate..,6: Average in 64 measurements in the accumulate..,7: Average in 128 measurements in the accumulate.."
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hexmask.long.byte 0x28 18.--23. 1. "TRKCYC7,Set additional input signal sampling/tracking time to the specified number of AUDADC clock cycles. (Note that a value of 0 in this register specifies the minimum required 5 cycles. A maximum of 64 specifies 69 cycles.)"
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newline
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bitfld.long 0x28 16.--17. "PRMODE7,Set the Precision Mode For Slot 7." "0: 12-bit precision mode,1: 12-bit precision mode,2: 10-bit precision mode,3: 8-bit precision mode"
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hexmask.long.byte 0x28 8.--11. 1. "CHSEL7,Select one of the 14 channel inputs for this slot."
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newline
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bitfld.long 0x28 1. "WCEN7,This bit enables the window compare function for slot 7." "0: Disable the window compare for slot 7.,1: Enable the window compare for slot 7."
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bitfld.long 0x28 0. "SLEN7,This bit enables slot 7 for AUDADC conversions." "0: Disable slot 7 for AUDADC conversions.,1: Enable slot 7 for AUDADC conversions."
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line.long 0x2C "WULIM,Window Comparator Upper Limits"
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hexmask.long.tbyte 0x2C 0.--19. 1. "ULIM,Sets the upper limit for the window comparator."
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line.long 0x30 "WLLIM,Window Comparator Lower Limits"
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hexmask.long.tbyte 0x30 0.--19. 1. "LLIM,Sets the lower limit for the window comparator."
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line.long 0x34 "SCWLIM,Scale Window Comparator Limits"
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bitfld.long 0x34 0. "SCWLIMEN,Scale the window limits compare values per precision mode. When set to 0x0 (default) the values in the 20-bit limits registers will compare directly with the FIFO values regardless of the precision mode the slot is configured to. When set to.." "0,1"
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line.long 0x38 "FIFO,The AUDADC FIFO Register contains up to 2 samples for a single channel (high and low gain PGA samples). each sample up to 12-bits. It also contains meta data in the form of which audio channel the sample(s) are from along with the PGA gain code for.."
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hexmask.long.word 0x38 20.--31. 1. "HGDATA,High-gain PGA sample data"
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bitfld.long 0x38 19. "MIC,Which audio channel this data is from encoded as int(slot number/2). In other words this is 1 if data is from slots 2 or 3 or 0 if from slots 0 or 1." "0,1"
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newline
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bitfld.long 0x38 16.--18. "METAHI,Meta data about this sample which represents the upper 3 bits of the PGA gain code" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x38 4.--15. 1. "LGDATA,Low-gain PGA sample data"
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newline
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hexmask.long.byte 0x38 0.--3. 1. "METALO,Meta data about this sample which represents the lower 4 bits of the PGA gain code"
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line.long 0x3C "FIFOPR,This is a pop-on-read mirrored copy of the ADCFIFO register with the only difference being that reading this register will result in a simultaneous FIFO POP which is also achieved by writing to the ADCFIFO Register. Note: The DFIFORDEN bit must be.."
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hexmask.long.word 0x3C 20.--31. 1. "HGDATAPR,High-gain PGA sample data"
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bitfld.long 0x3C 19. "MICPR,Which audio channel this data is from encoded as int(slot number/2). In other words this is 1 if data is from slots 2 or 3 or 0 if from slots 0 or 1." "0,1"
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newline
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bitfld.long 0x3C 16.--18. "METAHIPR,Meta data about this sample which represents the upper 3 bits of the PGA gain code" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x3C 4.--15. 1. "LGDATAPR,Low-gain PGA sample data"
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newline
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hexmask.long.byte 0x3C 0.--3. 1. "METALOPR,Meta data about this sample which represents the lower 4 bits of the PGA gain code"
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line.long 0x40 "INTTRIGTIMER,AUDADC-Internal Repeating Trigger Timer Configuration"
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bitfld.long 0x40 31. "TIMEREN,AUDADC-internal trigger timer enable." "0: Disable the AUDADC-internal trigger timer.,1: Enable the AUDADC-internal trigger timer."
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bitfld.long 0x40 16.--18. "CLKDIV,Configure number of divide-by-2 of clock source as input to trigger counter. (Max value of 5.) A value of 0 in this register would not divide down the AUDADC input clock. A value of 1 would divide the AUDADC input clock frequency by 2. A value of.." "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.word 0x40 0.--9. 1. "TIMERMAX,Trigger counter count max used as initial condition to trigger. Also used repeatedly each time counter reaches it to restart trigger timer at zero. To update this value first disable the INTTRIGTIMER by setting TIMEREN to DIS change TIMERMAX .."
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line.long 0x44 "FIFOSTAT,This register contains status of the data FIFO."
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hexmask.long.byte 0x44 0.--7. 1. "FIFOCNT,Number of valid entries in the AUDADC FIFO."
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line.long 0x48 "DATAOFFSET,ERROR: reg_brief VALUE MISSING"
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hexmask.long.word 0x48 0.--12. 1. "OFFSET,Add this signed offset to data before being written to the FIFO. This enables the user to convert unsigned samples to signed or remove a DC offset on the samples. Note that this does NOT affect the comparator limits which still operate on.."
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group.long 0x60++0xF
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line.long 0x0 "ZXCFG,Zero Crossing Comparator Configuration"
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bitfld.long 0x0 4. "ZXCHANSEL,Select which slots to use for zero crossing measurement. 0 enables zero crossing detection on slots 0 and 2. 1 enables zero crossing detection on slots 1 and 3." "0,1"
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bitfld.long 0x0 0. "ZXEN,Enable the ZX comparator" "0,1"
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line.long 0x4 "ZXLIM,Zero Crossing Comparator Limits"
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hexmask.long.word 0x4 16.--27. 1. "UZXC,Sets the upper integer sample limit for the ZX comparator. Note that these values are raw AUDADC values whose bounds are specified by PRMODE but not maniupulated by accumulate/divide logic. Therefore there is no oversampling and no binary point.."
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hexmask.long.word 0x4 0.--11. 1. "LZXC,Sets the lower integer sample limit for the ZX comparator. Note that these values are raw AUDADC values whose bounds are specified by PRMODE but not maniupulated by accumulate/divide logic. Therefore there is no oversampling and no binary point.."
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line.long 0x8 "GAINCFG,PGA Gain Configuration"
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bitfld.long 0x8 4. "UPDATEMODE,PGA update mode" "0: Immediate update mode. Once gain is written it..,1: Update gain only at detected zero crossing as.."
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bitfld.long 0x8 0. "PGACTRLEN,Enable PGA gain updates." "0,1"
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line.long 0xC "GAIN,PGA Gain Codes"
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hexmask.long.byte 0xC 24.--30. 1. "HGBDELTA,Specifies the high gain code (0 to 60 decimal specifies 0 dB to 30.0 dB in half-dB increments) as the delta from the LGB field for channel B (slot 3). Note that HGBDELTA must be LE (24 - LGB) dB."
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hexmask.long.byte 0xC 16.--22. 1. "LGB,Specifies the low gain code (0 to 60 decimal specifies -6.0 dB to 24.0 dB in half-dB increments) for channel B (slot 2)."
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newline
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hexmask.long.byte 0xC 8.--14. 1. "HGADELTA,Specifies the high gain code (0 to 60 decimal specifies 0 dB to 30.0 dB in half-dB increments) as the delta from the LGA field for channel A (slot 1). Note that HGADELTA must be LE (24 - LGA) dB."
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hexmask.long.byte 0xC 0.--6. 1. "LGA,Specifies the low gain code (0 to 60 decimal specifies -6.0 dB to 24.0 dB in half-dB increments) for channel A (slot 0)."
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group.long 0xA4++0xF
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line.long 0x0 "SATCFG,Saturation Comparator Configuration"
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bitfld.long 0x0 4. "SATCHANSEL,Select which slots to use for saturation measurement. 0 enables saturation on slots 0 and 2. 1 enables saturation on slots 1 and 3." "0,1"
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bitfld.long 0x0 0. "SATEN,Enable the saturation comparator" "0,1"
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line.long 0x4 "SATLIM,Saturation Comparator Limits"
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hexmask.long.word 0x4 16.--27. 1. "USATC,Sets the upper integer sample limit for the saturation comparator. Note that these values are raw AUDADC values whose bounds are specified by PRMODE but not manipulated by accumulate/divide logic. Therefore there is no oversampling and no binary.."
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hexmask.long.word 0x4 0.--11. 1. "LSATC,Sets the lower integer sample limit for the saturation comparator. Note that these values are raw AUDADC values whose bounds are specified by PRMODE but not manipulated by accumulate/divide logic. Therefore there is no oversampling and no binary.."
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line.long 0x8 "SATMAX,Saturation Comparator Event Counter Limits"
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hexmask.long.word 0x8 16.--27. 1. "SATCBMAX,Sets the number of saturation events that may occur before a SATCB interrupt occurs. Once this interrupt occurs the saturation event counter must be cleared by writing the SATCLR register. A value of 0 is invalid and will cause the saturation.."
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hexmask.long.word 0x8 0.--11. 1. "SATCAMAX,Sets the number of saturation events that may occur before a SATCA interrupt occurs. Once this interrupt occurs the saturation event counter must be cleared by writing the SATCLR register. A value of 0 is invalid and will cause the saturation.."
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line.long 0xC "SATCLR,Clears the saturation event counter registers"
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bitfld.long 0xC 1. "SATCBCLR,Clear saturation event counter register for channel B (slots 2 or 3 depending on SATCHANSEL)" "0,1"
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bitfld.long 0xC 0. "SATCACLR,Clear saturation event counter register for channel A (slots 0 or 1 depending on SATCHANSEL)" "0,1"
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group.long 0x200++0xF
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line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
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sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
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bitfld.long 0x0 11. "SATCB,Saturation - Channel B (Slots 2 or 3)" "?,1: Saturation as specified by SAT configuration.."
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bitfld.long 0x0 10. "SATCA,Saturation - Channel A (Slots 0 or 1)" "?,1: Saturation as specified by SAT configuration.."
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newline
|
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bitfld.long 0x0 9. "ZXCB,Zero Crossing - Channel B (Slots 2 or 3)" "?,1: Zero Crossing as specified by ZX configuration.."
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bitfld.long 0x0 8. "ZXCA,Zero Crossing - Channel A (Slots 0 or 1)" "?,1: Zero Crossing as specified by ZX configuration.."
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newline
|
|
bitfld.long 0x0 7. "DERR,DMA Error Condition" "?,1: DMA Error Condition Occurred"
|
|
bitfld.long 0x0 6. "DCMP,DMA Transfer Complete" "?,1: DMA Completed a transfer"
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|
newline
|
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bitfld.long 0x0 5. "WCINC,Window comparator voltage incursion interrupt." "?,1: Window comparator voltage incursion interrupt."
|
|
bitfld.long 0x0 4. "WCEXC,Window comparator voltage excursion interrupt." "?,1: Window comparator voltage excursion interrupt."
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|
newline
|
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bitfld.long 0x0 3. "FIFOOVR2,FIFO 100 percent full interrupt." "?,1: FIFO 100 percent full interrupt."
|
|
bitfld.long 0x0 2. "FIFOOVR1,FIFO 75 percent full interrupt." "?,1: FIFO 75 percent full interrupt."
|
|
newline
|
|
bitfld.long 0x0 1. "SCNCMP,AUDADC scan complete interrupt." "?,1: AUDADC scan complete interrupt."
|
|
bitfld.long 0x0 0. "CNVCMP,AUDADC conversion complete interrupt." "?,1: AUDADC conversion complete interrupt."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 10. "SATCA,Saturation - Channel A (Slots 0 or 1)" "0: No Saturation,1: Saturation as specified by SAT configuration.."
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 9. "ZXCB,Zero Crossing - Channel B (Slots 2 or 3)" "0: Non Zero Crossing,1: Zero Crossing as specified by ZX configuration.."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 8. "ZXCA,Zero Crossing - Channel A (Slots 0 or 1)" "0: Non Zero Crossing,1: Zero Crossing as specified by ZX configuration.."
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 7. "DERR,DMA Error Condition" "0: DMA Error Condition did not Occurred,1: DMA Error Condition Occurred"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 6. "DCMP,DMA Transfer Complete" "0: DMA completion is pending or not triggered.,1: DMA Completed a transfer"
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 5. "WCINC,Window comparator voltage incursion interrupt." "0: Not a Window comparator voltage incursion..,1: Window comparator voltage incursion interrupt."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 4. "WCEXC,Window comparator voltage excursion interrupt." "0: Not a Window comparator voltage excursion..,1: Window comparator voltage excursion interrupt."
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 3. "FIFOOVR2,FIFO 100 percent full interrupt." "0: Not a FIFO 100 percent full interrupt.,1: FIFO 100 percent full interrupt."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 2. "FIFOOVR1,FIFO 75 percent full interrupt." "0: Not FIFO 75 percent full interrupt.,1: FIFO 75 percent full interrupt."
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 1. "SCNCMP,AUDADC scan complete interrupt." "0: No AUDADC scan complete interrupt.,1: AUDADC scan complete interrupt."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 0. "CNVCMP,AUDADC conversion complete interrupt." "0: No AUDADC conversion complete interrupt.,1: AUDADC conversion complete interrupt."
|
|
endif
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
bitfld.long 0x4 11. "SATCB,Saturation - Channel B (Slots 2 or 3)" "?,1: Saturation as specified by SAT configuration.."
|
|
bitfld.long 0x4 10. "SATCA,Saturation - Channel A (Slots 0 or 1)" "?,1: Saturation as specified by SAT configuration.."
|
|
newline
|
|
bitfld.long 0x4 9. "ZXCB,Zero Crossing - Channel B (Slots 2 or 3)" "?,1: Zero Crossing as specified by ZX configuration.."
|
|
bitfld.long 0x4 8. "ZXCA,Zero Crossing - Channel A (Slots 0 or 1)" "?,1: Zero Crossing as specified by ZX configuration.."
|
|
newline
|
|
bitfld.long 0x4 7. "DERR,DMA Error Condition" "?,1: DMA Error Condition Occurred"
|
|
bitfld.long 0x4 6. "DCMP,DMA Transfer Complete" "?,1: DMA Completed a transfer"
|
|
newline
|
|
bitfld.long 0x4 5. "WCINC,Window comparator voltage incursion interrupt." "?,1: Window comparator voltage incursion interrupt."
|
|
bitfld.long 0x4 4. "WCEXC,Window comparator voltage excursion interrupt." "?,1: Window comparator voltage excursion interrupt."
|
|
newline
|
|
bitfld.long 0x4 3. "FIFOOVR2,FIFO 100 percent full interrupt." "?,1: FIFO 100 percent full interrupt."
|
|
bitfld.long 0x4 2. "FIFOOVR1,FIFO 75 percent full interrupt." "?,1: FIFO 75 percent full interrupt."
|
|
newline
|
|
bitfld.long 0x4 1. "SCNCMP,AUDADC scan complete interrupt." "?,1: AUDADC scan complete interrupt."
|
|
bitfld.long 0x4 0. "CNVCMP,AUDADC conversion complete interrupt." "?,1: AUDADC conversion complete interrupt."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 10. "SATCA,Saturation - Channel A (Slots 0 or 1)" "0: No Saturation,1: Saturation as specified by SAT configuration.."
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 9. "ZXCB,Zero Crossing - Channel B (Slots 2 or 3)" "0: Non Zero Crossing,1: Zero Crossing as specified by ZX configuration.."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 8. "ZXCA,Zero Crossing - Channel A (Slots 0 or 1)" "0: Non Zero Crossing,1: Zero Crossing as specified by ZX configuration.."
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 7. "DERR,DMA Error Condition" "0: DMA Error Condition did not Occurred,1: DMA Error Condition Occurred"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 6. "DCMP,DMA Transfer Complete" "0: DMA completion is pending or not triggered.,1: DMA Completed a transfer"
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 5. "WCINC,Window comparator voltage incursion interrupt." "0: Not a Window comparator voltage incursion..,1: Window comparator voltage incursion interrupt."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 4. "WCEXC,Window comparator voltage excursion interrupt." "0: Not a Window comparator voltage excursion..,1: Window comparator voltage excursion interrupt."
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 3. "FIFOOVR2,FIFO 100 percent full interrupt." "0: Not a FIFO 100 percent full interrupt.,1: FIFO 100 percent full interrupt."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 2. "FIFOOVR1,FIFO 75 percent full interrupt." "0: Not FIFO 75 percent full interrupt.,1: FIFO 75 percent full interrupt."
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 1. "SCNCMP,AUDADC scan complete interrupt." "0: No AUDADC scan complete interrupt.,1: AUDADC scan complete interrupt."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 0. "CNVCMP,AUDADC conversion complete interrupt." "0: No AUDADC conversion complete interrupt.,1: AUDADC conversion complete interrupt."
|
|
endif
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
bitfld.long 0x8 11. "SATCB,Saturation - Channel B (Slots 2 or 3)" "?,1: Saturation as specified by SAT configuration.."
|
|
bitfld.long 0x8 10. "SATCA,Saturation - Channel A (Slots 0 or 1)" "?,1: Saturation as specified by SAT configuration.."
|
|
newline
|
|
bitfld.long 0x8 9. "ZXCB,Zero Crossing - Channel B (Slots 2 or 3)" "?,1: Zero Crossing as specified by ZX configuration.."
|
|
bitfld.long 0x8 8. "ZXCA,Zero Crossing - Channel A (Slots 0 or 1)" "?,1: Zero Crossing as specified by ZX configuration.."
|
|
newline
|
|
bitfld.long 0x8 7. "DERR,DMA Error Condition" "?,1: DMA Error Condition Occurred"
|
|
bitfld.long 0x8 6. "DCMP,DMA Transfer Complete" "?,1: DMA Completed a transfer"
|
|
newline
|
|
bitfld.long 0x8 5. "WCINC,Window comparator voltage incursion interrupt." "?,1: Window comparator voltage incursion interrupt."
|
|
bitfld.long 0x8 4. "WCEXC,Window comparator voltage excursion interrupt." "?,1: Window comparator voltage excursion interrupt."
|
|
newline
|
|
bitfld.long 0x8 3. "FIFOOVR2,FIFO 100 percent full interrupt." "?,1: FIFO 100 percent full interrupt."
|
|
bitfld.long 0x8 2. "FIFOOVR1,FIFO 75 percent full interrupt." "?,1: FIFO 75 percent full interrupt."
|
|
newline
|
|
bitfld.long 0x8 1. "SCNCMP,AUDADC scan complete interrupt." "?,1: AUDADC scan complete interrupt."
|
|
bitfld.long 0x8 0. "CNVCMP,AUDADC conversion complete interrupt." "?,1: AUDADC conversion complete interrupt."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 10. "SATCA,Saturation - Channel A (Slots 0 or 1)" "0: No Saturation,1: Saturation as specified by SAT configuration.."
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 9. "ZXCB,Zero Crossing - Channel B (Slots 2 or 3)" "0: Non Zero Crossing,1: Zero Crossing as specified by ZX configuration.."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 8. "ZXCA,Zero Crossing - Channel A (Slots 0 or 1)" "0: Non Zero Crossing,1: Zero Crossing as specified by ZX configuration.."
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 7. "DERR,DMA Error Condition" "0: DMA Error Condition did not Occurred,1: DMA Error Condition Occurred"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 6. "DCMP,DMA Transfer Complete" "0: DMA completion is pending or not triggered.,1: DMA Completed a transfer"
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 5. "WCINC,Window comparator voltage incursion interrupt." "0: Not a Window comparator voltage incursion..,1: Window comparator voltage incursion interrupt."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 4. "WCEXC,Window comparator voltage excursion interrupt." "0: Not a Window comparator voltage excursion..,1: Window comparator voltage excursion interrupt."
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 3. "FIFOOVR2,FIFO 100 percent full interrupt." "0: Not a FIFO 100 percent full interrupt.,1: FIFO 100 percent full interrupt."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 2. "FIFOOVR1,FIFO 75 percent full interrupt." "0: Not FIFO 75 percent full interrupt.,1: FIFO 75 percent full interrupt."
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 1. "SCNCMP,AUDADC scan complete interrupt." "0: No AUDADC scan complete interrupt.,1: AUDADC scan complete interrupt."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 0. "CNVCMP,AUDADC conversion complete interrupt." "0: No AUDADC conversion complete interrupt.,1: AUDADC conversion complete interrupt."
|
|
endif
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
bitfld.long 0xC 11. "SATCB,Saturation - Channel B (Slots 2 or 3)" "?,1: Saturation as specified by SAT configuration.."
|
|
bitfld.long 0xC 10. "SATCA,Saturation - Channel A (Slots 0 or 1)" "?,1: Saturation as specified by SAT configuration.."
|
|
newline
|
|
bitfld.long 0xC 9. "ZXCB,Zero Crossing - Channel B (Slots 2 or 3)" "?,1: Zero Crossing as specified by ZX configuration.."
|
|
bitfld.long 0xC 8. "ZXCA,Zero Crossing - Channel A (Slots 0 or 1)" "?,1: Zero Crossing as specified by ZX configuration.."
|
|
newline
|
|
bitfld.long 0xC 7. "DERR,DMA Error Condition" "?,1: DMA Error Condition Occurred"
|
|
bitfld.long 0xC 6. "DCMP,DMA Transfer Complete" "?,1: DMA Completed a transfer"
|
|
newline
|
|
bitfld.long 0xC 5. "WCINC,Window comparator voltage incursion interrupt." "?,1: Window comparator voltage incursion interrupt."
|
|
bitfld.long 0xC 4. "WCEXC,Window comparator voltage excursion interrupt." "?,1: Window comparator voltage excursion interrupt."
|
|
newline
|
|
bitfld.long 0xC 3. "FIFOOVR2,FIFO 100 percent full interrupt." "?,1: FIFO 100 percent full interrupt."
|
|
bitfld.long 0xC 2. "FIFOOVR1,FIFO 75 percent full interrupt." "?,1: FIFO 75 percent full interrupt."
|
|
newline
|
|
bitfld.long 0xC 1. "SCNCMP,AUDADC scan complete interrupt." "?,1: AUDADC scan complete interrupt."
|
|
bitfld.long 0xC 0. "CNVCMP,AUDADC conversion complete interrupt." "?,1: AUDADC conversion complete interrupt."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0xC 10. "SATCA,Saturation - Channel A (Slots 0 or 1)" "0: No Saturation,1: Saturation as specified by SAT configuration.."
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0xC 9. "ZXCB,Zero Crossing - Channel B (Slots 2 or 3)" "0: Non Zero Crossing,1: Zero Crossing as specified by ZX configuration.."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0xC 8. "ZXCA,Zero Crossing - Channel A (Slots 0 or 1)" "0: Non Zero Crossing,1: Zero Crossing as specified by ZX configuration.."
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0xC 7. "DERR,DMA Error Condition" "0: DMA Error Condition did not Occurred,1: DMA Error Condition Occurred"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0xC 6. "DCMP,DMA Transfer Complete" "0: DMA completion is pending or not triggered.,1: DMA Completed a transfer"
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0xC 5. "WCINC,Window comparator voltage incursion interrupt." "0: Not a Window comparator voltage incursion..,1: Window comparator voltage incursion interrupt."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0xC 4. "WCEXC,Window comparator voltage excursion interrupt." "0: Not a Window comparator voltage excursion..,1: Window comparator voltage excursion interrupt."
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0xC 3. "FIFOOVR2,FIFO 100 percent full interrupt." "0: Not a FIFO 100 percent full interrupt.,1: FIFO 100 percent full interrupt."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0xC 2. "FIFOOVR1,FIFO 75 percent full interrupt." "0: Not FIFO 75 percent full interrupt.,1: FIFO 75 percent full interrupt."
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0xC 1. "SCNCMP,AUDADC scan complete interrupt." "0: No AUDADC scan complete interrupt.,1: AUDADC scan complete interrupt."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0xC 0. "CNVCMP,AUDADC conversion complete interrupt." "0: No AUDADC conversion complete interrupt.,1: AUDADC conversion complete interrupt."
|
|
endif
|
|
group.long 0x240++0x7
|
|
line.long 0x0 "DMATRIGEN,DMA Trigger Enable"
|
|
bitfld.long 0x0 1. "DFIFOFULL,Trigger DMA upon FIFO 100 percent Full" "0,1"
|
|
bitfld.long 0x0 0. "DFIFO75,Trigger DMA upon FIFO 75 percent Full" "0,1"
|
|
line.long 0x4 "DMATRIGSTAT,DMA Trigger Status"
|
|
bitfld.long 0x4 1. "DFULLSTAT,Triggered DMA from FIFO 100 percent Full" "0,1"
|
|
bitfld.long 0x4 0. "D75STAT,Triggered DMA from FIFO 75 percent Full" "0,1"
|
|
group.long 0x280++0x3
|
|
line.long 0x0 "DMACFG,DMA Configuration"
|
|
bitfld.long 0x0 18. "DPWROFF,Power Off the AUDADC System upon DMACPL." "0,1"
|
|
bitfld.long 0x0 9. "DMADYNPRI,Enables dynamic priority based on FIFO fullness. When FIFO is full priority is automatically set to HIGH. Otherwise DMAPRI is used." "0: Disable dynamic priority (use DMAPRI setting only),1: Enable dynamic priority"
|
|
newline
|
|
bitfld.long 0x0 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
|
|
bitfld.long 0x0 2. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction,1: Memory to Peripheral transaction"
|
|
newline
|
|
bitfld.long 0x0 0. "DMAEN,DMA Enable" "0: Disable DMA Function,1: Enable DMA Function"
|
|
group.long 0x288++0xB
|
|
line.long 0x0 "DMATOTCOUNT,DMA Total Transfer Count"
|
|
hexmask.long.word 0x0 2.--17. 1. "TOTCOUNT,Total Transfer Count"
|
|
line.long 0x4 "DMATARGADDR,DMA Target Address"
|
|
hexmask.long.byte 0x4 28.--31. 1. "UTARGADDR,SRAM Target"
|
|
hexmask.long 0x4 0.--27. 1. "LTARGADDR,DMA Target Address"
|
|
line.long 0x8 "DMASTAT,DMA Status"
|
|
bitfld.long 0x8 2. "DMAERR,DMA Error" "0,1"
|
|
bitfld.long 0x8 1. "DMACPL,DMA Transfer Complete" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "DMATIP,DMA Transfer In Progress" "0,1"
|
|
tree.end
|
|
endif
|
|
tree "CLKGEN (Clock Generator)"
|
|
base ad:0x40004000
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "OCTRL,This register includes controls for autocalibration in addition to the RTC oscillator controls."
|
|
bitfld.long 0x0 7. "OSEL,Selects the RTC oscillator (1=LFRC 0=XT)This selection bit and clocking the RTC with the external crystal (XT) are inoperable in silicon revisions A and B0." "0: XT)This selection bit and clocking the RTC with..,1: LFRC"
|
|
line.long 0x4 "CLKOUT,This register enables the CLKOUT to the GPIOs. and selects the clock source to that."
|
|
bitfld.long 0x4 7. "CKEN,Enable the CLKOUT signal" "0: Disable CLKOUT,1: Enable CLKOUT"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "CKSEL,CLKOUT signal select"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "HFADJ,This register controls the HFRC adjustment. The HFRC clock can change with temperature and process corners. and this register controls the HFRC adjustment logic which reduces the fluctuations to the clock."
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x0 24.--28. 1. "HFADJMAXDELTA,Maximum delta for HF Adjustments. 0=Disabled 1-31=maximum delta step"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 24.--28. 1. "HFADJMAXDELTA,Maximum delta for HF Adjustments. 0=Disabled 1-31=maximum delta step"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 21.--23. "HFADJGAIN,Gain control for HFRC adjustment" "0: HF Adjust with Gain of 1,1: HF Adjust with Gain of 0.5,2: HF Adjust with Gain of 0.25,3: HF Adjust with Gain of 0.125,4: HF Adjust with Gain of 0.0625,5: HF Adjust with Gain of 0.03125,?,?"
|
|
newline
|
|
bitfld.long 0x0 20. "HFWARMUP,XT warmup period for HFRC adjustment" "0: Autoadjust XT warmup period = 1-2 seconds,1: Autoadjust XT warmup period = 2-4 seconds"
|
|
newline
|
|
hexmask.long.word 0x0 8.--19. 1. "HFXTADJ,Target HFRC adjustment value."
|
|
newline
|
|
bitfld.long 0x0 1.--3. "HFADJCK,Repeat period for HFRC adjustment" "0: Autoadjust repeat period = 4 seconds,1: Autoadjust repeat period = 16 seconds,2: Autoadjust repeat period = 32 seconds,3: Autoadjust repeat period = 64 seconds,4: Autoadjust repeat period = 128 seconds,5: Autoadjust repeat period = 256 seconds,6: Autoadjust repeat period = 512 seconds,7: Autoadjust repeat period = 1024 seconds"
|
|
newline
|
|
bitfld.long 0x0 0. "HFADJEN,HFRC adjustment control" "0: Disable the HFRC adjustment,1: Enable the HFRC adjustment"
|
|
group.long 0x30++0xB
|
|
line.long 0x0 "CLOCKENSTAT,This register provides the enable status to all the peripheral clocks."
|
|
hexmask.long 0x0 0.--31. 1. "CLOCKENSTAT,Clock enable status"
|
|
line.long 0x4 "CLOCKEN2STAT,This is a continuation of the clock enable status."
|
|
hexmask.long 0x4 0.--31. 1. "CLOCKEN2STAT,Clock enable status 2"
|
|
line.long 0x8 "CLOCKEN3STAT,This is a continuation of the clock enable status."
|
|
hexmask.long 0x8 0.--31. 1. "CLOCKEN3STAT,Clock enable status 3"
|
|
group.long 0x44++0x13
|
|
line.long 0x0 "MISC,This register controls a 'safe' mode for burst. which disables the clock when burst transition is happening. It also includes a register to force the HFRC during deep sleep. It is mainly used for debug and testing."
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 25. "CLKGENMISCSPARE,Spare/Unused Chicken Bit" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 25. "CLKGENMISCSPARE,Spare/Unused Chicken Bit" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 24. "HFRC96TRUNKGATE,DO NOT USE. HFRC96_TRUNK_GATE. Setting this bit when BIT23=0 will kill HFRC root clock." "0: Disable HFRC96_TRUNK_GATE,1: DO NOT USE. HFRC96_TRUNK_GATE. Setting this bit.."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 24. "HFRC96TRUNKGATE,DO NOT USE. HFRC96_TRUNK_GATE. Setting this bit when BIT23=0 will kill HFRC root clock." "0: Disable HFRC96_TRUNK_GATE,1: DO NOT USE. HFRC96_TRUNK_GATE. Setting this bit.."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 23. "HFRCFUNCCLKGATEEN,Chicken bit to enable clock gating on HFRC_FUNC_CLK" "0: Disable clock gate,1: Enable clock gate"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 23. "HFRCFUNCCLKGATEEN,Chicken bit to enable clock gating on HFRC_FUNC_CLK" "0: Disable clock gate,1: Enable clock gate"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 22. "ETMTRACECLKCLKGATEEN,Chicken bit to enable clock gating on ETM TRACE CLK" "0: Disable clock gate,1: Enable clock gate"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 22. "ETMTRACECLKCLKGATEEN,Chicken bit to enable clock gating on ETM TRACE CLK" "0: Disable clock gate,1: Enable clock gate"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 21. "APBDMACPUCLKCLKGATEEN,Chicken bit to enable clock gating on APB DMA CPU CLK" "0: Disable clock gate,1: Enable clock gate"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 21. "APBDMACPUCLKCLKGATEEN,Chicken bit to enable clock gating on APB DMA CPU CLK" "0: Disable clock gate,1: Enable clock gate"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 20. "GFXAXICLKCLKGATEEN,Chicken bit to enable clock gating on GFX AXI CLK" "0: Disable clock gate,1: Enable clock gate"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 20. "GFXAXICLKCLKGATEEN,Chicken bit to enable clock gating on GFX AXI CLK" "0: Disable clock gate,1: Enable clock gate"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 19. "GFXCLKCLKGATEEN,Chicken bit to enable clock gating on GFX CLK" "0: Disable clock gate,1: Enable clock gate"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 19. "GFXCLKCLKGATEEN,Chicken bit to enable clock gating on GFX CLK" "0: Disable clock gate,1: Enable clock gate"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x0 18.--25. 1. "CLKGENMISCSPARES,This field is used for the clock gating workaround."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 18. "CM4DAXICLKGATEEN,Chicken bit to enable clock gating on CM4 DAXI CLK" "0: Disable clock gate,1: Enable clock gate"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 18. "CM4DAXICLKGATEEN,Chicken bit to enable clock gating on CM4 DAXI CLK" "0: Disable clock gate,1: Enable clock gate"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 17. "PWRONCLKENUSBREFCLK,Chicken bit to disable Rev B clock enable during reset" "0: Enable USB REF Clock to run during reset,1: Chicken bit to revert to rev A"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 16. "PWRONCLKENI2S1REFCLK,Chicken bit to disable Rev B clock enable during reset" "0: Enable I2S instance 1 Clock to run during reset,1: Chicken bit to revert to rev A"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 16. "PWRONCLKENI2S1REFCLK,Chicken bit to disable Rev B clock enable during reset" "0: Enable I2S instance 1 Clock to run during reset,1: Chicken bit to revert to rev A"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 15. "PWRONCLKENI2S0REFCLK,Chicken bit to disable Rev B clock enable during reset" "0: Enable I2S instance 0 Clock to run during reset,1: Chicken bit to revert to rev A"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 15. "PWRONCLKENI2S0REFCLK,Chicken bit to disable Rev B clock enable during reset" "0: Enable I2S instance 0 Clock to run during reset,1: Chicken bit to revert to rev A"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 14. "AXIXACLKENOVRRIDE,Chicken bit to disable Rev B added clock gating" "0: Fine grain clock gating enabled,1: AXI Clock enabled when core is not in Sleep mode"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 14. "AXIXACLKENOVRRIDE,Chicken bit to disable Rev B added clock gating" "0: Fine grain clock gating enabled,1: AXI Clock enabled when core is not in Sleep mode"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 13. "PWRONCLKENI2S1,Chicken bit to disable Rev B clock enable during reset" "0: Enable I2S instance 1 engine Clock to run during..,1: Chicken bit to revert to rev A"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 13. "PWRONCLKENI2S1,Chicken bit to disable Rev B clock enable during reset" "0: Enable I2S instance 1 engine Clock to run during..,1: Chicken bit to revert to rev A"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 12. "PWRONCLKENI2S0,Chicken bit to disable Rev B clock enable during reset" "0: Enable I2S instance 0 engine Clock to run during..,1: Chicken bit to revert to rev A"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 12. "PWRONCLKENI2S0,Chicken bit to disable Rev B clock enable during reset" "0: Enable I2S instance 0 engine Clock to run during..,1: Chicken bit to revert to rev A"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 11. "PWRONCLKENCRYPTO,Chicken bit to disable Rev B clock enable during reset" "0: Enable Cryto engine Clock to run during reset,1: Chicken bit to revert to rev A"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 11. "PWRONCLKENCRYPTO,Chicken bit to disable Rev B clock enable during reset" "0: Enable Cryto engine Clock to run during reset,1: Chicken bit to revert to rev A"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 10. "PWRONCLKENSDIO,Chicken bit to disable Rev B clock enable during reset" "0: Enable SDIO Clock to run during reset,1: Chicken bit to revert to rev A"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 10. "PWRONCLKENSDIO,Chicken bit to disable Rev B clock enable during reset" "0: Enable SDIO Clock to run during reset,1: Chicken bit to revert to rev A"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 9. "PWRONCLKENUSB,Chicken bit to disable Rev B clock enable during reset" "0: Enable USB Clock to run during reset,1: Chicken bit to revert to rev A"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 8. "PWRONCLKENGFX,Chicken bit to disable Rev B clock enable during reset" "0: Enable GFX Clock to run during reset,1: Chicken bit to revert to rev A"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 8. "PWRONCLKENGFX,Chicken bit to disable Rev B clock enable during reset" "0: Enable GFX Clock to run during reset,1: Chicken bit to revert to rev A"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 7. "PWRONCLKENDISPPHY,Chicken bit to disable Rev B clock enable during reset" "0: Enable Display Phy Clock to run during reset,1: Chicken bit to revert to rev A"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 7. "PWRONCLKENDISPPHY,Chicken bit to disable Rev B clock enable during reset" "0: Enable Display Phy Clock to run during reset,1: Chicken bit to revert to rev A"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 6. "PWRONCLKENDISP,For Apollo4 revB disables display clock enable during reset basically reverting to revA behavior." "0: Enable Display Clock to run during reset,1: Revert to revA behavior. Disable display clock.."
|
|
newline
|
|
bitfld.long 0x0 5. "FRCHFRC2,Force HFRC2 On.Setting this bit forces HFRC2 to remain on including in deep sleep. When changing a module's clock source to HFRC2 this bit must be set and remain set when any module is using HFRC2 as its clock." "0: Do not force HFRC2 on; stops in deep sleep mode.,1: Force HFRC2 on; runs in deep sleep mode."
|
|
newline
|
|
bitfld.long 0x0 4. "USEHFRC2FQ192MHZ,Use HFRC-192MHz or HFRC2-192MHz for MCU" "0: Use HFRC-192MHz,1: Use HFRC2-192MHz"
|
|
newline
|
|
bitfld.long 0x0 3. "USEHFRC2FQ96MHZ,Use HFRC-96MHz or HFRC2-96MHz for DSP" "0: Use HFRC-96MHz,1: Use HFRC2-96MHz"
|
|
newline
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 2. "USEHFRC2FQ48MHZ,Use HFRC-48MHz or HFRC2-48MHz for DSP" "0: Use HFRC-48MHz,1: Use HFRC2-48MHz"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 2. "USEHFRC2FQ48MHZ,Use HFRC-48MHz or HFRC2-48MHz for DSP" "0: Use HFRC-48MHz,1: Use HFRC2-48MHz"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 1. "FRCBURSTOFF,Force fclk hclk fclk_wic and fclk_pmu to be turned off during burst transition." "0: fclk hclk and fclk_wic are turned on during the..,1: fclk hclk and fclk are turned off during burst.."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 1. "FRCBURSTOFF,Force fclk hclk fclk_wic and fclk_pmu to be turned off during burst transition." "0: fclk hclk and fclk_wic are turned on during the..,1: fclk hclk and fclk are turned off during burst.."
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 0. "FRCHFRC,Force HFRC On ." "0: HFRC stops in deep sleep mode,1: HFRC runs in deep sleep mode"
|
|
line.long 0x4 "HF2ADJ0,This register controls hf2adj enable. fast_start enable. fast_start_delay setting and counter input offset."
|
|
bitfld.long 0x4 29. "HF2ADJXTHSMUXSEL,0=XTHS 1=EXTREF select" "0: XTHS 1=EXTREF select,?"
|
|
newline
|
|
hexmask.long.word 0x4 15.--28. 1. "HF2ADJCNTINOFFSET,Counter input offset"
|
|
newline
|
|
hexmask.long.word 0x4 2.--14. 1. "HF2ADJFASTSTRDLY,Fast_start_delay value setting"
|
|
newline
|
|
bitfld.long 0x4 1. "HF2ADJFASTSTREN,Fast_start_delay control" "0: Fast_start_delay disable,1: Fast_start_delay enable"
|
|
newline
|
|
bitfld.long 0x4 0. "HF2ADJEN,HF2ADJ control" "0: HF2ADJ disable,1: HF2ADJ enable"
|
|
line.long 0x8 "HF2ADJ1,This register controls hf2adj trimming enable and trimming offset."
|
|
hexmask.long.word 0x8 3.--13. 1. "HF2ADJTRIMOFFSET,HF2ADJ trimming offset. (signed number)"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "HF2ADJTRIMEN,HF2ADJ output selection" "0: 0,1: HF2ADJTRIMOUT,2: HF2ADJTRIMOFFSET,3: HF2ADJTRIMOUT + HF2ADJTRIMOFFSET,4: HF2TUNE,5: HF2ADJTRIMOUT + HF2TUNE,6: HF2ADJTRIMOFFSET + HF2TUNE,7: HF2ADJTRIMOUT + HF2ADJTRIMOFFSET + HF2TUNE"
|
|
line.long 0xC "HF2ADJ2,This register controls xtal32m divider ratio and HF2ADJ ration setting."
|
|
hexmask.long 0xC 2.--30. 1. "HF2ADJRATIO,HF2ADJ ratio setting."
|
|
newline
|
|
bitfld.long 0xC 0.--1. "HF2ADJXTALDIVRATIO,XTAL32MHz divider ratio for HF2ADJ." "0: XTAL32MHz,1: XTAL32MHz / 2,2: XTAL32MHz / 4,3: XTAL32MHz / 8"
|
|
line.long 0x10 "HF2VAL,This register provides the read back of the HF2TUNE"
|
|
hexmask.long.word 0x10 0.--10. 1. "HF2ADJTRIMOUT,HF2ADJ trimming output"
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "LFRCCTRL,LFRC control"
|
|
bitfld.long 0x0 1. "LFRCPWD,Power down LFRC" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "LFRCOUT,Disable LFRC output" "0,1"
|
|
group.long 0x84++0x3
|
|
line.long 0x0 "DISPCLKCTRL,Provides ability to select the PLL reference clock. and derivative of the display clock"
|
|
bitfld.long 0x0 7. "DCCLKEN,Enable for the PLL clock through clkgen" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "DISPCLKSEL,Selection for PLL reference clock." "0: Static value of 0 selected for DPHY clock input,1: 48MHz sourced from the HFRC,2: 96MHz sourced from the HFRC,3: DPHY PLL"
|
|
newline
|
|
bitfld.long 0x0 3. "PLLCLKEN,Enable for the PLL clock through clkgen" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "PLLCLKSEL,Selection for PLL reference clock." "0: Static value of 0 selected for DPHY clock input,1: 12MHz sourced from the HFRC,2: 6MHz sourced from the HFRC,3: High Frequency XTAL input (16MHz)"
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
group.long 0x88++0x7
|
|
line.long 0x0 "CLKGENSPARES,CLKGEN Spare Regs"
|
|
hexmask.long 0x0 0.--31. 1. "CLKGENSPARES,Placeholer spare registes that can be used as needed for future use"
|
|
line.long 0x4 "HFRCIDLECOUNTERS,Provides SW controlled # idle cycles before powering down HFRC. HFRC2.. core clock enable(s)"
|
|
bitfld.long 0x4 31. "UPDATEENABLE,usage : Clear UPDATEENABLE or 1'b0; Update other bits fields of this register. Set this register to 1'b1 for HW to update." "0,1"
|
|
hexmask.long.byte 0x4 24.--29. 1. "HFRC2CLKREQDELAY,Enable for the PLL clock through clkgen"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--21. 1. "HFRC2PWRDOWNDELAY,Idle counter for HFRC2 POWER DOWN DELAY"
|
|
hexmask.long.byte 0x4 8.--13. 1. "HFRCCLKREQDELAY,Idle counter for HFRC CLK REQ DELAY"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "HFRCPWRDOWNDELAY,Idle counter for HFRC POWER DOWN DELAY"
|
|
group.long 0x100++0xF
|
|
line.long 0x0 "INTRPTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 0. "OF,XT Oscillator Fail interrupt" "0,1"
|
|
line.long 0x4 "INTRPTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 0. "OF,XT Oscillator Fail interrupt" "0,1"
|
|
line.long 0x8 "INTRPTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 0. "OF,XT Oscillator Fail interrupt" "0,1"
|
|
line.long 0xC "INTRPTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 0. "OF,XT Oscillator Fail interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
group.long 0x88++0x7
|
|
line.long 0x0 "CLKGENSPARES,CLKGEN Spare Regs"
|
|
hexmask.long 0x0 0.--31. 1. "CLKGENSPARES,Placeholer spare registes that can be used as needed for future use"
|
|
line.long 0x4 "HFRCIDLECOUNTERS,Provides SW controlled # idle cycles before powering down HFRC. HFRC2.. core clock enable(s)"
|
|
bitfld.long 0x4 31. "UPDATEENABLE,usage : Clear UPDATEENABLE or 1'b0; Update other bits fields of this register. Set this register to 1'b1 for HW to update." "0,1"
|
|
hexmask.long.byte 0x4 24.--29. 1. "HFRC2CLKREQDELAY,Enable for the PLL clock through clkgen"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--21. 1. "HFRC2PWRDOWNDELAY,Idle counter for HFRC2 POWER DOWN DELAY"
|
|
hexmask.long.byte 0x4 8.--13. 1. "HFRCCLKREQDELAY,Idle counter for HFRC CLK REQ DELAY"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "HFRCPWRDOWNDELAY,Idle counter for HFRC POWER DOWN DELAY"
|
|
group.long 0x100++0xF
|
|
line.long 0x0 "INTRPTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 0. "OF,XT Oscillator Fail interrupt" "0,1"
|
|
line.long 0x4 "INTRPTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 0. "OF,XT Oscillator Fail interrupt" "0,1"
|
|
line.long 0x8 "INTRPTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 0. "OF,XT Oscillator Fail interrupt" "0,1"
|
|
line.long 0xC "INTRPTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 0. "OF,XT Oscillator Fail interrupt" "0,1"
|
|
endif
|
|
tree.end
|
|
tree "CPU (CM4 Complex Registers)"
|
|
base ad:0x48000000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CACHECFG,CM4 Cache Control"
|
|
bitfld.long 0x0 24. "ENABLEMONITOR,Enable Cache Monitoring Stats. Cache monitoring consumes additional power and should only be enabled when profiling code and counters will increment when this bit is set. Counter values will be retained when this is set to 0 allowing.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "DATACLKGATE,Enable aggressive clock gating of entire data array. This bit should be set to 1 for optimal power efficiency." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NC0CACHELOCK,Only valid when Cache Mode D is set. When high sets the mode of the the NC0 region such that all accesse to this region are cached in to the lower half of the cache. When set low then NCR0 is non cacheable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "NC1CACHELOCK,Only valid when Cache Mode D is set. When high sets the mode of the the NC1 region such that all accesse to this region are cached in to the upper half of the cache. When set low then NCR1 is non cacheable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "LS,Enable LS (light sleep) of cache RAMs. Software should DISABLE this bit since cache activity is too high to benefit from LS usage." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "CLKGATE,Enable clock gating of cache TAG RAM. Software should enable this bit for optimal power efficiency." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "DENABLE,Enable CM4 Data Caching." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "IENABLE,Enable CM4 Instruction Caching" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "CONFIG,Sets the cache configuration"
|
|
newline
|
|
bitfld.long 0x0 3. "NC1ENABLE,Enable Non-cacheable region 1. See NCR1 registers to define the region." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NC0ENABLE,Enable Non-cacheable region 0. See NCR0 registers to define the region." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LRU,Sets the cache repleacment policy. 0=LRR (least recently replaced) 1=LRU (least recently used). LRR minimizes writes to the TAG SRAM." "0: LRR,1: LRU"
|
|
newline
|
|
bitfld.long 0x0 0. "ENABLE,Enables the CM4 cache controller and enables power to the cache SRAMs. The ICACHE_ENABLE and DCACHE_ENABLE should be set to enable caching for each type of access." "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CACHECTRL,Cache Control"
|
|
bitfld.long 0x0 2. "CACHEREADY,Cache Ready Status (enabled and not processing an invalidate operation)" "0,1"
|
|
newline
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 1. "RESETSTAT,Reset Cache Statistics. When written to a 1 the cache monitor counters will be cleared. The monitor counters can be reset only when the CACHECFG.ENABLE_MONITOR bit is set." "0: default Cache Stats,1: Clear Cache Stats"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 1. "RESETSTAT,Reset Cache Statistics. When written to a 1 the cache monitor counters will be cleared. The monitor counters can be reset only when the CACHECFG.ENABLE_MONITOR bit is set." "0: default Cache Stats,1: Clear Cache Stats"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
bitfld.long 0x0 1. "RESETSTAT,Reset Cache Statistics. When written to a 1 the cache monitor counters will be cleared. The monitor counters can be reset only when the CACHECFG.ENABLE_MONITOR bit is set." "?,1: Clear Cache Stats"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 0. "INVALIDATE,Writing a 1 to this bitfield invalidates the CM4 cache contents." "0,1"
|
|
group.long 0x10++0xF
|
|
line.long 0x0 "NCR0START,CM4 Cache Noncachable Region 0 Start"
|
|
hexmask.long 0x0 4.--28. 1. "ADDR,Start address for non-cacheable region 0"
|
|
line.long 0x4 "NCR0END,CM4 Cache Noncachable Region 0 End"
|
|
hexmask.long 0x4 4.--28. 1. "ADDR,End address for non-cacheable region 0"
|
|
line.long 0x8 "NCR1START,CM4 Cache Noncachable Region 1 Start"
|
|
hexmask.long 0x8 4.--28. 1. "ADDR,Start address for non-cacheable region 1"
|
|
line.long 0xC "NCR1END,CM4 Cache Noncachable Region 1 End"
|
|
hexmask.long 0xC 4.--28. 1. "ADDR,End address for non-cacheable region 1"
|
|
group.long 0x50++0x7
|
|
line.long 0x0 "DAXICFG,DAXI Config"
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 24.--25. "MRUGROUPLEVEL,Sets the MRU group population limit." "0: Maximum level for current number of buffers..,1: One less than maximum level or zero for current..,2: Two less than maximum level or zero for current..,3: Three less than maximum level or zero for.."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 24.--25. "MRUGROUPLEVEL,Sets the MRU group population limit." "0: Maximum level for current number of buffers..,1: One less than maximum level or zero for current..,2: Two less than maximum level or zero for current..,3: Three less than maximum level or zero for.."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x0 16.--23. 1. "AGINGCOUNTER,Specifies the relative time that DAXI buffers may remain unused before being flushed. Counter is based on CPU clock cycles and buffers will generally be flushed in 1-2 AGINGCOUNTER timesteps."
|
|
newline
|
|
bitfld.long 0x0 8.--9. "BUFFERENABLE,Enables DAXI buffers" "0: Single buffer mode,1: Enable Two buffers,2: Enable Three buffers,3: Enable Four buffers"
|
|
newline
|
|
bitfld.long 0x0 0. "FLUSHLEVEL,When set to 0 and 3 or 4 buffers are enabled the DAXI will attempt to maintain two free buffers. When set to 1 and 3 or 4 buffers are enabled the DAXI will attempt to maintain three free buffers. When set to 0 and 2 buffers are enabled .." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 16.--20. 1. "AGINGCOUNTER,Specifies the relative time that DAXI buffers may remain unused before being flushed. Counter is based on CPU clock cycles and buffers will generally be flushed in 1-2 AGINGCOUNTER timesteps."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 16.--20. 1. "AGINGCOUNTER,Specifies the relative time that DAXI buffers may remain unused before being flushed. Counter is based on CPU clock cycles and buffers will generally be flushed in 1-2 AGINGCOUNTER timesteps."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 8.--11. 1. "BUFFERENABLE,Enables DAXI buffers"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 8.--11. 1. "BUFFERENABLE,Enables DAXI buffers"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 5. "DAXISTATECLKGATEEN,Enables clock gating of DAXI state." "0: Enable clock gating of DAXI state.,1: Disable clock gating of DAXI state."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 5. "DAXISTATECLKGATEEN,Enables clock gating of DAXI state." "0: Enable clock gating of DAXI state.,1: Disable clock gating of DAXI state."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 4. "DAXIDATACLKGATEEN,Enables clock gating of DAXI line buffer data." "0: Enable clock gating of DAXI line buffer data.,1: Disable clock gating of DAXI line buffer data."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 4. "DAXIDATACLKGATEEN,Enables clock gating of DAXI line buffer data." "0: Enable clock gating of DAXI line buffer data.,1: Disable clock gating of DAXI line buffer data."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 3. "DAXIBECLKGATEEN,Enables clock gating of DAXI line buffer byte enables." "0: Enable clock gating of DAXI line buffer byte..,1: Disable clock gating of DAXI line buffer byte.."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 3. "DAXIBECLKGATEEN,Enables clock gating of DAXI line buffer byte enables." "0: Enable clock gating of DAXI line buffer byte..,1: Disable clock gating of DAXI line buffer byte.."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 2. "DAXIPASSTHROUGH,Passes requests through DAXI logic disables caching lines in the DAXI line buffers." "0: Disable pass through mode caching lines in DAXI..,1: Enable pass through mode caching lines in DAXI.."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 2. "DAXIPASSTHROUGH,Passes requests through DAXI logic disables caching lines in the DAXI line buffers." "0: Disable pass through mode caching lines in DAXI..,1: Enable pass through mode caching lines in DAXI.."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 1. "AGINGSENABLE,Enables flushing out shared lines using the aging mechanism." "0: Flushing out shared entries using aging..,1: Flushing out shared entries using aging.."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 1. "AGINGSENABLE,Enables flushing out shared lines using the aging mechanism." "0: Flushing out shared entries using aging..,1: Flushing out shared entries using aging.."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 0. "FLUSHLEVEL,Level of free buffers to flush out dirty buffers." "0: Flush out dirty buffers if 3 or more ane enabled..,1: Flush out dirty buffers if 3 or more are enabled.."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 0. "FLUSHLEVEL,Level of free buffers to flush out dirty buffers." "0: Flush out dirty buffers if 3 or more ane enabled..,1: Flush out dirty buffers if 3 or more are enabled.."
|
|
endif
|
|
line.long 0x4 "DAXICTRL,DAXI Control"
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 12. "DAXIRAXIBUSY,DAXI status indicating the DAXI RAXI interface is busy." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 12. "DAXIRAXIBUSY,DAXI status indicating the DAXI RAXI interface is busy." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 11. "DAXIBRESPPENDING,DAXI status indicating at least one AXI B repsonse for a store is pending." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 11. "DAXIBRESPPENDING,DAXI status indicating at least one AXI B repsonse for a store is pending." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 10. "DAXISTORE,DAXI status indicating at least one buffer has outstanding store waiting to complete." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 10. "DAXISTORE,DAXI status indicating at least one buffer has outstanding store waiting to complete." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 9. "DAXIWRLOAD,DAXI status indicating at least one partially written buffer is waiting for load to convert to modified." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 9. "DAXIWRLOAD,DAXI status indicating at least one partially written buffer is waiting for load to convert to modified." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 8. "DAXIWALLOC,DAXI status indicating at least one write allocation is waiting for prior store to complete." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 8. "DAXIWALLOC,DAXI status indicating at least one write allocation is waiting for prior store to complete." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 7. "DAXIWRITE,DAXI status indicating at least one partially written buffer has modified data." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 7. "DAXIWRITE,DAXI status indicating at least one partially written buffer has modified data." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 6. "DAXIMODIFIED,DAXI status indicating at least one full buffer has modified data." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 6. "DAXIMODIFIED,DAXI status indicating at least one full buffer has modified data." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 5. "DAXISHARED,DAXI status indicating at least one full buffer is shared." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 5. "DAXISHARED,DAXI status indicating at least one full buffer is shared." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 4. "DAXIAHBBUSY,DAXI status indicating DAXI AHB interface is busy." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 4. "DAXIAHBBUSY,DAXI status indicating DAXI AHB interface is busy." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 3. "DAXIBUSY,DAXI status indicating DAXI is busy." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 3. "DAXIBUSY,DAXI status indicating DAXI is busy." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 2. "DAXIREADY,DAXI Ready Status (enabled and not processing a flush of WRITE or MODIFIED buffers)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 2. "DAXIREADY,DAXI Ready Status (enabled and not processing a flush of WRITE or MODIFIED buffers)" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x4 1. "DAXIINVALIDATE,Writing a 1 to this bitfield invalidates any SHARED data buffers" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DAXIFLUSHWRITE,Writing a 1 to this bitfield forces a flush of WRITE or MODIFIED buffers" "0,1"
|
|
group.long 0x80++0x13
|
|
line.long 0x0 "ICODEFAULTADDR,ICODE bus address which was present when a bus fault occurred."
|
|
hexmask.long 0x0 0.--31. 1. "ICODEFAULTADDR,The ICODE bus address observed when a Bus Fault occurred. Once an address is captured in this field it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register."
|
|
line.long 0x4 "DCODEFAULTADDR,DCODE bus address which was present when a bus fault occurred."
|
|
hexmask.long 0x4 0.--31. 1. "DCODEFAULTADDR,The DCODE bus address observed when a Bus Fault occurred. Once an address is captured in this field it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register."
|
|
line.long 0x8 "SYSFAULTADDR,System bus address which was present when a bus fault occurred."
|
|
hexmask.long 0x8 0.--31. 1. "SYSFAULTADDR,SYS bus address observed when a Bus Fault occurred. Once an address is captured in this field it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register."
|
|
line.long 0xC "FAULTSTATUS,Reflects the status of the bus decoders' fault detection. Any write to this register will clear all of the status bits within the register."
|
|
bitfld.long 0xC 2. "SYSFAULT,SYS Bus Decoder Fault Detected bit. When set a fault has been detected and the SYSFAULTADDR register will contain the bus address which generated the fault." "0: No bus fault has been detected.,1: Bus fault detected."
|
|
newline
|
|
bitfld.long 0xC 1. "DCODEFAULT,DCODE Bus Decoder Fault Detected bit. When set a fault has been detected and the DCODEFAULTADDR register will contain the bus address which generated the fault." "0: No DCODE fault has been detected.,1: DCODE fault detected."
|
|
newline
|
|
bitfld.long 0xC 0. "ICODEFAULT,The ICODE Bus Decoder Fault Detected bit. When set a fault has been detected and the ICODEFAULTADDR register will contain the bus address which generated the fault." "0: No ICODE fault has been detected.,1: ICODE fault detected."
|
|
line.long 0x10 "FAULTCAPTUREEN,Enable the fault capture registers"
|
|
bitfld.long 0x10 0. "FAULTCAPTUREEN,Fault Capture Enable field. When set the Fault Capture monitors are enabled and addresses which generate a hard fault are captured into the FAULTADDR registers." "0: Disable fault capture.,1: Enable fault capture."
|
|
group.long 0xC0++0x13
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 0. "AXIWERROR,AXI Write Error Occurred" "0,1"
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 0. "AXIWERROR,AXI Write Error Occurred" "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 0. "AXIWERROR,AXI Write Error Occurred" "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 0. "AXIWERROR,AXI Write Error Occurred" "0,1"
|
|
line.long 0x10 "WRITEERRADDR,DAXI Write Error Address"
|
|
hexmask.long 0x10 0.--31. 1. "WERRADDR,This address will be approximate since multiple write transactions might be in flight at any given time. However it should be accurate when debugging/single-stepping"
|
|
group.long 0x100++0x1F
|
|
line.long 0x0 "DMON0,Data Cache Total Accesses"
|
|
hexmask.long 0x0 0.--31. 1. "DACCESS,Total accesses to data cache. All performance metrics should be relative to the number of accesses performed."
|
|
line.long 0x4 "DMON1,Data Cache Tag Lookups"
|
|
hexmask.long 0x4 0.--31. 1. "DLOOKUP,Total tag lookups from data cache."
|
|
line.long 0x8 "DMON2,Data Cache Hits"
|
|
hexmask.long 0x8 0.--31. 1. "DHIT,Cache hits from lookup operations."
|
|
line.long 0xC "DMON3,Data Cache Line Hits"
|
|
hexmask.long 0xC 0.--31. 1. "DLINE,Cache hits from line cache"
|
|
line.long 0x10 "IMON0,Instruction Cache Total Accesses"
|
|
hexmask.long 0x10 0.--31. 1. "IACCESS,Total accesses to Instruction cache"
|
|
line.long 0x14 "IMON1,Instruction Cache Tag Lookups"
|
|
hexmask.long 0x14 0.--31. 1. "ILOOKUP,Total tag lookups from Instruction cache"
|
|
line.long 0x18 "IMON2,Instruction Cache Hits"
|
|
hexmask.long 0x18 0.--31. 1. "IHIT,Cache hits from lookup operations"
|
|
line.long 0x1C "IMON3,Instruction Cache Line Hits"
|
|
hexmask.long 0x1C 0.--31. 1. "ILINE,Cache hits from line cache"
|
|
tree.end
|
|
tree "CRYPTO (Crypto Acceleration)"
|
|
base ad:0x400C0000
|
|
group.long 0x0++0xBB
|
|
line.long 0x0 "MEMORYMAP0,This register maps the virtual register R0 to a physical address in memory."
|
|
hexmask.long.word 0x0 1.--10. 1. "PHYSADDRMAP0,Contains the physical address in memory to map the R0 register."
|
|
line.long 0x4 "MEMORYMAP1,This register maps the virtual register R1 to a physical address in memory."
|
|
hexmask.long.word 0x4 1.--10. 1. "PHYSADDRMAP1,Contains the physical address in memory to map the R1 register."
|
|
line.long 0x8 "MEMORYMAP2,This register maps the virtual register R2 to a physical address in memory."
|
|
hexmask.long.word 0x8 1.--10. 1. "PHYSADDRMAP2,Contains the physical address in memory to map the R2 register."
|
|
line.long 0xC "MEMORYMAP3,This register maps the virtual register R3 to a physical address in memory."
|
|
hexmask.long.word 0xC 1.--10. 1. "PHYSADDRMAP3,Contains the physical address in memory to map the R3 register."
|
|
line.long 0x10 "MEMORYMAP4,This register maps the virtual register R4 to a physical address in memory."
|
|
hexmask.long.word 0x10 1.--10. 1. "PHYSADDRMAP4,Contains the physical address in memory to map the R4 register."
|
|
line.long 0x14 "MEMORYMAP5,This register maps the virtual register R5 to a physical address in memory."
|
|
hexmask.long.word 0x14 1.--10. 1. "PHYSADDRMAP5,Contains the physical address in memory to map the R5 register."
|
|
line.long 0x18 "MEMORYMAP6,This register maps the virtual register R6 to a physical address in memory."
|
|
hexmask.long.word 0x18 1.--10. 1. "PHYSADDRMAP6,Contains the physical address in memory to map the R6 register."
|
|
line.long 0x1C "MEMORYMAP7,This register maps the virtual register R7 to a physical address in memory."
|
|
hexmask.long.word 0x1C 1.--10. 1. "PHYSADDRMAP7,Contains the physical address in memory to map the R7 register."
|
|
line.long 0x20 "MEMORYMAP8,This register maps the virtual register R8 to a physical address in memory."
|
|
hexmask.long.word 0x20 1.--10. 1. "PHYSADDRMAP8,Contains the physical address in memory to map the R8 register."
|
|
line.long 0x24 "MEMORYMAP9,This register maps the virtual register R9 to a physical address in memory."
|
|
hexmask.long.word 0x24 1.--10. 1. "PHYSADDRMAP9,Contains the physical address in memory to map the R9 register."
|
|
line.long 0x28 "MEMORYMAP10,This register maps the virtual register R10 to a physical address in memory."
|
|
hexmask.long.word 0x28 1.--10. 1. "PHYSADDRMAP10,Contains the physical address in memory to map the R10 register."
|
|
line.long 0x2C "MEMORYMAP11,This register maps the virtual register R11 to a physical address in memory."
|
|
hexmask.long.word 0x2C 1.--10. 1. "PHYSADDRMAP11,Contains the physical address in memory to map the R11 register."
|
|
line.long 0x30 "MEMORYMAP12,This register maps the virtual register R12 to a physical address in memory."
|
|
hexmask.long.word 0x30 1.--10. 1. "PHYSADDRMAP12,Contains the physical address in memory to map the R12 register."
|
|
line.long 0x34 "MEMORYMAP13,This register maps the virtual register R13 to a physical address in memory."
|
|
hexmask.long.word 0x34 1.--10. 1. "PHYSADDRMAP13,Contains the physical address in memory to map the R13 register."
|
|
line.long 0x38 "MEMORYMAP14,This register maps the virtual register R14 to a physical address in memory."
|
|
hexmask.long.word 0x38 1.--10. 1. "PHYSADDRMAP14,Contains the physical address in memory to map the R14 register."
|
|
line.long 0x3C "MEMORYMAP15,This register maps the virtual register R15 to a physical address in memory."
|
|
hexmask.long.word 0x3C 1.--10. 1. "PHYSADDRMAP15,Contains the physical address in memory to map the R15 registero."
|
|
line.long 0x40 "MEMORYMAP16,This register maps the virtual register R16 to a physical address in memory."
|
|
hexmask.long.word 0x40 1.--10. 1. "PHYSADDRMAP16,Contains the physical address in memory to map the R16 register."
|
|
line.long 0x44 "MEMORYMAP17,This register maps the virtual register R17 to a physical address in memory."
|
|
hexmask.long.word 0x44 1.--10. 1. "PHYSADDRMAP17,Contains the physical address in memory to map the R17 registero."
|
|
line.long 0x48 "MEMORYMAP18,This register maps the virtual register R18 to a physical address in memory."
|
|
hexmask.long.word 0x48 1.--10. 1. "PHYSADDRMAP18,Contains the physical address in memory to map the R18 register."
|
|
line.long 0x4C "MEMORYMAP19,This register maps the virtual register R19 to a physical address in memory."
|
|
hexmask.long.word 0x4C 1.--10. 1. "PHYSADDRMAP19,Contains the physical address in memory to map the R19 register to."
|
|
line.long 0x50 "MEMORYMAP20,This register maps the virtual register R20 to a physical address in memory."
|
|
hexmask.long.word 0x50 1.--10. 1. "PHYSADDRMAP20,Contains the physical address in memory to map the R20 register to."
|
|
line.long 0x54 "MEMORYMAP21,This register maps the virtual register R21 to a physical address in memory."
|
|
hexmask.long.word 0x54 1.--10. 1. "PHYSADDRMAP21,Contains the physical address in memory to map the R21 register to."
|
|
line.long 0x58 "MEMORYMAP22,This register maps the virtual register R22 to a physical address in memory."
|
|
hexmask.long.word 0x58 1.--10. 1. "PHYSADDRMAP22,Contains the physical address in memory to map the R22 register to."
|
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line.long 0x5C "MEMORYMAP23,This register maps the virtual register R23 to a physical address in memory."
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hexmask.long.word 0x5C 1.--10. 1. "PHYSADDRMAP23,Contains the physical address in memory to map the R23 register to."
|
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line.long 0x60 "MEMORYMAP24,This register maps the virtual register R24 to a physical address in memory."
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hexmask.long.word 0x60 1.--10. 1. "PHYSADDRMAP24,Contains the physical address in memory to map the R24 register to."
|
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line.long 0x64 "MEMORYMAP25,This register maps the virtual register R25 to a physical address in memory."
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hexmask.long.word 0x64 1.--10. 1. "PHYSADDRMAP25,Contains the physical address in memory to map the R25 register to."
|
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line.long 0x68 "MEMORYMAP26,This register maps the virtual register R26 to a physical address in memory."
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hexmask.long.word 0x68 1.--10. 1. "PHYSADDRMAP26,Contains the physical address in memory to map the R26 register to."
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line.long 0x6C "MEMORYMAP27,This register maps the virtual register R27 to a physical address in memory."
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hexmask.long.word 0x6C 1.--10. 1. "PHYSADDRMAP27,Contains the physical address in memory to map the R27 register to."
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line.long 0x70 "MEMORYMAP28,This register maps the virtual register R28 to a physical address in memory."
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hexmask.long.word 0x70 1.--10. 1. "PHYSADDRMAP28,Contains the physical address in memory to map the R28 register."
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line.long 0x74 "MEMORYMAP29,This register maps the virtual register R29 to a physical address in memory."
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hexmask.long.word 0x74 1.--10. 1. "PHYSADDRMAP29,Contains the physical address in memory to map the R29 register."
|
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line.long 0x78 "MEMORYMAP30,This register maps the virtual register R30 to a physical address in memory."
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hexmask.long.word 0x78 1.--10. 1. "PHYSADDRMAP30,Contains the physical address in memory to map the R30 register."
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line.long 0x7C "MEMORYMAP31,This register maps the virtual register R31 to a physical address in memory."
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hexmask.long.word 0x7C 1.--10. 1. "PHYSADDRMAP31,Contains the physical address in memory to map the R31 register."
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|
line.long 0x80 "OPCODE,This register holds the PKAs OPCODE."
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hexmask.long.byte 0x80 27.--31. 1. "OPCODE,Defines the PKA operation:"
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bitfld.long 0x80 24.--26. "LEN,The length of the operation. The value serves as a pointer to PKA length register for example if the value is 0 PKA_L0 holds the size of the operation." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x80 18.--23. 1. "REGA,Operand A virtual address 0-15."
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|
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hexmask.long.byte 0x80 12.--17. 1. "REGB,Operand B virtual address 0-15."
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hexmask.long.byte 0x80 6.--11. 1. "REGR,Result register virtual address 0-15."
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hexmask.long.byte 0x80 0.--5. 1. "TAG,Holds the operations tag or the operand C virtual address."
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line.long 0x84 "NNPT0T1ADDR,This register maps N_NP_T0_T1 to a virtual address."
|
|
hexmask.long.byte 0x84 15.--19. 1. "T1VIRTUALADDR,Virtual address of temporary register number 1"
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hexmask.long.byte 0x84 10.--14. 1. "T0VIRTUALADDR,Virtual address of temporary register number 0"
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hexmask.long.byte 0x84 5.--9. 1. "NPVIRTUALADDR,Virtual address of register NP."
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hexmask.long.byte 0x84 0.--4. 1. "NVIRTUALADDR,Virtual address of register N."
|
|
line.long 0x88 "PKASTATUS,This register holds the PKA pipe status."
|
|
hexmask.long.byte 0x88 16.--20. 1. "OPCODE,Opcode of the last operation"
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bitfld.long 0x88 15. "MODINVOFZERO,Indicates the Modular inverse of zero." "0,1"
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bitfld.long 0x88 14. "DIVBYZERO,Indication if the division is done by zero." "0,1"
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bitfld.long 0x88 13. "ALUMODOVRFLW,Modular overflow flag." "0,1"
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bitfld.long 0x88 12. "ALUOUTZERO,Indicates if the result of ALU OUT is zero." "0,1"
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|
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bitfld.long 0x88 11. "ALUSUBISZERO,Indicates the last subtraction operations sign ." "0,1"
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bitfld.long 0x88 10. "ALUCARRYMOD,holds the carry of the last Modular operation." "0,1"
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bitfld.long 0x88 9. "ALUCARRY,Holds the carry of the last ALU operation." "0,1"
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bitfld.long 0x88 8. "ALUSIGNOUT,Indicates the last operations sign (MSB)." "0,1"
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|
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hexmask.long.byte 0x88 4.--7. 1. "ALULSB4BITS,The least significant 4-bits of the operand updated in shift operation."
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hexmask.long.byte 0x88 0.--3. 1. "ALUMSB4BITS,The most significant 4-bits of the operand updated in shift operation."
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line.long 0x8C "PKASWRESET,Writing to this register triggers a software reset of the PKA."
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bitfld.long 0x8C 0. "PKASWRESET,The reset mechanism takes about four PKA clock cycles until the reset line is deasserted" "0,1"
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line.long 0x90 "PKAL0,This register holds one of the optional size of the operation."
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hexmask.long.word 0x90 0.--12. 1. "PKAL0,Size of the operation in bytes."
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line.long 0x94 "PKAL1,This register holds one of the optional size of the operation."
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hexmask.long.word 0x94 0.--12. 1. "PKAL1,Size of the operation in bytes."
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line.long 0x98 "PKAL2,This register holds one of the optional size of the operation."
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hexmask.long.word 0x98 0.--12. 1. "PKAL2,Size of the operation in bytes."
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line.long 0x9C "PKAL3,This register holds one of the optional size of the operation."
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hexmask.long.word 0x9C 0.--12. 1. "PKAL3,Size of the operation in bytes."
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line.long 0xA0 "PKAL4,This register holds one of the optional size of the operation."
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hexmask.long.word 0xA0 0.--12. 1. "PKAL4,Size of the operation in bytes."
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line.long 0xA4 "PKAL5,This register holds one of the optional size of the operation."
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hexmask.long.word 0xA4 0.--12. 1. "PKAL5,Size of the operation in bytes."
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line.long 0xA8 "PKAL6,This register holds one of the optional size of the operation."
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hexmask.long.word 0xA8 0.--12. 1. "PKAL6,Size of the operation in bytes."
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line.long 0xAC "PKAL7,This register holds one of the optional size of the operation."
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hexmask.long.word 0xAC 0.--12. 1. "PKAL7,Size of the operation in bytes."
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line.long 0xB0 "PKAPIPERDY,This register indicates whether the PKA pipe is ready to receive a new OPCODE."
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bitfld.long 0xB0 0. "PKAPIPERDY,Indication whether PKA pipe is ready for new OPCODE." "0,1"
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line.long 0xB4 "PKADONE,This register indicates whether PKA operation is completed."
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bitfld.long 0xB4 0. "PKADONE,Indicates if PKA operation is completed and pipe is empty." "0,1"
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line.long 0xB8 "PKAMONSELECT,This register defines which PKA FSM monitor is being output."
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hexmask.long.byte 0xB8 0.--3. 1. "PKAMONSELECT,Defines which PKA FSM monitor is being output."
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group.long 0xC4++0x3
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line.long 0x0 "PKAVERSION,This register holds the pka version"
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hexmask.long 0x0 0.--31. 1. "PKAVERSION,This is the PKA version"
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group.long 0xD0++0x17
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line.long 0x0 "PKAMONREAD,The PKA monitor bus register."
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hexmask.long 0x0 0.--31. 1. "PKAMONREAD,This is the PKA monitor bus register output"
|
|
line.long 0x4 "PKASRAMADDR,first address given to PKA SRAM for write transactions."
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hexmask.long 0x4 0.--31. 1. "PKASRAMADDR,PKA SRAM write starting address"
|
|
line.long 0x8 "PKASRAMWDATA,Write data to PKA SRAM."
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hexmask.long 0x8 0.--31. 1. "PKASRAMWDATA,32 bit write to PKA SRAM: triggers the SRAM write DMA address automatically incremented"
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|
line.long 0xC "PKASRAMRDATA,Read data from PKA SRAM."
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hexmask.long 0xC 0.--31. 1. "PKASRAMRDATA,32 bit read from PKA SRAM: read - triggers the SRAM read DMA address automatically incremented"
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line.long 0x10 "PKASRAMWRCLR,Write buffer clean."
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hexmask.long 0x10 0.--31. 1. "PKASRAMWRCLR,Clear the write buffer."
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line.long 0x14 "PKASRAMRADDR,first address given to PKA SRAM for read transactions."
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hexmask.long 0x14 0.--31. 1. "PKASRAMRADDR,PKA SRAM read starting address"
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group.long 0xF0++0x3
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line.long 0x0 "PKAWORDACCESS,This register holds the data written to PKA memory using the wop opcode."
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hexmask.long 0x0 0.--31. 1. "PKAWORDACCESS,32 bit read_write data."
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group.long 0xF8++0x3
|
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line.long 0x0 "PKABUFFADDR,This register maps the virtual buffer registers to a physical address in memory."
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hexmask.long.word 0x0 0.--11. 1. "PKABUFADDR,Contains the physical address in memory to map the buffer registers."
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group.long 0x100++0x3B
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line.long 0x0 "RNGIMR,Interrupt masking register. Consists of {prng_imr trng_imr} bit[31-16] - PRNG_IMR bit[15-0] - TRNG_IMR(Ws - PRNG bit exists only if PRNG_EXISTS flag)"
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bitfld.long 0x0 5. "RNGDMADONEINT,0x1 - masks the RNG DMA completion interrupt. No interrupt is generated." "?,1: masks the RNG DMA completion interrupt"
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bitfld.long 0x0 4. "WATCHDOGINTMASK,0x1 - masks the watchdog interrupt. No interrupt is generated." "?,1: masks the watchdog interrupt"
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bitfld.long 0x0 3. "VNERRINTMASK,0x1 - masks the Von-Neumann error interrupt. No interrupt is generated." "?,1: masks the Von-Neumann error interrupt"
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bitfld.long 0x0 2. "CRNGTERRINTMASK,0x1 - masks the CRNGT error interrupt. No interrupt is generated." "?,1: masks the CRNGT error interrupt"
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bitfld.long 0x0 1. "AUTOCORRERRINTMASK,0x1 - masks the autocorrelation interrupt. No interrupt is generated." "?,1: masks the autocorrelation interrupt"
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bitfld.long 0x0 0. "EHRVALIDINTMASK,0x1 - masks the EHR interrupt. No interrupt is generated." "?,1: masks the EHR interrupt"
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line.long 0x4 "RNGISR,Status register. If corresponding RNG_IMR bit is unmasked. an interrupt is generated.Consists of trng_isr and prng_isr bit[15-0] - TRNG bit[31-16] - PRNG"
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bitfld.long 0x4 25.--26. "WHICHKATERR,When the KAT_ERR bit is set these bits represent which Known Answer Test had failed:" "0: first test of instantiation,1: second test of instantiation,2: first test of reseeding,3: second test of reseeding"
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bitfld.long 0x4 24. "KATERR,0x1 indicates that one of the KAT (Known Answer Tests) tests has failed. When set the entire engine ceases to function." "0,1"
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bitfld.long 0x4 23. "REQSIZE,0x1 indicates that the request size counter (which represents how many generations of random bits in the PRNG have been produced) has reached 2^12 thus requiring a working state update before generating new random numbers." "0,1"
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bitfld.long 0x4 22. "PRNGCRNGTERR,0x1 indicates CRNGT in the PRNG test failed. Failure occurs when two consecutive results of AES are equal" "0,1"
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bitfld.long 0x4 21. "RESEEDCNTRTOP40,0x1 indicates that the top 40 bits of the reseed counter are set (that is the reseed counter is larger than 2^48-2^8). This is a recommendation for running the reseed algorithm before the counter reaches its max value." "0,1"
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bitfld.long 0x4 20. "RESEEDCNTRFULL,0x1 indicates that the reseed counter has reached 2^48 requiring to run the reseed algorithm before generating new random numbers." "0,1"
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bitfld.long 0x4 19. "OUTPUTREADY,0x1 indicates that the result of PRNG is valid and ready to be read. The result can be read from the RNG_READOUT register." "0,1"
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bitfld.long 0x4 18. "FINALUPDATEDONE,0x1 indicates completion of final update algorithm." "0,1"
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bitfld.long 0x4 17. "INSTANTIATIONDONE,0x1 indicates completion of instantiation algorithm with no errors." "0,1"
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bitfld.long 0x4 16. "RESEEDINGDONE,0x1 indicates completion of reseeding algorithm with no errors." "0,1"
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bitfld.long 0x4 5. "RNGDMADONE,0x1 indicates RNG DMA to SRAM is completed." "0,1"
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bitfld.long 0x4 3. "VNERR,0x1 indicates Von Neumann error. Error in von Neumann occurs if 32 consecutive collected bits are identical ZERO or ONE." "0,1"
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bitfld.long 0x4 2. "CRNGTERR,0x1 indicates CRNGT in the TRNG test failed. Failure occurs when two consecutive blocks of 16 collected bits are equal." "0,1"
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bitfld.long 0x4 1. "AUTOCORRERR,0x1 indicates Autocorrelation test failed four times in a row. When it set TRNG ceases to function until next reset." "0,1"
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bitfld.long 0x4 0. "EHRVALID,0x1 indicates that 192 bits have been collected in the TRNG and are ready to be read." "0,1"
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line.long 0x8 "RNGICR,Interrupt_status bit clear Register. Consists of trng_icr and prng_icr bit[15-0] - TRNG bit[31-16] - PRNG"
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bitfld.long 0x8 25.--26. "WHICHKATERR,Cannot be cleared by SW! Only RNG reset clears this bit." "0,1,2,3"
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bitfld.long 0x8 24. "KATERR,Cannot be cleared by SW! Only RNG reset clears this bit." "0,1"
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bitfld.long 0x8 23. "REQSIZE,Writing value 0x1 - clears corresponding bit in RNGISR" "?,1: clears corresponding bit in RNGISR"
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bitfld.long 0x8 22. "PRNGCRNGTERR,Writing value 0x1 - clears corresponding bit in RNGISR" "?,1: clears corresponding bit in RNGISR"
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bitfld.long 0x8 21. "RESEEDCNTRTOP40,Writing value 0x1 - clears corresponding bit in RNGISR" "?,1: clears corresponding bit in RNGISR"
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bitfld.long 0x8 20. "RESEEDCNTRFULL,Writing value 0x1 - clears corresponding bit in RNGISR" "?,1: clears corresponding bit in RNGISR"
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bitfld.long 0x8 19. "OUTPUTREADY,Writing value 0x1 - clears corresponding bit in RNGISR" "?,1: clears corresponding bit in RNGISR"
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bitfld.long 0x8 18. "FINALUPDATEDONE,Writing value 0x1 - clears corresponding bit in RNGISR" "?,1: clears corresponding bit in RNGISR"
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bitfld.long 0x8 17. "INSTANTIATIONDONE,Writing value 0x1 - clears corresponding bit in RNGISR" "?,1: clears corresponding bit in RNGISR"
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bitfld.long 0x8 16. "RESEEDINGDONE,Writing value 0x1 - clears corresponding bit in RNGISR" "?,1: clears corresponding bit in RNGISR"
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bitfld.long 0x8 5. "RNGDMADONE,Writing value 0x1 - clears corresponding bit in RNGISR" "?,1: clears corresponding bit in RNGISR"
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bitfld.long 0x8 4. "RNGWATCHDOG,Writing value 0x1 - clears corresponding bit in RNGISR" "?,1: clears corresponding bit in RNGISR"
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bitfld.long 0x8 3. "VNERR,Writing value 0x1 - clears corresponding bit in RNGISR" "?,1: clears corresponding bit in RNGISR"
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bitfld.long 0x8 2. "CRNGTERR,Writing value 0x1 - clears corresponding bit in RNGISR" "?,1: clears corresponding bit in RNGISR"
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bitfld.long 0x8 1. "AUTOCORRERR,Cannot be cleared by SW! Only RNG reset clears this bit." "0,1"
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|
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bitfld.long 0x8 0. "EHRVALID,Writing value 0x1 - clears corresponding bit in RNGISR" "?,1: clears corresponding bit in RNGISR"
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line.long 0xC "TRNGCONFIG,This register handles TRNG configuration"
|
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bitfld.long 0xC 2. "SOPSEL,Secure Output Port selection:" "0: sop_data port reflects PRNG output..,1: sop_data port reflects TRNG output (EHR_DATA)."
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bitfld.long 0xC 0.--1. "RNDSRCSEL,Defines the length of the oscillator ring (= the number of inverters) out of four possible selections." "0,1,2,3"
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line.long 0x10 "TRNGVALID,This register indicates that the TRNG data is valid."
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bitfld.long 0x10 0. "EHRVALID,0x1 indicates that collection of bits in the TRNG is completed and data can be read from the EHR_DATA register." "0,1"
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line.long 0x14 "EHRDATA0,This register contains the data collected in the TRNG[31_0]. Note: can only be set while in debug mode (rng_debug_enable input is set)."
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hexmask.long 0x14 0.--31. 1. "EHRDATA,Contains the data collected in the TRNG[31_0]. Note: can only be set while in debug mode (rng_debug_enable input is set)."
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line.long 0x18 "EHRDATA1,This register contains the data collected in the TRNG[63_32]. Note: can only be set while in debug mode (rng_debug_enable input is set)."
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hexmask.long 0x18 0.--31. 1. "EHRDATA,Contains the data collected in the TRNG[63_32]. Note: can only be set while in debug mode (rng_debug_enable input is set)."
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line.long 0x1C "EHRDATA2,This register contains the data collected in the TRNG[95_64]. Note: can only be set while in debug mode (rng_debug_enable input is set)."
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hexmask.long 0x1C 0.--31. 1. "EHRDATA,Contains the data collected in the TRNG[95_64]. Note: can only be set while in debug mode (rng_debug_enable input is set)."
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line.long 0x20 "EHRDATA3,This register contains the data collected in the TRNG[127_96]. Note: can only be set while in debug mode (rng_debug_enable input is set)."
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hexmask.long 0x20 0.--31. 1. "EHRDATA,Contains the data collected in the TRNG[127_96]. Note: can only be set while in debug mode (rng_debug_enable input is set)."
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line.long 0x24 "EHRDATA4,This register contains the data collected in the TRNG[159_128]. Note: can only be set while in debug mode (rng_debug_enable input is set)."
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hexmask.long 0x24 0.--31. 1. "EHRDATA,Contains the data collected in the TRNG[159_128]. Note: can only be set while in debug mode (rng_debug_enable input is set)."
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line.long 0x28 "EHRDATA5,This register contains the data collected in the TRNG[191_160]. Note: can only be set while in debug mode (rng_debug_enable input is set)."
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hexmask.long 0x28 0.--31. 1. "EHRDATA,Contains the data collected in the TRNG[191_160]. Note: can only be set while in debug mode (rng_debug_enable input is set)."
|
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line.long 0x2C "RNDSOURCEENABLE,This register holds the enable signal for the random source."
|
|
bitfld.long 0x2C 0. "RNDSRCEN,Enable signal for the random source." "0,1"
|
|
line.long 0x30 "SAMPLECNT1,Counts clocks between sampling of random bit."
|
|
hexmask.long 0x30 0.--31. 1. "SAMPLECNTR1,Sets the number of rng_clk cycles between two consecutive ring oscillator samples. Note: If the Von-Neumann is bypassed the minimum value for sample counter must not be less than decimal seventeen."
|
|
line.long 0x34 "AUTOCORRSTATISTIC,Statistics about autocorrelation test activations."
|
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hexmask.long.byte 0x34 14.--21. 1. "AUTOCORRFAILS,Count each time an autocorrelation test fails. Any write to the register resets the counter. Stops collecting statistics if one of the counters has reached the limit."
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hexmask.long.word 0x34 0.--13. 1. "AUTOCORRTRYS,Count each time an autocorrelation test starts. Any write to the register resets the counter. Stops collecting statistics if one of the counters has reached the limit."
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line.long 0x38 "TRNGDEBUGCONTROL,This register is used to debug the TRNG"
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bitfld.long 0x38 3. "AUTOCORRELATEBYPASS,When this bit is set the autocorrelation test in the TRNG module is bypassed. Note: Can only be set while in debug mode. If TRNG_TESTS_BYPASS_EN HW flag is defined this bit can be set while not in debug mode." "0,1"
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bitfld.long 0x38 2. "TRNGCRNGTBYPASS,When this bit is set the CRNGT test in the TRNG is bypassed. Note: Can only be set while in debug mode. If TRNG_TESTS_BYPASS_EN HW flag is defined this bit can be set while not in debug mode." "0,1"
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bitfld.long 0x38 1. "VNCBYPASS,When this bit is set the Von-Neumann balancer is bypassed (including the 32 consecutive bits test). Note: Can only be set while in debug mode. If TRNG_TESTS_BYPASS_EN HW flag is defined this bit can be set while not in debug mode." "0,1"
|
|
group.long 0x140++0x3
|
|
line.long 0x0 "RNGSWRESET,Generate SW reset solely to RNG block."
|
|
bitfld.long 0x0 0. "RNGSWRESET,Any value written (0x0 or 0x1) causes a reset cycle to the TRNG block." "0,1"
|
|
group.long 0x1B4++0x1F
|
|
line.long 0x0 "RNGDEBUGENINPUT,Defines the RNG in debug mode"
|
|
bitfld.long 0x0 0. "RNGDEBUGEN,Reflects the rng_debug_enable input port" "0,1"
|
|
line.long 0x4 "RNGBUSY,RNG busy indication"
|
|
bitfld.long 0x4 2. "PRNGBUSY,Reflects prng_busy." "0,1"
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bitfld.long 0x4 1. "TRNGBUSY,Reflects trng_busy." "0,1"
|
|
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bitfld.long 0x4 0. "RNGBUSY,Reflects rng_busy output port which Consists of trng_busy and prng_busy." "0,1"
|
|
line.long 0x8 "RSTBITSCOUNTER,Resets the counter of collected bits in the TRNG"
|
|
bitfld.long 0x8 0. "RSTBITSCOUNTER,Writing any value to this address resets the bits counter and trng valid registers." "0,1"
|
|
line.long 0xC "RNGVERSION,This register holds the RNG version"
|
|
bitfld.long 0xC 7. "RNGUSE5SBOXES,RNG use 5 (or 20) SBOX AES" "0: 20 SBOX AES,1: 5 SBOX AES"
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bitfld.long 0xC 6. "RESEEDINGEXISTS,Reseeding exists." "0: Reseed does not exists,1: exists"
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newline
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bitfld.long 0xC 5. "KATEXISTS,KAT exists." "0: does not exist,1: exists"
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newline
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bitfld.long 0xC 4. "PRNGEXISTS,PRNG Exists." "0: does not exist,1: exists"
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newline
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bitfld.long 0xC 3. "TRNGTESTSBYPASSEN,TRNG tests bypass enable." "0: trng tests bypass not enabled,1: trng tests bypass enabled"
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newline
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bitfld.long 0xC 2. "AUTOCORREXISTS,Auto correct exists." "0: does not exist,1: exists"
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newline
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bitfld.long 0xC 1. "CRNGTEXISTS,CRNGT exists." "0: does not exist,1: exists"
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newline
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bitfld.long 0xC 0. "EHRWIDTH192,EHR width selection." "0: 128 bit EHR,1: 192 bit EHR"
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line.long 0x10 "RNGCLKENABLE,Writing to this register enables_disables the RNG clock."
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bitfld.long 0x10 0. "EN,Writing value 0x1 enables RNG clock." "0,1"
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line.long 0x14 "RNGDMAENABLE,Writing to this register enables_disables the RNG DMA."
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bitfld.long 0x14 0. "EN,Writing value 0x1 enables RNG DMA to SRAM. The Value is cleared when DMA completes its operation." "0,1"
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line.long 0x18 "RNGDMASRCMASK,This register defines which ring-oscillator length should be used when using the RNG DMA."
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bitfld.long 0x18 3. "ENSRCSEL3,Writing value 0x1 enables SRC_SEL 3." "0,1"
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newline
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bitfld.long 0x18 2. "ENSRCSEL2,Writing value 0x1 enables SRC_SEL 2." "0,1"
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newline
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bitfld.long 0x18 1. "ENSRCSEL1,Writing value 0x1 enables SRC_SEL 1." "0,1"
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newline
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bitfld.long 0x18 0. "ENSRCSEL0,Writing value 0x1 enables SRC_SEL 0." "0,1"
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line.long 0x1C "RNGDMASRAMADDR,This register defines the start address of the DMA for the TRNG data."
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hexmask.long.word 0x1C 0.--10. 1. "RNGSRAMDMAADDR,Defines the start address of the DMA for the TRNG data."
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group.long 0x1D8++0x7
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line.long 0x0 "RNGWATCHDOGVAL,This register defines the number of 192-bits samples that the DMA collects per RNG configuration.bitfield 7:0 RNG_SAMPLES_NUM rw 0x0 Defines the number of 192-bits samples that the DMA collects per RNG configuration.bitfield 31:8.."
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hexmask.long 0x0 0.--31. 1. "RNGWATCHDOGVAL,Defines the maximum number of clock cycles per TRNG collection of 192 samples. If the number of cycles for a collection exceeds this threshold TRNG signals an interrupt."
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line.long 0x4 "RNGDMASTATUS,This register holds the RNG DMA status."
|
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hexmask.long.byte 0x4 3.--10. 1. "NUMOFSAMPLES,Number of samples already collected in the current ring oscillator chain length."
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newline
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bitfld.long 0x4 1.--2. "DMASRCSEL,The active ring oscillator length using by DMA" "0,1,2,3"
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|
newline
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bitfld.long 0x4 0. "RNGDMABUSY,Indicates whether DMA is busy." "0,1"
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group.long 0x380++0x6B
|
|
line.long 0x0 "CHACHACONTROLREG,CHACHA general configuration."
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|
bitfld.long 0x0 10. "USEIV96BIT,If use 96bit IV" "0,1"
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newline
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bitfld.long 0x0 9. "RESETBLOCKCNT,For new message" "0,1"
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newline
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bitfld.long 0x0 4.--5. "NUMOFROUNDS,The core of ChaCha is a hash function which based on rotation operations. The hash function consist in application of 20 rounds (default value). In additional ChaCha have two variants (they work exactly as the original algorithm): ChaCha20_8.." "0: 20 rounds,1: 12 rounds,2: 8 rounds,3: Not applicable"
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|
newline
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bitfld.long 0x0 3. "KEYLEN,For All Core:" "0: 256 bit.,1: 128 bit."
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newline
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bitfld.long 0x0 2. "CALCKEYFORPOLY1305,Only if ChaCha core:" "0: disable.,1: enable."
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newline
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bitfld.long 0x0 1. "INITFROMHOST,Start init for new Message:" "0: disable.,1: enable."
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newline
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bitfld.long 0x0 0. "CHACHAORSALSA,Core:" "0: ChaCha mode,1: Salsa mode."
|
|
line.long 0x4 "CHACHAVERSION,CHACHA Version"
|
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hexmask.long 0x4 0.--31. 1. "CHACHAVERSION,CHACHA version."
|
|
line.long 0x8 "CHACHAKEY0,bits 255:224 of CHACHA Key"
|
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hexmask.long 0x8 0.--31. 1. "CHACHAKEY0,bits 255:224 of CHACHA Key"
|
|
line.long 0xC "CHACHAKEY1,bits 223:192 of CHACHA Key"
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hexmask.long 0xC 0.--31. 1. "CHACHAKEY1,bits 223:192 of CHACHA Key"
|
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line.long 0x10 "CHACHAKEY2,bits 191:160 of CHACHA Key"
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hexmask.long 0x10 0.--31. 1. "CHACHAKEY2,bits191:160 of CHACHA Key"
|
|
line.long 0x14 "CHACHAKEY3,bits159:128 of CHACHA Key"
|
|
hexmask.long 0x14 0.--31. 1. "CHACHAKEY3,bits 159:128 of CHACHA Key"
|
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line.long 0x18 "CHACHAKEY4,bits 127:96 of CHACHA Key"
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hexmask.long 0x18 0.--31. 1. "CHACHAKEY4,bits 127:96 of CHACHA Key"
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line.long 0x1C "CHACHAKEY5,bits 95:64 of CHACHA Key"
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hexmask.long 0x1C 0.--31. 1. "CHACHAKEY5,bits 95:64 of CHACHA Key"
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line.long 0x20 "CHACHAKEY6,bits 63:32 of CHACHA Key"
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hexmask.long 0x20 0.--31. 1. "CHACHAKEY6,bits 63:32 of CHACHA Key"
|
|
line.long 0x24 "CHACHAKEY7,bits 31:0 of CHACHA Key"
|
|
hexmask.long 0x24 0.--31. 1. "CHACHAKEY7,bits 31:0 of CHACHA Key"
|
|
line.long 0x28 "CHACHAIV0,bits 31:0 of CHACHA_IV0 register"
|
|
hexmask.long 0x28 0.--31. 1. "CHACHAIV0,bits 31:0 of CHACHA_IV0 register"
|
|
line.long 0x2C "CHACHAIV1,bits 31:0 of CHACHA_IV1 register"
|
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hexmask.long 0x2C 0.--31. 1. "CHACHAIV1,bits 31:0 of CHACHA_IV1 register"
|
|
line.long 0x30 "CHACHABUSY,This register is set when the CHACHA_SALSA core is active"
|
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bitfld.long 0x30 0. "CHACHABUSY,CHACHA_BUSY Register. This register is set when the CHACHA_SALSA core is active." "0,1"
|
|
line.long 0x34 "CHACHAHWFLAGS,This register holds the pre-synthesis HW flag configuration of the CHACHA_SALSA engine"
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bitfld.long 0x34 2. "FASTCHACHA,If this flag is set the next matrix calculated when the current one is written to data output path (same flag for Salsa core):" "0: disable.,1: enable."
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|
newline
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bitfld.long 0x34 1. "SALSAEXISTS,If this flag is set the Salsa_ChaCha engine include Salsa implementation:" "0: disable.,1: enable."
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|
newline
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bitfld.long 0x34 0. "CHACHAEXISTS,If this flag is set the Salsa_ChaCha engine include ChaCha implementation:" "0: disable.,1: enable."
|
|
line.long 0x38 "CHACHABLOCKCNTLSB,The two first words (n) in the last row of the cipher matrix are the block counter. At the end of each block (512b). the block_cnt for the next block is written by HW to the block_cnt_lsb and block_cnt_msb registers. Need reset block.."
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hexmask.long 0x38 0.--31. 1. "CHACHABLOCKCNTLSB,bits 31:0 of CHACHA_BLOCK_CNT_LSB register."
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line.long 0x3C "CHACHABLOCKCNTMSB,The two first words (n) in the last row of the cipher matrix are the block counter. At the end of each block (512b). the block_cnt for the next block is written by HW to the block_cnt_lsb and block_cnt_msb registers. Need reset block.."
|
|
hexmask.long 0x3C 0.--31. 1. "CHACHABLOCKCNTMSB,bits 31:0 of CHACHA_BLOCK_CNT_MSB register."
|
|
line.long 0x40 "CHACHASWRESET,Resets CHACHA_SALSA engine."
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|
bitfld.long 0x40 0. "CHACHSWRESET,Writing to this address resets the only FSM of CHACHA engine. The reset takes 4 CORE_CLK cycles." "0,1"
|
|
line.long 0x44 "CHACHAFORPOLYKEY0,bits 255:224 of CHACHA_FOR_POLY_KEY"
|
|
hexmask.long 0x44 0.--31. 1. "CHACHAFORPOLYKEY0,bits 255:224 of CHACHA_FOR_POLY_KEY"
|
|
line.long 0x48 "CHACHAFORPOLYKEY1,bits 223:192 of CHACHA_FOR_POLY_KEY"
|
|
hexmask.long 0x48 0.--31. 1. "CHACHAFORPOLYKEY1,bits 223:192 of CHACHA_FOR_POLY_KEY"
|
|
line.long 0x4C "CHACHAFORPOLYKEY2,bits191:160 of CHACHA_FOR_POLY_KEY"
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hexmask.long 0x4C 0.--31. 1. "CHACHAFORPOLYKEY2,bits191:160 of CHACHA_FOR_POLY_KEY"
|
|
line.long 0x50 "CHACHAFORPOLYKEY3,bits159:128 of CHACHA_FOR_POLY_KEY"
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|
hexmask.long 0x50 0.--31. 1. "CHACHAFORPOLYKEY3,bits 159:128 of CHACHA_FOR_POLY_KEY"
|
|
line.long 0x54 "CHACHAFORPOLYKEY4,bits 127:96 of CHACHA_FOR_POLY_KEY"
|
|
hexmask.long 0x54 0.--31. 1. "CHACHAFORPOLYKEY4,bits 127:96 of CHACHA_FOR_POLY_KEY"
|
|
line.long 0x58 "CHACHAFORPOLYKEY5,bits 95:64 of CHACHA_FOR_POLY_KEY"
|
|
hexmask.long 0x58 0.--31. 1. "CHACHAFORPOLYKEY5,bits 95:64 of CHACHA_FOR_POLY_KEY"
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|
line.long 0x5C "CHACHAFORPOLYKEY6,bits 63:32 of CHACHA_FOR_POLY_KEY"
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hexmask.long 0x5C 0.--31. 1. "CHACHAFORPOLYKEY6,bits 63:32 of CHACHA_FOR_POLY_KEY"
|
|
line.long 0x60 "CHACHAFORPOLYKEY7,bits 31:0 of CHACHA_FOR_POLY_KEY"
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|
hexmask.long 0x60 0.--31. 1. "CHACHAFORPOLYKEY7,bits 31:0 of CHACHA_FOR_POLY_KEY"
|
|
line.long 0x64 "CHACHABYTEWORDORDERCNTLREG,CHACHA_SALSA DATA ORDER configuration."
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|
bitfld.long 0x64 4. "CHACHADOUTBYTEORDER,Change the byte order of the output data." "0: disable.,1: enable. (reverse each byte in each word output.."
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newline
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bitfld.long 0x64 3. "CHACHADOUTWORDORDER,Change the words order of the output data." "0: disable.,1: enable. (reverse each word in 128 bit output (.."
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|
newline
|
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bitfld.long 0x64 2. "CHACHACOREMATRIXLBEORDER,Change the quarter of a matrix order in core" "0: disable.,1: enable. (reverse each quarter of a matrix.."
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|
newline
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bitfld.long 0x64 1. "CHACHADINBYTEORDER,Change the byte order of the input data." "0: disable.,1: enable. (reverse each byte in each word input.."
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|
newline
|
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bitfld.long 0x64 0. "CHACHADINWORDORDER,Change the words order of the input data." "0: disable.,1: enable. (reverse each word in 128 bit input (.."
|
|
line.long 0x68 "CHACHADEBUGREG,This register is used to debug the CHACHA engine"
|
|
bitfld.long 0x68 0.--1. "CHACHADEBUGFSMSTATE,CHACHA_DEBUG_FSM_STATE" "0: The idle state.,1: The init state.,?,?"
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|
group.long 0x400++0x73
|
|
line.long 0x0 "AESKEY00,bits 31:0 of AES Key0 (used as the AES key in non-tunneling operations. and as the first tunnel stage key in tunneling operations)."
|
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hexmask.long 0x0 0.--31. 1. "AESKEY00,bits 31:0 of AES Key0."
|
|
line.long 0x4 "AESKEY01,bits 63:32 of AES Key0 (used as the AES key in non-tunneling operations. and as the first tunnel stage key in tunneling operations)."
|
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hexmask.long 0x4 0.--31. 1. "AESKEY01,bits 63:32 of AES Key0."
|
|
line.long 0x8 "AESKEY02,bits 95:64 of AES Key0 (used as the AES key in non-tunneling operations. and as the first tunnel stage key in tunneling operations)."
|
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hexmask.long 0x8 0.--31. 1. "AESKEY02,bits 95:64 of AES Key0."
|
|
line.long 0xC "AESKEY03,bits 127:96 of AES Key0 (used as the AES key in non-tunneling operations. and as the first tunnel stage key in tunneling operations)."
|
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hexmask.long 0xC 0.--31. 1. "AESKEY03,bits 127:96 of AES Key0."
|
|
line.long 0x10 "AESKEY04,bits 159:128 of AES Key0 (used as the AES key in non-tunneling operations. and as the first tunnel stage key in tunneling operations)."
|
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hexmask.long 0x10 0.--31. 1. "AESKEY04,bits 159:128 of AES Key0 ."
|
|
line.long 0x14 "AESKEY05,bits 191:160 of AES Key0 (used as the AES key in non-tunneling operations. and as the first tunnel stage key in tunneling operations)."
|
|
hexmask.long 0x14 0.--31. 1. "AESKEY05,bits 191:160 of AES Key0."
|
|
line.long 0x18 "AESKEY06,bits 223:192 of AES Key0 (used as the AES key in non-tunneling operations. and as the first tunnel stage key in tunneling operations)."
|
|
hexmask.long 0x18 0.--31. 1. "AESKEY06,bits 223:192 of AES Key0."
|
|
line.long 0x1C "AESKEY07,bits 255:224 of AES Key0 (used as the AES key in non-tunneling operations. and as the first tunnel stage key in tunneling operations)."
|
|
hexmask.long 0x1C 0.--31. 1. "AESKEY07,bits 255:224 of AES Key0."
|
|
line.long 0x20 "AESKEY10,bits 31:0 of AES Key1 (used as the second AES tunnel stage key in tunneling operations)."
|
|
hexmask.long 0x20 0.--31. 1. "AESKEY10,bits 31:0 of AES Key1."
|
|
line.long 0x24 "AESKEY11,bits 63:32 of AES Key1 (used as the second AES tunnel stage key in tunneling operations)."
|
|
hexmask.long 0x24 0.--31. 1. "AESKEY11,bits 63:32 of AES Key1."
|
|
line.long 0x28 "AESKEY12,bits 95:64 of AES Key1 (used as the second AES tunnel stage key in tunneling operations)."
|
|
hexmask.long 0x28 0.--31. 1. "AESKEY12,bits 95:64 of AES Key1."
|
|
line.long 0x2C "AESKEY13,bits 127:96 of AES Key1 (used as the second AES tunnel stage key in tunneling operations)."
|
|
hexmask.long 0x2C 0.--31. 1. "AESKEY13,bits 127:96 of AES Key1."
|
|
line.long 0x30 "AESKEY14,bits 159:128 of AES Key1 (used as the second AES tunnel stage key in tunneling operations)."
|
|
hexmask.long 0x30 0.--31. 1. "AESKEY14,bits 159:128 of AES Key1."
|
|
line.long 0x34 "AESKEY15,bits 191:160 of AES Key1 (used as the second AES tunnel stage key in tunneling operations)."
|
|
hexmask.long 0x34 0.--31. 1. "AESKEY15,bits 191:160 of AES Key1."
|
|
line.long 0x38 "AESKEY16,bits 223:192 of AES Key1 (used as the second AES tunnel stage key in tunneling operations)."
|
|
hexmask.long 0x38 0.--31. 1. "AESKEY16,bits 223:192 of AES Key1."
|
|
line.long 0x3C "AESKEY17,bits 255:224 of AES Key1 (used as the second AES tunnel stage key in tunneling operations)."
|
|
hexmask.long 0x3C 0.--31. 1. "AESKEY17,bits 255:224 of AES Key1."
|
|
line.long 0x40 "AESIV00,bits 31:0 of AES_IV0 register. AES IV0 is used as the AES IV (Initialization Value) register in non-tunneling operations.and as the first tunnel stage IV register in tunneling operations.The IV register should be loaded according to the AES.."
|
|
hexmask.long 0x40 0.--31. 1. "AESIV00,bits 31:0 of AES_IV0 register."
|
|
line.long 0x44 "AESIV01,bits 63:32 of AES_IV0 128b register.For the description of AES_IV0. see the AES_IV_0_0 register description"
|
|
hexmask.long 0x44 0.--31. 1. "AESIV01,bits 63:32 of AES_IV0 register."
|
|
line.long 0x48 "AESIV02,bits 95:64 of AES_IV0 128b register.For the description of AES_IV0. see the AES_IV_0_0 register description"
|
|
hexmask.long 0x48 0.--31. 1. "AESIV02,bits 95:64 of AES_IV0 register."
|
|
line.long 0x4C "AESIV03,bits 127:96 of AES_IV0 128b register.For the description of AES_IV0. see the AES_IV_0_0 register description"
|
|
hexmask.long 0x4C 0.--31. 1. "AESIV03,bits 127:96 of AES_IV0 register."
|
|
line.long 0x50 "AESIV10,bits 31:0 of AES_IV1 128b register.AES IV1 is used as the AES IV (Initialization Value) register as the second tunnel stage IV register in tunneling operations.The IV register should be loaded according to the AES mode:in AES CBC_CBC-MAC - the.."
|
|
hexmask.long 0x50 0.--31. 1. "AESIV10,bits 31:0 of AES_IV1 register."
|
|
line.long 0x54 "AESIV11,bits 63:32 of AES_IV1 128b register.For the description of AES_IV1. see the AES_IV_1_0 register description"
|
|
hexmask.long 0x54 0.--31. 1. "AESIV11,bits 63:32 of AES_IV1 register."
|
|
line.long 0x58 "AESIV12,bits 95:64 of AES_IV1 128b register.For the description of AES_IV1. see the AES_IV_1_0 register description"
|
|
hexmask.long 0x58 0.--31. 1. "AESIV12,bits 95:64 of AES_IV1 register."
|
|
line.long 0x5C "AESIV13,bits 127:96 of AES_IV1 128b register.For the description of AES_IV1. see the AES_IV_1_0 register description"
|
|
hexmask.long 0x5C 0.--31. 1. "AESIV13,bits 127:96 of AES_IV1 register."
|
|
line.long 0x60 "AESCTR00,bits 31:0 of AES_CTR0 128b register.AES CTR0 is used as the AES CTR (counter) register in non-tunneling operations. and as the first tunnel stage CTR register in tunneling operations.The CTR register should be loaded according to the AES mode:in.."
|
|
hexmask.long 0x60 0.--31. 1. "AESCTR00,bits 31:0 of AES_CTR0 register."
|
|
line.long 0x64 "AESCTR01,bits 63:32 of AES_CTR0 128b register.For the description of AES_CTR0. see the AES_CTR_0_0 register description."
|
|
hexmask.long 0x64 0.--31. 1. "AESCTR01,bits 63:32 of AES_CTR0 register."
|
|
line.long 0x68 "AESCTR02,bits 95:64 of AES_CTR0 128b register.For the description of AES_CTR0. see the AES_CTR_0_0 register description."
|
|
hexmask.long 0x68 0.--31. 1. "AESCTR02,bits 95:64 of AES_CTR0 register."
|
|
line.long 0x6C "AESCTR03,bits 127:96 of AES_CTR0 128b register.For the description of AES_CTR0. see the AES_CTR_0_0 register description."
|
|
hexmask.long 0x6C 0.--31. 1. "AESCTR03,bits 127:96 of AES_CTR0 register."
|
|
line.long 0x70 "AESBUSY,This register is set when the AES core is active"
|
|
bitfld.long 0x70 0. "AESBUSY,AES_BUSY register. This register is set when the AES core is active" "0,1"
|
|
group.long 0x478++0x7
|
|
line.long 0x0 "AESSK,writing to this address causes sampling of the HW key to the AES_KEY0 register"
|
|
bitfld.long 0x0 0. "AESSK,writing to this address causes sampling of the HW key to the AES_KEY0 register" "0,1"
|
|
line.long 0x4 "AESCMACINIT,Writing to this address triggers the AES engine generating of K1 and K2 for AES CMAC operations. Note: This is a special register. affected by internal logic. Test result of this register is NA."
|
|
bitfld.long 0x4 0. "AESCMACINIT,Writing to this address starts the generating of K1 and K2 for AES CMAC operations" "0,1"
|
|
group.long 0x4B4++0x3
|
|
line.long 0x0 "AESSK1,writing to this address causes sampling of the HW key to the AES_KEY1 register"
|
|
bitfld.long 0x0 0. "AESSK1,writing to this address causes sampling of the HW key to the AES_KEY1 register" "0,1"
|
|
group.long 0x4BC++0x7
|
|
line.long 0x0 "AESREMAININGBYTES,This register should be set with the amount of remaining bytes until the end of the current AES operation. The AES engine counts down from this value to determine the last _ one before last blocks in AES CMAC. XTS AES and AES CCM."
|
|
hexmask.long 0x0 0.--31. 1. "AESREMAININGBYTES,This register should be set with the amount of remaining bytes until the end of the current AES operation. The AES engine counts down from this value to determine the last _ one before last blocks in AES CMAC XTS AES and AES CCM."
|
|
line.long 0x4 "AESCONTROL,This register holds the configuration of the AES engine. Note: This is a special register. affected by internal logic. Test result of this register is NA."
|
|
bitfld.long 0x4 31. "DIRECTACCESS,Using direct access and not the din-dout interface" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "AESXORCRYPTOKEY,This field determines the value that is written to AES_KEY0 when AES_SK is kicked:" "0: The value that is written to AES_KEY0 is the..,1: The value that is written to AES_KEY0 is the.."
|
|
newline
|
|
bitfld.long 0x4 28. "AESOUTMIDTUNTOHASH,This field determines for AES-TO-HASH-AND-DOUT tunneling operations whether the AES outputs to the HASH the result of the first or the second tunneling stage:" "0: The AES engine writes to the hash the result of..,1: The AES engine writes to the hash the result of.."
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|
newline
|
|
bitfld.long 0x4 26. "AESTUNNELB1PADEN,This field determines whether the input data to the second tunnel stage is padded with zeroes (according to the remaining_bytes value) or not:" "0: The data input to the second tunnel block is not..,1: The data input to the second tunnel block is.."
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|
newline
|
|
bitfld.long 0x4 25. "AESOUTPUTMIDTUNNELDATA,This fields determines whether the AES output is the result of the first or second tunneling stage:" "0: The AES engine outputs the result of the second..,1: The AES engine outputs the result of the first.."
|
|
newline
|
|
bitfld.long 0x4 24. "AESTUNNEL0ENCRYPT,This field determines whether the first tunnel stage performs encrypt or decrypt operation :" "0: the first tunnel stage performs decrypt..,1: the first tunnel stage performs encrypt.."
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|
newline
|
|
bitfld.long 0x4 23. "AESTUNB1USESPADDEDDATAIN,This field determines for tunneling operations the data that is fed to the second tunneling stage:" "0: the output of the first block (standard..,1: data_in after padding rather than the output of.."
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|
newline
|
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bitfld.long 0x4 22. "AESTUNNEL1DECRYPT,This field determines whether the second tunnel stage performs encrypt or decrypt operation :" "0: the second tunnel stage performs encrypt..,1: the second tunnel stage performs decrypt.."
|
|
newline
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|
bitfld.long 0x4 14.--15. "NKKEY1,This field determines the AES key length of the second stage operation in tunneling operations:" "0: 128 bits key,1: 192 bits key,2: 256 bits key,3: Not applicable"
|
|
newline
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bitfld.long 0x4 12.--13. "NKKEY0,This field determines the AES Key length in non tunneling operations and the AES key length of the first stage in tunneling operations:" "0: 128 bits key,1: 192 bits key,2: 256 bits key,3: Not applicable"
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|
newline
|
|
bitfld.long 0x4 11. "CBCISBITLOCKER,If MODE_KEY0 is set to 3b001 (CBC) and this field is set - the mode isBITLOCKER." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "AESTUNNELISON,This field determines whether the AES performs dual-tunnel operations or standard non-tunneling operations:" "0: standard non-tunneling operations,1: tunneling operations."
|
|
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bitfld.long 0x4 8. "CBCISESSIV,If MODE_KEY0 is set to 3b001 (CBC) and this field is set - the mode is CBC with ESSIV." "0,1"
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|
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bitfld.long 0x4 5.--7. "MODEKEY1,This field determines the AES mode of the second stage operation in tunneling operations:" "0: ECB modekey1,1: CBC modekey1,2: CTR modekey1,3: CBC MAC modekey1,4: XEX_XTS modekey1,5: XCBC MAC modekey1,6: OFB modekey1,7: CMAC modekey1"
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|
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bitfld.long 0x4 2.--4. "MODEKEY0,This field determines the AES mode in non tunneling operations and the AES mode of the first stage in tunneling operations:" "0: ECB modekey0,1: CBC modekey0,2: CTR modekey0,3: CBCMAC modekey0,4: XEX XTS modekey0,5: XCBC MAC modekey0,6: OFB modekey0,7: CMAC modekey0"
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bitfld.long 0x4 1. "MODE0ISCBCCTS,If MODE_KEY0 is set to 3b001 (CBC) and this field is set - the mode is CBC-CTS. In addition If MODE_KEY0 is set to 3b010 (CTR) and this field is set - the mode is GCTR." "0,1"
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bitfld.long 0x4 0. "DECKEY0,This field determines whether the AES performs Decrypt_Encrypt operations in non-tunneling operations:" "0: Encrypt,1: Decrypt"
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|
group.long 0x4C8++0x3
|
|
line.long 0x0 "AESHWFLAGS,This register holds the pre-synthesis HW flag configuration of the AES engine"
|
|
bitfld.long 0x0 12. "DFACNTRMSREXIST,the DFA_CNTRMSR_EXIST flag" "0,1"
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|
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|
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bitfld.long 0x0 11. "SECONDREGSSETEXIST,the SECOND_REGS_SET_EXIST flag" "0,1"
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|
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|
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bitfld.long 0x0 10. "aestunnelexists,the aes_tunnel_exists flag" "0,1"
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|
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|
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bitfld.long 0x0 9. "AESSUPPORTPREVIV,the AES_SUPPORT_PREV_IV flag" "0,1"
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|
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bitfld.long 0x0 8. "USE5SBOXES,the USE_5_SBOXES flag" "0,1"
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|
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|
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bitfld.long 0x0 5. "USESBOXTABLE,the USE_SBOX_TABLE flag" "0,1"
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|
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bitfld.long 0x0 4. "ONLYENCRYPT,the ONLY_ENCRYPT flag" "0,1"
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|
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bitfld.long 0x0 3. "CTREXIST,the CTR_EXIST flag" "0,1"
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|
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bitfld.long 0x0 2. "DPACNTRMSREXIST,the DPA_CNTRMSR_EXIST flag" "0,1"
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|
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bitfld.long 0x0 1. "AESLARGERKEK,the AES_LARGE_RKEK flag" "0,1"
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|
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|
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bitfld.long 0x0 0. "SUPPORT256192KEY,the SUPPORT_256_192_KEY flag" "0,1"
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|
group.long 0x4D8++0x3
|
|
line.long 0x0 "AESCTRNOINCREMENT,This register enables the AES CTR no increment mode (in which the counter mode is not incremented between 2 blocks)"
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|
bitfld.long 0x0 0. "AESCTRNOINCREMENT,This field enables the AES CTR 'no increment' mode (in which the counter mode is not incremented between 2 blocks)" "0,1"
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|
group.long 0x4F0++0x3
|
|
line.long 0x0 "AESDFAISON,This register disable_enable the AES dfa. Note: This is a special register. affected by internal logic. Test result of this register is NA."
|
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bitfld.long 0x0 0. "AESDFAISON,writing to this register turns the DFA counter-measures on. this register exists only if DFA countermeasures are supported" "0,1"
|
|
group.long 0x4F8++0x3
|
|
line.long 0x0 "AESDFAERRSTATUS,dfa error status register."
|
|
bitfld.long 0x0 0. "AESDFAERRSTATUS,after a DFA violation this register is set and the AES block is disabled) until the next reset. this register only exists if DFA countermeasures is are supported" "0,1"
|
|
group.long 0x524++0x3
|
|
line.long 0x0 "AESCMACSIZE0KICK,writing to this address triggers the AES engine to perform a CMAC operation with size 0. The CMAC result can be read from the AES_IV0 register."
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bitfld.long 0x0 0. "AESCMACSIZE0KICK,writing to this address triggers the AES engine to perform a CMAC operation with size 0. The CMAC result can be read from the AES_IV0 register." "0,1"
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|
group.long 0x640++0x23
|
|
line.long 0x0 "HASHH0,H0 data. can only be written in the following HASH_CONTROL modes: MD5 SHA1 SHA224 SHA256 SHA384 SHA512"
|
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hexmask.long 0x0 0.--31. 1. "HASHH0,1) Write initial Hash value."
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line.long 0x4 "HASHH1,H1 data. can only be written in the following HASH_CONTROL modes: MD5 SHA1 SHA224 SHA256 SHA384 SHA512"
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hexmask.long 0x4 0.--31. 1. "HASHH1,1) Write initial Hash value."
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line.long 0x8 "HASHH2,H2 data. can only be written in the following HASH_CONTROL modes: MD5 SHA1 SHA224 SHA256 SHA384 SHA512"
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hexmask.long 0x8 0.--31. 1. "HASHH2,1) Write initial Hash value."
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line.long 0xC "HASHH3,H3 data. can only be written in the following HASH_CONTROL modes: MD5 SHA1 SHA224 SHA256 SHA384 SHA512"
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hexmask.long 0xC 0.--31. 1. "HASHH3,1) Write initial Hash value."
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line.long 0x10 "HASHH4,H4 data. can only be written in the following HASH_CONTROL modes: SHA1 SHA224 SHA256 SHA384 SHA512"
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hexmask.long 0x10 0.--31. 1. "HASHH4,1) Write initial Hash value."
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|
line.long 0x14 "HASHH5,H5 data. can only be written in the following HASH_CONTROL modes: SHA224 SHA256 SHA384 SHA512"
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hexmask.long 0x14 0.--31. 1. "HASHH5,1) Write initial Hash value."
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|
line.long 0x18 "HASHH6,H6 data. can only be written in the following HASH_CONTROL modes: SHA224 SHA256 SHA384 SHA512"
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hexmask.long 0x18 0.--31. 1. "HASHH6,1) Write initial Hash value."
|
|
line.long 0x1C "HASHH7,H7 data. can only be written in the following HASH_CONTROL modes: SHA224 SHA256 SHA384 SHA512"
|
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hexmask.long 0x1C 0.--31. 1. "HASHH7,1) Write initial Hash value."
|
|
line.long 0x20 "HASHH8,H8 data. can only be written in the following HASH_CONTROL modes: SHA384 SHA512"
|
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hexmask.long 0x20 0.--31. 1. "HASHH8,1) Write initial Hash value."
|
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group.long 0x684++0x7
|
|
line.long 0x0 "AUTOHWPADDING,HW padding automatically activated by engine. For the special case of ZERO bytes data vector this register should not be used! instead use HASH_PAD_CFG"
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|
bitfld.long 0x0 0. "EN,0x1 - Enable Automatic HW padding (No need for SW intervention by writing PAD_CFG). Note: Not supported for 0 bytes ! Note: Disable this register when HASH op is done" "?,1: Enable Automatic HW padding"
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|
line.long 0x4 "HASHXORDIN,This register is always xored with the input to the hash engine.it should be 0 if xored is not reqiured ."
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hexmask.long 0x4 0.--31. 1. "HASHXORDATA,This register holds the value to be xor-ed with hash input data."
|
|
group.long 0x694++0x3
|
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line.long 0x0 "LOADINITSTATE,Indication to HASH that the following data is to be loaded into initial value registers in HASH(H0:H15) or IV to AES MAC"
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bitfld.long 0x0 0. "LOAD,Load data to initial state registers. digest_iv for hash_aes_mac. When done loading data this bit should be reset" "0,1"
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|
group.long 0x6A4++0x3
|
|
line.long 0x0 "HASHSELAESMAC,select the AES MAC module rather than the hash module"
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|
bitfld.long 0x0 1. "GHASHSEL,GHASH select." "0: select the hash module,1: select the ghash module"
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|
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bitfld.long 0x0 0. "HASHSELAESMAC,Hash or AES MAC module select." "0: select the hash module,1: select the AES mac module"
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|
group.long 0x7B0++0x3
|
|
line.long 0x0 "HASHVERSION,HASH VERSION Register"
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hexmask.long.byte 0x0 12.--15. 1. "MAJORVERSIONNUMBER,major version number"
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|
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hexmask.long.byte 0x0 8.--11. 1. "MINORVERSIONNUMBER,minor version number"
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|
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|
hexmask.long.byte 0x0 0.--7. 1. "FIXES,Fixes field."
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|
group.long 0x7C0++0x13
|
|
line.long 0x0 "HASHCONTROL,Selects which HASH mode to run"
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bitfld.long 0x0 3. "MODE3,bit 3 of the HASH mode field. The hash mode field possible values are:4b0000 - MD5 if present 0x0001 SHA 1 4b0010 - SHA-256 4b1010 - SHA-224" "0: MD5 if present 0x0001 SHA 1 4b0010,?"
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bitfld.long 0x0 0.--1. "MODE01,bits 1:0 of the HASH mode field. The hash mode field possible values are:" "0: MD5 if present,1: SHA-1,2: SHA-256,?"
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|
line.long 0x4 "HASHPADEN,Enables the hash hw padding."
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|
bitfld.long 0x4 0. "EN,0x1 : Enable generation of padding by HW Pad block. 0x0 : Disable generation of padding by HW Pad block." "0: Disable generation of padding by HW Pad block,1: Enable generation of padding by HW Pad block"
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line.long 0x8 "HASHPADCFG,This is a special register. affected by internal logic. Test result of this register is NA."
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bitfld.long 0x8 2. "DOPAD,Enable Padding generation. must be reset upon completion of padding." "0,1"
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line.long 0xC "HASHCURLEN0,This register holds the length of current hash operation bit 31:0."
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hexmask.long 0xC 0.--31. 1. "Length,Represent the current length of valid bits where digest need to be computed In Bytes."
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line.long 0x10 "HASHCURLEN1,This register holds the length of current hash operation bit 63:32."
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hexmask.long 0x10 0.--31. 1. "Length,Represent the current length of valid bits where digest need to be computed In Bytes."
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group.long 0x7DC++0x3
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|
line.long 0x0 "HASHPARAM,HASH_PARAM Register."
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bitfld.long 0x0 18. "DUMPHASHTODOUTEXISTS,Indicate if HASH to dout is present in the design" "0,1"
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bitfld.long 0x0 17. "HASHCOMPAREEXISTS,Indicate if COMPARE digest logic is present in the design" "0,1"
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|
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bitfld.long 0x0 16. "SHA256EXISTS,Indicate if SHA-256 is present in the design" "0,1"
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|
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bitfld.long 0x0 15. "HMACEXISTS,Indicate if HMAC logic is present in the design" "0,1"
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|
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bitfld.long 0x0 14. "MD5EXISTS,Indicate if MD5 is present in HW" "0,1"
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bitfld.long 0x0 13. "PADEXISTS,Indicate if pad block is present in the design. 0 - pad function is not supported by hardware. 1 - pad function is supported by hardware." "0: pad function is not supported by hardware,1: pad function is supported by hardware"
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bitfld.long 0x0 12. "SHA512EXISTS,Indicate if SHA-512 is present in the design. By default SHA-1 and SHA-256 are present. 0 - SHA-1 and SHA-256 are present only 1 - SHA-1 and all SHA-2 are present (SHA-256 SHA-512)." "0: SHA-1 and SHA-256 are present only 1,?"
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|
newline
|
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hexmask.long.byte 0x0 8.--11. 1. "DW,Determine the granularity of word size. 0 - 32 bit word data. 1 - 64 bit word data."
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|
newline
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hexmask.long.byte 0x0 4.--7. 1. "CH,Indicate if Hi adders are present for each Hi value or 1 adder is shared for all Hi. 0 - One Hi value is updated at a time 1 - All Hi values are updated at the same time."
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newline
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hexmask.long.byte 0x0 0.--3. 1. "CW,Indicates the number of concurrent words the hash is using to compute signature. 1 - One concurrent w(t). 2 - Two concurrent w(t)."
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group.long 0x7E4++0x7
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line.long 0x0 "HASHAESSWRESET,Software reset of the AES."
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bitfld.long 0x0 0. "HASHAESSWRESET,Hash receive reset internally." "0,1"
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line.long 0x4 "HASHENDIANESS,This register holds the HASH_ENDIANESS configuration."
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bitfld.long 0x4 0. "ENDIAN,The default value is little-endian. The data and generation of padding can be swapped to be big-endian." "0,1"
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group.long 0x810++0x3
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line.long 0x0 "AESCLKENABLE,This is a special register. affected by internal logic. Test result of this register is NA."
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bitfld.long 0x0 0. "EN,Enable the AES clock." "0: the AES clock is disabled.,1: the AES clock is enabled."
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group.long 0x818++0xF
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line.long 0x0 "HASHCLKENABLE,The HASH clock enable register. Note: This is a special register. affected by internal logic. Test result of this register is NA."
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bitfld.long 0x0 0. "EN,Enable the hash clock." "0: the HASH clock is disabled.,1: the HASH clock is enabled."
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line.long 0x4 "PKACLKENABLE,The PKA clock enable register. Note: This is a special register. affected by internal logic. Test result of this register is NA."
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bitfld.long 0x4 0. "EN,Enable the PKA clock." "0: the PKA clock is disabled.,1: the PKA clock is enabled."
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line.long 0x8 "DMACLKENABLE,DMA_CLK enable register. Note: This is a special register. affected by internal logic. Test result of this register is NA."
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bitfld.long 0x8 0. "EN,Enable the DMA clock." "0: the DMA clock is disabled.,1: the DMA clock is enabled."
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line.long 0xC "CLKSTATUS,The CryptoCell clocks status register. Note: This is a special register. affected by internal logic. Test result of this register is NA."
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bitfld.long 0xC 8. "DMACLKSTATUS,Status of DMA clock enable." "0: the DMA clock is disabled.,1: the DMA clock is enabled."
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newline
|
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bitfld.long 0xC 7. "CHACHACLKSTATUS,Status of CHACHA clock enable." "0: the CHACHA clock is disabled.,1: the CHACHA clock is enabled."
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newline
|
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bitfld.long 0xC 3. "PKACLKSTATUS,Status of PKA clock enable." "0: the PKA clock is disabled.,1: the PKA clock is enabled."
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newline
|
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bitfld.long 0xC 2. "HASHCLKSTATUS,Status of HASH clock clock enable." "0: the HASH clock is disabled.,1: the HASH clock is enabled."
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|
newline
|
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bitfld.long 0xC 0. "AESCLKSTATUS,Status of AES clock enable." "0: the AES clock is disabled.,1: the AES clock is enabled."
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group.long 0x858++0x3
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line.long 0x0 "CHACHACLKENABLE,CHACHA _SALSA clock enable register. Note: This is a special register. affected by internal logic. Test result of this register is NA."
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bitfld.long 0x0 0. "EN,Enable the CHACHA SALSA clock enable." "0: the CHACHA SALSA clock is disabled.,1: the CHACHA SALSA clock is enabled."
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group.long 0x900++0x3
|
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line.long 0x0 "CRYPTOCTL,Defines the cryptographic flow."
|
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hexmask.long.byte 0x0 0.--4. 1. "MODE,Determines the active cryptographic engine:"
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group.long 0x910++0x3
|
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line.long 0x0 "CRYPTOBUSY,This register is set when the cryptographic core is busy."
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bitfld.long 0x0 0. "CRYPTOBUSY,Crypto busy status." "0: Ready,1: Busy"
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group.long 0x91C++0x3
|
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line.long 0x0 "HASHBUSY,This register is set when the Hash engine is busy."
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bitfld.long 0x0 0. "HASHBUSY,Hash busy status." "0: Ready,1: Busy"
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group.long 0x930++0x3
|
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line.long 0x0 "CONTEXTID,A general RD_WR register. For Firmware use."
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hexmask.long.byte 0x0 0.--7. 1. "CONTEXTID,Context ID"
|
|
group.long 0x960++0x27
|
|
line.long 0x0 "GHASHSUBKEY00,Bits 31:0 of GHASH Key0 (used as the GHASH module key)."
|
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hexmask.long 0x0 0.--31. 1. "GHASHSUBKEY00,Bits 31:0 of GHASH Key0."
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line.long 0x4 "GHASHSUBKEY01,Bits 63:32 of GHASH Key0 (used as the GHASH module key)."
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hexmask.long 0x4 0.--31. 1. "GHASHSUBKEY01,Bits 63:32 of GHASH Key0."
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line.long 0x8 "GHASHSUBKEY02,Bits 95:64 of GHASH Key0 (used as the GHASH module key)."
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hexmask.long 0x8 0.--31. 1. "GHASHSUBKEY02,Bits 95:64 of GHASH Key0."
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line.long 0xC "GHASHSUBKEY03,Bits 127:96 of GHASH Key0 (used as the GHASH module key)."
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hexmask.long 0xC 0.--31. 1. "GHASHSUBKEY03,Bits 127:96 of GHASH Key0."
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line.long 0x10 "GHASHIV00,Bits 31:0 of GHASH_IV0 register. GHASH IV0 is used as the GHASH IV (Initialization Value) register."
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hexmask.long 0x10 0.--31. 1. "GHASHIV00,Bits 31:0 of GHASH_IV0 register of the GHASH module. For the description of GHASH_IV0 see the GHASH_0_0 register description"
|
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line.long 0x14 "GHASHIV01,Bits 63:32 of GHASH_IV0 register. GHASH IV0 is used as the GHASH IV (Initialization Value) register."
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hexmask.long 0x14 0.--31. 1. "GHASHIV01,Bits 63:32 of GHASH_IV0 register of the GHASH module."
|
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line.long 0x18 "GHASHIV02,Bits 95:64 of GHASH_IV0 register. GHASH IV0 is used as the GHASH IV (Initialization Value) register."
|
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hexmask.long 0x18 0.--31. 1. "GHASHIV02,Bits 95:64 of GHASH_IV0 register of the GHASH module."
|
|
line.long 0x1C "GHASHIV03,Bits 127:96 of GHASH_IV0 register.GHASH IV0 is used as the GHASH IV (Initialization Value) register."
|
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hexmask.long 0x1C 0.--31. 1. "GHASHIV03,Bits 127:96 of GHASH_IV0 register of the GHASH module."
|
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line.long 0x20 "GHASHBUSY,The GHASH module GHASH_BUSY Register. This register is set when the GHASH core is active."
|
|
bitfld.long 0x20 0. "GHASHBUSY,GHASH_BUSY Register. This register is set when the GHASH core is active" "0,1"
|
|
line.long 0x24 "GHASHINIT,Writing to this address sets the GHASH engine to be ready to a new GHASH operation."
|
|
bitfld.long 0x24 0. "GHASHINIT,Writing to this address sets the GHASH engine to be ready to a new GHASH operation." "0,1"
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|
group.long 0xA00++0xF
|
|
line.long 0x0 "HOSTRGFIRR,The Interrupt Request register. Each bit of this register holds the interrupt status of a single interrupt source."
|
|
bitfld.long 0x0 11. "SYMDMACOMPLETED,The GPR interrupt status." "0,1"
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|
newline
|
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bitfld.long 0x0 10. "RNGINT,The RNG interrupt status." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PKAEXPINT,The PKA end of operation interrupt status." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "AHBERRINT,The AXI error interrupt status." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "DOUTTOMEMINT,The DOUT to memory DMA done interrupt status. This interrupt is asserted when all data was delivered to memory buffer from DOUT." "0,1"
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|
newline
|
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bitfld.long 0x0 6. "MEMTODININT,The memory to DIN DMA done interrupt status. This interrupt is asserted when all data was delivered to DIN buffer from memory." "0,1"
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|
newline
|
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bitfld.long 0x0 5. "DOUTTOSRAMINT,The DOUT to SRAM DMA done interrupt status. This interrupt is asserted when all data was delivered to SRAM buffer from DOUT." "0,1"
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|
newline
|
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bitfld.long 0x0 4. "SRAMTODININT,The SRAM to DIN DMA done interrupt status. This interrupt is asserted when all data was delivered to DIN buffer from SRAM." "0,1"
|
|
line.long 0x4 "HOSTRGFIMR,The Interrupt Mask register. Each bit of this register holds the mask of a single interrupt source."
|
|
bitfld.long 0x4 11. "SYMDMACOMPLETEDMASK,The GPR interrupt mask." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "RNGINTMASK,The RNG interrupt mask." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PKAEXPMASK,The PKA end of operation interrupt mask." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "AXIERRMASK,The AXI error interrupt mask." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "DOUTTOMEMMASK,The DOUT to memory DMA done interrupt mask." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "MEMTODINMASK,The memory to DIN DMA done interrupt mask." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DOUTTOSRAMMASK,The DOUT to SRAM DMA done interrupt mask." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SRAMTODINMASK,The SRAM to DIN DMA done interrupt mask." "0,1"
|
|
line.long 0x8 "HOSTRGFICR,Interrupt Clear Register."
|
|
bitfld.long 0x8 11. "SYMDMACOMPLETEDCLEAR,The GPR interrupt clear." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "RNGINTCLEAR,The RNG interrupt clear." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PKAEXPCLEAR,The PKA end of operation interrupt clear." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "AXIERRCLEAR,The AXI error interrupt clear." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "DOUTTOMEMCLEAR,The DOUT to memory DMA done interrupt clear." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "MEMTODINCLEAR,The memory to DIN DMA done interrupt clear." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "DOUTTOSRAMCLEAR,The DOUT to SRAM DMA done interrupt clear." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "SRAMTODINCLEAR,The SRAM to DIN DMA done interrupt clear." "0,1"
|
|
line.long 0xC "HOSTRGFENDIAN,This register defines the endianness of the Host-accessible registers. Note: This is a special register. affected by internal logic. Test result of this register is NA."
|
|
bitfld.long 0xC 15. "DINRDWBG,DIN write word endianness:" "0: little endian,1: big endian"
|
|
newline
|
|
bitfld.long 0xC 11. "DOUTWRWBG,DOUT write word endianness:" "0: little endian,1: big endian"
|
|
newline
|
|
bitfld.long 0xC 7. "DINRDBG,DIN write endianness:" "0: little endian,1: big endian"
|
|
newline
|
|
bitfld.long 0xC 3. "DOUTWRBG,DOUT write endianness:" "0: little endian,1: big endian"
|
|
group.long 0xA24++0x7
|
|
line.long 0x0 "HOSTRGFSIGNATURE,This register holds the CryptoCell product signature."
|
|
hexmask.long 0x0 0.--31. 1. "HOSTSIGNATURE,Identification 'signature': always returns a fixed value used by Host driver to verify CryptoCell presence at this address."
|
|
line.long 0x4 "HOSTBOOT,This register holds the values of CryptoCells pre-synthesis flags"
|
|
bitfld.long 0x4 30. "AESEXISTSLOCAL,AES_EXISTS_LOCAL" "0,1"
|
|
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|
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bitfld.long 0x4 29. "ONLYENCRYPTLOCAL,ONLY_ENCRYPT_LOCAL" "0,1"
|
|
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|
|
bitfld.long 0x4 28. "SUPPORT256192KEYLOCAL,SUPPORT_256_192_KEY_LOCAL" "0,1"
|
|
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|
|
bitfld.long 0x4 27. "TUNNELINGENBLOCAL,TUNNELING_ENB_LOCAL" "0,1"
|
|
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|
|
bitfld.long 0x4 26. "AESDINBYTERESOLUTIONLOCAL,AES_DIN_BYTE_RESOLUTION_LOCAL" "0,1"
|
|
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|
|
bitfld.long 0x4 25. "CTREXISTSLOCAL,CTR_EXISTS_LOCAL" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "AESXEXEXISTSLOCAL,AES_XEX_EXISTS_LOCAL" "0,1"
|
|
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|
|
bitfld.long 0x4 23. "AESXEXHWTCALCLOCAL,AES_XEX_HW_T_CALC_LOCAL" "0,1"
|
|
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|
|
bitfld.long 0x4 22. "AESCCMEXISTSLOCAL,AES_CCM_EXISTS_LOCAL" "0,1"
|
|
newline
|
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bitfld.long 0x4 21. "AESCMACEXISTSLOCAL,AES_CMAC_EXISTS_LOCAL" "0,1"
|
|
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|
|
bitfld.long 0x4 20. "AESXCBCMACEXISTSLOCAL,AES_XCBC_MAC_EXISTS_LOCAL" "0,1"
|
|
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|
|
bitfld.long 0x4 19. "DESEXISTSLOCAL,DES_EXISTS_LOCAL" "0,1"
|
|
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|
|
bitfld.long 0x4 18. "C2EXISTSLOCAL,C2_EXISTS_LOCAL" "0,1"
|
|
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|
|
bitfld.long 0x4 17. "HASHEXISTSLOCAL,HASH_EXISTS_LOCAL" "0,1"
|
|
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|
|
bitfld.long 0x4 16. "MD5PRSNTLOCAL,MD5_PRSNT_LOCAL" "0,1"
|
|
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|
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bitfld.long 0x4 15. "SHA256PRSNTLOCAL,SHA_256_PRSNT_LOCAL" "0,1"
|
|
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|
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bitfld.long 0x4 14. "SHA512PRSNTLOCAL,SHA_512_PRSNT_LOCAL" "0,1"
|
|
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|
|
bitfld.long 0x4 13. "RC4EXISTSLOCAL,RC4_EXISTS_LOCAL" "0,1"
|
|
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|
|
bitfld.long 0x4 12. "PKAEXISTSLOCAL,PKA_EXISTS_LOCAL" "0,1"
|
|
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|
|
bitfld.long 0x4 11. "RNGEXISTSLOCAL,RNG_EXISTS_LOCAL" "0,1"
|
|
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|
|
bitfld.long 0x4 10. "PAUEXISTSLOCAL,PAU_EXISTS_LOCAL" "0,1"
|
|
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|
|
bitfld.long 0x4 9. "DSCRPTREXISTSLOCAL,DSCRPTR_EXISTS_LOCAL" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6.--8. "SRAMSIZELOCAL,SRAM_SIZE_LOCAL" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 5. "RKEKECCEXISTSLOCALN,RKEK_ECC_EXISTS_LOCAL_N" "0,1"
|
|
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|
|
bitfld.long 0x4 3. "EXTMEMSECUREDLOCAL,EXT_MEM_SECURED_LOCAL" "0,1"
|
|
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|
|
bitfld.long 0x4 2. "HASHINFUSESLOCAL,HASH_IN_FUSES_LOCAL" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "LARGERKEKLOCAL,LARGE_RKEK_LOCAL" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "SYNTHESISCONFIG,POWER_GATING_EXISTS_LOCAL" "0,1"
|
|
group.long 0xA38++0x3
|
|
line.long 0x0 "HOSTCRYPTOKEYSEL,AES hardware key select. Note: This is a special register. affected by internal logic. Test result of this register is NA."
|
|
bitfld.long 0x0 0.--2. "SELCRYPTOKEY,Select the source of the HW key that is used by the AES engine:" "0: rkek,1: the Krtl.,2: the provision key KCP.,3: the code encryption key KCE.,4: the KPICV The ICV provisioning key .,5: the code encryption key KCEICV Note: When..,?,?"
|
|
group.long 0xA78++0x13
|
|
line.long 0x0 "HOSTCORECLKGATINGENABLE,This register enables the core clk gating by masking_enabling the cc_idle_state output signal."
|
|
bitfld.long 0x0 0. "HOSTCORECLKGATINGENABLE,Enable the core clk gating " "0,1"
|
|
line.long 0x4 "HOSTCCISIDLE,This register holds the idle indication of CC . Note: This is a special register. affected by internal logic. Test result of this register is NA."
|
|
bitfld.long 0x4 9. "CRYPTOISIDLE,crypto flow is done" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "PKAISIDLE,pka is idle" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RNGISIDLE,rng is idle" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FATALWR,fatal write" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "NVMISIDLE,nvm is idle" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "NVMARBISIDLE,nvm arbiter is idle" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "AHBISIDLE,ahb stste machine is idle" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SYMISBUSY,symetric flow is busy" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "HOSTCCISIDLEEVENT,The event that indicates that CC is idle." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "HOSTCCISIDLE,Read if CC is idle." "0,1"
|
|
line.long 0x8 "HOSTPOWERDOWN,This register start the power-down sequence. Note: This is a special register. affected by internal logic. Test result of this register is NA."
|
|
bitfld.long 0x8 0. "HOSTPOWERDOWN,Power down enable register." "0,1"
|
|
line.long 0xC "HOSTREMOVEGHASHENGINE,These inputs are to be statically tied to 0 or 1 by the customers. When such an input is set. the matching engines inputs are tied to zero and its outputs are disconnected. so that the engine will be entirely removed by Synthesis"
|
|
bitfld.long 0xC 0. "HOSTREMOVEGHASHENGINE,Read the Remove_chacha_engine input" "0,1"
|
|
line.long 0x10 "HOSTREMOVECHACHAENGINE,These inputs are to be statically tied to 0 or 1 by the customers. When such an input is set. the matching engines inputs are tied to zero and its outputs are disconnected. so that the engine will be entirely removed by Synthesis"
|
|
bitfld.long 0x10 0. "HOSTREMOVECHACHAENGINE,Read the Remove_ghash_engine input" "0,1"
|
|
group.long 0xB00++0xF
|
|
line.long 0x0 "AHBMSINGLES,This register forces the ahb transactions to be always singles."
|
|
bitfld.long 0x0 0. "AHBSINGLES,Force ahb singles" "0,1"
|
|
line.long 0x4 "AHBMHPROT,This register holds the ahb prot value"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AHBPROT,The ahb prot value"
|
|
line.long 0x8 "AHBMHMASTLOCK,This register holds ahb hmastlock value"
|
|
bitfld.long 0x8 0. "AHBHMASTLOCK,The hmastlock value." "0,1"
|
|
line.long 0xC "AHBMHNONSEC,This register holds ahb hnonsec value"
|
|
bitfld.long 0xC 1. "AHBREADHNONSEC,The hnonsec value for read transaction." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "AHBWRITEHNONSEC,The hnonsec value for write transaction." "0,1"
|
|
group.long 0xC00++0x3
|
|
line.long 0x0 "DINBUFFER,This address can be used by the CPU to write data directly to the DIN buffer to be sent to engines."
|
|
hexmask.long 0x0 0.--31. 1. "DINBUFFERDATA,This register is mapped into 8 addresses in order to enable a CPU burst."
|
|
group.long 0xC20++0x3
|
|
line.long 0x0 "DINMEMDMABUSY,Indicates whether memory (AXI) source DMA (DIN) is busy."
|
|
bitfld.long 0x0 0. "DINMEMDMABUSY,DIN memory DMA busy" "0: DMA not busy,1: DMA busy"
|
|
group.long 0xC28++0x17
|
|
line.long 0x0 "SRCLLIWORD0,This register is used in direct LLI mode - holds the location of the data source in the memory (AXI)."
|
|
hexmask.long 0x0 0.--31. 1. "SRCLLIWORD0,Source address within memory."
|
|
line.long 0x4 "SRCLLIWORD1,This register is used in direct LLI mode - holds the number of bytes to be read from the memory (AXI). Writing to this register triggers the DMA. Note: This is a special register. affected by internal logic. Test result of this register is NA."
|
|
bitfld.long 0x4 31. "LAST,0x1 - Indicates the last LLI entry" "?,1: Indicates the last LLI entry"
|
|
newline
|
|
bitfld.long 0x4 30. "FIRST,0x1 - Indicates the first LLI entry" "?,1: Indicates the first LLI entry"
|
|
newline
|
|
hexmask.long 0x4 0.--29. 1. "BYTESNUM,Total number of bytes to read using DMA in this entry"
|
|
line.long 0x8 "SRAMSRCADDR,Location of data (start address) to be read from SRAM. Note: This is a special register. affected by internal logic. Test result of this register is NA."
|
|
hexmask.long 0x8 0.--31. 1. "SRAMSOURCE,SRAM source base address of data"
|
|
line.long 0xC "DINSRAMBYTESLEN,This register holds the size of the data (in bytes) to be read from the SRAM. Note: This is a special register. affected by internal logic. Test result of this register is NA."
|
|
hexmask.long 0xC 0.--31. 1. "BYTESLEN,Size of data to read from SRAM (bytes). This is the trigger to the SRAM SRC DMA."
|
|
line.long 0x10 "DINSRAMDMABUSY,This register holds the status of the SRAM DMA DIN."
|
|
bitfld.long 0x10 0. "BUSY,DIN SRAM DMA busy:" "0: not busy,1: busy"
|
|
line.long 0x14 "DINSRAMENDIANNESS,This register defines the endianness of the DIN interface to SRAM."
|
|
bitfld.long 0x14 0. "SRAMDINENDIANNESS,Defines the endianness of DIN interface to SRAM:" "0: little endianness,1: big-endianness"
|
|
group.long 0xC48++0x3
|
|
line.long 0x0 "DINCPUDATASIZE,This register hold the number of bytes to be transmited using external DMA. Note: This is a special register. affected by internal logic. Test result of this register is NA."
|
|
hexmask.long.word 0x0 0.--15. 1. "CPUDINSIZE,When using external DMA the size of transmited data in bytes should be written to this register."
|
|
group.long 0xC50++0x3
|
|
line.long 0x0 "FIFOINEMPTY,DIN FIFO empty indication"
|
|
bitfld.long 0x0 0. "EMPTY,0x1 - FIFO empty" "?,1: FIFO empty"
|
|
group.long 0xC58++0x3
|
|
line.long 0x0 "DINFIFORSTPNTR,Writing to this register resets the DIN_FIFO pointers."
|
|
bitfld.long 0x0 0. "RST,Writing any value to this address resets the DIN_FIFO pointers." "0,1"
|
|
group.long 0xD00++0x3
|
|
line.long 0x0 "DOUTBUFFER,Cryptographic result - CPU can directly access it. Note: This is a special register. affected by internal logic. Test result of this register is NA."
|
|
hexmask.long 0x0 0.--31. 1. "DATA,DOUT This address can be used by the CPU to read data directly from the DOUT buffer."
|
|
group.long 0xD20++0x3
|
|
line.long 0x0 "DOUTMEMDMABUSY,DOUT memory DMA busy - Indicates that memory (AXI) destination DMA (DOUT) is busy."
|
|
bitfld.long 0x0 0. "DOUTMEMDMABUSY,DOUT memory DMA busy:" "0: not busy,1: busy"
|
|
group.long 0xD28++0x17
|
|
line.long 0x0 "DSTLLIWORD0,This register is used in direct LLI mode - holds the location of the data destination in the memory (AXI)"
|
|
hexmask.long 0x0 0.--31. 1. "DSTLLIWORD0,Destination address within memory"
|
|
line.long 0x4 "DSTLLIWORD1,This register is used in direct LLI mode - holds the number of bytes to be written to the memory (AXI). Note: This is a special register. affected by internal logic. Test result of this register is NA."
|
|
bitfld.long 0x4 31. "LAST,0x1 - Indicates the last LLI entry" "?,1: Indicates the last LLI entry"
|
|
newline
|
|
bitfld.long 0x4 30. "FIRST,0x1 - Indicates the first LLI entry" "?,1: Indicates the first LLI entry"
|
|
newline
|
|
hexmask.long 0x4 0.--29. 1. "BYTESNUM,Total byte number to be written by DMA in this entry"
|
|
line.long 0x8 "SRAMDESTADDR,Location of result to be sent to in SRAM. Note: This is a special register. affected by internal logic. Test result of this register is NA."
|
|
hexmask.long 0x8 0.--31. 1. "SRAMDEST,SRAM destination base address for data."
|
|
line.long 0xC "DOUTSRAMBYTESLEN,This register holds the size of the data (in bytes) to be written to the SRAM. Note: This is a special register. affected by internal logic. Test result of this register is NA."
|
|
hexmask.long 0xC 0.--31. 1. "BYTESLEN,Size of data to write to SRAM (bytes). This is the trigger to the SRAM DST DMA."
|
|
line.long 0x10 "DOUTSRAMDMABUSY,This register holds the status of the SRAM DMA DOUT."
|
|
bitfld.long 0x10 0. "BUSY,DOUT SRAM DMA busy status." "0: all data was written to SRAM.,1: DOUT SRAM DMA busy."
|
|
line.long 0x14 "DOUTSRAMENDIANNESS,This register defines the endianness of the DOUT interface from SRAM."
|
|
bitfld.long 0x14 0. "DOUTSRAMENDIANNESS,Defines the endianness of DOUT interface from SRAM:" "0: little endianness,1: big-endianness"
|
|
group.long 0xD44++0x3
|
|
line.long 0x0 "READALIGNLAST,Indication that the next read from the CPU is the last one. This is needed only when the data size is NOT modulo 4 (e.g. HASH padding)."
|
|
bitfld.long 0x0 0. "LAST,0x1 - Flush the read aligner content (used for reading the last data)." "?,1: Flush the read aligner content"
|
|
group.long 0xD50++0x3
|
|
line.long 0x0 "DOUTFIFOEMPTY,DOUT_FIFO_EMPTY Register."
|
|
bitfld.long 0x0 0. "DOUTFIFOEMPTY,DOUT FIFO empty status." "0: DOUT FIFO is not empty,1: FIFO is empty"
|
|
group.long 0xF00++0xB
|
|
line.long 0x0 "SRAMDATA,READ WRITE DATA FROM SRAM. Note: This is a special register. affected by internal logic. Test result of this register is NA."
|
|
hexmask.long 0x0 0.--31. 1. "SRAMDATA,32 bit write or read from SRAM: read - triggers the SRAM read DMA address automatically incremented write - triggers the SRAM write DMA address automatically incremented"
|
|
line.long 0x4 "SRAMADDR,first address given to SRAM DMA for read_write transactions from SRAM"
|
|
hexmask.long.word 0x4 0.--14. 1. "SRAMADDR,SRAM starting address"
|
|
line.long 0x8 "SRAMDATAREADY,The SRAM content is ready for read in SRAM_DATA."
|
|
bitfld.long 0x8 0. "SRAMREADY,SRAM content is ready for read in SRAM_DATA." "0,1"
|
|
group.long 0xFD0++0x3
|
|
line.long 0x0 "PERIPHERALID4,Peripheral ID 4 (PID4)."
|
|
hexmask.long.byte 0x0 0.--3. 1. "DES2JEP106,for ARM products."
|
|
group.long 0xFE0++0x1F
|
|
line.long 0x0 "PERIPHERALID0,Peripheral ID 0 (PID0)."
|
|
hexmask.long.byte 0x0 0.--7. 1. "PART0,Identification register part number bits[7:0]"
|
|
line.long 0x4 "PERIPHERALID1,Peripheral ID 1 (PID1)."
|
|
hexmask.long.byte 0x4 4.--7. 1. "DES0JEP106,for ARM products."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "PART1,Identification register part number bits[11:8]"
|
|
line.long 0x8 "PERIPHERALID2,Peripheral ID 2 (PID2)."
|
|
hexmask.long.byte 0x8 4.--7. 1. "REVISION,starts at zero and increments for every new IP release."
|
|
newline
|
|
bitfld.long 0x8 3. "JEDEC,constant 0x1. Indicates that a JEDEC assigned value is used." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "DES1JEP106,for ARM products." "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "PERIPHERALID3,Peripheral ID 3 (PID3)."
|
|
hexmask.long.byte 0xC 4.--7. 1. "REVAND,starts at zero for every Revision and increments if metal fixes are applied between 2 IP releases."
|
|
newline
|
|
hexmask.long.byte 0xC 0.--3. 1. "CMOD,Customer Modified normally zero but if a partner applies any changes themselves they must change this value."
|
|
line.long 0x10 "COMPONENTID0,Component ID0."
|
|
hexmask.long.byte 0x10 0.--7. 1. "PRMBL0,constant 0xD"
|
|
line.long 0x14 "COMPONENTID1,Component ID1."
|
|
hexmask.long.byte 0x14 4.--7. 1. "CLASS,component type 0 0xF for Cryptocell"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--3. 1. "PRMBL1,constant 0x0"
|
|
line.long 0x18 "COMPONENTID2,Component ID2."
|
|
hexmask.long.byte 0x18 0.--7. 1. "PRMBL2,constant 0x5"
|
|
line.long 0x1C "COMPONENTID3,Component ID3."
|
|
hexmask.long.byte 0x1C 0.--7. 1. "PRMBL3,constant 0xB1"
|
|
group.long 0x1E00++0x43
|
|
line.long 0x0 "HOSTDCUEN0,The DCU [31:0] enable register. Note: This is a special register. affected by internal logic. Test result of this register is NA."
|
|
hexmask.long 0x0 0.--31. 1. "HOSTDCUEN0,Debug Control Unit (DCU) Enable bits."
|
|
line.long 0x4 "HOSTDCUEN1,The DCU [63:32] enable register. Note: This is a special register. affected by internal logic. Test result of this register is NA."
|
|
hexmask.long 0x4 0.--31. 1. "HOSTDCUEN1,Debug Control Unit (DCU) Enable bits."
|
|
line.long 0x8 "HOSTDCUEN2,The DCU [95:64] enable register. Note: This is a special register. affected by internal logic. Test result of this register is NA."
|
|
hexmask.long 0x8 0.--31. 1. "HOSTDCUEN2,Debug Control Unit (DCU) Enable bits."
|
|
line.long 0xC "HOSTDCUEN3,The DCU [1271:96] enable register. Note: This is a special register. affected by internal logic. Test result of this register is NA."
|
|
hexmask.long 0xC 0.--31. 1. "HOSTDCUEN3,Debug Control Unit (DCU) Enable bits."
|
|
line.long 0x10 "HOSTDCULOCK0,The DCU lock register. Note: This is a special register. affected by internal logic. Test result of this register is NA."
|
|
hexmask.long 0x10 0.--31. 1. "HOSTDCULOCK0,DCU_lock [31:0] register (a dedicated lock register per DCU bit)."
|
|
line.long 0x14 "HOSTDCULOCK1,The DCU lock register. Note: This is a special register. affected by internal logic. Test result of this register is NA."
|
|
hexmask.long 0x14 0.--31. 1. "HOSTDCULOCK1,DCU_lock [63:32] register (a dedicated lock register per DCU bit)."
|
|
line.long 0x18 "HOSTDCULOCK2,The DCU lock register. Note: This is a special register. affected by internal logic. Test result of this register is NA."
|
|
hexmask.long 0x18 0.--31. 1. "HOSTDCULOCK2,DCU_lock [95:64] register (a dedicated lock register per DCU bit)."
|
|
line.long 0x1C "HOSTDCULOCK3,The DCU lock register. Note: This is a special register. affected by internal logic. Test result of this register is NA."
|
|
hexmask.long 0x1C 0.--31. 1. "HOSTDCULOCK3,DCU_lock [127:96] register (a dedicated lock register per DCU bit)."
|
|
line.long 0x20 "AOICVDCURESTRICTIONMASK0,The DCU lock register."
|
|
hexmask.long 0x20 0.--31. 1. "AOICVDCURESTRICTIONMASK0,AO_ICV_DCU_RESTRICTION_MASK [31:0] parameter that will be a customer modifiable."
|
|
line.long 0x24 "AOICVDCURESTRICTIONMASK1,The 'ICV_DCU_restriction_mask' parameter is read by FW during the secure debug verification to prevent OEM from setting specific DCUs that protect ICV secrets"
|
|
hexmask.long 0x24 0.--31. 1. "AOICVDCURESTRICTIONMASK1,AO_ICV_DCU_RESTRICTION_MASK [63:32] parameter that will be a customer modifiable."
|
|
line.long 0x28 "AOICVDCURESTRICTIONMASK2,The 'ICV_DCU_restriction_mask' parameter is read by FW during the secure debug verification to prevent OEM from setting specific DCUs that protect ICV secrets"
|
|
hexmask.long 0x28 0.--31. 1. "AOICVDCURESTRICTIONMASK2,AO_ICV_DCU_RESTRICTION_MASK [95:64] parameter that will be a customer modifiable."
|
|
line.long 0x2C "AOICVDCURESTRICTIONMASK3,The 'ICV_DCU_restriction_mask' parameter is read by FW during the secure debug verification to prevent OEM from setting specific DCUs that protect ICV secrets"
|
|
hexmask.long 0x2C 0.--31. 1. "AOICVDCURESTRICTIONMASK3,AO_ICV_DCU_RESTRICTION_MASK [127:96] parameter that will be a customer modifiable."
|
|
line.long 0x30 "AOCCSECDEBUGRESET,The reset-upon-debug indication"
|
|
bitfld.long 0x30 0. "AOCCSECDEBUGRESET,For resets Cerberus and prevents loading the HW keys after that reset" "0,1"
|
|
line.long 0x34 "HOSTAOLOCKBITS,These masks will define. per LCS. which DCU bits will be tied to zero. even if the Host tries to set them. Note: This is a special register. affected by internal logic. Test result of this register is NA."
|
|
bitfld.long 0x34 8. "HOSTDFAENABLELOCK,When this FW control is set the DFA_ENABLE register cant be written until the next POR. The DFA_ENABLE_LOCK register is set-once (per POR)." "0,1"
|
|
newline
|
|
bitfld.long 0x34 7. "HOSTFORCEDFAENABLE,When this FW controlled register is set the AES DFA countermeasures are enabled_disabled (regardless of the AES_DFA_IS_ON register value)." "0,1"
|
|
newline
|
|
bitfld.long 0x34 6. "RESETUPONDEBUGDISABLE,The RESET_UPON_DEBUG_DISABLE register is set-once (per POR)." "0,1"
|
|
newline
|
|
bitfld.long 0x34 5. "HOSTICVRMALOCK,The ICV_RMA_LOCK register is set-once (per POR)." "0,1"
|
|
newline
|
|
bitfld.long 0x34 4. "HOSTKCELOCK,When this FW controlled register is set the Kce HW key is masked (to zero)." "0,1"
|
|
newline
|
|
bitfld.long 0x34 3. "HOSTKCPLOCK,When this FW controlled register is set the Kcp HW key is masked (to zero)." "0,1"
|
|
newline
|
|
bitfld.long 0x34 2. "HOSTKCEICVLOCK,When this FW controlled register is set the Kceicv HW key is masked (to zero)." "0,1"
|
|
newline
|
|
bitfld.long 0x34 1. "HOSTKPICVLOCK,When this FW controlled register is set the Kpicv HW key is masked (to zero)." "0,1"
|
|
newline
|
|
bitfld.long 0x34 0. "HOSTFATALERR,When the 'FATAL_ERROR' register is asserted - HW keys will not be copied from OTP" "0,1"
|
|
line.long 0x38 "AOAPBFILTERING,This register holds the AO_APB_FILTERING data. Note: This is a special register. affected by internal logic. Test result of this register is NA."
|
|
bitfld.long 0x38 9. "APBCONLYINSTACCESSALLOWLOCK,when this FW controlled register is set the APBC_ONLY_INST_ACCESS_ALLOWED register cant be modified (until the next POR)" "0,1"
|
|
newline
|
|
bitfld.long 0x38 8. "APBCONLYINSTACCESSALLOW,when this FW controlled register is set the APB-C slave accepts only instruction accesses" "0,1"
|
|
newline
|
|
bitfld.long 0x38 7. "APBCONLYPRIVACCESSALLOWLOCK,when this FW controlled register is set the APBC_ONLY_PRIV_ACCESS_ALLOWED register cant be modified (until the next POR)" "0,1"
|
|
newline
|
|
bitfld.long 0x38 6. "APBCONLYPRIVACCESSALLOW,when this FW controlled register is set the APB-C slave accepts only privileged accesses" "0,1"
|
|
newline
|
|
bitfld.long 0x38 5. "APBCONLYSECACCESSALLOWLOCK,when this FW controlled register is set the APBC_ONLY_SEC_ACCESS_ALLOWED register cant be modified (until the next POR)." "0,1"
|
|
newline
|
|
bitfld.long 0x38 4. "APBCONLYSECACCESSALLOW,when this FW controlled register is set the APB-C slave accepts only secure accesses" "0,1"
|
|
newline
|
|
bitfld.long 0x38 3. "ONLYPRIVACCESSALLOWLOCK,when this FW controlled register is set the APBC_ONLY_PRIV_ACCESS_ALLOWED register cant be modified (until the next POR)" "0,1"
|
|
newline
|
|
bitfld.long 0x38 2. "ONLYPRIVACCESSALLOW,when this FW controlled register is set the APB slave accepts only privileged accesses" "0,1"
|
|
newline
|
|
bitfld.long 0x38 1. "ONLYSECACCESSALLOWLOCK,when this FW controlled register is set the ONLY_SEC_ACCESS_ALLOWED register cant be modified (until the next POR)." "0,1"
|
|
newline
|
|
bitfld.long 0x38 0. "ONLYSECACCESSALLOW,when this FW controlled register is set the APB slave accepts only secure accesses" "0,1"
|
|
line.long 0x3C "AOCCGPPC,holds the AO_CC_GPPC value from AONote: This is a special register. affected by internal logic. Test result of this register is NA."
|
|
hexmask.long.byte 0x3C 0.--7. 1. "AOCCGPPC,The AO_CC_GPPC value"
|
|
line.long 0x40 "HOSTRGFCCSWRST,Writing to this register generates a general reset to CryptoCell. This reset takes about 4 core clock cycles.Note: This is a special register. affected by internal logic. Test result of this register is NA."
|
|
bitfld.long 0x40 0. "HOSTRGFCCSWRST,Writing 1 to this field generates a general reset to CryptoCell." "0,1"
|
|
group.long 0x1F04++0x2B
|
|
line.long 0x0 "AIBFUSEPROGCOMPLETED,This register reflects the fuse_aib_prog_completed input. which indicates that the fuse programming was completed.Note: This is a special register. affected by internal logic. Test result of this register is NA."
|
|
bitfld.long 0x0 0. "AIBFUSEPROGCOMPLETED,Indicates if the fuse programming operation has been completed." "0,1"
|
|
line.long 0x4 "NVMDEBUGSTATUS,AIB debug status register. Note: This is a special register. affected by internal logic. Test result of this register is NA."
|
|
bitfld.long 0x4 1.--3. "NVMSM,Main nvm fsm" "0: IDLE NVMSM,1: READ_DUMMY NVMSM,2: READ_MAN_FLAG NVMSM,3: READ_OEM_FLAG NVMSM,4: READ_GPPC NVMSM,5: DECODE NVMSM,6: OTP_LCS_VALID NVMSM,7: LCS_IS_VALID NVMSM"
|
|
line.long 0x8 "LCSISVALID,Indicates that the LCS register holds a valid value.Note: This is a special register. affected by internal logic. Test result of this register is NA."
|
|
bitfld.long 0x8 0. "LCSISVALIDREG,Indicates whether LCS is valid." "0,1"
|
|
line.long 0xC "NVMISIDLE,Indicates that the LCS register holds a valid value.Note: This is a special register. affected by internal logic. Test result of this register is NA."
|
|
bitfld.long 0xC 0. "NVMISIDLEREG,Indicates whether the NVM manager finishes its operation calculates the LCS reads the HW keys compares the number of zeros and clears the keys" "0,1"
|
|
line.long 0x10 "LCSREG,The lifecycle state register. Note: This is a special register. affected by internal logic. Test result of this register is NA."
|
|
bitfld.long 0x10 12. "ERRORKCEICVZEROCNT,Indication that the number of zeroes in the loaded KCEICV is not equal to the value set in the manufacture flag." "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "ERRORKPICVZEROCNT,Indication that the number of zeroes in the loaded KPICV is not equal to the value set in the manufacture flag." "0,1"
|
|
newline
|
|
bitfld.long 0x10 10. "ERRORKCEZEROCNT,Indication that the number of zeroes in the loaded KCE is not equal to the value set in the OEM flag." "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "ERRORPROVZEROCNT,Indication that the number of zeroes in the loaded KCP is not equal to the value set in the OEM flag." "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "ERRORKDRZEROCNT,Indication that the number of zeroes in the loaded KDR is not equal to the value set in the manufacture flag." "0,1"
|
|
newline
|
|
bitfld.long 0x10 0.--2. "LCSREG,Indicates the LCS (Lifecycle State) value." "0: CM lifecycle state,1: DM lifecycle state,?,?,?,5: SE lifecycle state,?,7: RMA lifecycle state"
|
|
line.long 0x14 "HOSTSHADOWKDRREG,This register interface is used to update the RKEK(KDR) registers when the device is in CM or DM mode . it is Write-once (per warm boot) in RMA LCS. The RKEK is updated by shifting ."
|
|
bitfld.long 0x14 0. "HOSTSHADOWKDRREG,This field is used to update the KDR registers when the device is in CM DM or RMA mode The KDR is updated by shifting ." "0,1"
|
|
line.long 0x18 "HOSTSHADOWKCPREG,This register interface is used to update the KCP registers when the device is in CM or DM mode. The KCP is updated by shifting"
|
|
bitfld.long 0x18 0. "HOSTSHADOWKCPREG,This field is used to update the KCP registers when the device is in CM or DM mode The KCP is updated by shifting" "0,1"
|
|
line.long 0x1C "HOSTSHADOWKCEREG,This register interface is used to update the KCE registers when the device is in CM or DM mode. The KCE is updated by shifting"
|
|
bitfld.long 0x1C 0. "HOSTSHADOWKCEREG,This field is used to update the KCE registers when the device is in CM or DM mode The KCE is updated by shifting" "0,1"
|
|
line.long 0x20 "HOSTSHADOWKPICVREG,This register interface is used to update the KPICV registers when the device is in CM or DM mode. The KPICV is updated by shifting"
|
|
bitfld.long 0x20 0. "HOSTSHADOWKPICVREG,This field is used to update the KPICV registers when the device is in CM or DM mode The KPICV is updated by shifting" "0,1"
|
|
line.long 0x24 "HOSTSHADOWKCEICVREG,This register interface is used to update the KCEICV registers when the device is in CM or DM mode. The KCEICV is updated by shifting"
|
|
bitfld.long 0x24 0. "HOSTSHADOWKCEICVREG,This field is used to update the KCEICV registers when the device is in CM or DM mode The KCEICV is updated by shifting" "0,1"
|
|
line.long 0x28 "OTPADDRWIDTHDEF,OTP_ADDR_WIDTH parameter. that will define the integrated OTP address width (address in words). The supported sizes are 6 (for 2 Kbits).7.8.9.11 (for 64 Kbits). The default value in the provided RTL will be 6.Note: This is a special.."
|
|
hexmask.long.byte 0x28 0.--3. 1. "OTPADDRWIDTHDEF,Holds the OTP_ADDR_WIDTH_DEF value."
|
|
tree.end
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMA4B2KP")||cpuis("AMAP42KK")||cpuis("AMAP42KP"))
|
|
tree "DC (Display Controller)"
|
|
base ad:0x400A0000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MODE,General control register that activates the NEMAp|dc400 controller and various parameters. sets the timing signals' polarity. activates the global look-up table for gamma correction and chooses the output display formats to meet LCD color.."
|
|
bitfld.long 0x0 31. "DC400ACT,When set to 1 the dc400 controller is activated" "0,1"
|
|
bitfld.long 0x0 30. "CUSOREN,When set to 1 programmable cursor is enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RSVD4,This field is reserved." "0,1"
|
|
bitfld.long 0x0 28. "VSYNCPOL,Defines VSYNC polarity" "0: VSYNC polarity is positive,1: VSYNC polarity is negative"
|
|
newline
|
|
bitfld.long 0x0 27. "HSYNCPOL,Defines HSYNC polarity" "0: HSYNC polarity is positive,1: HSYNC polarity is negative"
|
|
bitfld.long 0x0 26. "DEPOL,Defines DE polarity" "0: DE polarity is positive,1: DE polarity is negative"
|
|
newline
|
|
bitfld.long 0x0 25. "RSVD3,This field is reserved." "0,1"
|
|
bitfld.long 0x0 24. "DITHEREN,When set to 1 dithering is enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "VSYNCEN,When set to 1 VSYNC for a single cycle per line is enabled" "0,1"
|
|
bitfld.long 0x0 22. "PIXCLKPOL,Defines Pixel Clock out polarity" "0: Pixel Clock out polarity is positive,1: Pixel Clock out polarity is negative"
|
|
newline
|
|
bitfld.long 0x0 21. "RSVD2,This field is reserved." "0,1"
|
|
bitfld.long 0x0 20. "GAMARAMPEN,When set to 1 gamma ramp is enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "BLANKFRC,When set to 1 forces output to blank" "0,1"
|
|
bitfld.long 0x0 18. "RSVD1,This field is reserved." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "FRAMEUPDTEN,When set to 1 single frame update is enabled" "0,1"
|
|
hexmask.long.byte 0x0 12.--16. 1. "RSVD0,This field is reserved."
|
|
newline
|
|
bitfld.long 0x0 11. "PLLCLKNDIV,When set to 1 PLL_CLK is not divided" "0,1"
|
|
bitfld.long 0x0 10. "LVDSPADSEN,When set to 1 LVDS output pads are enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "COLFMT,Output color format:" "0: RGB format is enabled,1: YUV/YCbCr format is enabled"
|
|
hexmask.long.byte 0x0 5.--8. 1. "DISPFMT,Display data format"
|
|
newline
|
|
bitfld.long 0x0 4. "DBITYPEBEN,When set to 1 DBI Type-B interface is enabled" "0,1"
|
|
bitfld.long 0x0 3. "YUYVEN,When set to 1 the following output color formats are enabled : Byte-3 beat Interface enabled Byte-4 beat (RGBX) Interface enabled Two phase serial 12-bit enabled YUYV (16-bit mode) enabled BT.656 enabled JDI MIP enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "LVDSINTEN,When set to 1 LVDS interface is enabled" "0,1"
|
|
bitfld.long 0x0 1. "DBLHORSCANEN,When set to 1 double horizontal scan is enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TSTMODEN,When set to 1 test mode is enabled" "0,1"
|
|
line.long 0x4 "CLKCTRL,Setup proper timing with divisor control bits and specify the number of lines to be prefetched before the start of frame."
|
|
hexmask.long.byte 0x4 27.--31. 1. "SECCLKDIV,Value of secondary clock divider"
|
|
bitfld.long 0x4 24.--26. "LVDS,Clock phase shift value for LVDS operation" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "PLL,Select PLL Clock"
|
|
bitfld.long 0x4 14.--15. "RSVD1,This field is reserved." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--13. 1. "LINENUM,Number of lines to be prefetched before starting the frame through DMA. Maximum value is 32"
|
|
bitfld.long 0x4 6.--7. "RSVD0,This field is reserved." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "DIVIDEVALUE,Value of first clock divider"
|
|
line.long 0x8 "BGCOLOR,Specifies the main background color."
|
|
hexmask.long.byte 0x8 24.--31. 1. "REDCOLOR,Color red is used as background color"
|
|
hexmask.long.byte 0x8 16.--23. 1. "GREENCOLOR,Color green is used as background color"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "BLUECOLOR,Color blue is used as background color"
|
|
hexmask.long.byte 0x8 0.--7. 1. "ALPHACOLOR,Color alpha is used as background color"
|
|
line.long 0xC "RESXY,Specifies the main X and Y resolutions."
|
|
hexmask.long.word 0xC 16.--31. 1. "XRES,Value of X resolution in pixels"
|
|
hexmask.long.word 0xC 0.--15. 1. "YRES,Value of Y resolution in pixels"
|
|
group.long 0x14++0xF
|
|
line.long 0x0 "FRONTPORCHXY,Specifies the X and Y dimensions for the Front Porch."
|
|
hexmask.long.word 0x0 16.--31. 1. "FPCLKCYCLES,Specify the pixel clock cycles for the front porch X dimension"
|
|
hexmask.long.word 0x0 0.--15. 1. "FLINES,Specify the number of lines for the front porch Y dimension"
|
|
line.long 0x4 "BLANKINGXY,Specifies the X and Y dimensions for the Blanking Period."
|
|
hexmask.long.word 0x4 16.--31. 1. "HSYNCPULSE,Specify the HSYNC pulse length for the X dimension blanking period"
|
|
hexmask.long.word 0x4 0.--15. 1. "VSYNCLINES,Specify the VSYNC lines for the Y dimension blanking period"
|
|
line.long 0x8 "BACKPORCHXY,Specifies the X and Y dimensions for the Back Porch."
|
|
hexmask.long.word 0x8 16.--31. 1. "BPCLKCYCLES,Specify the pixel clock cycles for the back porch X dimension"
|
|
hexmask.long.word 0x8 0.--15. 1. "BLINES,Specify the number of lines for the back porch Y dimension"
|
|
line.long 0xC "CURSORXY,Specifies the cursor's start X and Y coordinates."
|
|
hexmask.long.word 0xC 16.--31. 1. "CURSORX,Specify cursor's X dimension"
|
|
hexmask.long.word 0xC 0.--15. 1. "CURSORY,Specify cursor's Y dimension"
|
|
group.long 0x28++0x87
|
|
line.long 0x0 "DBICFG,Register for the configuration DBI Type-B interface and the activation of SPI 3-/4-wire interfaces."
|
|
bitfld.long 0x0 31. "DBIINTACT,When set to 1 the DBI interface is activated" "0,1"
|
|
bitfld.long 0x0 30. "CSXCFG,When set to 1 the value of the CSX signal of the DBI interface can be configured from the DBI_CFG[29] register bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "CSXSET,Sets the value of DBIB_CSX signal:" "0: is set to zero if DBI_CFG[29] has the value of..,1: is set to one if DBI_CFG[29] has the value of one"
|
|
bitfld.long 0x0 28. "DBIBTEDIS,When set to 1 the DBIB_TE signal is disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "RSVD4,This field is reserved." "0,1,2,3"
|
|
bitfld.long 0x0 25. "RESXLOW,When set to 1 drives RESX signal low to reset DBI Type-B interface" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "RSVD3,This field is reserved." "0,1"
|
|
bitfld.long 0x0 23. "SPI3,When set to 1 SPI 3-wire interface is enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "SPI4,When set to 1 SPI 4-wire interface is enabled" "0,1"
|
|
hexmask.long.byte 0x0 18.--21. 1. "RSVD2,This field is reserved."
|
|
newline
|
|
bitfld.long 0x0 17. "BINDCMDS,When set to 1 binds the store commands with the RGB data and two-byte address is sent with each horizontal line" "0,1"
|
|
bitfld.long 0x0 16. "INVHRZLINE,When set to 1 inverts the bit-order of the horizontal line address (used along with DBI_CFG[17] register bit)" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "RSVD1,This field is reserved."
|
|
bitfld.long 0x0 11. "BACKPRESSUREEN,When set to 1 back pressure support is enabled (not currently supported)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "RSVD0,This field is reserved." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "TYPEBWIDTH,Set DBI Type-B interface width (8 9 or 16 bits) and the serial interface:" "0: 16-bit interface,1: 9-bit interface,2: 8-bit interface,3: Serial interface"
|
|
newline
|
|
bitfld.long 0x0 3.--5. "DATAWDORDER,Set the data order of the 8-bit data word:" "0: option 0,1: option 1,2: option 2,3: option 3,?,?,?,?"
|
|
bitfld.long 0x0 0.--2. "DBICOLORFMT,Set the color format for DBI interface" "?,1: RGB111 (3 bits/pixel),2: RGB332 (8 bits/pixel),3: RGB444 (12 bits/pixel),?,5: RGB565 (16 bits/pixel),6: RGB666 (18 bits/pixel),7: RGB888 (24 bits/pixel)"
|
|
line.long 0x4 "DCGPIO,General Purpose register: read/write GPIO external pins. This is accumulated as- {CGBYPASS_in.13'd0.ADVANCE_ANYWAY_in.5'd0.GPIO_in}"
|
|
hexmask.long.word 0x4 22.--31. 1. "CGBYPASS,No idea what this is"
|
|
hexmask.long.word 0x4 9.--21. 1. "RSVD1,This field is reserved."
|
|
newline
|
|
bitfld.long 0x4 7.--8. "ADVANCEANYWAY,No idea what this is" "0,1,2,3"
|
|
hexmask.long.byte 0x4 2.--6. 1. "RSVD0,This field is reserved."
|
|
newline
|
|
bitfld.long 0x4 0.--1. "RWPINS,These are not implemented" "0,1,2,3"
|
|
line.long 0x8 "LAYER0MODE,LAYER0_MODE: Activate and set-up layer 0."
|
|
bitfld.long 0x8 31. "LAYER0EN,When set to 1 layer n is enabled" "0,1"
|
|
bitfld.long 0x8 30. "LAYER0FORCE,When set to 1 force alpha with global alpha is enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "LAYER0BFILTER,When set to 1 bilinear filtering is enabled" "0,1"
|
|
bitfld.long 0x8 28. "LAYER0PREMULT,When set to 1 premultiply image alpha is enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "LAYER0HLOCK,When set to 1 HLOCK signal on AHB DMAs is asserted" "0,1"
|
|
bitfld.long 0x8 26. "LAYER0GAMMA,When set to 1 Gamma Look Up Table is enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x8 24.--25. "RSVD1,This field is reserved." "0,1,2,3"
|
|
hexmask.long.byte 0x8 16.--23. 1. "LAYER0ALPHA,Alpha layer global value (0x00-0xFF range)"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--15. 1. "LAYER0DBLEND,Destination blending function"
|
|
hexmask.long.byte 0x8 8.--11. 1. "LAYER0SBLEND,Source blending function"
|
|
newline
|
|
bitfld.long 0x8 5.--7. "RSVD0,This field is reserved." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x8 0.--4. 1. "LAYER0COLMODE,Color mode"
|
|
line.long 0xC "LAYER0STARTXY,X and Y start dimensions of layer 0."
|
|
hexmask.long.word 0xC 16.--31. 1. "LAYER0XOFF,Specify the pixel offset of the starting X dimension of layer 0"
|
|
hexmask.long.word 0xC 0.--15. 1. "LAYER0YOFF,Specify the pixel offset of the starting Y dimension of layer 0"
|
|
line.long 0x10 "LAYER0SIZEXY,X and Y size of layer 0."
|
|
hexmask.long.word 0x10 16.--31. 1. "LAYER0PIXSZEX,Specify the pixel size of the layer 0 in the X dimension"
|
|
hexmask.long.word 0x10 0.--15. 1. "LAYER0PIXSZEY,Specify the pixel size of the layer 0 in the Y dimension"
|
|
line.long 0x14 "LAYER0ADDR,The start address of the framebuffer to be accessed by layer 0."
|
|
hexmask.long 0x14 0.--31. 1. "LAYER0STARTADDRFBUF,Specify the start address of framebuffer for each layer 0."
|
|
line.long 0x18 "LAYER0STRIDE,Specify the stride and the AXI bus burst of layer 0."
|
|
hexmask.long.word 0x18 21.--31. 1. "RSVD,This field is reserved."
|
|
bitfld.long 0x18 19.--20. "LAYER0AXIFIFOTHLD,Specify the AXI fifo threshold burst start in layer 0" "0: half fifo (default),1: 2 burst-size,2: 4 burst-size,3: 8 burst-size"
|
|
newline
|
|
bitfld.long 0x18 16.--18. "LAYER0AXIBURSTBITS,Specify the AXI bits per burst in layer 0" "0: 16-beats (default),1: 2-beats,2: 4-beats,3: 8-beats,4: 16-beats (CHECK mistake?),5: 32-beats (AXI4 only),6: 64-beats (AXI4 only),7: 128-beats (AXI4 only)"
|
|
hexmask.long.word 0x18 0.--15. 1. "LAYER0STRIDEDIST,Specify the stride which is the distance from line to line in bytes for each layer 0 memory"
|
|
line.long 0x1C "LAYER0RESXY,X and Y dimensions for the resolution of layer 0."
|
|
hexmask.long.word 0x1C 16.--31. 1. "LAYER0PIXRESX,Specify the layer n pixel resolution in the X dimension"
|
|
hexmask.long.word 0x1C 0.--15. 1. "LAYER0PIXRESY,Specify the layer n pixel resolution in the Y dimension"
|
|
line.long 0x20 "LAYER0SCALEX,Scale X factor of layer 0."
|
|
hexmask.long 0x20 0.--31. 1. "LAYER0XFACTOR,Specify the scale X factor of layer n (4.14 fixed point number)"
|
|
line.long 0x24 "LAYER0SCALEY,Scale Y factor of layer 0."
|
|
hexmask.long 0x24 0.--31. 1. "LAYER0YFACTOR,Specify the scale Y factor of layer n (4.14 fixed point number)"
|
|
line.long 0x28 "LAYER1MODE,Activate and set-up layer 1."
|
|
bitfld.long 0x28 31. "LAYER1EN,When set to 1 layer n is enabled" "0,1"
|
|
bitfld.long 0x28 30. "LAYER1FORCE,When set to 1 force alpha with global alpha is enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x28 29. "LAYER1BFILTER,When set to 1 bilinear filtering is enabled" "0,1"
|
|
bitfld.long 0x28 28. "LAYER1PREMULT,When set to 1 premultiply image alpha is enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x28 27. "LAYER1HLOCK,When set to 1 HLOCK signal on AHB DMAs is asserted" "0,1"
|
|
bitfld.long 0x28 26. "LAYER1GAMMA,When set to 1 Gamma Look Up Table is enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x28 24.--25. "RSVD1,This field is reserved." "0,1,2,3"
|
|
hexmask.long.byte 0x28 16.--23. 1. "LAYER1ALPHA,Alpha layer global value (0x00-0xFF range)"
|
|
newline
|
|
hexmask.long.byte 0x28 12.--15. 1. "LAYER1DBLEND,Destination blending function"
|
|
hexmask.long.byte 0x28 8.--11. 1. "LAYER1SBLEND,Source blending function"
|
|
newline
|
|
bitfld.long 0x28 5.--7. "RSVD0,This field is reserved." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x28 0.--4. 1. "LAYER1COLORMODE,Color mode"
|
|
line.long 0x2C "LAYER1STARTXY,X and Y start dimensions of layer 1."
|
|
hexmask.long.word 0x2C 16.--31. 1. "LAYER1XOFF,Specify the pixel offset of the starting X dimension of layer 1"
|
|
hexmask.long.word 0x2C 0.--15. 1. "LAYER1YOFF,Specify the pixel offset of the starting Y dimension of layer 1"
|
|
line.long 0x30 "LAYER1SIZEXY,X and Y size of layer 1."
|
|
hexmask.long.word 0x30 16.--31. 1. "LAYER1PIXSZEX,Specify the pixel size of the layer 1 in the X dimension"
|
|
hexmask.long.word 0x30 0.--15. 1. "LAYER1PIXSZEY,Specify the pixel size of the layer 1 in the Y dimension"
|
|
line.long 0x34 "LAYER1ADDR,The start address of the framebuffer to be accessed by layer 1."
|
|
hexmask.long 0x34 0.--31. 1. "LAYER1STARTADDRFBUF,Specify the start address of framebuffer for each layer 1."
|
|
line.long 0x38 "LAYER1STRIDE,Specify the stride and the AXI bus burst of layer 1."
|
|
hexmask.long.word 0x38 21.--31. 1. "RSVD,This field is reserved."
|
|
bitfld.long 0x38 19.--20. "LAYER1AXIFIFOTHLD,Specify the AXI fifo threshold burst start in layer 1" "0: half fifo (default),1: 2 burst-size,2: 4 burst-size,3: 8 burst-size"
|
|
newline
|
|
bitfld.long 0x38 16.--18. "LAYER1AXIBURSTBITS,Specify the AXI bits per burst in layer 1" "0: 16-beats (default),1: 2-beats,2: 4-beats,3: 8-beats,4: 16-beats (CHECK mistake?),5: 32-beats (AXI4 only),6: 64-beats (AXI4 only),7: 128-beats (AXI4 only)"
|
|
hexmask.long.word 0x38 0.--15. 1. "LAYER1STRIDEDIST,Specify the stride which is the distance from line to line in bytes for each layer 1 memory"
|
|
line.long 0x3C "LAYER1RESXY,X and Y dimensions for the resolution of layer 1."
|
|
hexmask.long.word 0x3C 16.--31. 1. "LAYER1PIXRESX,Specify the layer n pixel resolution in the X dimension"
|
|
hexmask.long.word 0x3C 0.--15. 1. "LAYER1PIXRESY,Specify the layer n pixel resolution in the Y dimension"
|
|
line.long 0x40 "LAYER1SCALEX,Scale X factor of layer 1."
|
|
hexmask.long 0x40 0.--31. 1. "LAYER1XFACTOR,Specify the scale X factor of layer n (4.14 fixed point number)"
|
|
line.long 0x44 "LAYER1SCALEY,Scale Y factor of layer 1."
|
|
hexmask.long 0x44 0.--31. 1. "LAYER1YFACTOR,Specify the scale Y factor of layer n (4.14 fixed point number)"
|
|
line.long 0x48 "LAYER2MODE,Activate and set-up layer 2."
|
|
bitfld.long 0x48 31. "LAYER2EN,When set to 1 layer n is enabled" "0,1"
|
|
bitfld.long 0x48 30. "LAYER2FORCE,When set to 1 force alpha with global alpha is enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x48 29. "LAYER2BFILTER,When set to 1 bilinear filtering is enabled" "0,1"
|
|
bitfld.long 0x48 28. "LAYER2PREMULT,When set to 1 premultiply image alpha is enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x48 27. "LAYER2HLOCK,When set to 1 HLOCK signal on AHB DMAs is asserted" "0,1"
|
|
bitfld.long 0x48 26. "LAYER2GAMMA,When set to 1 Gamma Look Up Table is enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x48 24.--25. "RSVD1,This field is reserved." "0,1,2,3"
|
|
hexmask.long.byte 0x48 16.--23. 1. "LAYER2ALPHA,Alpha layer global value (0x00-0xFF range)"
|
|
newline
|
|
hexmask.long.byte 0x48 12.--15. 1. "LAYER2DBLEND,Destination blending function"
|
|
hexmask.long.byte 0x48 8.--11. 1. "LAYER2SBLEND,Source blending function"
|
|
newline
|
|
bitfld.long 0x48 5.--7. "RSVD0,This field is reserved." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x48 0.--4. 1. "LAYER2COLORMODE,Color mode"
|
|
line.long 0x4C "LAYER2STARTXY,X and Y start dimensions of layer 2."
|
|
hexmask.long.word 0x4C 16.--31. 1. "LAYER2XOFF,Specify the pixel offset of the starting X dimension of layer 2"
|
|
hexmask.long.word 0x4C 0.--15. 1. "LAYER2YOFF,Specify the pixel offset of the starting Y dimension of layer 2"
|
|
line.long 0x50 "LAYER2SIZEXY,X and Y size of layer 2."
|
|
hexmask.long.word 0x50 16.--31. 1. "LAYER2PIXSZEX,Specify the pixel size of the layer 2 in the X dimension"
|
|
hexmask.long.word 0x50 0.--15. 1. "LAYER2PIXSZEY,Specify the pixel size of the layer 2 in the Y dimension"
|
|
line.long 0x54 "LAYER2ADDR,The start address of the framebuffer to be accessed by layer 2."
|
|
hexmask.long 0x54 0.--31. 1. "LAYER2STARTADDRFBUF,Specify the start address of framebuffer for each layer 2."
|
|
line.long 0x58 "LAYER2STRIDE,Specify the stride and the AXI bus burst of layer 2."
|
|
hexmask.long.word 0x58 21.--31. 1. "RSVD,This field is reserved."
|
|
bitfld.long 0x58 19.--20. "LAYER2AXIFIFOTHLD,Specify the AXI fifo threshold burst start in layer 2" "0: half fifo (default),1: 2 burst-size,2: 4 burst-size,3: 8 burst-size"
|
|
newline
|
|
bitfld.long 0x58 16.--18. "LAYER2AXIBURSTBITS,Specify the AXI bits per burst in layer 2" "0: 16-beats (default),1: 2-beats,2: 4-beats,3: 8-beats,4: 16-beats (CHECK mistake?),5: 32-beats (AXI4 only),6: 64-beats (AXI4 only),7: 128-beats (AXI4 only)"
|
|
hexmask.long.word 0x58 0.--15. 1. "LAYER2STRIDEDIST,Specify the stride which is the distance from line to line in bytes for each layer 2 memory"
|
|
line.long 0x5C "LAYER2RESXY,X and Y dimensions for the resolution of layer 2."
|
|
hexmask.long.word 0x5C 16.--31. 1. "LAYER2PIXRESX,Specify the layer n pixel resolution in the X dimension"
|
|
hexmask.long.word 0x5C 0.--15. 1. "LAYER2PIXRESY,Specify the layer n pixel resolution in the Y dimension"
|
|
line.long 0x60 "LAYER2SCALEX,Scale X factor of layer 2."
|
|
hexmask.long 0x60 0.--31. 1. "LAYER2XFACTOR,Specify the scale X factor of layer n (4.14 fixed point number)"
|
|
line.long 0x64 "LAYER2SCALEY,Scale Y factor of layer 2."
|
|
hexmask.long 0x64 0.--31. 1. "LAYER2YFACTOR,Specify the scale Y factor of layer n (4.14 fixed point number)"
|
|
line.long 0x68 "LAYER3MODE,Activate and set-up layer 3."
|
|
bitfld.long 0x68 31. "LAYER3EN,When set to 1 layer n is enabled" "0,1"
|
|
bitfld.long 0x68 30. "LAYER3FORCE,When set to 1 force alpha with global alpha is enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x68 29. "LAYER3BFILTER,When set to 1 bilinear filtering is enabled" "0,1"
|
|
bitfld.long 0x68 28. "LAYER3PREMULT,When set to 1 premultiply image alpha is enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x68 27. "LAYER3HLOCK,When set to 1 HLOCK signal on AHB DMAs is asserted" "0,1"
|
|
bitfld.long 0x68 26. "LAYER3GAMMA,When set to 1 Gamma Look Up Table is enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x68 24.--25. "RSVD1,This field is reserved." "0,1,2,3"
|
|
hexmask.long.byte 0x68 16.--23. 1. "LAYER3ALPHA,Alpha layer global value (0x00-0xFF range)"
|
|
newline
|
|
hexmask.long.byte 0x68 12.--15. 1. "LAYER3DBLEND,Destination blending function"
|
|
hexmask.long.byte 0x68 8.--11. 1. "LAYER3SBLEND,Source blending function"
|
|
newline
|
|
bitfld.long 0x68 5.--7. "RSVD0,This field is reserved." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x68 0.--4. 1. "LAYER3COLORMODE,Color mode"
|
|
line.long 0x6C "LAYER3STARTXY,X and Y start dimensions of layer 3."
|
|
hexmask.long.word 0x6C 16.--31. 1. "LAYER3XOFF,Specify the pixel offset of the starting X dimension of layer 3"
|
|
hexmask.long.word 0x6C 0.--15. 1. "LAYER3YOFF,Specify the pixel offset of the starting Y dimension of layer 3"
|
|
line.long 0x70 "LAYER3SIZEXY,X and Y size of layer 3."
|
|
hexmask.long.word 0x70 16.--31. 1. "LAYER3PIXSZEX,Specify the pixel size of the layer 3 in the X dimension"
|
|
hexmask.long.word 0x70 0.--15. 1. "LAYER3PIXSZEY,Specify the pixel size of the layer 3 in the Y dimension"
|
|
line.long 0x74 "LAYER3ADDR,The start address of the framebuffer to be accessed by layer 3."
|
|
hexmask.long 0x74 0.--31. 1. "LAYER3STARTADDRFBUF,Specify the start address of framebuffer for each layer 3."
|
|
line.long 0x78 "LAYER3STRIDE,Specify the stride and the AXI bus burst of layer 3."
|
|
hexmask.long.word 0x78 21.--31. 1. "RSVD,This field is reserved."
|
|
bitfld.long 0x78 19.--20. "LAYER3AXIFIFOTHLD,Specify the AXI fifo threshold burst start in layer 3" "0: half fifo (default),1: 2 burst-size,2: 4 burst-size,3: 8 burst-size"
|
|
newline
|
|
bitfld.long 0x78 16.--18. "LAYER3AXIBURSTBITS,Specify the AXI bits per burst in layer 3" "0: 16-beats (default),1: 2-beats,2: 4-beats,3: 8-beats,4: 16-beats (CHECK mistake?),5: 32-beats (AXI4 only),6: 64-beats (AXI4 only),7: 128-beats (AXI4 only)"
|
|
hexmask.long.word 0x78 0.--15. 1. "LAYER3STRIDEDIST,Specify the stride which is the distance from line to line in bytes for each layer 3 memory"
|
|
line.long 0x7C "LAYER3RESXY,X and Y dimensions for the resolution of layer 3."
|
|
hexmask.long.word 0x7C 16.--31. 1. "LAYER3PIXRESX,Specify the layer n pixel resolution in the X dimension"
|
|
hexmask.long.word 0x7C 0.--15. 1. "LAYER3PIXRESY,Specify the layer n pixel resolution in the Y dimension"
|
|
line.long 0x80 "LAYER3SCALEX,Scale X factor of layer 3."
|
|
hexmask.long 0x80 0.--31. 1. "LAYER3XFACTOR,Specify the scale X factor of layer n (4.14 fixed point number)"
|
|
line.long 0x84 "LAYER3SCALEY,Scale Y factor of layer 3."
|
|
hexmask.long 0x84 0.--31. 1. "LAYER3YFACTOR,Specify the scale Y factor of layer n (4.14 fixed point number)"
|
|
group.long 0xE8++0x1B
|
|
line.long 0x0 "DBICMD,Register to read/write commands from/to DBI Type-B interface."
|
|
bitfld.long 0x0 31. "RSVD2,This field is reserved." "0,1"
|
|
bitfld.long 0x0 30. "DIRECTDATA,Send direct data of type 'command' to the DBI interface" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RSVD1,This field is reserved." "0,1"
|
|
bitfld.long 0x0 28. "READDBI,Read from DBI interface" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LOCALSTORE,When set to 1 bits [15:0] are locally stored as base address of the horizontal line; it is used along with the DBI_CFG[17:16] register bits for the SPI interface" "0,1"
|
|
hexmask.long.word 0x0 16.--26. 1. "RSVD0,This field is reserved."
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA2DBI,Data to send to the DBI interface"
|
|
line.long 0x4 "DBIRDAT,Data read by DBI Type-B interface are stored in the DBI_RDAT register."
|
|
hexmask.long 0x4 0.--31. 1. "READTYPEB,Read data from DBI Type-B interface"
|
|
line.long 0x8 "CONFG,Information of the layers n activation and setup."
|
|
hexmask.long.byte 0x8 24.--31. 1. "RSVD,This field is reserved."
|
|
bitfld.long 0x8 23. "CFGLAYER3GAMMALUT,Indicates that layer 3 has gamma LUT" "0,1"
|
|
newline
|
|
bitfld.long 0x8 22. "CFGLAYER3SCALAR,Indicates that layer 3 has scaler" "0,1"
|
|
bitfld.long 0x8 21. "CFGLAYER3BLENDER,Indicates that layer 3 has blender" "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "CFGLAYER3EN,Indicates that layer 3 is enabled" "0,1"
|
|
bitfld.long 0x8 19. "CFGLAYER2GAMMALUT,Indicates that layer 2 has gamma LUT" "0,1"
|
|
newline
|
|
bitfld.long 0x8 18. "CFGLAYER2SCALAR,Indicates that layer 2 has scaler" "0,1"
|
|
bitfld.long 0x8 17. "CFGLAYER2BLENDER,Indicates that layer 2 has blender" "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "CFGLAYER2EN,Indicates that layer 2 is enabled" "0,1"
|
|
bitfld.long 0x8 15. "CFGLAYER1GAMMALUT,Indicates that layer 1 has gamma LUT" "0,1"
|
|
newline
|
|
bitfld.long 0x8 14. "CFGLAYER1SCALAR,Indicates that layer 1 has scaler" "0,1"
|
|
bitfld.long 0x8 13. "CFGLAYER1BLENDER,Indicates that layer 1 has blender" "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "CFGLAYER1EN,Indicates that layer 1 is enabled" "0,1"
|
|
bitfld.long 0x8 11. "CFGLAYER0GAMMALUT,Indicates that layer 0 has gamma LUT" "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "CFGLAYER0SCALAR,Indicates that layer 0 has scaler" "0,1"
|
|
bitfld.long 0x8 9. "CFGLAYER0BLENDER,Indicates that layer 0 has blender" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "CFGLAYER0EN,Indicates that layer 0 is enabled" "0,1"
|
|
bitfld.long 0x8 7. "CFGRGB2YUVEN,Indicates that RGB to YUV converter is enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "CFGDBITYPEBEN,Indicates that DBI Type-B interface is enabled" "0,1"
|
|
bitfld.long 0x8 5. "CFGYUVCNVTEN,Indicates that high quality YUV converter is enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "CFGFORMATTEN,Indicates that formatting is enabled" "0,1"
|
|
bitfld.long 0x8 3. "CFGDITHEREN,Indicates that dithering is enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "CFGPCURSOREN,Indicates that programmable cursor is enabled" "0,1"
|
|
bitfld.long 0x8 1. "CFGFCURSOREN,Indicates that fixed cursor is enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "CFGGLBGAMMAEN,Indicates that Global Gamma/Palette is enabled" "0,1"
|
|
line.long 0xC "IDREG,Identification Register."
|
|
hexmask.long 0xC 0.--31. 1. "DCID,Fixed value for DC ID"
|
|
line.long 0x10 "INTERRUPT,Register interrupts enabled. level or edge enabled."
|
|
bitfld.long 0x10 31. "INTTRIGGER,Interrupt request trigger control" "0: Edge triggering is enabled,1: Level triggering is enabled"
|
|
bitfld.long 0x10 3. "INTTEEN,When set to 1 TE interrupt enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "INTMMUERR,When set to 1 MMU error interrupt enabled" "0,1"
|
|
bitfld.long 0x10 1. "INTHSYNCEN,When set to 1 HSYNC interrupt enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "INTVSYNCEN,When set to 1 VSYNC interrupt enabled" "0,1"
|
|
line.long 0x14 "STATUS,DSI Status register (interrupt and pending activity)"
|
|
bitfld.long 0x14 12. "STATDBIPENDTRANS,Indicates pending output transaction in DBI interface" "0,1"
|
|
bitfld.long 0x14 11. "STATDBIPENDCOM,Indicates pending commands in DBI interface" "0,1"
|
|
newline
|
|
bitfld.long 0x14 10. "STATDBIRGB,Indicates pending RGB data in DBI interface" "0,1"
|
|
bitfld.long 0x14 8. "STATTEAR,Indicates DBI Type-B tearing effect" "0,1"
|
|
newline
|
|
bitfld.long 0x14 7. "STATSTICKY,Indicates sticky underflow. This bit clears when interrupt register is written" "0,1"
|
|
bitfld.long 0x14 6. "STATUF,Indicates current underflow" "0,1"
|
|
newline
|
|
bitfld.long 0x14 5. "STATLAST,Indicates that the last row is currently displayed" "0,1"
|
|
bitfld.long 0x14 4. "STATCSYNC,Indicates the CSYNC signal status (0 or 1) at the current time of reading" "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. "STATVSYNC,Indicates the VSYNC signal status and the tearing e?ect signal status (0 or 1) at the current time of reading" "0,1"
|
|
bitfld.long 0x14 2. "STATHSYNC,Indicates the HSYNC signal status (0 or 1) at the current time of reading" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "STATDE,Indicates the DE signal status (0 or 1) at the current time of reading" "0,1"
|
|
bitfld.long 0x14 0. "STATNOTBLANK,Indicates that the controller is not in active vertical blanking" "0,1"
|
|
line.long 0x18 "COLMOD,Color mode status register indicating formats/back pressure are enabled."
|
|
bitfld.long 0x18 31. "CLMDBKPRESSURE,Indicates that back pressure support for the DBI Type B interface is enabled" "0,1"
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x18 30. "CLMDLVDS,Indicates that back pressure support for the DBI Type B interface is enabled" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x18 29. "CLMDJDI,Indicates that back pressure support for the DBI Type B interface is enabled" "0,1"
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x18 22. "CLMDARGB4444,Indicates that back pressure support for the DBI Type B interface is enabled" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x18 21. "CLMDRGBA4444,Indicates that back pressure support for the DBI Type B interface is enabled" "0,1"
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x18 20. "CLMDQPI,Indicates that back pressure support for the DBI Type B interface is enabled" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x18 19. "CLMDDBIBEXTCTRL,Indicates that back pressure support for the DBI Type B interface is enabled" "0,1"
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x18 18. "CLMDTSC6,Indicates that back pressure support for the DBI Type B interface is enabled" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x18 17. "CLMDTSC,Indicates that back pressure support for the DBI Type B interface is enabled" "0,1"
|
|
endif
|
|
bitfld.long 0x18 16. "CLMDLUT8,Indicates that the LUT8 color format is enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x18 15. "CLMDRGBA5551,Indicates that the RGBA5551 16-bit color format is enabled" "0,1"
|
|
bitfld.long 0x18 14. "CLMDRGBA8888,Indicates that the RGBA8888 32-bit color format is enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x18 13. "CLMDRGB332,Indicates that the RGB332 8-bit color format is enabled" "0,1"
|
|
bitfld.long 0x18 12. "CLMDRGB565,Indicates that the RGB565 16-bit color format is enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x18 11. "CLMDARGB8888,Indicates that the ARGB8888 32-bit color format is enabled" "0,1"
|
|
bitfld.long 0x18 10. "CLMDL8,Indicates that the L8 color format is enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x18 9. "CLMDL1,Indicates that the L1 color format is enabled" "0,1"
|
|
bitfld.long 0x18 8. "CLMDL4,Indicates that the L4 color format is enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x18 7. "CLMDYUYV,Indicates that the YUYV color format is enabled" "0,1"
|
|
bitfld.long 0x18 6. "CLMDRGB888,Indicates that the RGB888 24-bit color format is enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x18 5. "CLMDYUY2,Indicates that the YUY2 color format is enabled" "0,1"
|
|
bitfld.long 0x18 4. "CLMDABGR8888,Indicates that the ABGR8888 32-bit color format is enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x18 3. "CLMDBGRA8888,Indicates that the BGRA8888 32-bit color format is enabled" "0,1"
|
|
bitfld.long 0x18 2. "CLMDVYUV420,Indicates that the V_YUV420 color format is enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x18 1. "CLMDTLYUV420,Indicates that the TLYUV420 color format is enabled" "0,1"
|
|
bitfld.long 0x18 0. "CLMDTSC4TSC6,Indicates that the TSc4/TSc6 propietary color format is enabled" "0,1"
|
|
group.long 0x184++0x3
|
|
line.long 0x0 "CRC,if cyclic redundancy errors occur. they are written in the CRC register."
|
|
hexmask.long 0x0 0.--31. 1. "CRCREG,CRC value if CRC error exists"
|
|
group.long 0x400++0x3
|
|
line.long 0x0 "GLLUT,R[0]G[0]B[0] thru R[255]G[255]B[255] Global palette. gamma correction memory region where x starts at 0 thru 255.Access to all 256 registers is best accomplished by passing an index via a macro. e.g. pseudocode #define DC_L0LUT(n) (*((volatile.."
|
|
hexmask.long.byte 0x0 16.--23. 1. "GLLUT0GAMRAMPR,Gamma ramp red bits"
|
|
hexmask.long.byte 0x0 8.--15. 1. "GLLUT0GAMRAMPG,Gamma ramp green bits"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "GLLUT0GAMRAMPB,Gamma ramp blue bits"
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "CURSORDATA,Color values for the pixel cursor that are used with the Cursor LUT where x starts at 0 thru 127.Access to all 16 registers is best accomplished by passing an index via a macro. e.g. pseudocode #define DC_CURSORDATA(n) (*((volatile.."
|
|
hexmask.long.tbyte 0x0 12.--31. 1. "CURDATA3112,Pixel 'xy' color look up bits"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CURDATA70,Pixel 'xy' color look up bits"
|
|
group.long 0xA00++0x3
|
|
line.long 0x0 "CURSORLUT,R[0]G[0]B[0] thru R[15]G[15]B[15] Cursor Look-up Table where x starts at 0 thru 15.Access to all 16 registers is best accomplished by passing an index via a macro. e.g. pseudocode #define DC_CURSORLUT(n) (*((volatile uint32_t*)(&CURSORLUT +.."
|
|
hexmask.long.byte 0x0 16.--23. 1. "CURLUT0R,Cursor LUT red bits"
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURLUT0G,Cursor LUT green bits"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "CURLUT0B,Cursor LUT blue bits"
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "L0LUT,A[0]R[0]G[0]B[0] thru A[255]R[255]G[255]B[255]. Layer 0 palette.gamma correction memory region where x starts at 0 thru 255."
|
|
hexmask.long.byte 0x0 24.--31. 1. "L0LUT0GAMRAMPA,Gamma ramp alpha bits"
|
|
hexmask.long.byte 0x0 16.--23. 1. "L0LUT0GAMRAMPR,Gamma ramp red bits"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "L0LUT0GAMRAMPG,Gamma ramp green bits"
|
|
hexmask.long.byte 0x0 0.--7. 1. "L0LUT0GAMRAMPB,Gamma ramp blue bits"
|
|
group.long 0x1400++0x3
|
|
line.long 0x0 "L1LUT,A[0]R[0]G[0]B[0] thru A[255]R[255]G[255]B[255] Layer 1 palette.gamma correction memory region where x starts at 0 thru 255.Access to all 256 registers is best accomplished by passing an index via a macro. e.g. pseudocode #define DC_L1LUT(n).."
|
|
hexmask.long.byte 0x0 24.--31. 1. "L1LUT0GAMRAMPA,Gamma ramp alpha bits"
|
|
hexmask.long.byte 0x0 16.--23. 1. "L1LUT0GAMRAMPR,Gamma ramp red bits"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "L1LUT0GAMRAMPG,Gamma ramp green bits"
|
|
hexmask.long.byte 0x0 0.--7. 1. "L1LUT0GAMRAMPB,Gamma ramp blue bits"
|
|
group.long 0x1800++0x3
|
|
line.long 0x0 "L2LUT0,A[0]R[0]G[0]B[0] thru A[255]R[255]G[255]B[255] Layer 2 palette.gamma correction memory region where x starts at 0 thru 255.Access to all 256 registers is best accomplished by passing an index via a macro. e.g. pseudocode #define DC_L2LUT(n).."
|
|
hexmask.long.byte 0x0 24.--31. 1. "L2LUT0GAMRAMPA,Gamma ramp alpha bits"
|
|
hexmask.long.byte 0x0 16.--23. 1. "L2LUT0GAMRAMPR,Gamma ramp red bits"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "L2LUT0GAMRAMPG,Gamma ramp green bits"
|
|
hexmask.long.byte 0x0 0.--7. 1. "L2LUT0GAMRAMPB,Gamma ramp blue bits"
|
|
group.long 0x1C00++0x3
|
|
line.long 0x0 "L3LUT,A[0]R[0]G[0]B[0] thru A[255]R[255]G[255]B[255] Layer 3 palette.gamma correction memory region where x starts at 0 thru 255.Access to all 256 registers is best accomplished by passing an index via a macro. e.g. pseudocode #define DC_L3LUT(n).."
|
|
hexmask.long.byte 0x0 24.--31. 1. "L3LUT0GAMRAMPA,Gamma ramp alpha bits"
|
|
hexmask.long.byte 0x0 16.--23. 1. "L3LUT0GAMRAMPR,Gamma ramp red bits"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "L3LUT0GAMRAMPG,Gamma ramp green bits"
|
|
hexmask.long.byte 0x0 0.--7. 1. "L3LUT0GAMRAMPB,Gamma ramp blue bits"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMA4B2KP")||cpuis("AMAP42KK")||cpuis("AMAP42KP"))
|
|
tree "DSI (Display Serial Interface)"
|
|
base ad:0x400A8000
|
|
group.long 0x0++0x23
|
|
line.long 0x0 "DEVICEREADY,Devide Ready register"
|
|
bitfld.long 0x0 3. "DISPLAYBUSPOSSESSEN,Inform DSI receiver has to be given the bus possession for receiving the tearing effect trigger message; Reset by the processor to stop the bus possession of the DSI receiver; Note: Tearing effect is supported only in Type1; Display.." "?,1: Even if the processor does not clear the.."
|
|
newline
|
|
bitfld.long 0x0 1.--2. "ULPS,ULPS field of the DEVICEREADY register." "0: pattern is set by the processor to make the DSI..,1: This pattern is set by the processor to inform..,2: This pattern is set by the processor to inform..,?"
|
|
newline
|
|
bitfld.long 0x0 0. "READY,Ready for programming after all count registers and timeout." "0: Set by the processor to inform that device is..,1: Set to 1 after dphy_parameter register all the.."
|
|
line.long 0x4 "INTRSTAT,The interrupt status register."
|
|
bitfld.long 0x4 31. "DPIPRGERR,(RW1C) Set to 1 indicates that the error in DPI parameters programming" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "DPILINETO,(RW1C) DPI line time out. Set to 1 indicates that the line time out during the DPI transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RXCNT,(RW1C) Rx Contention; Set to 1 if contention detected in the display" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "INITDONE,(RW1C) Set 1 indicates that the DSI initialization is done. DSI Tx is ready to accept the DPI or DBI or Generic transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "SPECIALPACK,(RW1C) Special packet command sent; Set to confirm the transmission of the DPI event specific commands set in the dpi control and dpi data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "RXDSIPROT,(RW1C) Rx DSI protocol violation; Set if acknowledge short packet shows DSI protocol violation error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "RXINVALID,(RW1C) Rx Invalid; Set if acknowledge short packet shows an invalid transmission count" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "ACKWNOERR,(RW1C) T ACK_with No_error; Set if acknowledge trigger message is received with out any error." "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "TURNARNDACK,(RW1C) Turn around acknowledge. Set if a turn around acknowledgement sequence is timeout not received from the display device" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "LPRXTIMEOUT,(RW1C) Set if a low power reception count expires this interrupt is generated" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "HSTXTIMEOUT,(RW1C) Set if a high speed transmission prevails for more than the expected count value this interrupt is raised" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "FIFOEMPTY,(RW1C) Set to 1 if all FIFOs are empty" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "LOWC,(RW1C) Low contention; Set to 1 if a LP low fault is registered by at the D-PHY contention detector. If this interrupt is set device should be re-enumerated" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "HIGHC,(RW1C) High contention;Set to 1 if a LP high fault is registered by at the D-PHY contention detector. If this interrupt is set device should be re-enumerated" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "TxDSII,(RW1C) TxDSI VC ID invalid; Set to 1 if the received virtual channel ID is invalid" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "TxDSIN,(RW1C) TxDSI data type not recognised; Set to 1 if the received data type is not recognised" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TXCHECKSUM,(RW1C) Txchecksum error; Set to 1 if the computed CRC differs from the received CRC value during the reception of packets by Arasan_DSI host" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "TXECCM,(RW1C) Set to 1 if there is no ECC correction for the packet or there are more than 2 bit errors in the packet received by Arasan_DSI_host." "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "TXECCS,(RW1C) Set to 1 if ECC syndrome was computed and is corrected for one bit error during the reception of packets by the Arasan_DSI_host." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "TXFALSECNTRL,(RW1C) TxFalse Control Error; Set to 1 if a control error is observed on the lanes by the Arasan_DSI_host" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "RxDSIDI,(RW1C) RxDSI VC ID invalid; Set to 1 if the virtual channel ID is invalid by the display device is reported in the Acknowledge packet by the display device" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "RxDSINR,(RW1C) RxDSI data type not recognised; Set to 1 if the data type is not recognised by the display device is reported in the Acknowledge packet by the display device" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "RXCHECKSUM,(RW1C) Set to 1 if the computed CRC differs from the received CRC value and is reported in the acknowledge packet by the display device" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "RxECCM,(RW1C) RxECC multibit error; Set to 1 if there is no ECC correction for the packet or there are more than 2 bit errors in the packet isreported in the Acknowledge packet by the display device" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RxECCS,(RW1C) RRxECC single bit error; Set to 1 if ECC syndrome was computed and corrected for one bit error is reported in the Acknowledge packet by the display device" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "RXFALSECNTRL,(RW1C) RxFalse Control Error; Set to 1 if a control error is reported in the acknowledge packet by the display device" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXPERIPHERAL,(RW1C) Rx Peripheral timeout Error; Set to 1 if the high speed receive timer value or LP Tx timer value are expired display device is reported in the Acknowledge packet" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXLPTXSYNCERR,(RW1C) Rx LP tx sync error; Set to 1 if Low power transmission sync error occurs in the display device and is reported in the Acknowledge packet by the display device" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXESCAPEMODE,(RW1C) Entry Error; Set to 1 if Escape Mode Entry command is not understandable by the display device and is reported in the Acknowledge packet by the display device." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXEOTSYNCERROR,(RW1C) Set to 1 if End of transmission synchronisation Error is reported in the acknowledgment packet by the display device" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RXSOTSYNCERROR,(RW1C) Set to 1 if synchronisation error occurrence in the start of transmission sequence is reported in the acknowledge packet by the display device" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXSOTERROR,(RW1C) Set to 1 if a start of transmission sequence error is reported in the Acknowledge packet by the display device" "0,1"
|
|
line.long 0x8 "INTREN,Interrupt enable register."
|
|
bitfld.long 0x8 31. "DPI,PGRMERR DPI program error; Set to 1 indicates that the error in DPI parameters programming" "0,1"
|
|
newline
|
|
bitfld.long 0x8 30. "DPILINETO,Dpi line timeout; Set to 1 indicates that the line time out during the DPI transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "RXCONTENT,Detected Rx Contention Detected; Set to enable the interrupt for contention detected error in the acknowledgment packet reports" "0,1"
|
|
newline
|
|
bitfld.long 0x8 28. "INITDONE,Set 1 indicates that the DSI initialisation is done DSI Tx is ready to accept the DPI or DBI or Generic transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "SPECIALPACK,Special packet command sent; Set to enable the confirmation interrupt for transmitting DPI events set in the dpi data and dpi control registers" "0,1"
|
|
newline
|
|
bitfld.long 0x8 26. "RXDSI,Rx DSI protocol violation; Set to enable DSI protocol violation error" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "RXINV,Rx Invalid transmission count error; Set to enable acknowledge invalid transmission counterror" "0,1"
|
|
newline
|
|
bitfld.long 0x8 24. "ACKWITHNOERR,ACK with No_error; Set to enable acknowledge trigger message reception with out any error" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "TURNARNDACK,Set to enable turn around acknowledgement sequence timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x8 22. "LPRXTIMEOUT,Set to enable low power reception count timeouts" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "HSTXTIMEOUT,Set to enable a high speed transmission timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "FIFOEMPTY,Set to enable a FIFO empty interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "LOWC,Low contention; Set to enable a LP low fault interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 18. "HIGHC,High contention; Set to enable a LP high fault interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "TxDSIV,TxDSI VC ID invalid; Set to enable the interrupt if the received packets virtual channel ID is invalid" "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "TxDSID,TxDSI data type not recognised; Set to enable the interrupt if the received packets data type is not recognised" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "TXCHCKSUM,Txchecksum error; Set to enable the interrupt if the computed CRC differs from the received CRC value for the received packets" "0,1"
|
|
newline
|
|
bitfld.long 0x8 14. "TxECCM,TxECC multibit; Set to enable the interrupt if there is no ECC correction for the packet or there are more than 2 bit errors in the packet received by Arasan DSI host" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "TxECCS,TxECC single bit; Set to enable the interrupt if ECC syndrome was computed and is corrected for one bit error during the reception of packets by the Arasan DSI Host" "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "TxFalseCntrl,TxFalse Control; Set to enable the interrupt for the control error observed on the lanes by the Arasan_DSI_host" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "RxDSIV,RxDSI VC ID invalid virtual channel; Set to enable the interrupt for invalid ID in the acknowledgment packet reports" "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "RxDSIData,RxDSI data type not recognised; Set to enable the interrupt for the un recognised data type in the acknowledgment packet reports" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "RXCHECKSUM,Rxchecksum error; Set to enable the interrupt for the computed CRC differs from the received CRC value in the acknowledgment packet reports" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "RXECCM,RxECC multibit error; Set to enable the interrupt for no ECC correction for the packet or there are more than 2 bit errors reported in the acknowledgment packet" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "RXECCS,RxECC single bit error; Set to enable the interrupt for ECC syndrome computation and one bit error correction for the acknowledgment packet" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "RXFALSE,RxFalse Control error; set to enable the interrupt for control error in the acknowledgment packet reports." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "RXPERIPHRCVTOE,Peripheral receive timeout Error; Set to enable the interrupt for the high speed timeout Error or Lp tx timeout error in the acknowledgment packet reports" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "RXLPTXSYNCERR,Rx LP tx sync error; Set to enable the interrupt for Low power transmission sync error in the acknowledgment packet reports" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "RXESCPMDETRYERR,RxEscape Mode Entry Error; Set to enable the interrupt for Escape Mode Entry command error in the acknowledgment packet reports" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "RXEOTSYNCRR,RxEot Sync Error l set to enable the interrupt for the end of transmission synchronisation Error in the acknowledgment packet reports" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "RXSOTSYNCERROR,RX start of transmission; Set to enable the interrupt for start of transmission synchronization error in the acknowledgement packet reports" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "RXSOTERROR,RX start of transmission; set to enable the interrupt for start of transmission" "0,1"
|
|
line.long 0xC "DSIFUNCPRG,DSI function programming register"
|
|
bitfld.long 0xC 13.--15. "REGNAME,Field description needed here." "0: mode is not supported],1: 16 bit data,2: 9 bit data,3: 8 bit data,?,?,?,?"
|
|
newline
|
|
bitfld.long 0xC 7.--9. "SUPCOLVIDMODE,Supported colour format for video mode." "0: Video mode is not supported,1: RGB565 or 16-bit format,2: RGB666 or 18-bit format,3: RGB 666 loosely packed format,4: RGB888 or 24-bit format,?,?,?"
|
|
newline
|
|
bitfld.long 0xC 5.--6. "CHNUMCMODE,Channel Number for command mode is programmed by the processor" "0: Virtual command mode channel 0,1: Virtual command mode channel 1,2: Virtual command mode channel 2,3: Virtual command mode channel 3"
|
|
newline
|
|
bitfld.long 0xC 3.--4. "CHNUMVM,Channel number for video mode" "0: Virtual video mode channel 0,1: Virtual video mode channel 1,2: Virtual video mode channel 2,3: Virtual video mode channel 3"
|
|
newline
|
|
bitfld.long 0xC 0.--2. "DATALANES,The number Data lanes to be supported is programmed by the processor" "0: Zero data lane,1: One data lane,2: Two data lane,3: Three data lane,4: Four data lane,?,?,?"
|
|
line.long 0x10 "HSTXTIMEOUT,Maximum duration allow for the DSi host to remain in High speed mode for transmission."
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "MAXDURTOCNT,The maximum duration allowed for the DSI host to remain in high speed mode for a transmission. If the counter expires processor is interrupted with HS_Tx_timeout interrupt"
|
|
line.long 0x14 "LPRXTO,Timeout value to be checked for reverse communicationl"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "TOCHKRVS,Timeout value to be checked for reverse communication. If the counter expires processor is interrupted with LP_Rx_timeout interrupt.The timeout value is protocol specific. Time out value is calculated from txclkesc(50ns)."
|
|
line.long 0x18 "TURNARNDTO,Timeout value to be checked after the DSI host makes a trun around in the direction of transfers."
|
|
hexmask.long.byte 0x18 0.--5. 1. "TIMOUT,If the counter expires processor is interrupted with Turn_around_ack timeout interrupt; this specified period shall be longer then the maximum possible turnaround delay for the unit to which the turnaround request was sent which is 23 clock.."
|
|
line.long 0x1C "DEVICERESETTIMER,Timeout value to be checked for device to be reset after issuing reset entry command"
|
|
hexmask.long.word 0x1C 0.--15. 1. "TIMOUT,If the timer expires the DSI Host enters normal operation; This time out value is used while contention recovery procedure; the time out value is equal to a value longer than the specified time required to complete the reset sequence"
|
|
line.long 0x20 "DPIRESOLUTION,Shows the horizontal address count in pixels"
|
|
hexmask.long 0x20 0.--31. 1. "DPIRESOLUTION,DPIRESOLUTION register description needed here."
|
|
group.long 0x28++0x5F
|
|
line.long 0x0 "HSYNCCNT,Shows the horizontal sync value in terms of byte clock."
|
|
hexmask.long.word 0x0 0.--15. 1. "HORZCNT,Shows the horizontal sync value in terms of byte clock (txbyteclkhs); Minimum HSA period should be sufficient to transmit a Hsync start short packet(4 bytes) i) For Non-burst Mode with sync pulse Min value - 4 in decimal (plus an optional 6.."
|
|
line.long 0x4 "HORIZBKPORCHCNT,Shows the horizontal back porch value in terms of txbyteclkhs."
|
|
hexmask.long.word 0x4 0.--15. 1. "HORZBKPCNT,For Non Burst Sync pulse mode for one lane. Minimum HBP count = Hsync End short packet + HBP Blanking packet overhead (header(4) + crc (2)) + RGB packet header For other lane counts minimum value = Minimum HBPcount / lane_count. For Non Burst.."
|
|
line.long 0x8 "HORIZFPORCHCNT,Shows the horizontal front porch value in terms of txbyteclkhs."
|
|
hexmask.long.word 0x8 0.--15. 1. "HORZFTPCNT,Minimum HFP period should be sufficient to transmit RGB Data packet footer (2 bytes) + Blanking packet overhead (6 bytes) +adjustable count (16 bytes) for non burst mode; For other lane counts Minimum value = (RGB Data packet footer(2 bytes) +.."
|
|
line.long 0xC "HORZACTIVEAREACNT,Horizontal active area count / time for active image data / Horizontal Address"
|
|
hexmask.long.word 0xC 0.--15. 1. "HORACTCNT,Shows the horizontal active area value in terms of txbyteclkhs. In Non Burst Mode Count equal to RGB word count value In Burst Mode RGB pixel packets are time compressed leaving more time during a scan line for LP mode (saving power) or for.."
|
|
line.long 0x10 "VSYNCCNT,Shows the vertical sync value"
|
|
hexmask.long.word 0x10 0.--15. 1. "VSC,Shows the vertical sync value in terms of lines. Min value - 2 Max value - any 12 bit value greater than 2 based on DPI resolution"
|
|
line.long 0x14 "VERTBKPORCHCNT,Shows the vertical back porch value"
|
|
hexmask.long.word 0x14 0.--15. 1. "VBPSC,Shows the vertical back porch value in terms of lines. Min value - 1; Max value - any 12 bit value greater than 1 based on DPI resolution"
|
|
line.long 0x18 "VERTFPORCHCNT,Shows the vertical front porch value"
|
|
hexmask.long.word 0x18 0.--15. 1. "VFPSC,Shows the vertical front porch value in terms of lines. Min value - 1; Max value - any 12 bit value greater than 1 based on DPI resolution"
|
|
line.long 0x1C "DATALANEHILOSWCNT,High speed to low power or Low power to high speed switching time"
|
|
hexmask.long.word 0x1C 0.--15. 1. "DATALHLSWCNT,High speed to low power or Low power to high speed power or Low switching time in terms byte clock (txbyteclkhs). This power to high speed switch count value is based on the byte clock (txbyteclkhs) and low power clock frequency (txclkesc);.."
|
|
line.long 0x20 "DPI,DPI control register."
|
|
bitfld.long 0x20 3. "COLORMODEOFF,Set to 1 to indicate a Color Mode OFF short packet has to be packetised for the DPIs virtual channel" "0,1"
|
|
newline
|
|
bitfld.long 0x20 2. "COLOR,MODEON Set to 1 to indicate a color Mode ON short packet has to be packetised for the DPIs virtual channel." "0,1"
|
|
newline
|
|
bitfld.long 0x20 1. "TURNON1,Set to 1 to indicate a Turn ON short packet has to be packetised for the DPIs virtual channel" "0,1"
|
|
newline
|
|
bitfld.long 0x20 0. "SHUTDOWN,Set to 1 to indicate a shut down short packet has to be packetised for the DPIs virtual channel" "0,1"
|
|
line.long 0x24 "PLLLOCKCNT,The PLL counter value"
|
|
hexmask.long.word 0x24 0.--15. 1. "PLLCNTVAL,Pll counter value in terms of low power clock."
|
|
line.long 0x28 "INITCNT,Count register to initialize the DSI HOST IP"
|
|
hexmask.long.word 0x28 0.--15. 1. "MSTR,Counter value in terms of low power clock to initialise the DSI Host IP (TINIT) that drives a stop state on the mipis D-PHY bus; DPHY Initialization period min 100 x B5s; Time out value is calculated by txclkesc and the count value is 7d0h(2000 in.."
|
|
line.long 0x2C "MAXRETPACSZE,MAXRETPACSZE register description needed here."
|
|
bitfld.long 0x2C 15. "HSLP,Indicates the data transfer type" "0,1"
|
|
newline
|
|
hexmask.long.word 0x2C 0.--10. 1. "COUNTVAL,Set the count value in bytes to collect the return data packet for reverse direction data flow in data lane0 in response to a DBI read operation; Count value equals the maximum size of the payload in a Long packet transmitted from peripheral.."
|
|
line.long 0x30 "VIDEOMODEFMT,Sets the Video mode format (packet sequence) to be supported in DSI."
|
|
bitfld.long 0x30 0.--1. "VIDEMDFMT,Sets the Video mode format (packet sequence) to be supported in DSI; in Non Burst Mode in addition to programming this register the horizontal active area count register value should also be programmed equal to RGB word count value; in Burst.." "0: VIDEMDFMT enum description needed here.,1: Non Burst Mode with Sync Pulse,2: Non Burst Mode with Sync events,3: MODE Burst Mode"
|
|
line.long 0x34 "CLKEOT,The EOT clock register disables the video."
|
|
bitfld.long 0x34 2. "BTA,Disable video; Set by the processor to inform the DSI controller to disable the BTA sent at the last blanking line of VFP. By default this bit is set to 0; 0 BTA sending at the last blanking line of VFP is enabled; 1 BTA sending at the last.." "0,1"
|
|
newline
|
|
bitfld.long 0x34 1. "CLOCK,Set by the processor to enable or disable clock; Stopping feature during BLLP timing in a DPI transfer in dual channel mode or during DPI only mode and also when there is no traffic in the DBI interface in DBI only enabled mode. By default this.." "0,1"
|
|
newline
|
|
bitfld.long 0x34 0. "EOT,Set by the processor to enable or disable EOT short disable_register packet transmission; vy default this register value is 0; for backward compatibility of earlier DSI systems EOT short packet transmission can be disabled; 0 EOT short packet.." "0,1"
|
|
line.long 0x38 "POLARITY,Polarity Register"
|
|
hexmask.long.byte 0x38 0.--3. 1. "PBITS,Polarity bits"
|
|
line.long 0x3C "CLKLANESWT,High speed to low power switching time in terms ofbyte clock (txbyteclkhs)"
|
|
hexmask.long.word 0x3C 16.--31. 1. "LOWPWR2HI,This value is based on the byte clock (txbyteclkhs) and low power clock frequency (txclkesc)LP to HS switch count = 4 * Tlpx + (programmed Tclk_prep + extracount (1 byteclk) ) + (programmed Tclk_zero + extracount (1 byteclk) ) + Tclk_pre + 2.."
|
|
newline
|
|
hexmask.long.word 0x3C 0.--15. 1. "HISPLPSW,High speed to low power switching time in terms byte clock (txbyteclkhs). This value is based on the byte clock (txbyteclkhs) and low power clock frequency; HS to LP switch count = Tclk_trail + THS_Exit + 3 byteclk Tclk_trail = programmed value.."
|
|
line.long 0x40 "LPBYTECLK,Low power clock equivalence in terms of byte clock."
|
|
hexmask.long.word 0x40 0.--15. 1. "VALBYTECLK,The value programmed in this register is equal to the number of byte clocks occupied in one low power clock; this value is based on the byte clock (txbyteclkhs) and low power clock frequency (txclkesc)"
|
|
line.long 0x44 "DPHYPARAM,This field provides the timing requirement in byte clocks for the high speed preparation time."
|
|
hexmask.long.byte 0x44 24.--31. 1. "HSEXIT,This field provides the timing requirement in byte clocks for the high speed exit time; this corresponds to the THS-EXIT parameter specified in the DPHY specification"
|
|
newline
|
|
hexmask.long.byte 0x44 16.--23. 1. "HSTRAIL,This field provides the timing requirement in byte clocks for the high speed trail time; this corresponds to the THS-TRAIL parameter specified in the DPHY specification"
|
|
newline
|
|
hexmask.long.byte 0x44 8.--15. 1. "HSZERO,This field provides the timing requirement in byte clocks for the high speed drive zero time. This corresponds to the THS-ZERO parameter specified in the DPHY specification"
|
|
newline
|
|
hexmask.long.byte 0x44 0.--7. 1. "HSPREP,This field provides the timing requirement in byte clocks for the high speed preparation time. This corresponds to the THS-PREP parameter specified in the DPHY specificaton"
|
|
line.long 0x48 "CLKLANETIMPARM,This field provides the timing requirement in byte clocks"
|
|
hexmask.long.byte 0x48 24.--31. 1. "HSEXIT,This field provides the timing requirement in byte clocks for the high speed exit time; This corresponds to the THS-EXIT parameter specified in the DPHY specification."
|
|
newline
|
|
hexmask.long.byte 0x48 16.--23. 1. "HSTRAIL,This field provides the timing requirement in byte clocks for the high speed trail time; This corresponds to the TCLK-TRAIL parameter specified in the DPHY specification"
|
|
newline
|
|
hexmask.long.byte 0x48 8.--15. 1. "HSZERO,This field provides the timing requirement in byte clocks for the high speed drive zero time; this corresponds to the TCLK-ZERO parameter specified in the DPHY specification"
|
|
newline
|
|
hexmask.long.byte 0x48 0.--7. 1. "HSPREP,This field provides the timing requirement in byte corresponds to the TCLK-PREP parameter specified in the DPHY specificatio"
|
|
line.long 0x4C "RSTENBDFE,This field provides the reset (enable) to the DFE"
|
|
bitfld.long 0x4C 0. "ENABLE,This field provides the reset (enable) to the DFE." "0,1"
|
|
line.long 0x50 "AFETRIM0,Afe Trim reg0"
|
|
hexmask.long 0x50 0.--31. 1. "AFETRIM0,Afe Trim reg0."
|
|
line.long 0x54 "AFETRIM1,Afe Trim reg1"
|
|
hexmask.long 0x54 0.--31. 1. "AFETRIM1,Afe Trim reg1."
|
|
line.long 0x58 "AFETRIM2,Afe Trim reg2"
|
|
hexmask.long 0x58 0.--31. 1. "AFETRIM2,Afe Trim reg2."
|
|
line.long 0x5C "AFETRIM3,Afe Trim reg3"
|
|
hexmask.long 0x5C 0.--31. 1. "AFETRIM3,Afe Trim reg3."
|
|
group.long 0x98++0xB
|
|
line.long 0x0 "ERRORAUTORCOV,Errir ayti recivert register"
|
|
bitfld.long 0x0 5. "LPRXTIMEOUTCLR,If this bit is set to 1 lp_rx_timeout_clr error recovery action is taken immediately by DSI TX" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "HSRXTIMEOUTCLR,If this bit is set to 1 Hs_rx_timeout_clr error recovery action is taken immediately by DSI TX" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "LOCONTCLR,If this bit is set to 1 lo_cont_clr error recovery action is taken immediately by DSI TX" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "HICONTCLR,If this bit is set to 1 Hi_cont_clr error recover action is taken immediately by DSI TX" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "INVLDDTCLR,If this bit is set to 1 Invld_dt_clr error recovery action is taken immediately by DSI TX" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ECCMULERRCLR,if this bit is set to 1 Ecc_mul_err_clr error recovery action is taken immediately by DSI TX" "0,1"
|
|
line.long 0x4 "MIPIDIRDPIDIFF,Mipi direction DPI difference"
|
|
hexmask.long.word 0x4 16.--31. 1. "DPIDIFF,This field provides the difference in one line time between DPI and DSI"
|
|
newline
|
|
bitfld.long 0x4 15. "DPIHIGH,This field provides information to check DPI line time is greater or DSI line time is greater" "0: one line time in DPI is less than to DSI line time,1: one line time in DPI is greater than or equal to.."
|
|
newline
|
|
bitfld.long 0x4 0. "MIPIDIR,This field provides the direction of MIPI bus;" "0: DSI Host has the control over MIPI bus,1: DSI Host is in Receive mode"
|
|
line.long 0x8 "DATALANEPOLSWAP,Data lane polarity swap register"
|
|
hexmask.long.byte 0x8 0.--3. 1. "DATALNPOLSWAP,Data lane Polarity sw"
|
|
tree.end
|
|
endif
|
|
tree "DSP (DSP Control Interface)"
|
|
base ad:0x40100000
|
|
group.long 0x40++0x1F
|
|
line.long 0x0 "MUTEX0,MUTEX 0"
|
|
bitfld.long 0x0 0.--2. "MUTEX0,Mutex Value (000=resource free 001=CPU owns mutex 010=DSP0 owns mutex 100=DSP1 owns mutex)" "0: resource free,1: CPU owns mutex,2: DSP0 Owns Mutex,?,4: DSP1 Owns Mutex,?,6: Clear Mutex (conditional),7: Set Mutex (conditional)"
|
|
line.long 0x4 "MUTEX1,MUTEX 1"
|
|
bitfld.long 0x4 0.--2. "MUTEX1,Mutex Value (000=resource free 001=CPU owns mutex 010=DSP0 owns mutex 100=DSP1 owns mutex)" "0: resource free,1: CPU owns mutex,2: DSP0 Owns Mutex,?,4: DSP1 Owns Mutex,?,6: Clear Mutex (conditional),7: Set Mutex (conditional)"
|
|
line.long 0x8 "MUTEX2,MUTEX 2"
|
|
bitfld.long 0x8 0.--2. "MUTEX2,Mutex Value (000=resource free 001=CPU owns mutex 010=DSP0 owns mutex 100=DSP1 owns mutex)" "0: resource free,1: CPU owns mutex,2: DSP0 Owns Mutex,?,4: DSP1 Owns Mutex,?,6: Clear Mutex (conditional),7: Set Mutex (conditional)"
|
|
line.long 0xC "MUTEX3,MUTEX 3"
|
|
bitfld.long 0xC 0.--2. "MUTEX3,Mutex Value (000=resource free 001=CPU owns mutex 010=DSP0 owns mutex 100=DSP1 owns mutex)" "0: resource free,1: CPU owns mutex,2: DSP0 Owns Mutex,?,4: DSP1 Owns Mutex,?,6: Clear Mutex (conditional),7: Set Mutex (conditional)"
|
|
line.long 0x10 "MUTEX4,MUTEX 4"
|
|
bitfld.long 0x10 0.--2. "MUTEX4,Mutex Value (000=resource free 001=CPU owns mutex 010=DSP0 owns mutex 100=DSP1 owns mutex)" "0: resource free,1: CPU owns mutex,2: DSP0 Owns Mutex,?,4: DSP1 Owns Mutex,?,6: Clear Mutex (conditional),7: Set Mutex (conditional)"
|
|
line.long 0x14 "MUTEX5,MUTEX 5"
|
|
bitfld.long 0x14 0.--2. "MUTEX5,Mutex Value (000=resource free 001=CPU owns mutex 010=DSP0 owns mutex 100=DSP1 owns mutex)" "0: resource free,1: CPU owns mutex,2: DSP0 Owns Mutex,?,4: DSP1 Owns Mutex,?,6: Clear Mutex (conditional),7: Set Mutex (conditional)"
|
|
line.long 0x18 "MUTEX6,MUTEX 6"
|
|
bitfld.long 0x18 0.--2. "MUTEX6,Mutex Value (000=resource free 001=CPU owns mutex 010=DSP0 owns mutex 100=DSP1 owns mutex)" "0: resource free,1: CPU owns mutex,2: DSP0 Owns Mutex,?,4: DSP1 Owns Mutex,?,6: Clear Mutex (conditional),7: Set Mutex (conditional)"
|
|
line.long 0x1C "MUTEX7,MUTEX 7"
|
|
bitfld.long 0x1C 0.--2. "MUTEX7,Mutex Value (000=resource free 001=CPU owns mutex 010=DSP0 owns mutex 100=DSP1 owns mutex)" "0: resource free,1: CPU owns mutex,2: DSP0 Owns Mutex,?,4: DSP1 Owns Mutex,?,6: Clear Mutex (conditional),7: Set Mutex (conditional)"
|
|
group.long 0x80++0x17
|
|
line.long 0x0 "CPUMBINTSET,CPU Mailbox Interrupt Set"
|
|
hexmask.long 0x0 0.--31. 1. "CPUMBINTSET,CPU Mailbox interrupt Set. The corresponding data bit will set the interrupt."
|
|
line.long 0x4 "CPUMBINTCLR,CPU Mailbox Interrupt Clear"
|
|
hexmask.long 0x4 0.--31. 1. "CPUMBINTCLR,CPU Mailbox interrupt Clear. The corresponding data bit will clear the interrupt."
|
|
line.long 0x8 "CPUMBINTSTAT,CPU Mailbox Interrupt Status"
|
|
hexmask.long 0x8 0.--31. 1. "CPUMBINTSTAT,CPU CPU Mailbox interrupt status"
|
|
line.long 0xC "CPUCPUMBDATA,CPU CPU Mailbox Data"
|
|
hexmask.long 0xC 0.--31. 1. "CPUCPUMBDATA,CPU CPU Mailbox data"
|
|
line.long 0x10 "DSP0CPUMBDATA,DSP0 to CPU Mailbox Data"
|
|
hexmask.long 0x10 0.--31. 1. "DSP0CPUMBDATA,DSP0 to CPU Mailbox data"
|
|
line.long 0x14 "DSP1CPUMBDATA,DSP1 to CPU Mailbox Data"
|
|
hexmask.long 0x14 0.--31. 1. "DSP1CPUMBDATA,DSP1 to CPU Mailbox data"
|
|
group.long 0xA0++0x17
|
|
line.long 0x0 "DSP0MBINTSET,DSP0 Mailbox Interrupt Set"
|
|
hexmask.long 0x0 0.--31. 1. "DSP0MBINTSET,DSP0 Mailbox interrupt Set. The corresponding data bit will set the interrupt."
|
|
line.long 0x4 "DSP0MBINTCLR,DSP0 Mailbox Interrupt Clear"
|
|
hexmask.long 0x4 0.--31. 1. "DSP0MBINTCLR,DSP0 Mailbox interrupt Clear. The corresponding data bit will clear the interrupt."
|
|
line.long 0x8 "DSP0MBINTSTAT,DSP 0 Mailbox Interrupt Status"
|
|
hexmask.long 0x8 0.--31. 1. "DSP0MBINTSTAT,DSP 0 CPU Mailbox interrupt"
|
|
line.long 0xC "CPUDSP0MBDATA,CPU to DSP 0 Mailbox Data"
|
|
hexmask.long 0xC 0.--31. 1. "CPUDSP0MBDATA,DSP 0 CPU Mailbox data"
|
|
line.long 0x10 "DSP0DSP0MBDATA,DSP0 to DSP 0 Mailbox Data"
|
|
hexmask.long 0x10 0.--31. 1. "DSP0DSP0MBDATA,DSP0 to DSP 0 Mailbox data"
|
|
line.long 0x14 "DSP1DSP0MBDATA,DSP1 to DSP 0 Mailbox Data"
|
|
hexmask.long 0x14 0.--31. 1. "DSP1DSP0MBDATA,DSP1 to DSP 0 Mailbox data"
|
|
group.long 0xC0++0x17
|
|
line.long 0x0 "DSP1MBINTSET,DSP1 Mailbox Interrupt Set"
|
|
hexmask.long 0x0 0.--31. 1. "DSP1MBINTSET,DSP1 Mailbox interrupt Set. The corresponding data bit will set the interrupt."
|
|
line.long 0x4 "DSP1MBINTCLR,DSP1 Mailbox Interrupt Clear"
|
|
hexmask.long 0x4 0.--31. 1. "DSP1MBINTCLR,DSP1 Mailbox interrupt Clear. The corresponding data bit will clear the interrupt."
|
|
line.long 0x8 "DSP1MBINTSTAT,DSP 1 Mailbox Interrupt Status"
|
|
hexmask.long 0x8 0.--31. 1. "DSP1MBINTSTAT,DSP 1 CPU Mailbox interrupt"
|
|
line.long 0xC "CPUDSP1MBDATA,CPU to DSP 1 Mailbox Data"
|
|
hexmask.long 0xC 0.--31. 1. "CPUDSP1MBDATA,DSP 1 CPU Mailbox data"
|
|
line.long 0x10 "DSP0DSP1MBDATA,DSP0 to DSP 1 Mailbox Data"
|
|
hexmask.long 0x10 0.--31. 1. "DSP0DSP1MBDATA,DSP0 to DSP 1 Mailbox data"
|
|
line.long 0x14 "DSP1DSP1MBDATA,DSP1 to DSP 1 Mailbox Data"
|
|
hexmask.long 0x14 0.--31. 1. "DSP1DSP1MBDATA,DSP1 to DSP 1 Mailbox data"
|
|
group.long 0x100++0x1B
|
|
line.long 0x0 "DSP0CONTROL,DSP 0 control settings"
|
|
hexmask.long.tbyte 0x0 8.--30. 1. "DSP0IDMAXTRIGSRC,DSP 0 IDMA Cross Trigger Source. All enabled sources are ANDed to generate a trigger enable. \n Bit30-12:IRQ18-0 Bit11: IDMATRIGPULSE Bit10: DSP Timer1 Bit9: DSP Timer0 Bit8: alternate DSP iDMA trigger out"
|
|
bitfld.long 0x0 4.--5. "DSP0IDMATRIG,DSP 0 IDMA Trigger Control" "0: Trigger is disabled. This will pause the iDMA..,1: Trigger is always enabled. With this set any..,2: Trigger is disabled until a trigger pulse (PULSE..,3: Trigger is disabled until a cross trigger pulse.."
|
|
newline
|
|
bitfld.long 0x0 3. "DSP0RUNSTALL,DSP 0 RunStall. When asserted DSP 0 will stall until bit is cleared." "0,1"
|
|
bitfld.long 0x0 2. "DSP0DRESET,DSP0 DReset. This is the reset used for debug functionality like OCD/TRAX etc." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DSP0BRESET,DSP0 BReset. This is the reset used for Xtensa core. S/w must clear this reset to use Dsp." "0,1"
|
|
bitfld.long 0x0 0. "DSP0STATVECSEL,DSP 0 StatVectorSel" "0,1"
|
|
line.long 0x4 "DSP0RESETVEC,DSP 0 Reset Vector"
|
|
hexmask.long 0x4 0.--31. 1. "DSP0RESETVEC,DSP 0 Reset Vector Address."
|
|
line.long 0x8 "DSP0IRQMASK,DSP 0 IRQ Mask"
|
|
hexmask.long.tbyte 0x8 0.--22. 1. "DSP0IRQMASK,DSP 0 IRQ Mask"
|
|
line.long 0xC "DSP0WAKEMASK,DSP 0 IRQ Wake Mask"
|
|
hexmask.long.tbyte 0xC 0.--22. 1. "DSP0WAKEMASK,DSP 0 IRQ Wake Mask"
|
|
line.long 0x10 "DSP0RAWIRQSTAT31to0,DSP 0 Raw IRQ31-0 Status"
|
|
hexmask.long 0x10 0.--31. 1. "DSP0RAWIRQSTAT31to0,DSP 0 Raw IRQ31-0 Status"
|
|
line.long 0x14 "DSP0RAWIRQSTAT63to32,DSP 0 Raw IRQ63-32 Status"
|
|
hexmask.long 0x14 0.--31. 1. "DSP0RAWIRQSTAT63to32,DSP 0 Raw IRQ63-32 Status"
|
|
line.long 0x18 "DSP0RAWIRQSTAT95to64,DSP 0 Raw IRQ95-64 Status"
|
|
hexmask.long 0x18 0.--31. 1. "DSP0RAWIRQSTAT95to64,DSP 0 Raw IRQ95-64 Status"
|
|
group.long 0x120++0x13
|
|
line.long 0x0 "DSP0L2LVLINT,DSP 0 L2 Level Interrupt Mux"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "DSP0L2LVLINT,DSP 0 L2 Level Interrupt Mux"
|
|
line.long 0x4 "DSP0L3LVLINT,DSP 0 L3 Level Interrupt Mux"
|
|
hexmask.long.tbyte 0x4 0.--18. 1. "DSP0L3LVLINT,DSP 0 L3 Level Interrupt Mux"
|
|
line.long 0x8 "DSP0L4LVLINT,DSP 0 L4 Level Interrupt Mux"
|
|
hexmask.long.tbyte 0x8 0.--18. 1. "DSP0L4LVLINT,DSP 0 L4 Level Interrupt Mux"
|
|
line.long 0xC "DSP0L5LVLINT,DSP 0 L5 Level Interrupt Mux"
|
|
hexmask.long.tbyte 0xC 0.--18. 1. "DSP0L5LVLINT,DSP 0 L5 Level Interrupt Mux"
|
|
line.long 0x10 "DSP0IDMATRIGCTL,DSP 0 IDMA Trigger Control and Status"
|
|
bitfld.long 0x10 4. "DSP0IDMATRIGPULSE,DSP 0 iDMA Trigger Pulse - When written a '1' this will cause a single step enable (valid only when IDMATRIG is set to SSTEP)" "0,1"
|
|
bitfld.long 0x10 0. "DSP0IDMATRIGSTAT,DSP 0 iDMA Trigger Status" "0,1"
|
|
group.long 0x140++0xB
|
|
line.long 0x0 "DSP0INTORMASK31TO0A,DSP0 Interrupt OR Mask A for IRQ31-0"
|
|
hexmask.long 0x0 0.--31. 1. "DSP0INTMCUIOORMASKA,DSP0 MCU IO Interrupt OR Mask A"
|
|
line.long 0x4 "DSP0INTORMASK63TO32A,DSP0 Interrupt OR Mask A for IRQ63-32"
|
|
hexmask.long.byte 0x4 24.--29. 1. "DSP0GPIOORMASKA,DSP0 GPIO Interrupt OR Mask A"
|
|
hexmask.long.byte 0x4 16.--19. 1. "DSP0PDMORMASKA,DSP0 PDM Interrupt OR Mask A"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "DSP0I2SORMASKA,DSP0 I2S Interrupt OR Mask A"
|
|
hexmask.long.word 0x4 0.--9. 1. "DSP0TMRORMASKA,DSP0 Timer Interrupt OR Mask A"
|
|
line.long 0x8 "DSP0INTORMASK95TO64A,DSP0 Interrupt OR Mask A for IRQ95-64"
|
|
hexmask.long 0x8 0.--31. 1. "DSP0MBINTORMASKA,DSP0 Mailbox Interrupt OR Mask A"
|
|
group.long 0x150++0xB
|
|
line.long 0x0 "DSP0INTORMASK31to0B,DSP0 Interrupt OR Mask B for IRQ31-0"
|
|
hexmask.long 0x0 0.--31. 1. "DSP0INTMCUIOORMASKB,DSP0 MCU IO Interrupt OR Mask B"
|
|
line.long 0x4 "DSP0INTORMASK63TO32B,DSP0 Interrupt OR Mask A for IRQ63-32"
|
|
hexmask.long.byte 0x4 24.--29. 1. "DSP0GPIOORMASKB,DSP0 GPIO Interrupt OR Mask B"
|
|
hexmask.long.byte 0x4 16.--19. 1. "DSP0PDMORMASKB,DSP0 PDM Interrupt OR Mask B"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "DSP0I2SORMASKB,DSP0 I2S Interrupt OR Mask B"
|
|
hexmask.long.word 0x4 0.--9. 1. "DSP0TMRORMASKB,DSP0 Timer Interrupt OR Mask B"
|
|
line.long 0x8 "DSP0INTORMASK95TO64B,DSP0 Interrupt OR Mask B for IRQ95-64"
|
|
hexmask.long 0x8 0.--31. 1. "DSP0MBINTORMASKB,DSP0 Mailbox Interrupt OR Mask B"
|
|
group.long 0x160++0xB
|
|
line.long 0x0 "DSP0INTENIRQ31TO0,DSP0 INT Enable for IRQ31-0"
|
|
hexmask.long 0x0 0.--31. 1. "DSP0INTENIRQ31TO0,DSP0 INT Enable for IRQ31-0"
|
|
line.long 0x4 "DSP0INTENIRQ63TO32,DSP0 INT Enable for IRQ63-32"
|
|
hexmask.long 0x4 0.--31. 1. "DSP0INTENIRQ63TO32,DSP0 INT Enable for IRQ63-32"
|
|
line.long 0x8 "DSP0INTENIRQ95TO64,DSP0 INT Enable for IRQ95-64"
|
|
hexmask.long 0x8 0.--31. 1. "DSP0INTENIRQ95TO64,DSP0 INT Enable for IRQ95-64"
|
|
group.long 0x200++0x1B
|
|
line.long 0x0 "DSP1CONTROL,DSP 1 control settings"
|
|
hexmask.long.tbyte 0x0 8.--30. 1. "DSP1IDMAXTRIGSRC,DSP 1 IDMA Cross Trigger Source. All enabled sources are ANDed to generate a trigger enable. \n Bit30-12:IRQ18-0 Bit11: IDMATRIGPULSE Bit10: DSP Timer1 Bit9: DSP Timer0 Bit8: alternate DSP iDMA trigger out"
|
|
bitfld.long 0x0 4.--5. "DSP1IDMATRIG,DSP 1 IDMA Trigger Control" "0: Trigger is disabled. This will pause the iDMA..,1: Trigger is always enabled. With this set any..,2: Trigger is disabled until a trigger pulse (PULSE..,3: Trigger is disabled until a cross trigger pulse.."
|
|
newline
|
|
bitfld.long 0x0 3. "DSP1RUNSTALL,DSP 1 RunStall. When asserted DSP 1 will stall until bit is cleared." "0,1"
|
|
bitfld.long 0x0 2. "DSP1DRESET,DSP1 DReset. This is the reset used for debug functionality like OCD/TRAX etc." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DSP1BRESET,DSP1 BReset. This is the reset used for Xtensa core. S/w must clear this reset to use Dsp." "0,1"
|
|
bitfld.long 0x0 0. "DSP1STATVECSEL,DSP 1 StatVectorSel" "0,1"
|
|
line.long 0x4 "DSP1RESETVEC,DSP 1 Reset Vector"
|
|
hexmask.long 0x4 0.--31. 1. "DSP1RESETVEC,DSP 1 Reset Vector Address."
|
|
line.long 0x8 "DSP1IRQMASK,DSP 1 IRQ Mask"
|
|
hexmask.long.tbyte 0x8 0.--22. 1. "DSP1IRQMASK,DSP 1 IRQ Mask"
|
|
line.long 0xC "DSP1WAKEMASK,DSP 1 IRQ Wake Mask"
|
|
hexmask.long.tbyte 0xC 0.--22. 1. "DSP1WAKEMASK,DSP 1 IRQ Wake Mask"
|
|
line.long 0x10 "DSP1RAWIRQSTAT31to0,DSP 1 Raw IRQ31-0 Status"
|
|
hexmask.long 0x10 0.--31. 1. "DSP1RAWIRQSTAT31to0,DSP 1 Raw IRQ31-0 Status"
|
|
line.long 0x14 "DSP1RAWIRQSTAT63to32,DSP 1 Raw IRQ63-32 Status"
|
|
hexmask.long 0x14 0.--31. 1. "DSP1RAWIRQSTAT63to32,DSP 1 Raw IRQ63-32 Status"
|
|
line.long 0x18 "DSP1RAWIRQSTAT95to64,DSP 1 Raw IRQ95-64 Status"
|
|
hexmask.long 0x18 0.--31. 1. "DSP1RAWIRQSTAT95to64,DSP 1 Raw IRQ95-64 Status"
|
|
group.long 0x220++0x13
|
|
line.long 0x0 "DSP1L2LVLINT,DSP 1 L2 Level Interrupt Mux"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "DSP1L2LVLINT,DSP 1 L2 Level Interrupt Mux"
|
|
line.long 0x4 "DSP1L3LVLINT,DSP 1 L3 Level Interrupt Mux"
|
|
hexmask.long.tbyte 0x4 0.--18. 1. "DSP1L3LVLINT,DSP 1 L3 Level Interrupt Mux"
|
|
line.long 0x8 "DSP1L4LVLINT,DSP 1 L4 Level Interrupt Mux"
|
|
hexmask.long.tbyte 0x8 0.--18. 1. "DSP1L4LVLINT,DSP 1 L4 Level Interrupt Mux"
|
|
line.long 0xC "DSP1L5LVLINT,DSP 1 L5 Level Interrupt Mux"
|
|
hexmask.long.tbyte 0xC 0.--18. 1. "DSP1L5LVLINT,DSP 1 L5 Level Interrupt Mux"
|
|
line.long 0x10 "DSP1IDMATRIGCTL,DSP 1 IDMA Trigger Control and Status"
|
|
bitfld.long 0x10 4. "DSP1IDMATRIGPULSE,DSP 1 iDMA Trigger Pulse - When written a '1' this will cause a single step enable (valid only when IDMATRIG is set to SSTEP)" "0,1"
|
|
bitfld.long 0x10 0. "DSP1IDMATRIGSTAT,DSP 1 iDMA Trigger Status" "0,1"
|
|
group.long 0x240++0xB
|
|
line.long 0x0 "DSP1INTORMASK31TO0A,DSP1 Interrupt OR Mask A for IRQ31-0"
|
|
hexmask.long 0x0 0.--31. 1. "DSP1INTMCUIOORMASKA,DSP1 MCU IO Interrupt OR Mask A"
|
|
line.long 0x4 "DSP1INTORMASK63TO32A,DSP1 Interrupt OR Mask A for IRQ63-32"
|
|
hexmask.long.byte 0x4 24.--29. 1. "DSP1GPIOORMASKA,DSP1 GPIO Interrupt OR Mask A"
|
|
hexmask.long.byte 0x4 16.--19. 1. "DSP1PDMORMASKA,DSP1 PDM Interrupt OR Mask A"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "DSP1I2SORMASKA,DSP1 I2S Interrupt OR Mask A"
|
|
hexmask.long.word 0x4 0.--9. 1. "DSP1TMRORMASKA,DSP1 Timer Interrupt OR Mask A"
|
|
line.long 0x8 "DSP1INTORMASK95TO64A,DSP1 Interrupt OR Mask A for IRQ95-64"
|
|
hexmask.long 0x8 0.--31. 1. "DSP1MBINTORMASKA,DSP1 Mailbox Interrupt OR Mask A"
|
|
group.long 0x250++0xB
|
|
line.long 0x0 "DSP1INTORMASK31to0B,DSP1 Interrupt OR Mask B for IRQ31-0"
|
|
hexmask.long 0x0 0.--31. 1. "DSP1INTMCUIOORMASKB,DSP1 MCU IO Interrupt OR Mask B"
|
|
line.long 0x4 "DSP1INTORMASK63TO32B,DSP1 Interrupt OR Mask A for IRQ63-32"
|
|
hexmask.long.byte 0x4 24.--29. 1. "DSP1GPIOORMASKB,DSP1 GPIO Interrupt OR Mask B"
|
|
hexmask.long.byte 0x4 16.--19. 1. "DSP1PDMORMASKB,DSP1 PDM Interrupt OR Mask B"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "DSP1I2SORMASKB,DSP1 I2S Interrupt OR Mask B"
|
|
hexmask.long.word 0x4 0.--9. 1. "DSP1TMRORMASKB,DSP1 Timer Interrupt OR Mask B"
|
|
line.long 0x8 "DSP1INTORMASK95TO64B,DSP1 Interrupt OR Mask B for IRQ95-64"
|
|
hexmask.long 0x8 0.--31. 1. "DSP1MBINTORMASKB,DSP1 Mailbox Interrupt OR Mask B"
|
|
group.long 0x260++0xB
|
|
line.long 0x0 "DSP1INTENIRQ31TO0,DSP1 INT Enable for IRQ31-0"
|
|
hexmask.long 0x0 0.--31. 1. "DSP1INTENIRQ31TO0,DSP1 INT Enable for IRQ31-0"
|
|
line.long 0x4 "DSP1INTENIRQ63TO32,DSP1 INT Enable for IRQ63-32"
|
|
hexmask.long 0x4 0.--31. 1. "DSP1INTENIRQ63TO32,DSP1 INT Enable for IRQ63-32"
|
|
line.long 0x8 "DSP1INTENIRQ95TO64,DSP1 INT Enable for IRQ95-64"
|
|
hexmask.long 0x8 0.--31. 1. "DSP1INTENIRQ95TO64,DSP1 INT Enable for IRQ95-64"
|
|
tree.end
|
|
tree "FPIO (Fast PIO Access)"
|
|
base ad:0x48001000
|
|
group.long 0x0++0x6F
|
|
line.long 0x0 "RD0,GPIO Input 0 (31-0)"
|
|
hexmask.long 0x0 0.--31. 1. "RD0,GPIO31-0 Reads pin state - read only. Returns the pad pin state for pins 0-31 if the PINCFG's input enable (INPEN) is active and RDZERO is inactive."
|
|
line.long 0x4 "RD1,GPIO Input 1 (63-32)"
|
|
hexmask.long 0x4 0.--31. 1. "RD1,GPIO63-32 Reads pin state - read only. Returns the pad pin state for pins 0-31 if the PINCFG's input enable (INPEN) is active and RDZERO is inactive."
|
|
line.long 0x8 "RD2,GPIO Input 2 (95-64)"
|
|
hexmask.long 0x8 0.--31. 1. "RD2,GPIO95-64 Reads pin state - read only. Returns the pad pin state for pins 0-31 if the PINCFG's input enable (INPEN) is active and RDZERO is inactive."
|
|
line.long 0xC "RD3,GPIO Input 3 (127-96)"
|
|
hexmask.long 0xC 0.--31. 1. "RD3,GPIO127-96 Reads pin state - read only. Returns the pad pin state for pins 0-31 if the PINCFG's input enable (INPEN) is active and RDZERO is inactive."
|
|
line.long 0x10 "WT0,GPIO Output 0 (31-0)"
|
|
hexmask.long 0x10 0.--31. 1. "WT0,GPIO31-0 Reads or writes pin state. Writes of 1 bits set output pad signal if the GPIO is enabled for output. Reads return status including sets/clears through the WTS and WTC registers."
|
|
line.long 0x14 "WT1,GPIO Output 1 (63-32)"
|
|
hexmask.long 0x14 0.--31. 1. "WT1,GPIO63-32 Reads or writes pin state. Writes of 1 bits set output pad signal if the GPIO is enabled for output. Reads return status including sets/clears through the WTS and WTC registers."
|
|
line.long 0x18 "WT2,GPIO Output 2 (95-64)"
|
|
hexmask.long 0x18 0.--31. 1. "WT2,GPIO95-64 Reads or writes pin state. Writes of 1 bits set output pad signal if the GPIO is enabled for output. Reads return status including sets/clears through the WTS and WTC registers."
|
|
line.long 0x1C "WT3,GPIO Output 3 (127-96)"
|
|
hexmask.long 0x1C 0.--31. 1. "WT3,GPIO127-96 Reads or writes pin state. Writes of 1 bits set output pad signal if the GPIO is enabled for output. Reads return status including sets/clears through the WTS and WTC registers."
|
|
line.long 0x20 "WTS0,GPIO Output Set 0 (31-0)"
|
|
hexmask.long 0x20 0.--31. 1. "WTS0,GPIO31-0 Sets pin state. Writing a 1 to any bit sets the corresponding bit in the WT register if the GPIO is enabled for output. Writing a value of 0 has no effect on the corresponding bit in the WT register. Status reads should be made via the WT.."
|
|
line.long 0x24 "WTS1,GPIO Output Set 1 (63-32)"
|
|
hexmask.long 0x24 0.--31. 1. "WTS1,GPIO63-32 Sets pin state. Writing a 1 to any bit sets the corresponding bit in the WT register if the GPIO is enabled for output. Writing a value of 0 has no effect on the corresponding bit in the WT register. Status reads should be made via the WT.."
|
|
line.long 0x28 "WTS2,GPIO Output Set 2 (95-64)"
|
|
hexmask.long 0x28 0.--31. 1. "WTS2,GPIO95-64 Sets pin state. Writing a 1 to any bit sets the corresponding bit in the WT register if the GPIO is enabled for output. Writing a value of 0 has no effect on the corresponding bit in the WT register. Status reads should be made via the WT.."
|
|
line.long 0x2C "WTS3,GPIO Output Set 3 (127-96)"
|
|
hexmask.long 0x2C 0.--31. 1. "WTS3,GPIO127-96 Sets pin state. Writing a 1 to any bit sets the corresponding bit in the WT register if the GPIO is enabled for output. Writing a value of 0 has no effect on the corresponding bit in the WT register. Status reads should be made via the WT.."
|
|
line.long 0x30 "WTC0,GPIO Output Clear 0 (31-0)"
|
|
hexmask.long 0x30 0.--31. 1. "WTC0,GPIO31-0 Clears pin state. Writing a 1 to any bit clears the corresponding bit in the WT register if the GPIO is enabled for output. Writing a value of 0 has no effect on the corresponding bit in the WT register. Status reads should be made via the.."
|
|
line.long 0x34 "WTC1,GPIO Output Clear 1 (63-32)"
|
|
hexmask.long 0x34 0.--31. 1. "WTC1,GPIO63-32 Clears pin state. Writing a 1 to any bit clears the corresponding bit in the WT register if the GPIO is enabled for output. Writing a value of 0 has no effect on the corresponding bit in the WT register. Status reads should be made via the.."
|
|
line.long 0x38 "WTC2,GPIO Output Clear 2 (95-64)"
|
|
hexmask.long 0x38 0.--31. 1. "WTC2,GPIO95-64 Clears pin state. Writing a 1 to any bit clears the corresponding bit in the WT register if the GPIO is enabled for output. Writing a value of 0 has no effect on the corresponding bit in the WT register. Status reads should be made via the.."
|
|
line.long 0x3C "WTC3,GPIO Output Clear 3 (127-96)"
|
|
hexmask.long 0x3C 0.--31. 1. "WTC3,GPIO127-96 Clears pin state. Writing a 1 to any bit clears the corresponding bit in the WT register if the GPIO is enabled for output. Writing a value of 0 has no effect on the corresponding bit in the WT register. Status reads should be made via.."
|
|
line.long 0x40 "EN0,GPIO Enable 0 (31-0)"
|
|
hexmask.long 0x40 0.--31. 1. "EN0,GPIO31-0 Enables tri-state pin output. Writing a 1 to any bit enables and writing a 0 to any bit disables the output for the corresponding GPIO. Reads return output enable/disable status of GPIO."
|
|
line.long 0x44 "EN1,GPIO Enable 1 (63-32)"
|
|
hexmask.long 0x44 0.--31. 1. "EN1,GPIO63-32 Enables tri-state pin output. Writing a 1 to any bit enables and writing a 0 to any bit disables the output for the corresponding GPIO. Reads return output enable/disable status of GPIO."
|
|
line.long 0x48 "EN2,GPIO Enable 2 (95-64)"
|
|
hexmask.long 0x48 0.--31. 1. "EN2,GPIO95-64 Enables tri-state pin output. Writing a 1 to any bit enables and writing a 0 to any bit disables the output for the corresponding GPIO. Reads return output enable/disable status of GPIO."
|
|
line.long 0x4C "EN3,GPIO Enable 3 (127-96)"
|
|
hexmask.long 0x4C 0.--31. 1. "EN3,GPIO127-96 Enables tri-state pin output. Writing a 1 to any bit enables and writing a 0 to any bit disables the output for the corresponding GPIO. Reads return output enable/disable status of GPIO."
|
|
line.long 0x50 "ENS0,GPIO Enable Set 0 (31-0)"
|
|
hexmask.long 0x50 0.--31. 1. "ENS0,GPIO31-0 Sets pin tri-state output enables. Writing a 1 to any bit sets the corresponding bit in the EN register. Writing a value of 0 has no effect on the corresponding bit in the EN register. Status reads should be made to the EN Register."
|
|
line.long 0x54 "ENS1,GPIO Enable Set 1 (63-32)"
|
|
hexmask.long 0x54 0.--31. 1. "ENS1,GPIO63-32 Sets pin tri-state output enables. Writing a 1 to any bit sets the corresponding bit in the EN register. Writing a value of 0 has no effect on the corresponding bit in the EN register. Status reads should be made to the EN Register."
|
|
line.long 0x58 "ENS2,GPIO Enable Set 2 (95-64)"
|
|
hexmask.long 0x58 0.--31. 1. "ENS2,GPIO95-64 Sets pin tri-state output enables. Writing a 1 to any bit sets the corresponding bit in the EN register. Writing a value of 0 has no effect on the corresponding bit in the EN register. Status reads should be made to the EN Register."
|
|
line.long 0x5C "ENS3,GPIO Enable Set 3 (127-96)"
|
|
hexmask.long 0x5C 0.--31. 1. "ENS3,GPIO127-96 Sets pin tri-state output enables. Writing a 1 to any bit sets the corresponding bit in the EN register. Writing a value of 0 has no effect on the corresponding bit in the EN register. Status reads should be made to the EN Register."
|
|
line.long 0x60 "ENC0,GPIO Enable Clear 0 (31-0)"
|
|
hexmask.long 0x60 0.--31. 1. "ENC0,GPIO31-0 Clears pin tri-state output enables. Writing a 1 to any bit clears the corresponding bit in the EN register. Writing a value of 0 has no effect on the corresponding bit in the EN register. Status reads should be made to the EN Register."
|
|
line.long 0x64 "ENC1,GPIO Enable Clear 1 (63-32)"
|
|
hexmask.long 0x64 0.--31. 1. "ENC1,GPIO63-32 Clears pin tri-state output enables. Writing a 1 to any bit clears the corresponding bit in the EN register. Writing a value of 0 has no effect on the corresponding bit in the EN register. Status reads should be made to the EN Register."
|
|
line.long 0x68 "ENC2,GPIO Enable Clear 2 (95-64)"
|
|
hexmask.long 0x68 0.--31. 1. "ENC2,GPIO95-64 Clears pin tri-state output enables. Writing a 1 to any bit clears the corresponding bit in the EN register. Writing a value of 0 has no effect on the corresponding bit in the EN register. Status reads should be made to the EN Register."
|
|
line.long 0x6C "ENC3,GPIO Enable Clear 3 (127-96)"
|
|
hexmask.long 0x6C 0.--31. 1. "ENC3,GPIO127-96 Clears pin tri-state output enables. Writing a 1 to any bit clears the corresponding bit in the EN register. Writing a value of 0 has no effect on the corresponding bit in the EN register. Status reads should be made to the EN Register."
|
|
tree.end
|
|
tree "GPIO (General Purpose I/O)"
|
|
base ad:0x40010000
|
|
group.long 0x0++0x2BB
|
|
line.long 0x0 "PINCFG0,Controls the operation of GPIO pin 0."
|
|
bitfld.long 0x0 27. "FOEN0,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x0 26. "FIEN0,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "NCEPOL0,Polarity select for NCE for GPIO 0" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x0 16.--21. 1. "NCESRC0,IOMSTR/MSPI N Chip Select 0 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x0 13.--15. "PULLCFG0,Pullup/Pulldown configuration for GPIO 0" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x0 12. "SR0,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "DS0,Drive strength selection for GPIO 0" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0x0 8.--9. "OUTCFG0,Pin IO mode selection for GPIO pin 0" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x0 6.--7. "IRPTEN0,Interrupt enable for GPIO 0" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x0 5. "RDZERO0,Return 0 for read data on GPIO 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "INPEN0,Input enable for GPIO 0" "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FNCSEL0,Function select for GPIO pin 0"
|
|
line.long 0x4 "PINCFG1,Controls the operation of GPIO pin 1."
|
|
bitfld.long 0x4 27. "FOEN1,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x4 26. "FIEN1,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "NCEPOL1,Polarity select for NCE for GPIO 1" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x4 16.--21. 1. "NCESRC1,IOMSTR/MSPI N Chip Select 1 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x4 13.--15. "PULLCFG1,Pullup/Pulldown configuration for GPIO 1" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x4 12. "SR1,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10.--11. "DS1,Drive strength selection for GPIO 1" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0x4 8.--9. "OUTCFG1,Pin IO mode selection for GPIO pin 1" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x4 6.--7. "IRPTEN1,Interrupt enable for GPIO 1" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x4 5. "RDZERO1,Return 0 for read data on GPIO 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "INPEN1,Input enable for GPIO 1" "0,1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FNCSEL1,Function select for GPIO pin 1"
|
|
line.long 0x8 "PINCFG2,Controls the operation of GPIO pin 2."
|
|
bitfld.long 0x8 27. "FOEN2,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x8 26. "FIEN2,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x8 22. "NCEPOL2,Polarity select for NCE for GPIO 2" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x8 16.--21. 1. "NCESRC2,IOMSTR/MSPI N Chip Select 2 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x8 13.--15. "PULLCFG2,Pullup/Pulldown configuration for GPIO 2" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x8 12. "SR2,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "DS2,Drive strength selection for GPIO 2" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0x8 8.--9. "OUTCFG2,Pin IO mode selection for GPIO pin 2" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x8 6.--7. "IRPTEN2,Interrupt enable for GPIO 2" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x8 5. "RDZERO2,Return 0 for read data on GPIO 2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "INPEN2,Input enable for GPIO 2" "0,1"
|
|
hexmask.long.byte 0x8 0.--3. 1. "FNCSEL2,Function select for GPIO pin 2"
|
|
line.long 0xC "PINCFG3,Controls the operation of GPIO pin 3."
|
|
bitfld.long 0xC 27. "FOEN3,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0xC 26. "FIEN3,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0xC 22. "NCEPOL3,Polarity select for NCE for GPIO 3" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0xC 16.--21. 1. "NCESRC3,IOMSTR/MSPI N Chip Select 3 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0xC 13.--15. "PULLCFG3,Pullup/Pulldown configuration for GPIO 3" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0xC 12. "SR3,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "DS3,Drive strength selection for GPIO 3" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0xC 8.--9. "OUTCFG3,Pin IO mode selection for GPIO pin 3" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0xC 6.--7. "IRPTEN3,Interrupt enable for GPIO 3" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0xC 5. "RDZERO3,Return 0 for read data on GPIO 3" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "INPEN3,Input enable for GPIO 3" "0,1"
|
|
hexmask.long.byte 0xC 0.--3. 1. "FNCSEL3,Function select for GPIO pin 3"
|
|
line.long 0x10 "PINCFG4,Controls the operation of GPIO pin 4."
|
|
bitfld.long 0x10 27. "FOEN4,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x10 26. "FIEN4,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x10 22. "NCEPOL4,Polarity select for NCE for GPIO 4" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x10 16.--21. 1. "NCESRC4,IOMSTR/MSPI N Chip Select 4 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x10 13.--15. "PULLCFG4,Pullup/Pulldown configuration for GPIO 4" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x10 12. "SR4,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x10 10.--11. "DS4,Drive strength selection for GPIO 4" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0x10 8.--9. "OUTCFG4,Pin IO mode selection for GPIO pin 4" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x10 6.--7. "IRPTEN4,Interrupt enable for GPIO 4" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x10 5. "RDZERO4,Return 0 for read data on GPIO 4" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "INPEN4,Input enable for GPIO 4" "0,1"
|
|
hexmask.long.byte 0x10 0.--3. 1. "FNCSEL4,Function select for GPIO pin 4"
|
|
line.long 0x14 "PINCFG5,Controls the operation of GPIO pin 5."
|
|
bitfld.long 0x14 27. "FOEN5,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x14 26. "FIEN5,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x14 22. "NCEPOL5,Polarity select for NCE for GPIO 5" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x14 16.--21. 1. "NCESRC5,IOMSTR/MSPI N Chip Select 5 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x14 13.--15. "PULLCFG5,Pullup/Pulldown configuration for GPIO 5" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x14 12. "SR5,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x14 10.--11. "DS5,Drive strength selection for GPIO 5" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x14 8.--9. "OUTCFG5,Pin IO mode selection for GPIO pin 5" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x14 6.--7. "IRPTEN5,Interrupt enable for GPIO 5" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x14 5. "RDZERO5,Return 0 for read data on GPIO 5" "0,1"
|
|
newline
|
|
bitfld.long 0x14 4. "INPEN5,Input enable for GPIO 5" "0,1"
|
|
hexmask.long.byte 0x14 0.--3. 1. "FNCSEL5,Function select for GPIO pin 5"
|
|
line.long 0x18 "PINCFG6,Controls the operation of GPIO pin 6."
|
|
bitfld.long 0x18 27. "FOEN6,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x18 26. "FIEN6,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x18 22. "NCEPOL6,Polarity select for NCE for GPIO 6" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x18 16.--21. 1. "NCESRC6,IOMSTR/MSPI N Chip Select 6 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x18 13.--15. "PULLCFG6,Pullup/Pulldown configuration for GPIO 6" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x18 12. "SR6,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x18 10.--11. "DS6,Drive strength selection for GPIO 6" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x18 8.--9. "OUTCFG6,Pin IO mode selection for GPIO pin 6" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x18 6.--7. "IRPTEN6,Interrupt enable for GPIO 6" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x18 5. "RDZERO6,Return 0 for read data on GPIO 6" "0,1"
|
|
newline
|
|
bitfld.long 0x18 4. "INPEN6,Input enable for GPIO 6" "0,1"
|
|
hexmask.long.byte 0x18 0.--3. 1. "FNCSEL6,Function select for GPIO pin 6"
|
|
line.long 0x1C "PINCFG7,Controls the operation of GPIO pin 7."
|
|
bitfld.long 0x1C 27. "FOEN7,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x1C 26. "FIEN7,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 22. "NCEPOL7,Polarity select for NCE for GPIO 7" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x1C 16.--21. 1. "NCESRC7,IOMSTR/MSPI N Chip Select 7 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x1C 13.--15. "PULLCFG7,Pullup/Pulldown configuration for GPIO 7" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x1C 12. "SR7,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 10.--11. "DS7,Drive strength selection for GPIO 7" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x1C 8.--9. "OUTCFG7,Pin IO mode selection for GPIO pin 7" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x1C 6.--7. "IRPTEN7,Interrupt enable for GPIO 7" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x1C 5. "RDZERO7,Return 0 for read data on GPIO 7" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 4. "INPEN7,Input enable for GPIO 7" "0,1"
|
|
hexmask.long.byte 0x1C 0.--3. 1. "FNCSEL7,Function select for GPIO pin 7"
|
|
line.long 0x20 "PINCFG8,Controls the operation of GPIO pin 8."
|
|
bitfld.long 0x20 27. "FOEN8,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x20 26. "FIEN8,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x20 22. "NCEPOL8,Polarity select for NCE for GPIO 8" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x20 16.--21. 1. "NCESRC8,IOMSTR/MSPI N Chip Select 8 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x20 13.--15. "PULLCFG8,Pullup/Pulldown configuration for GPIO 8" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x20 12. "SR8,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x20 10.--11. "DS8,Drive strength selection for GPIO 8" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x20 8.--9. "OUTCFG8,Pin IO mode selection for GPIO pin 8" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x20 6.--7. "IRPTEN8,Interrupt enable for GPIO 8" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x20 5. "RDZERO8,Return 0 for read data on GPIO 8" "0,1"
|
|
newline
|
|
bitfld.long 0x20 4. "INPEN8,Input enable for GPIO 8" "0,1"
|
|
hexmask.long.byte 0x20 0.--3. 1. "FNCSEL8,Function select for GPIO pin 8"
|
|
line.long 0x24 "PINCFG9,Controls the operation of GPIO pin 9."
|
|
bitfld.long 0x24 27. "FOEN9,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x24 26. "FIEN9,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x24 22. "NCEPOL9,Polarity select for NCE for GPIO 9" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x24 16.--21. 1. "NCESRC9,IOMSTR/MSPI N Chip Select 9 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x24 13.--15. "PULLCFG9,Pullup/Pulldown configuration for GPIO 9" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x24 12. "SR9,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x24 10.--11. "DS9,Drive strength selection for GPIO 9" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x24 8.--9. "OUTCFG9,Pin IO mode selection for GPIO pin 9" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x24 6.--7. "IRPTEN9,Interrupt enable for GPIO 9" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x24 5. "RDZERO9,Return 0 for read data on GPIO 9" "0,1"
|
|
newline
|
|
bitfld.long 0x24 4. "INPEN9,Input enable for GPIO 9" "0,1"
|
|
hexmask.long.byte 0x24 0.--3. 1. "FNCSEL9,Function select for GPIO pin 9"
|
|
line.long 0x28 "PINCFG10,Controls the operation of GPIO pin 10."
|
|
bitfld.long 0x28 27. "FOEN10,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x28 26. "FIEN10,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x28 22. "NCEPOL10,Polarity select for NCE for GPIO 10" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x28 16.--21. 1. "NCESRC10,IOMSTR/MSPI N Chip Select 10 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x28 13.--15. "PULLCFG10,Pullup/Pulldown configuration for GPIO 10" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x28 12. "SR10,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x28 10.--11. "DS10,Drive strength selection for GPIO 10" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x28 8.--9. "OUTCFG10,Pin IO mode selection for GPIO pin 10" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x28 6.--7. "IRPTEN10,Interrupt enable for GPIO 10" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x28 5. "RDZERO10,Return 0 for read data on GPIO 10" "0,1"
|
|
newline
|
|
bitfld.long 0x28 4. "INPEN10,Input enable for GPIO 10" "0,1"
|
|
hexmask.long.byte 0x28 0.--3. 1. "FNCSEL10,Function select for GPIO pin 10"
|
|
line.long 0x2C "PINCFG11,Controls the operation of GPIO pin 11."
|
|
bitfld.long 0x2C 27. "FOEN11,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x2C 26. "FIEN11,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 22. "NCEPOL11,Polarity select for NCE for GPIO 11" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x2C 16.--21. 1. "NCESRC11,IOMSTR/MSPI N Chip Select 11 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x2C 13.--15. "PULLCFG11,Pullup/Pulldown configuration for GPIO 11" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x2C 12. "SR11,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 10.--11. "DS11,Drive strength selection for GPIO 11" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0x2C 8.--9. "OUTCFG11,Pin IO mode selection for GPIO pin 11" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x2C 6.--7. "IRPTEN11,Interrupt enable for GPIO 11" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x2C 5. "RDZERO11,Return 0 for read data on GPIO 11" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 4. "INPEN11,Input enable for GPIO 11" "0,1"
|
|
hexmask.long.byte 0x2C 0.--3. 1. "FNCSEL11,Function select for GPIO pin 11"
|
|
line.long 0x30 "PINCFG12,Controls the operation of GPIO pin 12."
|
|
bitfld.long 0x30 27. "FOEN12,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x30 26. "FIEN12,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x30 22. "NCEPOL12,Polarity select for NCE for GPIO 12" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x30 16.--21. 1. "NCESRC12,IOMSTR/MSPI N Chip Select 12 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x30 13.--15. "PULLCFG12,Pullup/Pulldown configuration for GPIO 12" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x30 12. "SR12,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x30 10.--11. "DS12,Drive strength selection for GPIO 12" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0x30 8.--9. "OUTCFG12,Pin IO mode selection for GPIO pin 12" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x30 6.--7. "IRPTEN12,Interrupt enable for GPIO 12" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x30 5. "RDZERO12,Return 0 for read data on GPIO 12" "0,1"
|
|
newline
|
|
bitfld.long 0x30 4. "INPEN12,Input enable for GPIO 12" "0,1"
|
|
hexmask.long.byte 0x30 0.--3. 1. "FNCSEL12,Function select for GPIO pin 12"
|
|
line.long 0x34 "PINCFG13,Controls the operation of GPIO pin 13."
|
|
bitfld.long 0x34 27. "FOEN13,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x34 26. "FIEN13,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x34 22. "NCEPOL13,Polarity select for NCE for GPIO 13" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x34 16.--21. 1. "NCESRC13,IOMSTR/MSPI N Chip Select 13 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x34 13.--15. "PULLCFG13,Pullup/Pulldown configuration for GPIO 13" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x34 12. "SR13,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x34 10.--11. "DS13,Drive strength selection for GPIO 13" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0x34 8.--9. "OUTCFG13,Pin IO mode selection for GPIO pin 13" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x34 6.--7. "IRPTEN13,Interrupt enable for GPIO 13" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x34 5. "RDZERO13,Return 0 for read data on GPIO 13" "0,1"
|
|
newline
|
|
bitfld.long 0x34 4. "INPEN13,Input enable for GPIO 13" "0,1"
|
|
hexmask.long.byte 0x34 0.--3. 1. "FNCSEL13,Function select for GPIO pin 13"
|
|
line.long 0x38 "PINCFG14,Controls the operation of GPIO pin 14."
|
|
bitfld.long 0x38 27. "FOEN14,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x38 26. "FIEN14,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x38 22. "NCEPOL14,Polarity select for NCE for GPIO 14" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x38 16.--21. 1. "NCESRC14,IOMSTR/MSPI N Chip Select 14 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x38 13.--15. "PULLCFG14,Pullup/Pulldown configuration for GPIO 14" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x38 12. "SR14,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x38 10.--11. "DS14,Drive strength selection for GPIO 14" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0x38 8.--9. "OUTCFG14,Pin IO mode selection for GPIO pin 14" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x38 6.--7. "IRPTEN14,Interrupt enable for GPIO 14" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x38 5. "RDZERO14,Return 0 for read data on GPIO 14" "0,1"
|
|
newline
|
|
bitfld.long 0x38 4. "INPEN14,Input enable for GPIO 14" "0,1"
|
|
hexmask.long.byte 0x38 0.--3. 1. "FNCSEL14,Function select for GPIO pin 14"
|
|
line.long 0x3C "PINCFG15,Controls the operation of GPIO pin 15."
|
|
bitfld.long 0x3C 27. "FOEN15,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x3C 26. "FIEN15,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x3C 22. "NCEPOL15,Polarity select for NCE for GPIO 15" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x3C 16.--21. 1. "NCESRC15,IOMSTR/MSPI N Chip Select 15 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x3C 13.--15. "PULLCFG15,Pullup/Pulldown configuration for GPIO 15" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x3C 12. "SR15,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x3C 10.--11. "DS15,Drive strength selection for GPIO 15" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0x3C 8.--9. "OUTCFG15,Pin IO mode selection for GPIO pin 15" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x3C 6.--7. "IRPTEN15,Interrupt enable for GPIO 15" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x3C 5. "RDZERO15,Return 0 for read data on GPIO 15" "0,1"
|
|
newline
|
|
bitfld.long 0x3C 4. "INPEN15,Input enable for GPIO 15" "0,1"
|
|
hexmask.long.byte 0x3C 0.--3. 1. "FNCSEL15,Function select for GPIO pin 15"
|
|
line.long 0x40 "PINCFG16,Controls the operation of GPIO pin 16."
|
|
bitfld.long 0x40 27. "FOEN16,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x40 26. "FIEN16,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x40 22. "NCEPOL16,Polarity select for NCE for GPIO 16" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x40 16.--21. 1. "NCESRC16,IOMSTR/MSPI N Chip Select 16 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x40 13.--15. "PULLCFG16,Pullup/Pulldown configuration for GPIO 16" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x40 12. "SR16,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x40 10.--11. "DS16,Drive strength selection for GPIO 16" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0x40 8.--9. "OUTCFG16,Pin IO mode selection for GPIO pin 16" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x40 6.--7. "IRPTEN16,Interrupt enable for GPIO 16" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x40 5. "RDZERO16,Return 0 for read data on GPIO 16" "0,1"
|
|
newline
|
|
bitfld.long 0x40 4. "INPEN16,Input enable for GPIO 16" "0,1"
|
|
hexmask.long.byte 0x40 0.--3. 1. "FNCSEL16,Function select for GPIO pin 16"
|
|
line.long 0x44 "PINCFG17,Controls the operation of GPIO pin 17."
|
|
bitfld.long 0x44 27. "FOEN17,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x44 26. "FIEN17,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x44 22. "NCEPOL17,Polarity select for NCE for GPIO 17" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x44 16.--21. 1. "NCESRC17,IOMSTR/MSPI N Chip Select 17 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x44 13.--15. "PULLCFG17,Pullup/Pulldown configuration for GPIO 17" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x44 12. "SR17,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x44 10.--11. "DS17,Drive strength selection for GPIO 17" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0x44 8.--9. "OUTCFG17,Pin IO mode selection for GPIO pin 17" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x44 6.--7. "IRPTEN17,Interrupt enable for GPIO 17" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x44 5. "RDZERO17,Return 0 for read data on GPIO 17" "0,1"
|
|
newline
|
|
bitfld.long 0x44 4. "INPEN17,Input enable for GPIO 17" "0,1"
|
|
hexmask.long.byte 0x44 0.--3. 1. "FNCSEL17,Function select for GPIO pin 17"
|
|
line.long 0x48 "PINCFG18,Controls the operation of GPIO pin 18."
|
|
bitfld.long 0x48 27. "FOEN18,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x48 26. "FIEN18,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x48 22. "NCEPOL18,Polarity select for NCE for GPIO 18" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x48 16.--21. 1. "NCESRC18,IOMSTR/MSPI N Chip Select 18 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x48 13.--15. "PULLCFG18,Pullup/Pulldown configuration for GPIO 18" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x48 12. "SR18,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x48 10.--11. "DS18,Drive strength selection for GPIO 18" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0x48 8.--9. "OUTCFG18,Pin IO mode selection for GPIO pin 18" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x48 6.--7. "IRPTEN18,Interrupt enable for GPIO 18" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x48 5. "RDZERO18,Return 0 for read data on GPIO 18" "0,1"
|
|
newline
|
|
bitfld.long 0x48 4. "INPEN18,Input enable for GPIO 18" "0,1"
|
|
hexmask.long.byte 0x48 0.--3. 1. "FNCSEL18,Function select for GPIO pin 18"
|
|
line.long 0x4C "PINCFG19,Controls the operation of GPIO pin 19."
|
|
bitfld.long 0x4C 27. "FOEN19,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x4C 26. "FIEN19,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x4C 22. "NCEPOL19,Polarity select for NCE for GPIO 19" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x4C 16.--21. 1. "NCESRC19,IOMSTR/MSPI N Chip Select 19 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x4C 13.--15. "PULLCFG19,Pullup/Pulldown configuration for GPIO 19" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x4C 12. "SR19,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x4C 10.--11. "DS19,Drive strength selection for GPIO 19" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0x4C 8.--9. "OUTCFG19,Pin IO mode selection for GPIO pin 19" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x4C 6.--7. "IRPTEN19,Interrupt enable for GPIO 19" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x4C 5. "RDZERO19,Return 0 for read data on GPIO 19" "0,1"
|
|
newline
|
|
bitfld.long 0x4C 4. "INPEN19,Input enable for GPIO 19" "0,1"
|
|
hexmask.long.byte 0x4C 0.--3. 1. "FNCSEL19,Function select for GPIO pin 19"
|
|
line.long 0x50 "PINCFG20,Controls the operation of GPIO pin 20."
|
|
bitfld.long 0x50 27. "FOEN20,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x50 26. "FIEN20,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x50 22. "NCEPOL20,Polarity select for NCE for GPIO 20" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x50 16.--21. 1. "NCESRC20,IOMSTR/MSPI N Chip Select 20 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x50 13.--15. "PULLCFG20,Pullup/Pulldown configuration for GPIO 20" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x50 12. "SR20,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x50 10.--11. "DS20,Drive strength selection for GPIO 20" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0x50 8.--9. "OUTCFG20,Pin IO mode selection for GPIO pin 20" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x50 6.--7. "IRPTEN20,Interrupt enable for GPIO 20" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x50 5. "RDZERO20,Return 0 for read data on GPIO 20" "0,1"
|
|
newline
|
|
bitfld.long 0x50 4. "INPEN20,Input enable for GPIO 20" "0,1"
|
|
hexmask.long.byte 0x50 0.--3. 1. "FNCSEL20,Function select for GPIO pin 20"
|
|
line.long 0x54 "PINCFG21,Controls the operation of GPIO pin 21."
|
|
bitfld.long 0x54 27. "FOEN21,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x54 26. "FIEN21,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x54 22. "NCEPOL21,Polarity select for NCE for GPIO 21" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x54 16.--21. 1. "NCESRC21,IOMSTR/MSPI N Chip Select 21 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x54 13.--15. "PULLCFG21,Pullup/Pulldown configuration for GPIO 21" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x54 12. "SR21,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x54 10.--11. "DS21,Drive strength selection for GPIO 21" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0x54 8.--9. "OUTCFG21,Pin IO mode selection for GPIO pin 21" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x54 6.--7. "IRPTEN21,Interrupt enable for GPIO 21" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x54 5. "RDZERO21,Return 0 for read data on GPIO 21" "0,1"
|
|
newline
|
|
bitfld.long 0x54 4. "INPEN21,Input enable for GPIO 21" "0,1"
|
|
hexmask.long.byte 0x54 0.--3. 1. "FNCSEL21,Function select for GPIO pin 21"
|
|
line.long 0x58 "PINCFG22,Controls the operation of GPIO pin 22."
|
|
bitfld.long 0x58 27. "FOEN22,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x58 26. "FIEN22,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x58 22. "NCEPOL22,Polarity select for NCE for GPIO 22" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x58 16.--21. 1. "NCESRC22,IOMSTR/MSPI N Chip Select 22 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x58 13.--15. "PULLCFG22,Pullup/Pulldown configuration for GPIO 22" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x58 12. "SR22,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x58 10.--11. "DS22,Drive strength selection for GPIO 22" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x58 8.--9. "OUTCFG22,Pin IO mode selection for GPIO pin 22" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x58 6.--7. "IRPTEN22,Interrupt enable for GPIO 22" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x58 5. "RDZERO22,Return 0 for read data on GPIO 22" "0,1"
|
|
newline
|
|
bitfld.long 0x58 4. "INPEN22,Input enable for GPIO 22" "0,1"
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x58 0.--3. 1. "FNCSEL22,Function select for GPIO pin 22"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x58 0.--3. 1. "FNCSEL22,Function select for GPIO pin 22"
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x58 0.--3. 1. "FNCSEL22,Function select for GPIO pin 22"
|
|
endif
|
|
line.long 0x5C "PINCFG23,Controls the operation of GPIO pin 23."
|
|
bitfld.long 0x5C 27. "FOEN23,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x5C 26. "FIEN23,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x5C 22. "NCEPOL23,Polarity select for NCE for GPIO 23" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x5C 16.--21. 1. "NCESRC23,IOMSTR/MSPI N Chip Select 23 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x5C 13.--15. "PULLCFG23,Pullup/Pulldown configuration for GPIO 23" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x5C 12. "SR23,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x5C 10.--11. "DS23,Drive strength selection for GPIO 23" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x5C 8.--9. "OUTCFG23,Pin IO mode selection for GPIO pin 23" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x5C 6.--7. "IRPTEN23,Interrupt enable for GPIO 23" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x5C 5. "RDZERO23,Return 0 for read data on GPIO 23" "0,1"
|
|
newline
|
|
bitfld.long 0x5C 4. "INPEN23,Input enable for GPIO 23" "0,1"
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x5C 0.--3. 1. "FNCSEL23,Function select for GPIO pin 23"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x5C 0.--3. 1. "FNCSEL23,Function select for GPIO pin 23"
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x5C 0.--3. 1. "FNCSEL23,Function select for GPIO pin 23"
|
|
endif
|
|
line.long 0x60 "PINCFG24,Controls the operation of GPIO pin 24."
|
|
bitfld.long 0x60 27. "FOEN24,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x60 26. "FIEN24,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x60 22. "NCEPOL24,Polarity select for NCE for GPIO 24" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x60 16.--21. 1. "NCESRC24,IOMSTR/MSPI N Chip Select 24 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x60 13.--15. "PULLCFG24,Pullup/Pulldown configuration for GPIO 24" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x60 12. "SR24,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x60 10.--11. "DS24,Drive strength selection for GPIO 24" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x60 8.--9. "OUTCFG24,Pin IO mode selection for GPIO pin 24" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x60 6.--7. "IRPTEN24,Interrupt enable for GPIO 24" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x60 5. "RDZERO24,Return 0 for read data on GPIO 24" "0,1"
|
|
newline
|
|
bitfld.long 0x60 4. "INPEN24,Input enable for GPIO 24" "0,1"
|
|
hexmask.long.byte 0x60 0.--3. 1. "FNCSEL24,Function select for GPIO pin 24"
|
|
line.long 0x64 "PINCFG25,Controls the operation of GPIO pin 25."
|
|
bitfld.long 0x64 27. "FOEN25,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x64 26. "FIEN25,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x64 22. "NCEPOL25,Polarity select for NCE for GPIO 25" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x64 16.--21. 1. "NCESRC25,IOMSTR/MSPI N Chip Select 25 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x64 13.--15. "PULLCFG25,Pullup/Pulldown configuration for GPIO 25" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x64 12. "SR25,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x64 10.--11. "DS25,Drive strength selection for GPIO 25" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x64 8.--9. "OUTCFG25,Pin IO mode selection for GPIO pin 25" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x64 6.--7. "IRPTEN25,Interrupt enable for GPIO 25" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x64 5. "RDZERO25,Return 0 for read data on GPIO 25" "0,1"
|
|
newline
|
|
bitfld.long 0x64 4. "INPEN25,Input enable for GPIO 25" "0,1"
|
|
hexmask.long.byte 0x64 0.--3. 1. "FNCSEL25,Function select for GPIO pin 25"
|
|
line.long 0x68 "PINCFG26,Controls the operation of GPIO pin 26."
|
|
bitfld.long 0x68 27. "FOEN26,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x68 26. "FIEN26,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x68 22. "NCEPOL26,Polarity select for NCE for GPIO 26" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x68 16.--21. 1. "NCESRC26,IOMSTR/MSPI N Chip Select 26 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x68 13.--15. "PULLCFG26,Pullup/Pulldown configuration for GPIO 26" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x68 12. "SR26,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x68 10.--11. "DS26,Drive strength selection for GPIO 26" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x68 8.--9. "OUTCFG26,Pin IO mode selection for GPIO pin 26" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x68 6.--7. "IRPTEN26,Interrupt enable for GPIO 26" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x68 5. "RDZERO26,Return 0 for read data on GPIO 26" "0,1"
|
|
newline
|
|
bitfld.long 0x68 4. "INPEN26,Input enable for GPIO 26" "0,1"
|
|
hexmask.long.byte 0x68 0.--3. 1. "FNCSEL26,Function select for GPIO pin 26"
|
|
line.long 0x6C "PINCFG27,Controls the operation of GPIO pin 27."
|
|
bitfld.long 0x6C 27. "FOEN27,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x6C 26. "FIEN27,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x6C 22. "NCEPOL27,Polarity select for NCE for GPIO 27" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x6C 16.--21. 1. "NCESRC27,IOMSTR/MSPI N Chip Select 27 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x6C 13.--15. "PULLCFG27,Pullup/Pulldown configuration for GPIO 27" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x6C 12. "SR27,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x6C 10.--11. "DS27,Drive strength selection for GPIO 27" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x6C 8.--9. "OUTCFG27,Pin IO mode selection for GPIO pin 27" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x6C 6.--7. "IRPTEN27,Interrupt enable for GPIO 27" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x6C 5. "RDZERO27,Return 0 for read data on GPIO 27" "0,1"
|
|
newline
|
|
bitfld.long 0x6C 4. "INPEN27,Input enable for GPIO 27" "0,1"
|
|
hexmask.long.byte 0x6C 0.--3. 1. "FNCSEL27,Function select for GPIO pin 27"
|
|
line.long 0x70 "PINCFG28,Controls the operation of GPIO pin 28."
|
|
bitfld.long 0x70 27. "FOEN28,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x70 26. "FIEN28,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x70 22. "NCEPOL28,Polarity select for NCE for GPIO 28" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x70 16.--21. 1. "NCESRC28,IOMSTR/MSPI N Chip Select 28 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x70 13.--15. "PULLCFG28,Pullup/Pulldown configuration for GPIO 28" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x70 12. "SR28,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x70 10.--11. "DS28,Drive strength selection for GPIO 28" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0x70 8.--9. "OUTCFG28,Pin IO mode selection for GPIO pin 28" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x70 6.--7. "IRPTEN28,Interrupt enable for GPIO 28" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x70 5. "RDZERO28,Return 0 for read data on GPIO 28" "0,1"
|
|
newline
|
|
bitfld.long 0x70 4. "INPEN28,Input enable for GPIO 28" "0,1"
|
|
hexmask.long.byte 0x70 0.--3. 1. "FNCSEL28,Function select for GPIO pin 28"
|
|
line.long 0x74 "PINCFG29,Controls the operation of GPIO pin 29."
|
|
bitfld.long 0x74 27. "FOEN29,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x74 26. "FIEN29,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x74 25. "VSSPWRSWEN29,VSS power switch enable. Enable VSS power switch when driving pad signal to 0 for GPIO 29" "0: Power switch is disabled,1: Power switch is enabled"
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
bitfld.long 0x74 25. "VSSPWRSWEN29,VSS power switch enable. Enable VSS power switch when driving pad signal to 0 for GPIO 29" "0: Power switch is disabled,1: Power switch is enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x74 22. "NCEPOL29,Polarity select for NCE for GPIO 29" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x74 16.--21. 1. "NCESRC29,IOMSTR/MSPI N Chip Select 29 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x74 13.--15. "PULLCFG29,Pullup/Pulldown configuration for GPIO 29" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x74 12. "SR29,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x74 10.--11. "DS29,Drive strength selection for GPIO 29" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0x74 8.--9. "OUTCFG29,Pin IO mode selection for GPIO pin 29" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x74 6.--7. "IRPTEN29,Interrupt enable for GPIO 29" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x74 5. "RDZERO29,Return 0 for read data on GPIO 29" "0,1"
|
|
newline
|
|
bitfld.long 0x74 4. "INPEN29,Input enable for GPIO 29" "0,1"
|
|
hexmask.long.byte 0x74 0.--3. 1. "FNCSEL29,Function select for GPIO pin 29"
|
|
line.long 0x78 "PINCFG30,Controls the operation of GPIO pin 30."
|
|
bitfld.long 0x78 27. "FOEN30,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x78 26. "FIEN30,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x78 25. "VDDPWRSWEN30,VDD power switch enable. Enable VDD power switch when driving pad signal to 1 for GPIO 30" "0: Power switch is disabled,1: Power switch is enabled"
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
bitfld.long 0x78 25. "VDDPWRSWEN30,VDD power switch enable. Enable VDD power switch when driving pad signal to 1 for GPIO 30" "0: Power switch is disabled,1: Power switch is enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x78 22. "NCEPOL30,Polarity select for NCE for GPIO 30" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x78 16.--21. 1. "NCESRC30,IOMSTR/MSPI N Chip Select 30 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x78 13.--15. "PULLCFG30,Pullup/Pulldown configuration for GPIO 30" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x78 12. "SR30,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x78 10.--11. "DS30,Drive strength selection for GPIO 30" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0x78 8.--9. "OUTCFG30,Pin IO mode selection for GPIO pin 30" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x78 6.--7. "IRPTEN30,Interrupt enable for GPIO 30" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x78 5. "RDZERO30,Return 0 for read data on GPIO 30" "0,1"
|
|
newline
|
|
bitfld.long 0x78 4. "INPEN30,Input enable for GPIO 30" "0,1"
|
|
hexmask.long.byte 0x78 0.--3. 1. "FNCSEL30,Function select for GPIO pin 30"
|
|
line.long 0x7C "PINCFG31,Controls the operation of GPIO pin 31."
|
|
bitfld.long 0x7C 27. "FOEN31,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x7C 26. "FIEN31,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x7C 22. "NCEPOL31,Polarity select for NCE for GPIO 31" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x7C 16.--21. 1. "NCESRC31,IOMSTR/MSPI N Chip Select 31 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x7C 13.--15. "PULLCFG31,Pullup/Pulldown configuration for GPIO 31" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x7C 12. "SR31,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x7C 10.--11. "DS31,Drive strength selection for GPIO 31" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x7C 8.--9. "OUTCFG31,Pin IO mode selection for GPIO pin 31" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x7C 6.--7. "IRPTEN31,Interrupt enable for GPIO 31" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x7C 5. "RDZERO31,Return 0 for read data on GPIO 31" "0,1"
|
|
newline
|
|
bitfld.long 0x7C 4. "INPEN31,Input enable for GPIO 31" "0,1"
|
|
hexmask.long.byte 0x7C 0.--3. 1. "FNCSEL31,Function select for GPIO pin 31"
|
|
line.long 0x80 "PINCFG32,Controls the operation of GPIO pin 32."
|
|
bitfld.long 0x80 27. "FOEN32,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x80 26. "FIEN32,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x80 22. "NCEPOL32,Polarity select for NCE for GPIO 32" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x80 16.--21. 1. "NCESRC32,IOMSTR/MSPI N Chip Select 32 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x80 13.--15. "PULLCFG32,Pullup/Pulldown configuration for GPIO 32" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x80 12. "SR32,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x80 10.--11. "DS32,Drive strength selection for GPIO 32" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x80 8.--9. "OUTCFG32,Pin IO mode selection for GPIO pin 32" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x80 6.--7. "IRPTEN32,Interrupt enable for GPIO 32" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x80 5. "RDZERO32,Return 0 for read data on GPIO 32" "0,1"
|
|
newline
|
|
bitfld.long 0x80 4. "INPEN32,Input enable for GPIO 32" "0,1"
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x80 0.--3. 1. "FNCSEL32,Function select for GPIO pin 32"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x80 0.--3. 1. "FNCSEL32,Function select for GPIO pin 32"
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x80 0.--3. 1. "FNCSEL32,Function select for GPIO pin 32"
|
|
endif
|
|
line.long 0x84 "PINCFG33,Controls the operation of GPIO pin 33."
|
|
bitfld.long 0x84 27. "FOEN33,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x84 26. "FIEN33,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x84 22. "NCEPOL33,Polarity select for NCE for GPIO 33" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x84 16.--21. 1. "NCESRC33,IOMSTR/MSPI N Chip Select 33 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x84 13.--15. "PULLCFG33,Pullup/Pulldown configuration for GPIO 33" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x84 12. "SR33,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x84 10.--11. "DS33,Drive strength selection for GPIO 33" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x84 8.--9. "OUTCFG33,Pin IO mode selection for GPIO pin 33" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x84 6.--7. "IRPTEN33,Interrupt enable for GPIO 33" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x84 5. "RDZERO33,Return 0 for read data on GPIO 33" "0,1"
|
|
newline
|
|
bitfld.long 0x84 4. "INPEN33,Input enable for GPIO 33" "0,1"
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x84 0.--3. 1. "FNCSEL33,Function select for GPIO pin 33"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x84 0.--3. 1. "FNCSEL33,Function select for GPIO pin 33"
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x84 0.--3. 1. "FNCSEL33,Function select for GPIO pin 33"
|
|
endif
|
|
line.long 0x88 "PINCFG34,Controls the operation of GPIO pin 34."
|
|
bitfld.long 0x88 27. "FOEN34,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x88 26. "FIEN34,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x88 22. "NCEPOL34,Polarity select for NCE for GPIO 34" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x88 16.--21. 1. "NCESRC34,IOMSTR/MSPI N Chip Select 34 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x88 13.--15. "PULLCFG34,Pullup/Pulldown configuration for GPIO 34" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x88 12. "SR34,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x88 10.--11. "DS34,Drive strength selection for GPIO 34" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x88 8.--9. "OUTCFG34,Pin IO mode selection for GPIO pin 34" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x88 6.--7. "IRPTEN34,Interrupt enable for GPIO 34" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x88 5. "RDZERO34,Return 0 for read data on GPIO 34" "0,1"
|
|
newline
|
|
bitfld.long 0x88 4. "INPEN34,Input enable for GPIO 34" "0,1"
|
|
hexmask.long.byte 0x88 0.--3. 1. "FNCSEL34,Function select for GPIO pin 34"
|
|
line.long 0x8C "PINCFG35,Controls the operation of GPIO pin 35."
|
|
bitfld.long 0x8C 27. "FOEN35,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x8C 26. "FIEN35,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x8C 22. "NCEPOL35,Polarity select for NCE for GPIO 35" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x8C 16.--21. 1. "NCESRC35,IOMSTR/MSPI N Chip Select 35 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x8C 13.--15. "PULLCFG35,Pullup/Pulldown configuration for GPIO 35" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x8C 12. "SR35,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x8C 10.--11. "DS35,Drive strength selection for GPIO 35" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x8C 8.--9. "OUTCFG35,Pin IO mode selection for GPIO pin 35" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x8C 6.--7. "IRPTEN35,Interrupt enable for GPIO 35" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x8C 5. "RDZERO35,Return 0 for read data on GPIO 35" "0,1"
|
|
newline
|
|
bitfld.long 0x8C 4. "INPEN35,Input enable for GPIO 35" "0,1"
|
|
hexmask.long.byte 0x8C 0.--3. 1. "FNCSEL35,Function select for GPIO pin 35"
|
|
line.long 0x90 "PINCFG36,Controls the operation of GPIO pin 36."
|
|
bitfld.long 0x90 27. "FOEN36,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x90 26. "FIEN36,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x90 22. "NCEPOL36,Polarity select for NCE for GPIO 36" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x90 16.--21. 1. "NCESRC36,IOMSTR/MSPI N Chip Select 36 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x90 13.--15. "PULLCFG36,Pullup/Pulldown configuration for GPIO 36" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x90 12. "SR36,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x90 10.--11. "DS36,Drive strength selection for GPIO 36" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x90 8.--9. "OUTCFG36,Pin IO mode selection for GPIO pin 36" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x90 6.--7. "IRPTEN36,Interrupt enable for GPIO 36" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x90 5. "RDZERO36,Return 0 for read data on GPIO 36" "0,1"
|
|
newline
|
|
bitfld.long 0x90 4. "INPEN36,Input enable for GPIO 36" "0,1"
|
|
hexmask.long.byte 0x90 0.--3. 1. "FNCSEL36,Function select for GPIO pin 36"
|
|
line.long 0x94 "PINCFG37,Controls the operation of GPIO pin 37."
|
|
bitfld.long 0x94 27. "FOEN37,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x94 26. "FIEN37,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x94 22. "NCEPOL37,Polarity select for NCE for GPIO 37" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x94 16.--21. 1. "NCESRC37,IOMSTR/MSPI N Chip Select 37 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x94 13.--15. "PULLCFG37,Pullup/Pulldown configuration for GPIO 37" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x94 12. "SR37,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x94 10.--11. "DS37,Drive strength selection for GPIO 37" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x94 8.--9. "OUTCFG37,Pin IO mode selection for GPIO pin 37" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x94 6.--7. "IRPTEN37,Interrupt enable for GPIO 37" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x94 5. "RDZERO37,Return 0 for read data on GPIO 37" "0,1"
|
|
newline
|
|
bitfld.long 0x94 4. "INPEN37,Input enable for GPIO 37" "0,1"
|
|
hexmask.long.byte 0x94 0.--3. 1. "FNCSEL37,Function select for GPIO pin 37"
|
|
line.long 0x98 "PINCFG38,Controls the operation of GPIO pin 38."
|
|
bitfld.long 0x98 27. "FOEN38,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x98 26. "FIEN38,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x98 22. "NCEPOL38,Polarity select for NCE for GPIO 38" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x98 16.--21. 1. "NCESRC38,IOMSTR/MSPI N Chip Select 38 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x98 13.--15. "PULLCFG38,Pullup/Pulldown configuration for GPIO 38" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x98 12. "SR38,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x98 10.--11. "DS38,Drive strength selection for GPIO 38" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x98 8.--9. "OUTCFG38,Pin IO mode selection for GPIO pin 38" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x98 6.--7. "IRPTEN38,Interrupt enable for GPIO 38" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x98 5. "RDZERO38,Return 0 for read data on GPIO 38" "0,1"
|
|
newline
|
|
bitfld.long 0x98 4. "INPEN38,Input enable for GPIO 38" "0,1"
|
|
hexmask.long.byte 0x98 0.--3. 1. "FNCSEL38,Function select for GPIO pin 38"
|
|
line.long 0x9C "PINCFG39,Controls the operation of GPIO pin 39."
|
|
bitfld.long 0x9C 27. "FOEN39,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x9C 26. "FIEN39,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x9C 22. "NCEPOL39,Polarity select for NCE for GPIO 39" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x9C 16.--21. 1. "NCESRC39,IOMSTR/MSPI N Chip Select 39 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x9C 13.--15. "PULLCFG39,Pullup/Pulldown configuration for GPIO 39" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x9C 12. "SR39,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x9C 10.--11. "DS39,Drive strength selection for GPIO 39" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x9C 8.--9. "OUTCFG39,Pin IO mode selection for GPIO pin 39" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x9C 6.--7. "IRPTEN39,Interrupt enable for GPIO 39" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x9C 5. "RDZERO39,Return 0 for read data on GPIO 39" "0,1"
|
|
newline
|
|
bitfld.long 0x9C 4. "INPEN39,Input enable for GPIO 39" "0,1"
|
|
hexmask.long.byte 0x9C 0.--3. 1. "FNCSEL39,Function select for GPIO pin 39"
|
|
line.long 0xA0 "PINCFG40,Controls the operation of GPIO pin 40."
|
|
bitfld.long 0xA0 27. "FOEN40,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0xA0 26. "FIEN40,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0xA0 22. "NCEPOL40,Polarity select for NCE for GPIO 40" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0xA0 16.--21. 1. "NCESRC40,IOMSTR/MSPI N Chip Select 40 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0xA0 13.--15. "PULLCFG40,Pullup/Pulldown configuration for GPIO 40" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0xA0 12. "SR40,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0xA0 10.--11. "DS40,Drive strength selection for GPIO 40" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0xA0 8.--9. "OUTCFG40,Pin IO mode selection for GPIO pin 40" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0xA0 6.--7. "IRPTEN40,Interrupt enable for GPIO 40" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0xA0 5. "RDZERO40,Return 0 for read data on GPIO 40" "0,1"
|
|
newline
|
|
bitfld.long 0xA0 4. "INPEN40,Input enable for GPIO 40" "0,1"
|
|
hexmask.long.byte 0xA0 0.--3. 1. "FNCSEL40,Function select for GPIO pin 40"
|
|
line.long 0xA4 "PINCFG41,Controls the operation of GPIO pin 41."
|
|
bitfld.long 0xA4 27. "FOEN41,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0xA4 26. "FIEN41,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0xA4 22. "NCEPOL41,Polarity select for NCE for GPIO 41" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0xA4 16.--21. 1. "NCESRC41,IOMSTR/MSPI N Chip Select 41 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0xA4 13.--15. "PULLCFG41,Pullup/Pulldown configuration for GPIO 41" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0xA4 12. "SR41,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0xA4 10.--11. "DS41,Drive strength selection for GPIO 41" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0xA4 8.--9. "OUTCFG41,Pin IO mode selection for GPIO pin 41" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0xA4 6.--7. "IRPTEN41,Interrupt enable for GPIO 41" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0xA4 5. "RDZERO41,Return 0 for read data on GPIO 41" "0,1"
|
|
newline
|
|
bitfld.long 0xA4 4. "INPEN41,Input enable for GPIO 41" "0,1"
|
|
hexmask.long.byte 0xA4 0.--3. 1. "FNCSEL41,Function select for GPIO pin 41"
|
|
line.long 0xA8 "PINCFG42,Controls the operation of GPIO pin 42."
|
|
bitfld.long 0xA8 27. "FOEN42,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0xA8 26. "FIEN42,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0xA8 22. "NCEPOL42,Polarity select for NCE for GPIO 42" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0xA8 16.--21. 1. "NCESRC42,IOMSTR/MSPI N Chip Select 42 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0xA8 13.--15. "PULLCFG42,Pullup/Pulldown configuration for GPIO 42" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0xA8 12. "SR42,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0xA8 10.--11. "DS42,Drive strength selection for GPIO 42" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0xA8 8.--9. "OUTCFG42,Pin IO mode selection for GPIO pin 42" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0xA8 6.--7. "IRPTEN42,Interrupt enable for GPIO 42" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0xA8 5. "RDZERO42,Return 0 for read data on GPIO 42" "0,1"
|
|
newline
|
|
bitfld.long 0xA8 4. "INPEN42,Input enable for GPIO 42" "0,1"
|
|
hexmask.long.byte 0xA8 0.--3. 1. "FNCSEL42,Function select for GPIO pin 42"
|
|
line.long 0xAC "PINCFG43,Controls the operation of GPIO pin 43."
|
|
bitfld.long 0xAC 27. "FOEN43,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0xAC 26. "FIEN43,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0xAC 22. "NCEPOL43,Polarity select for NCE for GPIO 43" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0xAC 16.--21. 1. "NCESRC43,IOMSTR/MSPI N Chip Select 43 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0xAC 13.--15. "PULLCFG43,Pullup/Pulldown configuration for GPIO 43" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0xAC 12. "SR43,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0xAC 10.--11. "DS43,Drive strength selection for GPIO 43" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0xAC 8.--9. "OUTCFG43,Pin IO mode selection for GPIO pin 43" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0xAC 6.--7. "IRPTEN43,Interrupt enable for GPIO 43" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0xAC 5. "RDZERO43,Return 0 for read data on GPIO 43" "0,1"
|
|
newline
|
|
bitfld.long 0xAC 4. "INPEN43,Input enable for GPIO 43" "0,1"
|
|
hexmask.long.byte 0xAC 0.--3. 1. "FNCSEL43,Function select for GPIO pin 43"
|
|
line.long 0xB0 "PINCFG44,Controls the operation of GPIO pin 44."
|
|
bitfld.long 0xB0 27. "FOEN44,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0xB0 26. "FIEN44,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0xB0 22. "NCEPOL44,Polarity select for NCE for GPIO 44" "0: Polarity is active low,1: Polarity is active high"
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|
hexmask.long.byte 0xB0 16.--21. 1. "NCESRC44,IOMSTR/MSPI N Chip Select 44 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
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|
newline
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bitfld.long 0xB0 13.--15. "PULLCFG44,Pullup/Pulldown configuration for GPIO 44" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
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bitfld.long 0xB0 12. "SR44,Configure the slew rate" "0,1"
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newline
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bitfld.long 0xB0 10.--11. "DS44,Drive strength selection for GPIO 44" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
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bitfld.long 0xB0 8.--9. "OUTCFG44,Pin IO mode selection for GPIO pin 44" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
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|
newline
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bitfld.long 0xB0 6.--7. "IRPTEN44,Interrupt enable for GPIO 44" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
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bitfld.long 0xB0 5. "RDZERO44,Return 0 for read data on GPIO 44" "0,1"
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|
newline
|
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bitfld.long 0xB0 4. "INPEN44,Input enable for GPIO 44" "0,1"
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hexmask.long.byte 0xB0 0.--3. 1. "FNCSEL44,Function select for GPIO pin 44"
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line.long 0xB4 "PINCFG45,Controls the operation of GPIO pin 45."
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bitfld.long 0xB4 27. "FOEN45,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
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bitfld.long 0xB4 26. "FIEN45,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
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newline
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bitfld.long 0xB4 22. "NCEPOL45,Polarity select for NCE for GPIO 45" "0: Polarity is active low,1: Polarity is active high"
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hexmask.long.byte 0xB4 16.--21. 1. "NCESRC45,IOMSTR/MSPI N Chip Select 45 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
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|
newline
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bitfld.long 0xB4 13.--15. "PULLCFG45,Pullup/Pulldown configuration for GPIO 45" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
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bitfld.long 0xB4 12. "SR45,Configure the slew rate" "0,1"
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|
newline
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bitfld.long 0xB4 10.--11. "DS45,Drive strength selection for GPIO 45" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
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bitfld.long 0xB4 8.--9. "OUTCFG45,Pin IO mode selection for GPIO pin 45" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
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|
newline
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bitfld.long 0xB4 6.--7. "IRPTEN45,Interrupt enable for GPIO 45" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
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bitfld.long 0xB4 5. "RDZERO45,Return 0 for read data on GPIO 45" "0,1"
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|
newline
|
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bitfld.long 0xB4 4. "INPEN45,Input enable for GPIO 45" "0,1"
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hexmask.long.byte 0xB4 0.--3. 1. "FNCSEL45,Function select for GPIO pin 45"
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line.long 0xB8 "PINCFG46,Controls the operation of GPIO pin 46."
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bitfld.long 0xB8 27. "FOEN46,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
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bitfld.long 0xB8 26. "FIEN46,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
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newline
|
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bitfld.long 0xB8 22. "NCEPOL46,Polarity select for NCE for GPIO 46" "0: Polarity is active low,1: Polarity is active high"
|
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hexmask.long.byte 0xB8 16.--21. 1. "NCESRC46,IOMSTR/MSPI N Chip Select 46 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
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|
newline
|
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bitfld.long 0xB8 13.--15. "PULLCFG46,Pullup/Pulldown configuration for GPIO 46" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
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bitfld.long 0xB8 12. "SR46,Configure the slew rate" "0,1"
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newline
|
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bitfld.long 0xB8 10.--11. "DS46,Drive strength selection for GPIO 46" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
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bitfld.long 0xB8 8.--9. "OUTCFG46,Pin IO mode selection for GPIO pin 46" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
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|
newline
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bitfld.long 0xB8 6.--7. "IRPTEN46,Interrupt enable for GPIO 46" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
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bitfld.long 0xB8 5. "RDZERO46,Return 0 for read data on GPIO 46" "0,1"
|
|
newline
|
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bitfld.long 0xB8 4. "INPEN46,Input enable for GPIO 46" "0,1"
|
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hexmask.long.byte 0xB8 0.--3. 1. "FNCSEL46,Function select for GPIO pin 46"
|
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line.long 0xBC "PINCFG47,Controls the operation of GPIO pin 47."
|
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bitfld.long 0xBC 27. "FOEN47,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
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bitfld.long 0xBC 26. "FIEN47,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
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bitfld.long 0xBC 22. "NCEPOL47,Polarity select for NCE for GPIO 47" "0: Polarity is active low,1: Polarity is active high"
|
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hexmask.long.byte 0xBC 16.--21. 1. "NCESRC47,IOMSTR/MSPI N Chip Select 47 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
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bitfld.long 0xBC 13.--15. "PULLCFG47,Pullup/Pulldown configuration for GPIO 47" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
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bitfld.long 0xBC 12. "SR47,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0xBC 10.--11. "DS47,Drive strength selection for GPIO 47" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
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bitfld.long 0xBC 8.--9. "OUTCFG47,Pin IO mode selection for GPIO pin 47" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
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bitfld.long 0xBC 6.--7. "IRPTEN47,Interrupt enable for GPIO 47" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
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bitfld.long 0xBC 5. "RDZERO47,Return 0 for read data on GPIO 47" "0,1"
|
|
newline
|
|
bitfld.long 0xBC 4. "INPEN47,Input enable for GPIO 47" "0,1"
|
|
hexmask.long.byte 0xBC 0.--3. 1. "FNCSEL47,Function select for GPIO pin 47"
|
|
line.long 0xC0 "PINCFG48,Controls the operation of GPIO pin 48."
|
|
bitfld.long 0xC0 27. "FOEN48,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
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bitfld.long 0xC0 26. "FIEN48,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0xC0 22. "NCEPOL48,Polarity select for NCE for GPIO 48" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0xC0 16.--21. 1. "NCESRC48,IOMSTR/MSPI N Chip Select 48 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0xC0 13.--15. "PULLCFG48,Pullup/Pulldown configuration for GPIO 48" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0xC0 12. "SR48,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0xC0 10.--11. "DS48,Drive strength selection for GPIO 48" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
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bitfld.long 0xC0 8.--9. "OUTCFG48,Pin IO mode selection for GPIO pin 48" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
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bitfld.long 0xC0 6.--7. "IRPTEN48,Interrupt enable for GPIO 48" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
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bitfld.long 0xC0 5. "RDZERO48,Return 0 for read data on GPIO 48" "0,1"
|
|
newline
|
|
bitfld.long 0xC0 4. "INPEN48,Input enable for GPIO 48" "0,1"
|
|
hexmask.long.byte 0xC0 0.--3. 1. "FNCSEL48,Function select for GPIO pin 48"
|
|
line.long 0xC4 "PINCFG49,Controls the operation of GPIO pin 49."
|
|
bitfld.long 0xC4 27. "FOEN49,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0xC4 26. "FIEN49,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0xC4 22. "NCEPOL49,Polarity select for NCE for GPIO 49" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0xC4 16.--21. 1. "NCESRC49,IOMSTR/MSPI N Chip Select 49 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0xC4 13.--15. "PULLCFG49,Pullup/Pulldown configuration for GPIO 49" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0xC4 12. "SR49,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0xC4 10.--11. "DS49,Drive strength selection for GPIO 49" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0xC4 8.--9. "OUTCFG49,Pin IO mode selection for GPIO pin 49" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0xC4 6.--7. "IRPTEN49,Interrupt enable for GPIO 49" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0xC4 5. "RDZERO49,Return 0 for read data on GPIO 49" "0,1"
|
|
newline
|
|
bitfld.long 0xC4 4. "INPEN49,Input enable for GPIO 49" "0,1"
|
|
hexmask.long.byte 0xC4 0.--3. 1. "FNCSEL49,Function select for GPIO pin 49"
|
|
line.long 0xC8 "PINCFG50,Controls the operation of GPIO pin 50."
|
|
bitfld.long 0xC8 27. "FOEN50,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0xC8 26. "FIEN50,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0xC8 22. "NCEPOL50,Polarity select for NCE for GPIO 50" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0xC8 16.--21. 1. "NCESRC50,IOMSTR/MSPI N Chip Select 50 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0xC8 13.--15. "PULLCFG50,Pullup/Pulldown configuration for GPIO 50" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0xC8 12. "SR50,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0xC8 10.--11. "DS50,Drive strength selection for GPIO 50" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0xC8 8.--9. "OUTCFG50,Pin IO mode selection for GPIO pin 50" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0xC8 6.--7. "IRPTEN50,Interrupt enable for GPIO 50" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0xC8 5. "RDZERO50,Return 0 for read data on GPIO 50" "0,1"
|
|
newline
|
|
bitfld.long 0xC8 4. "INPEN50,Input enable for GPIO 50" "0,1"
|
|
hexmask.long.byte 0xC8 0.--3. 1. "FNCSEL50,Function select for GPIO pin 50"
|
|
line.long 0xCC "PINCFG51,Controls the operation of GPIO pin 51."
|
|
bitfld.long 0xCC 27. "FOEN51,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0xCC 26. "FIEN51,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0xCC 22. "NCEPOL51,Polarity select for NCE for GPIO 51" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0xCC 16.--21. 1. "NCESRC51,IOMSTR/MSPI N Chip Select 51 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0xCC 13.--15. "PULLCFG51,Pullup/Pulldown configuration for GPIO 51" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0xCC 12. "SR51,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0xCC 10.--11. "DS51,Drive strength selection for GPIO 51" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0xCC 8.--9. "OUTCFG51,Pin IO mode selection for GPIO pin 51" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0xCC 6.--7. "IRPTEN51,Interrupt enable for GPIO 51" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0xCC 5. "RDZERO51,Return 0 for read data on GPIO 51" "0,1"
|
|
newline
|
|
bitfld.long 0xCC 4. "INPEN51,Input enable for GPIO 51" "0,1"
|
|
hexmask.long.byte 0xCC 0.--3. 1. "FNCSEL51,Function select for GPIO pin 51"
|
|
line.long 0xD0 "PINCFG52,Controls the operation of GPIO pin 52."
|
|
bitfld.long 0xD0 27. "FOEN52,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0xD0 26. "FIEN52,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0xD0 22. "NCEPOL52,Polarity select for NCE for GPIO 52" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0xD0 16.--21. 1. "NCESRC52,IOMSTR/MSPI N Chip Select 52 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0xD0 13.--15. "PULLCFG52,Pullup/Pulldown configuration for GPIO 52" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0xD0 12. "SR52,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0xD0 10.--11. "DS52,Drive strength selection for GPIO 52" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0xD0 8.--9. "OUTCFG52,Pin IO mode selection for GPIO pin 52" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0xD0 6.--7. "IRPTEN52,Interrupt enable for GPIO 52" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0xD0 5. "RDZERO52,Return 0 for read data on GPIO 52" "0,1"
|
|
newline
|
|
bitfld.long 0xD0 4. "INPEN52,Input enable for GPIO 52" "0,1"
|
|
hexmask.long.byte 0xD0 0.--3. 1. "FNCSEL52,Function select for GPIO pin 52"
|
|
line.long 0xD4 "PINCFG53,Controls the operation of GPIO pin 53."
|
|
bitfld.long 0xD4 27. "FOEN53,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0xD4 26. "FIEN53,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0xD4 22. "NCEPOL53,Polarity select for NCE for GPIO 53" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0xD4 16.--21. 1. "NCESRC53,IOMSTR/MSPI N Chip Select 53 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0xD4 13.--15. "PULLCFG53,Pullup/Pulldown configuration for GPIO 53" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0xD4 12. "SR53,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0xD4 10.--11. "DS53,Drive strength selection for GPIO 53" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0xD4 8.--9. "OUTCFG53,Pin IO mode selection for GPIO pin 53" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0xD4 6.--7. "IRPTEN53,Interrupt enable for GPIO 53" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0xD4 5. "RDZERO53,Return 0 for read data on GPIO 53" "0,1"
|
|
newline
|
|
bitfld.long 0xD4 4. "INPEN53,Input enable for GPIO 53" "0,1"
|
|
hexmask.long.byte 0xD4 0.--3. 1. "FNCSEL53,Function select for GPIO pin 53"
|
|
line.long 0xD8 "PINCFG54,Controls the operation of GPIO pin 54."
|
|
bitfld.long 0xD8 27. "FOEN54,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0xD8 26. "FIEN54,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0xD8 22. "NCEPOL54,Polarity select for NCE for GPIO 54" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0xD8 16.--21. 1. "NCESRC54,IOMSTR/MSPI N Chip Select 54 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0xD8 13.--15. "PULLCFG54,Pullup/Pulldown configuration for GPIO 54" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0xD8 12. "SR54,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0xD8 10.--11. "DS54,Drive strength selection for GPIO 54" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0xD8 8.--9. "OUTCFG54,Pin IO mode selection for GPIO pin 54" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0xD8 6.--7. "IRPTEN54,Interrupt enable for GPIO 54" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0xD8 5. "RDZERO54,Return 0 for read data on GPIO 54" "0,1"
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|
newline
|
|
bitfld.long 0xD8 4. "INPEN54,Input enable for GPIO 54" "0,1"
|
|
hexmask.long.byte 0xD8 0.--3. 1. "FNCSEL54,Function select for GPIO pin 54"
|
|
line.long 0xDC "PINCFG55,Controls the operation of GPIO pin 55."
|
|
bitfld.long 0xDC 27. "FOEN55,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0xDC 26. "FIEN55,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0xDC 22. "NCEPOL55,Polarity select for NCE for GPIO 55" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0xDC 16.--21. 1. "NCESRC55,IOMSTR/MSPI N Chip Select 55 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0xDC 13.--15. "PULLCFG55,Pullup/Pulldown configuration for GPIO 55" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0xDC 12. "SR55,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0xDC 10.--11. "DS55,Drive strength selection for GPIO 55" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
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|
bitfld.long 0xDC 8.--9. "OUTCFG55,Pin IO mode selection for GPIO pin 55" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
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|
newline
|
|
bitfld.long 0xDC 6.--7. "IRPTEN55,Interrupt enable for GPIO 55" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
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|
bitfld.long 0xDC 5. "RDZERO55,Return 0 for read data on GPIO 55" "0,1"
|
|
newline
|
|
bitfld.long 0xDC 4. "INPEN55,Input enable for GPIO 55" "0,1"
|
|
hexmask.long.byte 0xDC 0.--3. 1. "FNCSEL55,Function select for GPIO pin 55"
|
|
line.long 0xE0 "PINCFG56,Controls the operation of GPIO pin 56."
|
|
bitfld.long 0xE0 27. "FOEN56,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0xE0 26. "FIEN56,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0xE0 22. "NCEPOL56,Polarity select for NCE for GPIO 56" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0xE0 16.--21. 1. "NCESRC56,IOMSTR/MSPI N Chip Select 56 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0xE0 13.--15. "PULLCFG56,Pullup/Pulldown configuration for GPIO 56" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0xE0 12. "SR56,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0xE0 10.--11. "DS56,Drive strength selection for GPIO 56" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
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|
bitfld.long 0xE0 8.--9. "OUTCFG56,Pin IO mode selection for GPIO pin 56" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0xE0 6.--7. "IRPTEN56,Interrupt enable for GPIO 56" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0xE0 5. "RDZERO56,Return 0 for read data on GPIO 56" "0,1"
|
|
newline
|
|
bitfld.long 0xE0 4. "INPEN56,Input enable for GPIO 56" "0,1"
|
|
hexmask.long.byte 0xE0 0.--3. 1. "FNCSEL56,Function select for GPIO pin 56"
|
|
line.long 0xE4 "PINCFG57,Controls the operation of GPIO pin 57."
|
|
bitfld.long 0xE4 27. "FOEN57,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0xE4 26. "FIEN57,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0xE4 22. "NCEPOL57,Polarity select for NCE for GPIO 57" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0xE4 16.--21. 1. "NCESRC57,IOMSTR/MSPI N Chip Select 57 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0xE4 13.--15. "PULLCFG57,Pullup/Pulldown configuration for GPIO 57" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0xE4 12. "SR57,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0xE4 10.--11. "DS57,Drive strength selection for GPIO 57" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0xE4 8.--9. "OUTCFG57,Pin IO mode selection for GPIO pin 57" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0xE4 6.--7. "IRPTEN57,Interrupt enable for GPIO 57" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0xE4 5. "RDZERO57,Return 0 for read data on GPIO 57" "0,1"
|
|
newline
|
|
bitfld.long 0xE4 4. "INPEN57,Input enable for GPIO 57" "0,1"
|
|
hexmask.long.byte 0xE4 0.--3. 1. "FNCSEL57,Function select for GPIO pin 57"
|
|
line.long 0xE8 "PINCFG58,Controls the operation of GPIO pin 58."
|
|
bitfld.long 0xE8 27. "FOEN58,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0xE8 26. "FIEN58,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0xE8 22. "NCEPOL58,Polarity select for NCE for GPIO 58" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0xE8 16.--21. 1. "NCESRC58,IOMSTR/MSPI N Chip Select 58 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0xE8 13.--15. "PULLCFG58,Pullup/Pulldown configuration for GPIO 58" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0xE8 12. "SR58,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0xE8 10.--11. "DS58,Drive strength selection for GPIO 58" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0xE8 8.--9. "OUTCFG58,Pin IO mode selection for GPIO pin 58" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0xE8 6.--7. "IRPTEN58,Interrupt enable for GPIO 58" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0xE8 5. "RDZERO58,Return 0 for read data on GPIO 58" "0,1"
|
|
newline
|
|
bitfld.long 0xE8 4. "INPEN58,Input enable for GPIO 58" "0,1"
|
|
hexmask.long.byte 0xE8 0.--3. 1. "FNCSEL58,Function select for GPIO pin 58"
|
|
line.long 0xEC "PINCFG59,Controls the operation of GPIO pin 59."
|
|
bitfld.long 0xEC 27. "FOEN59,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0xEC 26. "FIEN59,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0xEC 22. "NCEPOL59,Polarity select for NCE for GPIO 59" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0xEC 16.--21. 1. "NCESRC59,IOMSTR/MSPI N Chip Select 59 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0xEC 13.--15. "PULLCFG59,Pullup/Pulldown configuration for GPIO 59" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0xEC 12. "SR59,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0xEC 10.--11. "DS59,Drive strength selection for GPIO 59" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0xEC 8.--9. "OUTCFG59,Pin IO mode selection for GPIO pin 59" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0xEC 6.--7. "IRPTEN59,Interrupt enable for GPIO 59" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0xEC 5. "RDZERO59,Return 0 for read data on GPIO 59" "0,1"
|
|
newline
|
|
bitfld.long 0xEC 4. "INPEN59,Input enable for GPIO 59" "0,1"
|
|
hexmask.long.byte 0xEC 0.--3. 1. "FNCSEL59,Function select for GPIO pin 59"
|
|
line.long 0xF0 "PINCFG60,Controls the operation of GPIO pin 60."
|
|
bitfld.long 0xF0 27. "FOEN60,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0xF0 26. "FIEN60,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0xF0 22. "NCEPOL60,Polarity select for NCE for GPIO 60" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0xF0 16.--21. 1. "NCESRC60,IOMSTR/MSPI N Chip Select 60 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0xF0 13.--15. "PULLCFG60,Pullup/Pulldown configuration for GPIO 60" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0xF0 12. "SR60,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0xF0 10.--11. "DS60,Drive strength selection for GPIO 60" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0xF0 8.--9. "OUTCFG60,Pin IO mode selection for GPIO pin 60" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0xF0 6.--7. "IRPTEN60,Interrupt enable for GPIO 60" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0xF0 5. "RDZERO60,Return 0 for read data on GPIO 60" "0,1"
|
|
newline
|
|
bitfld.long 0xF0 4. "INPEN60,Input enable for GPIO 60" "0,1"
|
|
hexmask.long.byte 0xF0 0.--3. 1. "FNCSEL60,Function select for GPIO pin 60"
|
|
line.long 0xF4 "PINCFG61,Controls the operation of GPIO pin 61."
|
|
bitfld.long 0xF4 27. "FOEN61,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0xF4 26. "FIEN61,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0xF4 22. "NCEPOL61,Polarity select for NCE for GPIO 61" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0xF4 16.--21. 1. "NCESRC61,IOMSTR/MSPI N Chip Select 61 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0xF4 13.--15. "PULLCFG61,Pullup/Pulldown configuration for GPIO 61" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0xF4 12. "SR61,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0xF4 10.--11. "DS61,Drive strength selection for GPIO 61" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0xF4 8.--9. "OUTCFG61,Pin IO mode selection for GPIO pin 61" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0xF4 6.--7. "IRPTEN61,Interrupt enable for GPIO 61" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0xF4 5. "RDZERO61,Return 0 for read data on GPIO 61" "0,1"
|
|
newline
|
|
bitfld.long 0xF4 4. "INPEN61,Input enable for GPIO 61" "0,1"
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0xF4 0.--3. 1. "FNCSEL61,Function select for GPIO pin 61"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0xF4 0.--3. 1. "FNCSEL61,Function select for GPIO pin 61"
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0xF4 0.--3. 1. "FNCSEL61,Function select for GPIO pin 61"
|
|
endif
|
|
line.long 0xF8 "PINCFG62,Controls the operation of GPIO pin 62."
|
|
bitfld.long 0xF8 27. "FOEN62,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0xF8 26. "FIEN62,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0xF8 22. "NCEPOL62,Polarity select for NCE for GPIO 62" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0xF8 16.--21. 1. "NCESRC62,IOMSTR/MSPI N Chip Select 62 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0xF8 13.--15. "PULLCFG62,Pullup/Pulldown configuration for GPIO 62" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0xF8 12. "SR62,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0xF8 10.--11. "DS62,Drive strength selection for GPIO 62" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0xF8 8.--9. "OUTCFG62,Pin IO mode selection for GPIO pin 62" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0xF8 6.--7. "IRPTEN62,Interrupt enable for GPIO 62" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0xF8 5. "RDZERO62,Return 0 for read data on GPIO 62" "0,1"
|
|
newline
|
|
bitfld.long 0xF8 4. "INPEN62,Input enable for GPIO 62" "0,1"
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0xF8 0.--3. 1. "FNCSEL62,Function select for GPIO pin 62"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0xF8 0.--3. 1. "FNCSEL62,Function select for GPIO pin 62"
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0xF8 0.--3. 1. "FNCSEL62,Function select for GPIO pin 62"
|
|
endif
|
|
line.long 0xFC "PINCFG63,Controls the operation of GPIO pin 63."
|
|
bitfld.long 0xFC 27. "FOEN63,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0xFC 26. "FIEN63,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0xFC 22. "NCEPOL63,Polarity select for NCE for GPIO 63" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0xFC 16.--21. 1. "NCESRC63,IOMSTR/MSPI N Chip Select 63 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0xFC 13.--15. "PULLCFG63,Pullup/Pulldown configuration for GPIO 63" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0xFC 12. "SR63,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0xFC 10.--11. "DS63,Drive strength selection for GPIO 63" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0xFC 8.--9. "OUTCFG63,Pin IO mode selection for GPIO pin 63" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0xFC 6.--7. "IRPTEN63,Interrupt enable for GPIO 63" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0xFC 5. "RDZERO63,Return 0 for read data on GPIO 63" "0,1"
|
|
newline
|
|
bitfld.long 0xFC 4. "INPEN63,Input enable for GPIO 63" "0,1"
|
|
hexmask.long.byte 0xFC 0.--3. 1. "FNCSEL63,Function select for GPIO pin 63"
|
|
line.long 0x100 "PINCFG64,Controls the operation of GPIO pin 64."
|
|
bitfld.long 0x100 27. "FOEN64,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x100 26. "FIEN64,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x100 22. "NCEPOL64,Polarity select for NCE for GPIO 64" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x100 16.--21. 1. "NCESRC64,IOMSTR/MSPI N Chip Select 64 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x100 13.--15. "PULLCFG64,Pullup/Pulldown configuration for GPIO 64" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x100 12. "SR64,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x100 10.--11. "DS64,Drive strength selection for GPIO 64" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x100 8.--9. "OUTCFG64,Pin IO mode selection for GPIO pin 64" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x100 6.--7. "IRPTEN64,Interrupt enable for GPIO 64" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x100 5. "RDZERO64,Return 0 for read data on GPIO 64" "0,1"
|
|
newline
|
|
bitfld.long 0x100 4. "INPEN64,Input enable for GPIO 64" "0,1"
|
|
hexmask.long.byte 0x100 0.--3. 1. "FNCSEL64,Function select for GPIO pin 64"
|
|
line.long 0x104 "PINCFG65,Controls the operation of GPIO pin 65."
|
|
bitfld.long 0x104 27. "FOEN65,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x104 26. "FIEN65,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x104 22. "NCEPOL65,Polarity select for NCE for GPIO 65" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x104 16.--21. 1. "NCESRC65,IOMSTR/MSPI N Chip Select 65 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x104 13.--15. "PULLCFG65,Pullup/Pulldown configuration for GPIO 65" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x104 12. "SR65,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x104 10.--11. "DS65,Drive strength selection for GPIO 65" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x104 8.--9. "OUTCFG65,Pin IO mode selection for GPIO pin 65" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x104 6.--7. "IRPTEN65,Interrupt enable for GPIO 65" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x104 5. "RDZERO65,Return 0 for read data on GPIO 65" "0,1"
|
|
newline
|
|
bitfld.long 0x104 4. "INPEN65,Input enable for GPIO 65" "0,1"
|
|
hexmask.long.byte 0x104 0.--3. 1. "FNCSEL65,Function select for GPIO pin 65"
|
|
line.long 0x108 "PINCFG66,Controls the operation of GPIO pin 66."
|
|
bitfld.long 0x108 27. "FOEN66,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x108 26. "FIEN66,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x108 22. "NCEPOL66,Polarity select for NCE for GPIO 66" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x108 16.--21. 1. "NCESRC66,IOMSTR/MSPI N Chip Select 66 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x108 13.--15. "PULLCFG66,Pullup/Pulldown configuration for GPIO 66" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x108 12. "SR66,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x108 10.--11. "DS66,Drive strength selection for GPIO 66" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x108 8.--9. "OUTCFG66,Pin IO mode selection for GPIO pin 66" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x108 6.--7. "IRPTEN66,Interrupt enable for GPIO 66" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x108 5. "RDZERO66,Return 0 for read data on GPIO 66" "0,1"
|
|
newline
|
|
bitfld.long 0x108 4. "INPEN66,Input enable for GPIO 66" "0,1"
|
|
hexmask.long.byte 0x108 0.--3. 1. "FNCSEL66,Function select for GPIO pin 66"
|
|
line.long 0x10C "PINCFG67,Controls the operation of GPIO pin 67."
|
|
bitfld.long 0x10C 27. "FOEN67,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x10C 26. "FIEN67,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x10C 22. "NCEPOL67,Polarity select for NCE for GPIO 67" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x10C 16.--21. 1. "NCESRC67,IOMSTR/MSPI N Chip Select 67 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x10C 13.--15. "PULLCFG67,Pullup/Pulldown configuration for GPIO 67" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x10C 12. "SR67,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x10C 10.--11. "DS67,Drive strength selection for GPIO 67" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x10C 8.--9. "OUTCFG67,Pin IO mode selection for GPIO pin 67" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x10C 6.--7. "IRPTEN67,Interrupt enable for GPIO 67" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x10C 5. "RDZERO67,Return 0 for read data on GPIO 67" "0,1"
|
|
newline
|
|
bitfld.long 0x10C 4. "INPEN67,Input enable for GPIO 67" "0,1"
|
|
hexmask.long.byte 0x10C 0.--3. 1. "FNCSEL67,Function select for GPIO pin 67"
|
|
line.long 0x110 "PINCFG68,Controls the operation of GPIO pin 68."
|
|
bitfld.long 0x110 27. "FOEN68,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x110 26. "FIEN68,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x110 22. "NCEPOL68,Polarity select for NCE for GPIO 68" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x110 16.--21. 1. "NCESRC68,IOMSTR/MSPI N Chip Select 68 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x110 13.--15. "PULLCFG68,Pullup/Pulldown configuration for GPIO 68" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x110 12. "SR68,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x110 10.--11. "DS68,Drive strength selection for GPIO 68" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x110 8.--9. "OUTCFG68,Pin IO mode selection for GPIO pin 68" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x110 6.--7. "IRPTEN68,Interrupt enable for GPIO 68" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x110 5. "RDZERO68,Return 0 for read data on GPIO 68" "0,1"
|
|
newline
|
|
bitfld.long 0x110 4. "INPEN68,Input enable for GPIO 68" "0,1"
|
|
hexmask.long.byte 0x110 0.--3. 1. "FNCSEL68,Function select for GPIO pin 68"
|
|
line.long 0x114 "PINCFG69,Controls the operation of GPIO pin 69."
|
|
bitfld.long 0x114 27. "FOEN69,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x114 26. "FIEN69,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x114 22. "NCEPOL69,Polarity select for NCE for GPIO 69" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x114 16.--21. 1. "NCESRC69,IOMSTR/MSPI N Chip Select 69 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x114 13.--15. "PULLCFG69,Pullup/Pulldown configuration for GPIO 69" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x114 12. "SR69,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x114 10.--11. "DS69,Drive strength selection for GPIO 69" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x114 8.--9. "OUTCFG69,Pin IO mode selection for GPIO pin 69" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x114 6.--7. "IRPTEN69,Interrupt enable for GPIO 69" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x114 5. "RDZERO69,Return 0 for read data on GPIO 69" "0,1"
|
|
newline
|
|
bitfld.long 0x114 4. "INPEN69,Input enable for GPIO 69" "0,1"
|
|
hexmask.long.byte 0x114 0.--3. 1. "FNCSEL69,Function select for GPIO pin 69"
|
|
line.long 0x118 "PINCFG70,Controls the operation of GPIO pin 70."
|
|
bitfld.long 0x118 27. "FOEN70,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x118 26. "FIEN70,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x118 22. "NCEPOL70,Polarity select for NCE for GPIO 70" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x118 16.--21. 1. "NCESRC70,IOMSTR/MSPI N Chip Select 70 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x118 13.--15. "PULLCFG70,Pullup/Pulldown configuration for GPIO 70" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x118 12. "SR70,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x118 10.--11. "DS70,Drive strength selection for GPIO 70" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x118 8.--9. "OUTCFG70,Pin IO mode selection for GPIO pin 70" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x118 6.--7. "IRPTEN70,Interrupt enable for GPIO 70" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x118 5. "RDZERO70,Return 0 for read data on GPIO 70" "0,1"
|
|
newline
|
|
bitfld.long 0x118 4. "INPEN70,Input enable for GPIO 70" "0,1"
|
|
hexmask.long.byte 0x118 0.--3. 1. "FNCSEL70,Function select for GPIO pin 70"
|
|
line.long 0x11C "PINCFG71,Controls the operation of GPIO pin 71."
|
|
bitfld.long 0x11C 27. "FOEN71,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x11C 26. "FIEN71,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x11C 22. "NCEPOL71,Polarity select for NCE for GPIO 71" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x11C 16.--21. 1. "NCESRC71,IOMSTR/MSPI N Chip Select 71 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x11C 13.--15. "PULLCFG71,Pullup/Pulldown configuration for GPIO 71" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x11C 12. "SR71,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x11C 10.--11. "DS71,Drive strength selection for GPIO 71" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x11C 8.--9. "OUTCFG71,Pin IO mode selection for GPIO pin 71" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x11C 6.--7. "IRPTEN71,Interrupt enable for GPIO 71" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x11C 5. "RDZERO71,Return 0 for read data on GPIO 71" "0,1"
|
|
newline
|
|
bitfld.long 0x11C 4. "INPEN71,Input enable for GPIO 71" "0,1"
|
|
hexmask.long.byte 0x11C 0.--3. 1. "FNCSEL71,Function select for GPIO pin 71"
|
|
line.long 0x120 "PINCFG72,Controls the operation of GPIO pin 72."
|
|
bitfld.long 0x120 27. "FOEN72,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x120 26. "FIEN72,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x120 22. "NCEPOL72,Polarity select for NCE for GPIO 72" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x120 16.--21. 1. "NCESRC72,IOMSTR/MSPI N Chip Select 72 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x120 13.--15. "PULLCFG72,Pullup/Pulldown configuration for GPIO 72" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x120 12. "SR72,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x120 10.--11. "DS72,Drive strength selection for GPIO 72" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x120 8.--9. "OUTCFG72,Pin IO mode selection for GPIO pin 72" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x120 6.--7. "IRPTEN72,Interrupt enable for GPIO 72" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x120 5. "RDZERO72,Return 0 for read data on GPIO 72" "0,1"
|
|
newline
|
|
bitfld.long 0x120 4. "INPEN72,Input enable for GPIO 72" "0,1"
|
|
hexmask.long.byte 0x120 0.--3. 1. "FNCSEL72,Function select for GPIO pin 72"
|
|
line.long 0x124 "PINCFG73,Controls the operation of GPIO pin 73."
|
|
bitfld.long 0x124 27. "FOEN73,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x124 26. "FIEN73,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x124 22. "NCEPOL73,Polarity select for NCE for GPIO 73" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x124 16.--21. 1. "NCESRC73,IOMSTR/MSPI N Chip Select 73 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x124 13.--15. "PULLCFG73,Pullup/Pulldown configuration for GPIO 73" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x124 12. "SR73,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x124 10.--11. "DS73,Drive strength selection for GPIO 73" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x124 8.--9. "OUTCFG73,Pin IO mode selection for GPIO pin 73" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x124 6.--7. "IRPTEN73,Interrupt enable for GPIO 73" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x124 5. "RDZERO73,Return 0 for read data on GPIO 73" "0,1"
|
|
newline
|
|
bitfld.long 0x124 4. "INPEN73,Input enable for GPIO 73" "0,1"
|
|
hexmask.long.byte 0x124 0.--3. 1. "FNCSEL73,Function select for GPIO pin 73"
|
|
line.long 0x128 "PINCFG74,Controls the operation of GPIO pin 74."
|
|
bitfld.long 0x128 27. "FOEN74,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x128 26. "FIEN74,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x128 22. "NCEPOL74,Polarity select for NCE for GPIO 74" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x128 16.--21. 1. "NCESRC74,IOMSTR/MSPI N Chip Select 74 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x128 13.--15. "PULLCFG74,Pullup/Pulldown configuration for GPIO 74" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x128 12. "SR74,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x128 10.--11. "DS74,Drive strength selection for GPIO 74" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x128 8.--9. "OUTCFG74,Pin IO mode selection for GPIO pin 74" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x128 6.--7. "IRPTEN74,Interrupt enable for GPIO 74" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x128 5. "RDZERO74,Return 0 for read data on GPIO 74" "0,1"
|
|
newline
|
|
bitfld.long 0x128 4. "INPEN74,Input enable for GPIO 74" "0,1"
|
|
hexmask.long.byte 0x128 0.--3. 1. "FNCSEL74,Function select for GPIO pin 74"
|
|
line.long 0x12C "PINCFG75,Controls the operation of GPIO pin 75."
|
|
bitfld.long 0x12C 27. "FOEN75,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x12C 26. "FIEN75,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x12C 22. "NCEPOL75,Polarity select for NCE for GPIO 75" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x12C 16.--21. 1. "NCESRC75,IOMSTR/MSPI N Chip Select 75 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x12C 13.--15. "PULLCFG75,Pullup/Pulldown configuration for GPIO 75" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x12C 12. "SR75,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x12C 10.--11. "DS75,Drive strength selection for GPIO 75" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
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|
bitfld.long 0x12C 8.--9. "OUTCFG75,Pin IO mode selection for GPIO pin 75" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
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|
newline
|
|
bitfld.long 0x12C 6.--7. "IRPTEN75,Interrupt enable for GPIO 75" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
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bitfld.long 0x12C 5. "RDZERO75,Return 0 for read data on GPIO 75" "0,1"
|
|
newline
|
|
bitfld.long 0x12C 4. "INPEN75,Input enable for GPIO 75" "0,1"
|
|
hexmask.long.byte 0x12C 0.--3. 1. "FNCSEL75,Function select for GPIO pin 75"
|
|
line.long 0x130 "PINCFG76,Controls the operation of GPIO pin 76."
|
|
bitfld.long 0x130 27. "FOEN76,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x130 26. "FIEN76,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x130 22. "NCEPOL76,Polarity select for NCE for GPIO 76" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x130 16.--21. 1. "NCESRC76,IOMSTR/MSPI N Chip Select 76 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x130 13.--15. "PULLCFG76,Pullup/Pulldown configuration for GPIO 76" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
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|
bitfld.long 0x130 12. "SR76,Configure the slew rate" "0,1"
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|
newline
|
|
bitfld.long 0x130 10.--11. "DS76,Drive strength selection for GPIO 76" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
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|
bitfld.long 0x130 8.--9. "OUTCFG76,Pin IO mode selection for GPIO pin 76" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x130 6.--7. "IRPTEN76,Interrupt enable for GPIO 76" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
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bitfld.long 0x130 5. "RDZERO76,Return 0 for read data on GPIO 76" "0,1"
|
|
newline
|
|
bitfld.long 0x130 4. "INPEN76,Input enable for GPIO 76" "0,1"
|
|
hexmask.long.byte 0x130 0.--3. 1. "FNCSEL76,Function select for GPIO pin 76"
|
|
line.long 0x134 "PINCFG77,Controls the operation of GPIO pin 77."
|
|
bitfld.long 0x134 27. "FOEN77,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x134 26. "FIEN77,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x134 22. "NCEPOL77,Polarity select for NCE for GPIO 77" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x134 16.--21. 1. "NCESRC77,IOMSTR/MSPI N Chip Select 77 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x134 13.--15. "PULLCFG77,Pullup/Pulldown configuration for GPIO 77" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
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|
bitfld.long 0x134 12. "SR77,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x134 10.--11. "DS77,Drive strength selection for GPIO 77" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x134 8.--9. "OUTCFG77,Pin IO mode selection for GPIO pin 77" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x134 6.--7. "IRPTEN77,Interrupt enable for GPIO 77" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
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bitfld.long 0x134 5. "RDZERO77,Return 0 for read data on GPIO 77" "0,1"
|
|
newline
|
|
bitfld.long 0x134 4. "INPEN77,Input enable for GPIO 77" "0,1"
|
|
hexmask.long.byte 0x134 0.--3. 1. "FNCSEL77,Function select for GPIO pin 77"
|
|
line.long 0x138 "PINCFG78,Controls the operation of GPIO pin 78."
|
|
bitfld.long 0x138 27. "FOEN78,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x138 26. "FIEN78,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x138 22. "NCEPOL78,Polarity select for NCE for GPIO 78" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x138 16.--21. 1. "NCESRC78,IOMSTR/MSPI N Chip Select 78 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x138 13.--15. "PULLCFG78,Pullup/Pulldown configuration for GPIO 78" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
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|
bitfld.long 0x138 12. "SR78,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x138 10.--11. "DS78,Drive strength selection for GPIO 78" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x138 8.--9. "OUTCFG78,Pin IO mode selection for GPIO pin 78" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x138 6.--7. "IRPTEN78,Interrupt enable for GPIO 78" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x138 5. "RDZERO78,Return 0 for read data on GPIO 78" "0,1"
|
|
newline
|
|
bitfld.long 0x138 4. "INPEN78,Input enable for GPIO 78" "0,1"
|
|
hexmask.long.byte 0x138 0.--3. 1. "FNCSEL78,Function select for GPIO pin 78"
|
|
line.long 0x13C "PINCFG79,Controls the operation of GPIO pin 79."
|
|
bitfld.long 0x13C 27. "FOEN79,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x13C 26. "FIEN79,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x13C 22. "NCEPOL79,Polarity select for NCE for GPIO 79" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x13C 16.--21. 1. "NCESRC79,IOMSTR/MSPI N Chip Select 79 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x13C 13.--15. "PULLCFG79,Pullup/Pulldown configuration for GPIO 79" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x13C 12. "SR79,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x13C 10.--11. "DS79,Drive strength selection for GPIO 79" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
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|
bitfld.long 0x13C 8.--9. "OUTCFG79,Pin IO mode selection for GPIO pin 79" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x13C 6.--7. "IRPTEN79,Interrupt enable for GPIO 79" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x13C 5. "RDZERO79,Return 0 for read data on GPIO 79" "0,1"
|
|
newline
|
|
bitfld.long 0x13C 4. "INPEN79,Input enable for GPIO 79" "0,1"
|
|
hexmask.long.byte 0x13C 0.--3. 1. "FNCSEL79,Function select for GPIO pin 79"
|
|
line.long 0x140 "PINCFG80,Controls the operation of GPIO pin 80."
|
|
bitfld.long 0x140 27. "FOEN80,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x140 26. "FIEN80,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x140 22. "NCEPOL80,Polarity select for NCE for GPIO 80" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x140 16.--21. 1. "NCESRC80,IOMSTR/MSPI N Chip Select 80 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x140 13.--15. "PULLCFG80,Pullup/Pulldown configuration for GPIO 80" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x140 12. "SR80,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x140 10.--11. "DS80,Drive strength selection for GPIO 80" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x140 8.--9. "OUTCFG80,Pin IO mode selection for GPIO pin 80" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x140 6.--7. "IRPTEN80,Interrupt enable for GPIO 80" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x140 5. "RDZERO80,Return 0 for read data on GPIO 80" "0,1"
|
|
newline
|
|
bitfld.long 0x140 4. "INPEN80,Input enable for GPIO 80" "0,1"
|
|
hexmask.long.byte 0x140 0.--3. 1. "FNCSEL80,Function select for GPIO pin 80"
|
|
line.long 0x144 "PINCFG81,Controls the operation of GPIO pin 81."
|
|
bitfld.long 0x144 27. "FOEN81,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x144 26. "FIEN81,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x144 22. "NCEPOL81,Polarity select for NCE for GPIO 81" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x144 16.--21. 1. "NCESRC81,IOMSTR/MSPI N Chip Select 81 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x144 13.--15. "PULLCFG81,Pullup/Pulldown configuration for GPIO 81" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x144 12. "SR81,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x144 10.--11. "DS81,Drive strength selection for GPIO 81" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x144 8.--9. "OUTCFG81,Pin IO mode selection for GPIO pin 81" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x144 6.--7. "IRPTEN81,Interrupt enable for GPIO 81" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x144 5. "RDZERO81,Return 0 for read data on GPIO 81" "0,1"
|
|
newline
|
|
bitfld.long 0x144 4. "INPEN81,Input enable for GPIO 81" "0,1"
|
|
hexmask.long.byte 0x144 0.--3. 1. "FNCSEL81,Function select for GPIO pin 81"
|
|
line.long 0x148 "PINCFG82,Controls the operation of GPIO pin 82."
|
|
bitfld.long 0x148 27. "FOEN82,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x148 26. "FIEN82,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x148 22. "NCEPOL82,Polarity select for NCE for GPIO 82" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x148 16.--21. 1. "NCESRC82,IOMSTR/MSPI N Chip Select 82 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x148 13.--15. "PULLCFG82,Pullup/Pulldown configuration for GPIO 82" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x148 12. "SR82,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x148 10.--11. "DS82,Drive strength selection for GPIO 82" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x148 8.--9. "OUTCFG82,Pin IO mode selection for GPIO pin 82" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x148 6.--7. "IRPTEN82,Interrupt enable for GPIO 82" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x148 5. "RDZERO82,Return 0 for read data on GPIO 82" "0,1"
|
|
newline
|
|
bitfld.long 0x148 4. "INPEN82,Input enable for GPIO 82" "0,1"
|
|
hexmask.long.byte 0x148 0.--3. 1. "FNCSEL82,Function select for GPIO pin 82"
|
|
line.long 0x14C "PINCFG83,Controls the operation of GPIO pin 83."
|
|
bitfld.long 0x14C 27. "FOEN83,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x14C 26. "FIEN83,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x14C 22. "NCEPOL83,Polarity select for NCE for GPIO 83" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x14C 16.--21. 1. "NCESRC83,IOMSTR/MSPI N Chip Select 83 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x14C 13.--15. "PULLCFG83,Pullup/Pulldown configuration for GPIO 83" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x14C 12. "SR83,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x14C 10.--11. "DS83,Drive strength selection for GPIO 83" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x14C 8.--9. "OUTCFG83,Pin IO mode selection for GPIO pin 83" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x14C 6.--7. "IRPTEN83,Interrupt enable for GPIO 83" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x14C 5. "RDZERO83,Return 0 for read data on GPIO 83" "0,1"
|
|
newline
|
|
bitfld.long 0x14C 4. "INPEN83,Input enable for GPIO 83" "0,1"
|
|
hexmask.long.byte 0x14C 0.--3. 1. "FNCSEL83,Function select for GPIO pin 83"
|
|
line.long 0x150 "PINCFG84,Controls the operation of GPIO pin 84."
|
|
bitfld.long 0x150 27. "FOEN84,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x150 26. "FIEN84,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x150 22. "NCEPOL84,Polarity select for NCE for GPIO 84" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x150 16.--21. 1. "NCESRC84,IOMSTR/MSPI N Chip Select 84 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x150 13.--15. "PULLCFG84,Pullup/Pulldown configuration for GPIO 84" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x150 12. "SR84,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x150 10.--11. "DS84,Drive strength selection for GPIO 84" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x150 8.--9. "OUTCFG84,Pin IO mode selection for GPIO pin 84" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x150 6.--7. "IRPTEN84,Interrupt enable for GPIO 84" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x150 5. "RDZERO84,Return 0 for read data on GPIO 84" "0,1"
|
|
newline
|
|
bitfld.long 0x150 4. "INPEN84,Input enable for GPIO 84" "0,1"
|
|
hexmask.long.byte 0x150 0.--3. 1. "FNCSEL84,Function select for GPIO pin 84"
|
|
line.long 0x154 "PINCFG85,Controls the operation of GPIO pin 85."
|
|
bitfld.long 0x154 27. "FOEN85,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x154 26. "FIEN85,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x154 22. "NCEPOL85,Polarity select for NCE for GPIO 85" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x154 16.--21. 1. "NCESRC85,IOMSTR/MSPI N Chip Select 85 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x154 13.--15. "PULLCFG85,Pullup/Pulldown configuration for GPIO 85" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x154 12. "SR85,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x154 10.--11. "DS85,Drive strength selection for GPIO 85" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x154 8.--9. "OUTCFG85,Pin IO mode selection for GPIO pin 85" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x154 6.--7. "IRPTEN85,Interrupt enable for GPIO 85" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x154 5. "RDZERO85,Return 0 for read data on GPIO 85" "0,1"
|
|
newline
|
|
bitfld.long 0x154 4. "INPEN85,Input enable for GPIO 85" "0,1"
|
|
hexmask.long.byte 0x154 0.--3. 1. "FNCSEL85,Function select for GPIO pin 85"
|
|
line.long 0x158 "PINCFG86,Controls the operation of GPIO pin 86."
|
|
bitfld.long 0x158 27. "FOEN86,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x158 26. "FIEN86,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x158 22. "NCEPOL86,Polarity select for NCE for GPIO 86" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x158 16.--21. 1. "NCESRC86,IOMSTR/MSPI N Chip Select 86 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x158 13.--15. "PULLCFG86,Pullup/Pulldown configuration for GPIO 86" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x158 12. "SR86,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x158 10.--11. "DS86,Drive strength selection for GPIO 86" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x158 8.--9. "OUTCFG86,Pin IO mode selection for GPIO pin 86" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x158 6.--7. "IRPTEN86,Interrupt enable for GPIO 86" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x158 5. "RDZERO86,Return 0 for read data on GPIO 86" "0,1"
|
|
newline
|
|
bitfld.long 0x158 4. "INPEN86,Input enable for GPIO 86" "0,1"
|
|
hexmask.long.byte 0x158 0.--3. 1. "FNCSEL86,Function select for GPIO pin 86"
|
|
line.long 0x15C "PINCFG87,Controls the operation of GPIO pin 87."
|
|
bitfld.long 0x15C 27. "FOEN87,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x15C 26. "FIEN87,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x15C 22. "NCEPOL87,Polarity select for NCE for GPIO 87" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x15C 16.--21. 1. "NCESRC87,IOMSTR/MSPI N Chip Select 87 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x15C 13.--15. "PULLCFG87,Pullup/Pulldown configuration for GPIO 87" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x15C 12. "SR87,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x15C 10.--11. "DS87,Drive strength selection for GPIO 87" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x15C 8.--9. "OUTCFG87,Pin IO mode selection for GPIO pin 87" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x15C 6.--7. "IRPTEN87,Interrupt enable for GPIO 87" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x15C 5. "RDZERO87,Return 0 for read data on GPIO 87" "0,1"
|
|
newline
|
|
bitfld.long 0x15C 4. "INPEN87,Input enable for GPIO 87" "0,1"
|
|
hexmask.long.byte 0x15C 0.--3. 1. "FNCSEL87,Function select for GPIO pin 87"
|
|
line.long 0x160 "PINCFG88,Controls the operation of GPIO pin 88."
|
|
bitfld.long 0x160 27. "FOEN88,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x160 26. "FIEN88,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x160 22. "NCEPOL88,Polarity select for NCE for GPIO 88" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x160 16.--21. 1. "NCESRC88,IOMSTR/MSPI N Chip Select 88 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x160 13.--15. "PULLCFG88,Pullup/Pulldown configuration for GPIO 88" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x160 12. "SR88,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x160 10.--11. "DS88,Drive strength selection for GPIO 88" "0: 0.1x output driver selected,1: 0.5x output driver selected,2: 0.75x output driver selected,3: 1.0x output driver selected"
|
|
bitfld.long 0x160 8.--9. "OUTCFG88,Pin IO mode selection for GPIO pin 88" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x160 6.--7. "IRPTEN88,Interrupt enable for GPIO 88" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x160 5. "RDZERO88,Return 0 for read data on GPIO 88" "0,1"
|
|
newline
|
|
bitfld.long 0x160 4. "INPEN88,Input enable for GPIO 88" "0,1"
|
|
hexmask.long.byte 0x160 0.--3. 1. "FNCSEL88,Function select for GPIO pin 88"
|
|
line.long 0x164 "PINCFG89,Controls the operation of GPIO pin 89."
|
|
bitfld.long 0x164 27. "FOEN89,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x164 26. "FIEN89,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x164 22. "NCEPOL89,Polarity select for NCE for GPIO 89" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x164 16.--21. 1. "NCESRC89,IOMSTR/MSPI N Chip Select 89 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x164 13.--15. "PULLCFG89,Pullup/Pulldown configuration for GPIO 89" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x164 12. "SR89,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x164 10.--11. "DS89,Drive strength selection for GPIO 89" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0x164 8.--9. "OUTCFG89,Pin IO mode selection for GPIO pin 89" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x164 6.--7. "IRPTEN89,Interrupt enable for GPIO 89" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x164 5. "RDZERO89,Return 0 for read data on GPIO 89" "0,1"
|
|
newline
|
|
bitfld.long 0x164 4. "INPEN89,Input enable for GPIO 89" "0,1"
|
|
hexmask.long.byte 0x164 0.--3. 1. "FNCSEL89,Function select for GPIO pin 89"
|
|
line.long 0x168 "PINCFG90,Controls the operation of GPIO pin 90."
|
|
bitfld.long 0x168 27. "FOEN90,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x168 26. "FIEN90,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x168 22. "NCEPOL90,Polarity select for NCE for GPIO 90" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x168 16.--21. 1. "NCESRC90,IOMSTR/MSPI N Chip Select 90 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x168 13.--15. "PULLCFG90,Pullup/Pulldown configuration for GPIO 90" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x168 12. "SR90,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x168 10.--11. "DS90,Drive strength selection for GPIO 90" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0x168 8.--9. "OUTCFG90,Pin IO mode selection for GPIO pin 90" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x168 6.--7. "IRPTEN90,Interrupt enable for GPIO 90" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x168 5. "RDZERO90,Return 0 for read data on GPIO 90" "0,1"
|
|
newline
|
|
bitfld.long 0x168 4. "INPEN90,Input enable for GPIO 90" "0,1"
|
|
hexmask.long.byte 0x168 0.--3. 1. "FNCSEL90,Function select for GPIO pin 90"
|
|
line.long 0x16C "PINCFG91,Controls the operation of GPIO pin 91."
|
|
bitfld.long 0x16C 27. "FOEN91,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x16C 26. "FIEN91,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x16C 22. "NCEPOL91,Polarity select for NCE for GPIO 91" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x16C 16.--21. 1. "NCESRC91,IOMSTR/MSPI N Chip Select 91 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x16C 13.--15. "PULLCFG91,Pullup/Pulldown configuration for GPIO 91" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x16C 12. "SR91,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x16C 10.--11. "DS91,Drive strength selection for GPIO 91" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0x16C 8.--9. "OUTCFG91,Pin IO mode selection for GPIO pin 91" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x16C 6.--7. "IRPTEN91,Interrupt enable for GPIO 91" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x16C 5. "RDZERO91,Return 0 for read data on GPIO 91" "0,1"
|
|
newline
|
|
bitfld.long 0x16C 4. "INPEN91,Input enable for GPIO 91" "0,1"
|
|
hexmask.long.byte 0x16C 0.--3. 1. "FNCSEL91,Function select for GPIO pin 91"
|
|
line.long 0x170 "PINCFG92,Controls the operation of GPIO pin 92."
|
|
bitfld.long 0x170 27. "FOEN92,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x170 26. "FIEN92,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x170 22. "NCEPOL92,Polarity select for NCE for GPIO 92" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x170 16.--21. 1. "NCESRC92,IOMSTR/MSPI N Chip Select 92 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x170 13.--15. "PULLCFG92,Pullup/Pulldown configuration for GPIO 92" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x170 12. "SR92,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x170 10.--11. "DS92,Drive strength selection for GPIO 92" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0x170 8.--9. "OUTCFG92,Pin IO mode selection for GPIO pin 92" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x170 6.--7. "IRPTEN92,Interrupt enable for GPIO 92" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x170 5. "RDZERO92,Return 0 for read data on GPIO 92" "0,1"
|
|
newline
|
|
bitfld.long 0x170 4. "INPEN92,Input enable for GPIO 92" "0,1"
|
|
hexmask.long.byte 0x170 0.--3. 1. "FNCSEL92,Function select for GPIO pin 92"
|
|
line.long 0x174 "PINCFG93,Controls the operation of GPIO pin 93."
|
|
bitfld.long 0x174 27. "FOEN93,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x174 26. "FIEN93,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x174 22. "NCEPOL93,Polarity select for NCE for GPIO 93" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x174 16.--21. 1. "NCESRC93,IOMSTR/MSPI N Chip Select 93 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x174 13.--15. "PULLCFG93,Pullup/Pulldown configuration for GPIO 93" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x174 12. "SR93,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x174 10.--11. "DS93,Drive strength selection for GPIO 93" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0x174 8.--9. "OUTCFG93,Pin IO mode selection for GPIO pin 93" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x174 6.--7. "IRPTEN93,Interrupt enable for GPIO 93" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x174 5. "RDZERO93,Return 0 for read data on GPIO 93" "0,1"
|
|
newline
|
|
bitfld.long 0x174 4. "INPEN93,Input enable for GPIO 93" "0,1"
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x174 0.--3. 1. "FNCSEL93,Function select for GPIO pin 93"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x174 0.--3. 1. "FNCSEL93,Function select for GPIO pin 93"
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x174 0.--3. 1. "FNCSEL93,Function select for GPIO pin 93"
|
|
endif
|
|
line.long 0x178 "PINCFG94,Controls the operation of GPIO pin 94."
|
|
bitfld.long 0x178 27. "FOEN94,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x178 26. "FIEN94,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x178 22. "NCEPOL94,Polarity select for NCE for GPIO 94" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x178 16.--21. 1. "NCESRC94,IOMSTR/MSPI N Chip Select 94 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x178 13.--15. "PULLCFG94,Pullup/Pulldown configuration for GPIO 94" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x178 12. "SR94,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x178 10.--11. "DS94,Drive strength selection for GPIO 94" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0x178 8.--9. "OUTCFG94,Pin IO mode selection for GPIO pin 94" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x178 6.--7. "IRPTEN94,Interrupt enable for GPIO 94" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x178 5. "RDZERO94,Return 0 for read data on GPIO 94" "0,1"
|
|
newline
|
|
bitfld.long 0x178 4. "INPEN94,Input enable for GPIO 94" "0,1"
|
|
hexmask.long.byte 0x178 0.--3. 1. "FNCSEL94,Function select for GPIO pin 94"
|
|
line.long 0x17C "PINCFG95,Controls the operation of GPIO pin 95."
|
|
bitfld.long 0x17C 27. "FOEN95,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x17C 26. "FIEN95,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x17C 22. "NCEPOL95,Polarity select for NCE for GPIO 95" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x17C 16.--21. 1. "NCESRC95,IOMSTR/MSPI N Chip Select 95 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x17C 13.--15. "PULLCFG95,Pullup/Pulldown configuration for GPIO 95" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x17C 12. "SR95,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x17C 10.--11. "DS95,Drive strength selection for GPIO 95" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0x17C 8.--9. "OUTCFG95,Pin IO mode selection for GPIO pin 95" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x17C 6.--7. "IRPTEN95,Interrupt enable for GPIO 95" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x17C 5. "RDZERO95,Return 0 for read data on GPIO 95" "0,1"
|
|
newline
|
|
bitfld.long 0x17C 4. "INPEN95,Input enable for GPIO 95" "0,1"
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x17C 0.--3. 1. "FNCSEL95,Function select for GPIO pin 95"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x17C 0.--3. 1. "FNCSEL95,Function select for GPIO pin 95"
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x17C 0.--3. 1. "FNCSEL95,Function select for GPIO pin 95"
|
|
endif
|
|
line.long 0x180 "PINCFG96,Controls the operation of GPIO pin 96."
|
|
bitfld.long 0x180 27. "FOEN96,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x180 26. "FIEN96,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x180 22. "NCEPOL96,Polarity select for NCE for GPIO 96" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x180 16.--21. 1. "NCESRC96,IOMSTR/MSPI N Chip Select 96 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x180 13.--15. "PULLCFG96,Pullup/Pulldown configuration for GPIO 96" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x180 12. "SR96,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x180 10.--11. "DS96,Drive strength selection for GPIO 96" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0x180 8.--9. "OUTCFG96,Pin IO mode selection for GPIO pin 96" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x180 6.--7. "IRPTEN96,Interrupt enable for GPIO 96" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x180 5. "RDZERO96,Return 0 for read data on GPIO 96" "0,1"
|
|
newline
|
|
bitfld.long 0x180 4. "INPEN96,Input enable for GPIO 96" "0,1"
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x180 0.--3. 1. "FNCSEL96,Function select for GPIO pin 96"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x180 0.--3. 1. "FNCSEL96,Function select for GPIO pin 96"
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x180 0.--3. 1. "FNCSEL96,Function select for GPIO pin 96"
|
|
endif
|
|
line.long 0x184 "PINCFG97,Controls the operation of GPIO pin 97."
|
|
bitfld.long 0x184 27. "FOEN97,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x184 26. "FIEN97,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x184 22. "NCEPOL97,Polarity select for NCE for GPIO 97" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x184 16.--21. 1. "NCESRC97,IOMSTR/MSPI N Chip Select 97 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x184 13.--15. "PULLCFG97,Pullup/Pulldown configuration for GPIO 97" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x184 12. "SR97,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x184 10.--11. "DS97,Drive strength selection for GPIO 97" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0x184 8.--9. "OUTCFG97,Pin IO mode selection for GPIO pin 97" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x184 6.--7. "IRPTEN97,Interrupt enable for GPIO 97" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x184 5. "RDZERO97,Return 0 for read data on GPIO 97" "0,1"
|
|
newline
|
|
bitfld.long 0x184 4. "INPEN97,Input enable for GPIO 97" "0,1"
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x184 0.--3. 1. "FNCSEL97,Function select for GPIO pin 97"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x184 0.--3. 1. "FNCSEL97,Function select for GPIO pin 97"
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x184 0.--3. 1. "FNCSEL97,Function select for GPIO pin 97"
|
|
endif
|
|
line.long 0x188 "PINCFG98,Controls the operation of GPIO pin 98."
|
|
bitfld.long 0x188 27. "FOEN98,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x188 26. "FIEN98,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x188 22. "NCEPOL98,Polarity select for NCE for GPIO 98" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x188 16.--21. 1. "NCESRC98,IOMSTR/MSPI N Chip Select 98 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x188 13.--15. "PULLCFG98,Pullup/Pulldown configuration for GPIO 98" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x188 12. "SR98,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x188 10.--11. "DS98,Drive strength selection for GPIO 98" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0x188 8.--9. "OUTCFG98,Pin IO mode selection for GPIO pin 98" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x188 6.--7. "IRPTEN98,Interrupt enable for GPIO 98" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x188 5. "RDZERO98,Return 0 for read data on GPIO 98" "0,1"
|
|
newline
|
|
bitfld.long 0x188 4. "INPEN98,Input enable for GPIO 98" "0,1"
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x188 0.--3. 1. "FNCSEL98,Function select for GPIO pin 98"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x188 0.--3. 1. "FNCSEL98,Function select for GPIO pin 98"
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x188 0.--3. 1. "FNCSEL98,Function select for GPIO pin 98"
|
|
endif
|
|
line.long 0x18C "PINCFG99,Controls the operation of GPIO pin 99."
|
|
bitfld.long 0x18C 27. "FOEN99,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x18C 26. "FIEN99,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x18C 22. "NCEPOL99,Polarity select for NCE for GPIO 99" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x18C 16.--21. 1. "NCESRC99,IOMSTR/MSPI N Chip Select 99 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x18C 13.--15. "PULLCFG99,Pullup/Pulldown configuration for GPIO 99" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x18C 12. "SR99,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x18C 10.--11. "DS99,Drive strength selection for GPIO 99" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0x18C 8.--9. "OUTCFG99,Pin IO mode selection for GPIO pin 99" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x18C 6.--7. "IRPTEN99,Interrupt enable for GPIO 99" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x18C 5. "RDZERO99,Return 0 for read data on GPIO 99" "0,1"
|
|
newline
|
|
bitfld.long 0x18C 4. "INPEN99,Input enable for GPIO 99" "0,1"
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x18C 0.--3. 1. "FNCSEL99,Function select for GPIO pin 99"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x18C 0.--3. 1. "FNCSEL99,Function select for GPIO pin 99"
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x18C 0.--3. 1. "FNCSEL99,Function select for GPIO pin 99"
|
|
endif
|
|
line.long 0x190 "PINCFG100,Controls the operation of GPIO pin 100."
|
|
bitfld.long 0x190 27. "FOEN100,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x190 26. "FIEN100,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x190 22. "NCEPOL100,Polarity select for NCE for GPIO 100" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x190 16.--21. 1. "NCESRC100,IOMSTR/MSPI N Chip Select 100 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x190 13.--15. "PULLCFG100,Pullup/Pulldown configuration for GPIO 100" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x190 12. "SR100,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x190 10.--11. "DS100,Drive strength selection for GPIO 100" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0x190 8.--9. "OUTCFG100,Pin IO mode selection for GPIO pin 100" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x190 6.--7. "IRPTEN100,Interrupt enable for GPIO 100" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x190 5. "RDZERO100,Return 0 for read data on GPIO 100" "0,1"
|
|
newline
|
|
bitfld.long 0x190 4. "INPEN100,Input enable for GPIO 100" "0,1"
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x190 0.--3. 1. "FNCSEL100,Function select for GPIO pin 100"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x190 0.--3. 1. "FNCSEL100,Function select for GPIO pin 100"
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x190 0.--3. 1. "FNCSEL100,Function select for GPIO pin 100"
|
|
endif
|
|
line.long 0x194 "PINCFG101,Controls the operation of GPIO pin 101."
|
|
bitfld.long 0x194 27. "FOEN101,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x194 26. "FIEN101,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x194 22. "NCEPOL101,Polarity select for NCE for GPIO 101" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x194 16.--21. 1. "NCESRC101,IOMSTR/MSPI N Chip Select 101 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x194 13.--15. "PULLCFG101,Pullup/Pulldown configuration for GPIO 101" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x194 12. "SR101,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x194 10.--11. "DS101,Drive strength selection for GPIO 101" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0x194 8.--9. "OUTCFG101,Pin IO mode selection for GPIO pin 101" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x194 6.--7. "IRPTEN101,Interrupt enable for GPIO 101" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x194 5. "RDZERO101,Return 0 for read data on GPIO 101" "0,1"
|
|
newline
|
|
bitfld.long 0x194 4. "INPEN101,Input enable for GPIO 101" "0,1"
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x194 0.--3. 1. "FNCSEL101,Function select for GPIO pin 101"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x194 0.--3. 1. "FNCSEL101,Function select for GPIO pin 101"
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x194 0.--3. 1. "FNCSEL101,Function select for GPIO pin 101"
|
|
endif
|
|
line.long 0x198 "PINCFG102,Controls the operation of GPIO pin 102."
|
|
bitfld.long 0x198 27. "FOEN102,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x198 26. "FIEN102,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x198 22. "NCEPOL102,Polarity select for NCE for GPIO 102" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x198 16.--21. 1. "NCESRC102,IOMSTR/MSPI N Chip Select 102 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x198 13.--15. "PULLCFG102,Pullup/Pulldown configuration for GPIO 102" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x198 12. "SR102,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x198 10.--11. "DS102,Drive strength selection for GPIO 102" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0x198 8.--9. "OUTCFG102,Pin IO mode selection for GPIO pin 102" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x198 6.--7. "IRPTEN102,Interrupt enable for GPIO 102" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x198 5. "RDZERO102,Return 0 for read data on GPIO 102" "0,1"
|
|
newline
|
|
bitfld.long 0x198 4. "INPEN102,Input enable for GPIO 102" "0,1"
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x198 0.--3. 1. "FNCSEL102,Function select for GPIO pin 102"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x198 0.--3. 1. "FNCSEL102,Function select for GPIO pin 102"
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x198 0.--3. 1. "FNCSEL102,Function select for GPIO pin 102"
|
|
endif
|
|
line.long 0x19C "PINCFG103,Controls the operation of GPIO pin 103."
|
|
bitfld.long 0x19C 27. "FOEN103,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x19C 26. "FIEN103,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x19C 22. "NCEPOL103,Polarity select for NCE for GPIO 103" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x19C 16.--21. 1. "NCESRC103,IOMSTR/MSPI N Chip Select 103 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x19C 13.--15. "PULLCFG103,Pullup/Pulldown configuration for GPIO 103" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x19C 12. "SR103,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x19C 10.--11. "DS103,Drive strength selection for GPIO 103" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0x19C 8.--9. "OUTCFG103,Pin IO mode selection for GPIO pin 103" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x19C 6.--7. "IRPTEN103,Interrupt enable for GPIO 103" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x19C 5. "RDZERO103,Return 0 for read data on GPIO 103" "0,1"
|
|
newline
|
|
bitfld.long 0x19C 4. "INPEN103,Input enable for GPIO 103" "0,1"
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x19C 0.--3. 1. "FNCSEL103,Function select for GPIO pin 103"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x19C 0.--3. 1. "FNCSEL103,Function select for GPIO pin 103"
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x19C 0.--3. 1. "FNCSEL103,Function select for GPIO pin 103"
|
|
endif
|
|
line.long 0x1A0 "PINCFG104,Controls the operation of GPIO pin 104."
|
|
bitfld.long 0x1A0 27. "FOEN104,Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed" "0,1"
|
|
bitfld.long 0x1A0 26. "FIEN104,Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed" "0,1"
|
|
newline
|
|
bitfld.long 0x1A0 22. "NCEPOL104,Polarity select for NCE for GPIO 104" "0: Polarity is active low,1: Polarity is active high"
|
|
hexmask.long.byte 0x1A0 16.--21. 1. "NCESRC104,IOMSTR/MSPI N Chip Select 104 DISP control signals DE CSX and CS. Polarity is determined by CE_POLARITY field"
|
|
newline
|
|
bitfld.long 0x1A0 13.--15. "PULLCFG104,Pullup/Pulldown configuration for GPIO 104" "0: No pullup or pulldown selected,1: 50K Pulldown selected,2: 1.5K Pullup selected,3: 6K Pullup selected,4: 12K Pullup selected,5: 24K Pullup selected,6: 50K Pullup selected,7: 100K Pullup selected"
|
|
bitfld.long 0x1A0 12. "SR104,Configure the slew rate" "0,1"
|
|
newline
|
|
bitfld.long 0x1A0 10.--11. "DS104,Drive strength selection for GPIO 104" "0: 0.1x output driver selected,1: 0.5x output driver selected,?,?"
|
|
bitfld.long 0x1A0 8.--9. "OUTCFG104,Pin IO mode selection for GPIO pin 104" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
newline
|
|
bitfld.long 0x1A0 6.--7. "IRPTEN104,Interrupt enable for GPIO 104" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
bitfld.long 0x1A0 5. "RDZERO104,Return 0 for read data on GPIO 104" "0,1"
|
|
newline
|
|
bitfld.long 0x1A0 4. "INPEN104,Input enable for GPIO 104" "0,1"
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x1A0 0.--3. 1. "FNCSEL104,Function select for GPIO pin 104"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x1A0 0.--3. 1. "FNCSEL104,Function select for GPIO pin 104"
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x1A0 0.--3. 1. "FNCSEL104,Function select for GPIO pin 104"
|
|
endif
|
|
line.long 0x1A4 "PINCFG105,Controls the operation of virtual GPIO pin 105."
|
|
bitfld.long 0x1A4 8.--9. "OUTCFG105,Pin IO mode selection for GPIO pin 105" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
bitfld.long 0x1A4 6.--7. "IRPTEN105,Interrupt enable for GPIO 105" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
newline
|
|
bitfld.long 0x1A4 5. "RDZERO105,Return 0 for read data on GPIO 105" "0,1"
|
|
bitfld.long 0x1A4 4. "INPEN105,Input enable for GPIO 105" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1A4 0.--3. 1. "FNCSEL105,Function select for GPIO pin 105"
|
|
line.long 0x1A8 "PINCFG106,Controls the operation of virtual GPIO pin 106."
|
|
bitfld.long 0x1A8 8.--9. "OUTCFG106,Pin IO mode selection for GPIO pin 106" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
bitfld.long 0x1A8 6.--7. "IRPTEN106,Interrupt enable for GPIO 106" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
newline
|
|
bitfld.long 0x1A8 5. "RDZERO106,Return 0 for read data on GPIO 106" "0,1"
|
|
bitfld.long 0x1A8 4. "INPEN106,Input enable for GPIO 106" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1A8 0.--3. 1. "FNCSEL106,Function select for GPIO pin 106"
|
|
line.long 0x1AC "PINCFG107,Controls the operation of virtual GPIO pin 107."
|
|
bitfld.long 0x1AC 8.--9. "OUTCFG107,Pin IO mode selection for GPIO pin 107" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
bitfld.long 0x1AC 6.--7. "IRPTEN107,Interrupt enable for GPIO 107" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
newline
|
|
bitfld.long 0x1AC 5. "RDZERO107,Return 0 for read data on GPIO 107" "0,1"
|
|
bitfld.long 0x1AC 4. "INPEN107,Input enable for GPIO 107" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1AC 0.--3. 1. "FNCSEL107,Function select for GPIO pin 107"
|
|
line.long 0x1B0 "PINCFG108,Controls the operation of virtual GPIO pin 108."
|
|
bitfld.long 0x1B0 8.--9. "OUTCFG108,Pin IO mode selection for GPIO pin 108" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
bitfld.long 0x1B0 6.--7. "IRPTEN108,Interrupt enable for GPIO 108" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
newline
|
|
bitfld.long 0x1B0 5. "RDZERO108,Return 0 for read data on GPIO 108" "0,1"
|
|
bitfld.long 0x1B0 4. "INPEN108,Input enable for GPIO 108" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1B0 0.--3. 1. "FNCSEL108,Function select for GPIO pin 108"
|
|
line.long 0x1B4 "PINCFG109,Controls the operation of virtual GPIO pin 109."
|
|
bitfld.long 0x1B4 8.--9. "OUTCFG109,Pin IO mode selection for GPIO pin 109" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
bitfld.long 0x1B4 6.--7. "IRPTEN109,Interrupt enable for GPIO 109" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
newline
|
|
bitfld.long 0x1B4 5. "RDZERO109,Return 0 for read data on GPIO 109" "0,1"
|
|
bitfld.long 0x1B4 4. "INPEN109,Input enable for GPIO 109" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1B4 0.--3. 1. "FNCSEL109,Function select for GPIO pin 109"
|
|
line.long 0x1B8 "PINCFG110,Controls the operation of virtual GPIO pin 110."
|
|
bitfld.long 0x1B8 8.--9. "OUTCFG110,Pin IO mode selection for GPIO pin 110" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
bitfld.long 0x1B8 6.--7. "IRPTEN110,Interrupt enable for GPIO 110" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
newline
|
|
bitfld.long 0x1B8 5. "RDZERO110,Return 0 for read data on GPIO 110" "0,1"
|
|
bitfld.long 0x1B8 4. "INPEN110,Input enable for GPIO 110" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1B8 0.--3. 1. "FNCSEL110,Function select for GPIO pin 110"
|
|
line.long 0x1BC "PINCFG111,Controls the operation of virtual GPIO pin 111."
|
|
bitfld.long 0x1BC 8.--9. "OUTCFG111,Pin IO mode selection for GPIO pin 111" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
bitfld.long 0x1BC 6.--7. "IRPTEN111,Interrupt enable for GPIO 111" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
newline
|
|
bitfld.long 0x1BC 5. "RDZERO111,Return 0 for read data on GPIO 111" "0,1"
|
|
bitfld.long 0x1BC 4. "INPEN111,Input enable for GPIO 111" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1BC 0.--3. 1. "FNCSEL111,Function select for GPIO pin 111"
|
|
line.long 0x1C0 "PINCFG112,Controls the operation of virtual GPIO pin 112."
|
|
bitfld.long 0x1C0 8.--9. "OUTCFG112,Pin IO mode selection for GPIO pin 112" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
bitfld.long 0x1C0 6.--7. "IRPTEN112,Interrupt enable for GPIO 112" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
newline
|
|
bitfld.long 0x1C0 5. "RDZERO112,Return 0 for read data on GPIO 112" "0,1"
|
|
bitfld.long 0x1C0 4. "INPEN112,Input enable for GPIO 112" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1C0 0.--3. 1. "FNCSEL112,Function select for GPIO pin 112"
|
|
line.long 0x1C4 "PINCFG113,Controls the operation of virtual GPIO pin 113."
|
|
bitfld.long 0x1C4 8.--9. "OUTCFG113,Pin IO mode selection for GPIO pin 113" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
bitfld.long 0x1C4 6.--7. "IRPTEN113,Interrupt enable for GPIO 113" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
newline
|
|
bitfld.long 0x1C4 5. "RDZERO113,Return 0 for read data on GPIO 113" "0,1"
|
|
bitfld.long 0x1C4 4. "INPEN113,Input enable for GPIO 113" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1C4 0.--3. 1. "FNCSEL113,Function select for GPIO pin 113"
|
|
line.long 0x1C8 "PINCFG114,Controls the operation of virtual GPIO pin 114."
|
|
bitfld.long 0x1C8 8.--9. "OUTCFG114,Pin IO mode selection for GPIO pin 114" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
bitfld.long 0x1C8 6.--7. "IRPTEN114,Interrupt enable for GPIO 114" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
newline
|
|
bitfld.long 0x1C8 5. "RDZERO114,Return 0 for read data on GPIO 114" "0,1"
|
|
bitfld.long 0x1C8 4. "INPEN114,Input enable for GPIO 114" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1C8 0.--3. 1. "FNCSEL114,Function select for GPIO pin 114"
|
|
line.long 0x1CC "PINCFG115,Controls the operation of virtual GPIO pin 115."
|
|
bitfld.long 0x1CC 8.--9. "OUTCFG115,Pin IO mode selection for GPIO pin 115" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
bitfld.long 0x1CC 6.--7. "IRPTEN115,Interrupt enable for GPIO 115" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
newline
|
|
bitfld.long 0x1CC 5. "RDZERO115,Return 0 for read data on GPIO 115" "0,1"
|
|
bitfld.long 0x1CC 4. "INPEN115,Input enable for GPIO 115" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1CC 0.--3. 1. "FNCSEL115,Function select for GPIO pin 115"
|
|
line.long 0x1D0 "PINCFG116,Controls the operation of virtual GPIO pin 116."
|
|
bitfld.long 0x1D0 8.--9. "OUTCFG116,Pin IO mode selection for GPIO pin 116" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
bitfld.long 0x1D0 6.--7. "IRPTEN116,Interrupt enable for GPIO 116" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
newline
|
|
bitfld.long 0x1D0 5. "RDZERO116,Return 0 for read data on GPIO 116" "0,1"
|
|
bitfld.long 0x1D0 4. "INPEN116,Input enable for GPIO 116" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1D0 0.--3. 1. "FNCSEL116,Function select for GPIO pin 116"
|
|
line.long 0x1D4 "PINCFG117,Controls the operation of virtual GPIO pin 117."
|
|
bitfld.long 0x1D4 8.--9. "OUTCFG117,Pin IO mode selection for GPIO pin 117" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
bitfld.long 0x1D4 6.--7. "IRPTEN117,Interrupt enable for GPIO 117" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
newline
|
|
bitfld.long 0x1D4 5. "RDZERO117,Return 0 for read data on GPIO 117" "0,1"
|
|
bitfld.long 0x1D4 4. "INPEN117,Input enable for GPIO 117" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1D4 0.--3. 1. "FNCSEL117,Function select for GPIO pin 117"
|
|
line.long 0x1D8 "PINCFG118,Controls the operation of virtual GPIO pin 118."
|
|
bitfld.long 0x1D8 8.--9. "OUTCFG118,Pin IO mode selection for GPIO pin 118" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
bitfld.long 0x1D8 6.--7. "IRPTEN118,Interrupt enable for GPIO 118" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
newline
|
|
bitfld.long 0x1D8 5. "RDZERO118,Return 0 for read data on GPIO 118" "0,1"
|
|
bitfld.long 0x1D8 4. "INPEN118,Input enable for GPIO 118" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1D8 0.--3. 1. "FNCSEL118,Function select for GPIO pin 118"
|
|
line.long 0x1DC "PINCFG119,Controls the operation of virtual GPIO pin 119."
|
|
bitfld.long 0x1DC 8.--9. "OUTCFG119,Pin IO mode selection for GPIO pin 119" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
bitfld.long 0x1DC 6.--7. "IRPTEN119,Interrupt enable for GPIO 119" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
newline
|
|
bitfld.long 0x1DC 5. "RDZERO119,Return 0 for read data on GPIO 119" "0,1"
|
|
bitfld.long 0x1DC 4. "INPEN119,Input enable for GPIO 119" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1DC 0.--3. 1. "FNCSEL119,Function select for GPIO pin 119"
|
|
line.long 0x1E0 "PINCFG120,Controls the operation of virtual GPIO pin 120."
|
|
bitfld.long 0x1E0 8.--9. "OUTCFG120,Pin IO mode selection for GPIO pin 120" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
bitfld.long 0x1E0 6.--7. "IRPTEN120,Interrupt enable for GPIO 120" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
newline
|
|
bitfld.long 0x1E0 5. "RDZERO120,Return 0 for read data on GPIO 120" "0,1"
|
|
bitfld.long 0x1E0 4. "INPEN120,Input enable for GPIO 120" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1E0 0.--3. 1. "FNCSEL120,Function select for GPIO pin 120"
|
|
line.long 0x1E4 "PINCFG121,Controls the operation of virtual GPIO pin 121."
|
|
bitfld.long 0x1E4 8.--9. "OUTCFG121,Pin IO mode selection for GPIO pin 121" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
bitfld.long 0x1E4 6.--7. "IRPTEN121,Interrupt enable for GPIO 121" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
newline
|
|
bitfld.long 0x1E4 5. "RDZERO121,Return 0 for read data on GPIO 121" "0,1"
|
|
bitfld.long 0x1E4 4. "INPEN121,Input enable for GPIO 121" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1E4 0.--3. 1. "FNCSEL121,Function select for GPIO pin 121"
|
|
line.long 0x1E8 "PINCFG122,Controls the operation of virtual GPIO pin 122."
|
|
bitfld.long 0x1E8 8.--9. "OUTCFG122,Pin IO mode selection for GPIO pin 122" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
bitfld.long 0x1E8 6.--7. "IRPTEN122,Interrupt enable for GPIO 122" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
newline
|
|
bitfld.long 0x1E8 5. "RDZERO122,Return 0 for read data on GPIO 122" "0,1"
|
|
bitfld.long 0x1E8 4. "INPEN122,Input enable for GPIO 122" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1E8 0.--3. 1. "FNCSEL122,Function select for GPIO pin 122"
|
|
line.long 0x1EC "PINCFG123,Controls the operation of virtual GPIO pin 123."
|
|
bitfld.long 0x1EC 8.--9. "OUTCFG123,Pin IO mode selection for GPIO pin 123" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
bitfld.long 0x1EC 6.--7. "IRPTEN123,Interrupt enable for GPIO 123" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
newline
|
|
bitfld.long 0x1EC 5. "RDZERO123,Return 0 for read data on GPIO 123" "0,1"
|
|
bitfld.long 0x1EC 4. "INPEN123,Input enable for GPIO 123" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1EC 0.--3. 1. "FNCSEL123,Function select for GPIO pin 123"
|
|
line.long 0x1F0 "PINCFG124,Controls the operation of virtual GPIO pin 124."
|
|
bitfld.long 0x1F0 8.--9. "OUTCFG124,Pin IO mode selection for GPIO pin 124" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
bitfld.long 0x1F0 6.--7. "IRPTEN124,Interrupt enable for GPIO 124" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
newline
|
|
bitfld.long 0x1F0 5. "RDZERO124,Return 0 for read data on GPIO 124" "0,1"
|
|
bitfld.long 0x1F0 4. "INPEN124,Input enable for GPIO 124" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1F0 0.--3. 1. "FNCSEL124,Function select for GPIO pin 124"
|
|
line.long 0x1F4 "PINCFG125,Controls the operation of virtual GPIO pin 125."
|
|
bitfld.long 0x1F4 8.--9. "OUTCFG125,Pin IO mode selection for GPIO pin 125" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
bitfld.long 0x1F4 6.--7. "IRPTEN125,Interrupt enable for GPIO 125" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
newline
|
|
bitfld.long 0x1F4 5. "RDZERO125,Return 0 for read data on GPIO 125" "0,1"
|
|
bitfld.long 0x1F4 4. "INPEN125,Input enable for GPIO 125" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1F4 0.--3. 1. "FNCSEL125,Function select for GPIO pin 125"
|
|
line.long 0x1F8 "PINCFG126,Controls the operation of virtual GPIO pin 126."
|
|
bitfld.long 0x1F8 8.--9. "OUTCFG126,Pin IO mode selection for GPIO pin 126" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
bitfld.long 0x1F8 6.--7. "IRPTEN126,Interrupt enable for GPIO 126" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
newline
|
|
bitfld.long 0x1F8 5. "RDZERO126,Return 0 for read data on GPIO 126" "0,1"
|
|
bitfld.long 0x1F8 4. "INPEN126,Input enable for GPIO 126" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1F8 0.--3. 1. "FNCSEL126,Function select for GPIO pin 126"
|
|
line.long 0x1FC "PINCFG127,Controls the operation of virtual GPIO pin 127."
|
|
bitfld.long 0x1FC 8.--9. "OUTCFG127,Pin IO mode selection for GPIO pin 127" "0: Output Disabled,1: Output configured in push pull mode. Will drive..,2: Output configured in open drain mode. Will only..,3: Output configured in Tristate-able push pull.."
|
|
bitfld.long 0x1FC 6.--7. "IRPTEN127,Interrupt enable for GPIO 127" "0: Interrupts are disabled for this GPIO,1: Interrupts are enabled for falling edge..,2: Interrupts are enabled for rising edge..,3: Interrupts are enabled for any edge transition.."
|
|
newline
|
|
bitfld.long 0x1FC 5. "RDZERO127,Return 0 for read data on GPIO 127" "0,1"
|
|
bitfld.long 0x1FC 4. "INPEN127,Input enable for GPIO 127" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1FC 0.--3. 1. "FNCSEL127,Function select for GPIO pin 127"
|
|
line.long 0x200 "PADKEY,Lock state of the PINCFG and GPIO configuration registers. Write a value of 0x73 to unlock write access to the PAD and GPIO."
|
|
hexmask.long 0x200 0.--31. 1. "PADKEY,Key register value."
|
|
line.long 0x204 "RD0,GPIO Input 0 (31-0)"
|
|
hexmask.long 0x204 0.--31. 1. "RD0,GPIO31-0 Reads pin state - read only. Returns the pad pin state for pins 0-31 if the PINCFG's input enable (INPEN) is active and RDZERO is inactive."
|
|
line.long 0x208 "RD1,GPIO Input 1 (63-32)"
|
|
hexmask.long 0x208 0.--31. 1. "RD1,GPIO63-32 Reads pin state - read only. Returns the pad pin state for pins 0-31 if the PINCFG's input enable (INPEN) is active and RDZERO is inactive."
|
|
line.long 0x20C "RD2,GPIO Input 2 (95-64)"
|
|
hexmask.long 0x20C 0.--31. 1. "RD2,GPIO95-64 Reads pin state - read only. Returns the pad pin state for pins 0-31 if the PINCFG's input enable (INPEN) is active and RDZERO is inactive."
|
|
line.long 0x210 "RD3,GPIO Input 3 (127-96)"
|
|
hexmask.long 0x210 0.--31. 1. "RD3,GPIO127-96 Reads pin state - read only. Returns the pad pin state for pins 0-31 if the PINCFG's input enable (INPEN) is active and RDZERO is inactive."
|
|
line.long 0x214 "WT0,GPIO Output 0 (31-0)"
|
|
hexmask.long 0x214 0.--31. 1. "WT0,GPIO31-0 Reads or writes pin state. Writes of 1 bits set output pad signal if the GPIO is enabled for output. Reads return status including sets/clears through the WTS and WTC registers."
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line.long 0x218 "WT1,GPIO Output 1 (63-32)"
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hexmask.long 0x218 0.--31. 1. "WT1,GPIO63-32 Reads or writes pin state. Writes of 1 bits set output pad signal if the GPIO is enabled for output. Reads return status including sets/clears through the WTS and WTC registers."
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line.long 0x21C "WT2,GPIO Output 2 (95-64)"
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hexmask.long 0x21C 0.--31. 1. "WT2,GPIO95-64 Reads or writes pin state. Writes of 1 bits set output pad signal if the GPIO is enabled for output. Reads return status including sets/clears through the WTS and WTC registers."
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line.long 0x220 "WT3,GPIO Output 3 (127-96)"
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hexmask.long 0x220 0.--31. 1. "WT3,GPIO127-96 Reads or writes pin state. Writes of 1 bits set output pad signal if the GPIO is enabled for output. Reads return status including sets/clears through the WTS and WTC registers."
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|
line.long 0x224 "WTS0,GPIO Output Set 0 (31-0)"
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hexmask.long 0x224 0.--31. 1. "WTS0,GPIO31-0 Sets pin state. Writing a 1 to any bit sets the corresponding bit in the WT register if the GPIO is enabled for output. Writing a value of 0 has no effect on the corresponding bit in the WT register. Status reads should be made via the WT.."
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|
line.long 0x228 "WTS1,GPIO Output Set 1 (63-32)"
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hexmask.long 0x228 0.--31. 1. "WTS1,GPIO63-32 Sets pin state. Writing a 1 to any bit sets the corresponding bit in the WT register if the GPIO is enabled for output. Writing a value of 0 has no effect on the corresponding bit in the WT register. Status reads should be made via the WT.."
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line.long 0x22C "WTS2,GPIO Output Set 2 (95-64)"
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hexmask.long 0x22C 0.--31. 1. "WTS2,GPIO95-64 Sets pin state. Writing a 1 to any bit sets the corresponding bit in the WT register if the GPIO is enabled for output. Writing a value of 0 has no effect on the corresponding bit in the WT register. Status reads should be made via the WT.."
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line.long 0x230 "WTS3,GPIO Output Set 3 (127-96)"
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hexmask.long 0x230 0.--31. 1. "WTS3,GPIO127-96 Sets pin state. Writing a 1 to any bit sets the corresponding bit in the WT register if the GPIO is enabled for output. Writing a value of 0 has no effect on the corresponding bit in the WT register. Status reads should be made via the WT.."
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|
line.long 0x234 "WTC0,GPIO Output Clear 0 (31-0)"
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hexmask.long 0x234 0.--31. 1. "WTC0,GPIO31-0 Clears pin state. Writing a 1 to any bit clears the corresponding bit in the WT register if the GPIO is enabled for output. Writing a value of 0 has no effect on the corresponding bit in the WT register. Status reads should be made via the.."
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|
line.long 0x238 "WTC1,GPIO Output Clear 1 (63-32)"
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|
hexmask.long 0x238 0.--31. 1. "WTC1,GPIO63-32 Clears pin state. Writing a 1 to any bit clears the corresponding bit in the WT register if the GPIO is enabled for output. Writing a value of 0 has no effect on the corresponding bit in the WT register. Status reads should be made via the.."
|
|
line.long 0x23C "WTC2,GPIO Output Clear 2 (95-64)"
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hexmask.long 0x23C 0.--31. 1. "WTC2,GPIO95-64 Clears pin state. Writing a 1 to any bit clears the corresponding bit in the WT register if the GPIO is enabled for output. Writing a value of 0 has no effect on the corresponding bit in the WT register. Status reads should be made via the.."
|
|
line.long 0x240 "WTC3,GPIO Output Clear 3 (127-96)"
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hexmask.long 0x240 0.--31. 1. "WTC3,GPIO127-96 Clears pin state. Writing a 1 to any bit clears the corresponding bit in the WT register if the GPIO is enabled for output. Writing a value of 0 has no effect on the corresponding bit in the WT register. Status reads should be made via.."
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|
line.long 0x244 "EN0,GPIO Enable 0 (31-0)"
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|
hexmask.long 0x244 0.--31. 1. "EN0,GPIO31-0 Enables tri-state pin output. Writing a 1 to any bit enables and writing a 0 to any bit disables the output for the corresponding GPIO. Reads return output enable/disable status of GPIO."
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|
line.long 0x248 "EN1,GPIO Enable 1 (63-32)"
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|
hexmask.long 0x248 0.--31. 1. "EN1,GPIO63-32 Enables tri-state pin output. Writing a 1 to any bit enables and writing a 0 to any bit disables the output for the corresponding GPIO. Reads return output enable/disable status of GPIO."
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line.long 0x24C "EN2,GPIO Enable 2 (95-64)"
|
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hexmask.long 0x24C 0.--31. 1. "EN2,GPIO95-64 Enables tri-state pin output. Writing a 1 to any bit enables and writing a 0 to any bit disables the output for the corresponding GPIO. Reads return output enable/disable status of GPIO."
|
|
line.long 0x250 "EN3,GPIO Enable 3 (127-96)"
|
|
hexmask.long 0x250 0.--31. 1. "EN3,GPIO127-96 Enables tri-state pin output. Writing a 1 to any bit enables and writing a 0 to any bit disables the output for the corresponding GPIO. Reads return output enable/disable status of GPIO."
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line.long 0x254 "ENS0,GPIO Enable Set 0 (31-0)"
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hexmask.long 0x254 0.--31. 1. "ENS0,GPIO31-0 Sets pin tri-state output enables. Writing a 1 to any bit sets the corresponding bit in the EN register. Writing a value of 0 has no effect on the corresponding bit in the EN register. Status reads should be made to the EN Register."
|
|
line.long 0x258 "ENS1,GPIO Enable Set 1 (63-32)"
|
|
hexmask.long 0x258 0.--31. 1. "ENS1,GPIO63-32 Sets pin tri-state output enables. Writing a 1 to any bit sets the corresponding bit in the EN register. Writing a value of 0 has no effect on the corresponding bit in the EN register. Status reads should be made to the EN Register."
|
|
line.long 0x25C "ENS2,GPIO Enable Set 2 (95-64)"
|
|
hexmask.long 0x25C 0.--31. 1. "ENS2,GPIO95-64 Sets pin tri-state output enables. Writing a 1 to any bit sets the corresponding bit in the EN register. Writing a value of 0 has no effect on the corresponding bit in the EN register. Status reads should be made to the EN Register."
|
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line.long 0x260 "ENS3,GPIO Enable Set 3 (127-96)"
|
|
hexmask.long 0x260 0.--31. 1. "ENS3,GPIO127-96 Sets pin tri-state output enables. Writing a 1 to any bit sets the corresponding bit in the EN register. Writing a value of 0 has no effect on the corresponding bit in the EN register. Status reads should be made to the EN Register."
|
|
line.long 0x264 "ENC0,GPIO Enable Clear 0 (31-0)"
|
|
hexmask.long 0x264 0.--31. 1. "ENC0,GPIO31-0 Clears pin tri-state output enables. Writing a 1 to any bit clears the corresponding bit in the EN register. Writing a value of 0 has no effect on the corresponding bit in the EN register. Status reads should be made to the EN Register."
|
|
line.long 0x268 "ENC1,GPIO Enable Clear 1 (63-32)"
|
|
hexmask.long 0x268 0.--31. 1. "ENC1,GPIO63-32 Clears pin tri-state output enables. Writing a 1 to any bit clears the corresponding bit in the EN register. Writing a value of 0 has no effect on the corresponding bit in the EN register. Status reads should be made to the EN Register."
|
|
line.long 0x26C "ENC2,GPIO Enable Clear 2 (95-64)"
|
|
hexmask.long 0x26C 0.--31. 1. "ENC2,GPIO95-64 Clears pin tri-state output enables. Writing a 1 to any bit clears the corresponding bit in the EN register. Writing a value of 0 has no effect on the corresponding bit in the EN register. Status reads should be made to the EN Register."
|
|
line.long 0x270 "ENC3,GPIO Enable Clear 3 (127-96)"
|
|
hexmask.long 0x270 0.--31. 1. "ENC3,GPIO127-96 Clears pin tri-state output enables. Writing a 1 to any bit clears the corresponding bit in the EN register. Writing a value of 0 has no effect on the corresponding bit in the EN register. Status reads should be made to the EN Register."
|
|
line.long 0x274 "IOM0IRQ,IOM0 IRQ select for flow control."
|
|
hexmask.long.byte 0x274 0.--6. 1. "IOM0IRQ,IOM0 IRQ pad select."
|
|
line.long 0x278 "IOM1IRQ,IOM1 IRQ select for flow control."
|
|
hexmask.long.byte 0x278 0.--6. 1. "IOM1IRQ,IOM1 IRQ pad select."
|
|
line.long 0x27C "IOM2IRQ,IOM2 IRQ select for flow control."
|
|
hexmask.long.byte 0x27C 0.--6. 1. "IOM2IRQ,IOM2 IRQ pad select."
|
|
line.long 0x280 "IOM3IRQ,IOM3 IRQ select for flow control."
|
|
hexmask.long.byte 0x280 0.--6. 1. "IOM3IRQ,IOM3 IRQ pad select."
|
|
line.long 0x284 "IOM4IRQ,IOM4 IRQ select for flow control."
|
|
hexmask.long.byte 0x284 0.--6. 1. "IOM4IRQ,IOM4 IRQ pad select."
|
|
line.long 0x288 "IOM5IRQ,IOM5 IRQ select for flow control."
|
|
hexmask.long.byte 0x288 0.--6. 1. "IOM5IRQ,IOM5 IRQ pad select."
|
|
line.long 0x28C "IOM6IRQ,IOM6 IRQ select for flow control."
|
|
hexmask.long.byte 0x28C 0.--6. 1. "IOM6IRQ,IOM6 IRQ pad select."
|
|
line.long 0x290 "IOM7IRQ,IOM7 IRQ select for flow control."
|
|
hexmask.long.byte 0x290 0.--6. 1. "IOM7IRQ,IOM7 IRQ pad select."
|
|
line.long 0x294 "SDIFCDWP,SDIF CD and WP Select."
|
|
hexmask.long.byte 0x294 8.--14. 1. "SDIFWP,SDIF WP pad select."
|
|
hexmask.long.byte 0x294 0.--6. 1. "SDIFCD,SDIF CD pad select."
|
|
line.long 0x298 "OBSDATA,GPIO Observation mode sample"
|
|
hexmask.long.word 0x298 0.--15. 1. "OBSDATA,Sample of the data output on the GPIO observation port. May have async sampling issues as the data is not synronized to the read operation. Intended for debug purposes only."
|
|
line.long 0x29C "IEOBS0,Read only. Reflects the value of the input enable signals for pads 31-0 sent to the pad."
|
|
hexmask.long 0x29C 0.--31. 1. "IEDATA0,1 indicates the input_en is active and the value of the pad will be trasmitted to the internal logic within the device."
|
|
line.long 0x2A0 "IEOBS1,Read only. Reflects the value of the input enable signals for pads 63-32 sent to the pad."
|
|
hexmask.long 0x2A0 0.--31. 1. "IEDATA1,1 indicates the input_en is active and the value of the pad will be trasmitted to the internal logic within the device."
|
|
line.long 0x2A4 "IEOBS2,Read only. Reflects the value of the input enable signals for pads 95-64 sent to the pad."
|
|
hexmask.long 0x2A4 0.--31. 1. "IEDATA2,1 indicates the input_en is active and the value of the pad will be trasmitted to the internal logic within the device."
|
|
line.long 0x2A8 "IEOBS3,Read only. Reflects the value of the input enable signals for pads 127-96 sent to the pad."
|
|
hexmask.long 0x2A8 0.--31. 1. "IEDATA3,1 indicates the input_en is active and the value of the pad will be trasmitted to the internal logic within the device."
|
|
line.long 0x2AC "OEOBS0,Read only. Reflects the value of the output enable signals for pads 31-0 sent to the pad."
|
|
hexmask.long 0x2AC 0.--31. 1. "OEDATA0,The signal is negative active and a value of 0 indicates the output_en_ is active and the MCU will be driving the pad."
|
|
line.long 0x2B0 "OEOBS1,Read only. Reflects the value of the output enable signals for pads 63-32 sent to the pad."
|
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hexmask.long 0x2B0 0.--31. 1. "OEDATA1,The signal is negative active and a value of 0 indicates the output_en_ is active and the MCU will be driving the pad."
|
|
line.long 0x2B4 "OEOBS2,Read only. Reflects the value of the output enable signals for pads 95-64 sent to the pad."
|
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hexmask.long 0x2B4 0.--31. 1. "OEDATA2,The signal is negative active and a value of 0 indicates the output_en_ is active and the MCU will be driving the pad."
|
|
line.long 0x2B8 "OEOBS3,Read only. Reflects the value of the output enable signals for pads 127-96 sent to the pad."
|
|
hexmask.long 0x2B8 0.--31. 1. "OEDATA3,The signal is negative active and a value of 0 indicates the output_en_ is active and the MCU will be driving the pad."
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|
group.long 0x2C0++0x17F
|
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line.long 0x0 "MCUN0INT0EN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 31. "MCUN0GPIO31,GPIO31 MCU N0-priority interrupt." "0: priority interrupt,?"
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|
bitfld.long 0x0 30. "MCUN0GPIO30,GPIO30 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x0 29. "MCUN0GPIO29,GPIO29 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x0 28. "MCUN0GPIO28,GPIO28 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x0 27. "MCUN0GPIO27,GPIO27 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x0 26. "MCUN0GPIO26,GPIO26 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x0 25. "MCUN0GPIO25,GPIO25 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x0 24. "MCUN0GPIO24,GPIO24 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x0 23. "MCUN0GPIO23,GPIO23 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x0 22. "MCUN0GPIO22,GPIO22 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x0 21. "MCUN0GPIO21,GPIO21 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x0 20. "MCUN0GPIO20,GPIO20 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x0 19. "MCUN0GPIO19,GPIO19 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x0 18. "MCUN0GPIO18,GPIO18 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x0 17. "MCUN0GPIO17,GPIO17 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x0 16. "MCUN0GPIO16,GPIO16 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x0 15. "MCUN0GPIO15,GPIO15 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x0 14. "MCUN0GPIO14,GPIO14 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x0 13. "MCUN0GPIO13,GPIO13 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x0 12. "MCUN0GPIO12,GPIO12 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x0 11. "MCUN0GPIO11,GPIO11 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x0 10. "MCUN0GPIO10,GPIO10 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x0 9. "MCUN0GPIO9,GPIO9 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x0 8. "MCUN0GPIO8,GPIO8 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x0 7. "MCUN0GPIO7,GPIO7 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x0 6. "MCUN0GPIO6,GPIO6 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x0 5. "MCUN0GPIO5,GPIO5 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x0 4. "MCUN0GPIO4,GPIO4 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x0 3. "MCUN0GPIO3,GPIO3 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x0 2. "MCUN0GPIO2,GPIO2 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x0 1. "MCUN0GPIO1,GPIO1 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x0 0. "MCUN0GPIO0,GPIO0 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x4 "MCUN0INT0STAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 31. "MCUN0GPIO31,GPIO31 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x4 30. "MCUN0GPIO30,GPIO30 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x4 29. "MCUN0GPIO29,GPIO29 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x4 28. "MCUN0GPIO28,GPIO28 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x4 27. "MCUN0GPIO27,GPIO27 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x4 26. "MCUN0GPIO26,GPIO26 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x4 25. "MCUN0GPIO25,GPIO25 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x4 24. "MCUN0GPIO24,GPIO24 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x4 23. "MCUN0GPIO23,GPIO23 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x4 22. "MCUN0GPIO22,GPIO22 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x4 21. "MCUN0GPIO21,GPIO21 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x4 20. "MCUN0GPIO20,GPIO20 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x4 19. "MCUN0GPIO19,GPIO19 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x4 18. "MCUN0GPIO18,GPIO18 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x4 17. "MCUN0GPIO17,GPIO17 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x4 16. "MCUN0GPIO16,GPIO16 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x4 15. "MCUN0GPIO15,GPIO15 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x4 14. "MCUN0GPIO14,GPIO14 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x4 13. "MCUN0GPIO13,GPIO13 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x4 12. "MCUN0GPIO12,GPIO12 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x4 11. "MCUN0GPIO11,GPIO11 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x4 10. "MCUN0GPIO10,GPIO10 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x4 9. "MCUN0GPIO9,GPIO9 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x4 8. "MCUN0GPIO8,GPIO8 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x4 7. "MCUN0GPIO7,GPIO7 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x4 6. "MCUN0GPIO6,GPIO6 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x4 5. "MCUN0GPIO5,GPIO5 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x4 4. "MCUN0GPIO4,GPIO4 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x4 3. "MCUN0GPIO3,GPIO3 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x4 2. "MCUN0GPIO2,GPIO2 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x4 1. "MCUN0GPIO1,GPIO1 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x4 0. "MCUN0GPIO0,GPIO0 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x8 "MCUN0INT0CLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 31. "MCUN0GPIO31,GPIO31 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x8 30. "MCUN0GPIO30,GPIO30 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x8 29. "MCUN0GPIO29,GPIO29 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x8 28. "MCUN0GPIO28,GPIO28 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x8 27. "MCUN0GPIO27,GPIO27 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x8 26. "MCUN0GPIO26,GPIO26 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x8 25. "MCUN0GPIO25,GPIO25 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x8 24. "MCUN0GPIO24,GPIO24 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x8 23. "MCUN0GPIO23,GPIO23 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x8 22. "MCUN0GPIO22,GPIO22 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x8 21. "MCUN0GPIO21,GPIO21 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x8 20. "MCUN0GPIO20,GPIO20 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x8 19. "MCUN0GPIO19,GPIO19 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x8 18. "MCUN0GPIO18,GPIO18 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x8 17. "MCUN0GPIO17,GPIO17 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x8 16. "MCUN0GPIO16,GPIO16 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x8 15. "MCUN0GPIO15,GPIO15 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x8 14. "MCUN0GPIO14,GPIO14 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x8 13. "MCUN0GPIO13,GPIO13 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x8 12. "MCUN0GPIO12,GPIO12 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x8 11. "MCUN0GPIO11,GPIO11 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x8 10. "MCUN0GPIO10,GPIO10 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x8 9. "MCUN0GPIO9,GPIO9 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x8 8. "MCUN0GPIO8,GPIO8 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x8 7. "MCUN0GPIO7,GPIO7 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x8 6. "MCUN0GPIO6,GPIO6 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x8 5. "MCUN0GPIO5,GPIO5 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x8 4. "MCUN0GPIO4,GPIO4 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x8 3. "MCUN0GPIO3,GPIO3 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x8 2. "MCUN0GPIO2,GPIO2 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x8 1. "MCUN0GPIO1,GPIO1 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x8 0. "MCUN0GPIO0,GPIO0 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0xC "MCUN0INT0SET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 31. "MCUN0GPIO31,GPIO31 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xC 30. "MCUN0GPIO30,GPIO30 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xC 29. "MCUN0GPIO29,GPIO29 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xC 28. "MCUN0GPIO28,GPIO28 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xC 27. "MCUN0GPIO27,GPIO27 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xC 26. "MCUN0GPIO26,GPIO26 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xC 25. "MCUN0GPIO25,GPIO25 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xC 24. "MCUN0GPIO24,GPIO24 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0xC 23. "MCUN0GPIO23,GPIO23 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xC 22. "MCUN0GPIO22,GPIO22 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xC 21. "MCUN0GPIO21,GPIO21 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xC 20. "MCUN0GPIO20,GPIO20 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xC 19. "MCUN0GPIO19,GPIO19 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xC 18. "MCUN0GPIO18,GPIO18 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xC 17. "MCUN0GPIO17,GPIO17 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xC 16. "MCUN0GPIO16,GPIO16 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xC 15. "MCUN0GPIO15,GPIO15 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xC 14. "MCUN0GPIO14,GPIO14 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xC 13. "MCUN0GPIO13,GPIO13 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xC 12. "MCUN0GPIO12,GPIO12 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xC 11. "MCUN0GPIO11,GPIO11 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xC 10. "MCUN0GPIO10,GPIO10 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xC 9. "MCUN0GPIO9,GPIO9 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xC 8. "MCUN0GPIO8,GPIO8 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xC 7. "MCUN0GPIO7,GPIO7 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xC 6. "MCUN0GPIO6,GPIO6 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xC 5. "MCUN0GPIO5,GPIO5 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xC 4. "MCUN0GPIO4,GPIO4 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xC 3. "MCUN0GPIO3,GPIO3 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xC 2. "MCUN0GPIO2,GPIO2 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xC 1. "MCUN0GPIO1,GPIO1 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xC 0. "MCUN0GPIO0,GPIO0 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x10 "MCUN0INT1EN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x10 31. "MCUN0GPIO63,GPIO63 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x10 30. "MCUN0GPIO62,GPIO62 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x10 29. "MCUN0GPIO61,GPIO61 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x10 28. "MCUN0GPIO60,GPIO60 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x10 27. "MCUN0GPIO59,GPIO59 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x10 26. "MCUN0GPIO58,GPIO58 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x10 25. "MCUN0GPIO57,GPIO57 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x10 24. "MCUN0GPIO56,GPIO56 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x10 23. "MCUN0GPIO55,GPIO55 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x10 22. "MCUN0GPIO54,GPIO54 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x10 21. "MCUN0GPIO53,GPIO53 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x10 20. "MCUN0GPIO52,GPIO52 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x10 19. "MCUN0GPIO51,GPIO51 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x10 18. "MCUN0GPIO50,GPIO50 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x10 17. "MCUN0GPIO49,GPIO49 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x10 16. "MCUN0GPIO48,GPIO48 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x10 15. "MCUN0GPIO47,GPIO47 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x10 14. "MCUN0GPIO46,GPIO46 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x10 13. "MCUN0GPIO45,GPIO45 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x10 12. "MCUN0GPIO44,GPIO44 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x10 11. "MCUN0GPIO43,GPIO43 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x10 10. "MCUN0GPIO42,GPIO42 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x10 9. "MCUN0GPIO41,GPIO41 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x10 8. "MCUN0GPIO40,GPIO40 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x10 7. "MCUN0GPIO39,GPIO39 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x10 6. "MCUN0GPIO38,GPIO38 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x10 5. "MCUN0GPIO37,GPIO37 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x10 4. "MCUN0GPIO36,GPIO36 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x10 3. "MCUN0GPIO35,GPIO35 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x10 2. "MCUN0GPIO34,GPIO34 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x10 1. "MCUN0GPIO33,GPIO33 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x10 0. "MCUN0GPIO32,GPIO32 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x14 "MCUN0INT1STAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x14 31. "MCUN0GPIO63,GPIO63 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x14 30. "MCUN0GPIO62,GPIO62 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x14 29. "MCUN0GPIO61,GPIO61 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x14 28. "MCUN0GPIO60,GPIO60 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x14 27. "MCUN0GPIO59,GPIO59 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x14 26. "MCUN0GPIO58,GPIO58 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x14 25. "MCUN0GPIO57,GPIO57 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x14 24. "MCUN0GPIO56,GPIO56 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x14 23. "MCUN0GPIO55,GPIO55 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x14 22. "MCUN0GPIO54,GPIO54 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x14 21. "MCUN0GPIO53,GPIO53 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x14 20. "MCUN0GPIO52,GPIO52 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x14 19. "MCUN0GPIO51,GPIO51 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x14 18. "MCUN0GPIO50,GPIO50 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x14 17. "MCUN0GPIO49,GPIO49 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x14 16. "MCUN0GPIO48,GPIO48 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x14 15. "MCUN0GPIO47,GPIO47 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x14 14. "MCUN0GPIO46,GPIO46 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x14 13. "MCUN0GPIO45,GPIO45 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x14 12. "MCUN0GPIO44,GPIO44 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x14 11. "MCUN0GPIO43,GPIO43 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x14 10. "MCUN0GPIO42,GPIO42 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x14 9. "MCUN0GPIO41,GPIO41 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x14 8. "MCUN0GPIO40,GPIO40 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x14 7. "MCUN0GPIO39,GPIO39 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x14 6. "MCUN0GPIO38,GPIO38 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x14 5. "MCUN0GPIO37,GPIO37 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x14 4. "MCUN0GPIO36,GPIO36 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x14 3. "MCUN0GPIO35,GPIO35 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x14 2. "MCUN0GPIO34,GPIO34 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x14 1. "MCUN0GPIO33,GPIO33 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x14 0. "MCUN0GPIO32,GPIO32 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x18 "MCUN0INT1CLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x18 31. "MCUN0GPIO63,GPIO63 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x18 30. "MCUN0GPIO62,GPIO62 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x18 29. "MCUN0GPIO61,GPIO61 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x18 28. "MCUN0GPIO60,GPIO60 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x18 27. "MCUN0GPIO59,GPIO59 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x18 26. "MCUN0GPIO58,GPIO58 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x18 25. "MCUN0GPIO57,GPIO57 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x18 24. "MCUN0GPIO56,GPIO56 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x18 23. "MCUN0GPIO55,GPIO55 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x18 22. "MCUN0GPIO54,GPIO54 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x18 21. "MCUN0GPIO53,GPIO53 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x18 20. "MCUN0GPIO52,GPIO52 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x18 19. "MCUN0GPIO51,GPIO51 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x18 18. "MCUN0GPIO50,GPIO50 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x18 17. "MCUN0GPIO49,GPIO49 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x18 16. "MCUN0GPIO48,GPIO48 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x18 15. "MCUN0GPIO47,GPIO47 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x18 14. "MCUN0GPIO46,GPIO46 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x18 13. "MCUN0GPIO45,GPIO45 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x18 12. "MCUN0GPIO44,GPIO44 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x18 11. "MCUN0GPIO43,GPIO43 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x18 10. "MCUN0GPIO42,GPIO42 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x18 9. "MCUN0GPIO41,GPIO41 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x18 8. "MCUN0GPIO40,GPIO40 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x18 7. "MCUN0GPIO39,GPIO39 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x18 6. "MCUN0GPIO38,GPIO38 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x18 5. "MCUN0GPIO37,GPIO37 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x18 4. "MCUN0GPIO36,GPIO36 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x18 3. "MCUN0GPIO35,GPIO35 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x18 2. "MCUN0GPIO34,GPIO34 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x18 1. "MCUN0GPIO33,GPIO33 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x18 0. "MCUN0GPIO32,GPIO32 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x1C "MCUN0INT1SET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0x1C 31. "MCUN0GPIO63,GPIO63 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x1C 30. "MCUN0GPIO62,GPIO62 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x1C 29. "MCUN0GPIO61,GPIO61 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x1C 28. "MCUN0GPIO60,GPIO60 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x1C 27. "MCUN0GPIO59,GPIO59 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x1C 26. "MCUN0GPIO58,GPIO58 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x1C 25. "MCUN0GPIO57,GPIO57 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x1C 24. "MCUN0GPIO56,GPIO56 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x1C 23. "MCUN0GPIO55,GPIO55 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x1C 22. "MCUN0GPIO54,GPIO54 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x1C 21. "MCUN0GPIO53,GPIO53 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x1C 20. "MCUN0GPIO52,GPIO52 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x1C 19. "MCUN0GPIO51,GPIO51 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x1C 18. "MCUN0GPIO50,GPIO50 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x1C 17. "MCUN0GPIO49,GPIO49 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x1C 16. "MCUN0GPIO48,GPIO48 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x1C 15. "MCUN0GPIO47,GPIO47 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x1C 14. "MCUN0GPIO46,GPIO46 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x1C 13. "MCUN0GPIO45,GPIO45 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x1C 12. "MCUN0GPIO44,GPIO44 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x1C 11. "MCUN0GPIO43,GPIO43 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x1C 10. "MCUN0GPIO42,GPIO42 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x1C 9. "MCUN0GPIO41,GPIO41 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x1C 8. "MCUN0GPIO40,GPIO40 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x1C 7. "MCUN0GPIO39,GPIO39 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x1C 6. "MCUN0GPIO38,GPIO38 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x1C 5. "MCUN0GPIO37,GPIO37 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x1C 4. "MCUN0GPIO36,GPIO36 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x1C 3. "MCUN0GPIO35,GPIO35 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x1C 2. "MCUN0GPIO34,GPIO34 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x1C 1. "MCUN0GPIO33,GPIO33 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x1C 0. "MCUN0GPIO32,GPIO32 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x20 "MCUN0INT2EN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x20 31. "MCUN0GPIO95,GPIO95 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x20 30. "MCUN0GPIO94,GPIO94 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x20 29. "MCUN0GPIO93,GPIO93 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x20 28. "MCUN0GPIO92,GPIO92 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x20 27. "MCUN0GPIO91,GPIO91 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x20 26. "MCUN0GPIO90,GPIO90 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x20 25. "MCUN0GPIO89,GPIO89 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x20 24. "MCUN0GPIO88,GPIO88 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x20 23. "MCUN0GPIO87,GPIO87 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x20 22. "MCUN0GPIO86,GPIO86 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x20 21. "MCUN0GPIO85,GPIO85 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x20 20. "MCUN0GPIO84,GPIO84 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x20 19. "MCUN0GPIO83,GPIO83 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x20 18. "MCUN0GPIO82,GPIO82 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x20 17. "MCUN0GPIO81,GPIO81 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x20 16. "MCUN0GPIO80,GPIO80 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x20 15. "MCUN0GPIO79,GPIO79 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x20 14. "MCUN0GPIO78,GPIO78 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x20 13. "MCUN0GPIO77,GPIO77 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x20 12. "MCUN0GPIO76,GPIO76 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x20 11. "MCUN0GPIO75,GPIO75 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x20 10. "MCUN0GPIO74,GPIO74 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x20 9. "MCUN0GPIO73,GPIO73 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x20 8. "MCUN0GPIO72,GPIO72 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x20 7. "MCUN0GPIO71,GPIO71 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x20 6. "MCUN0GPIO70,GPIO70 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x20 5. "MCUN0GPIO69,GPIO69 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x20 4. "MCUN0GPIO68,GPIO68 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x20 3. "MCUN0GPIO67,GPIO67 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x20 2. "MCUN0GPIO66,GPIO66 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x20 1. "MCUN0GPIO65,GPIO65 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x20 0. "MCUN0GPIO64,GPIO64 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x24 "MCUN0INT2STAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x24 31. "MCUN0GPIO95,GPIO95 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x24 30. "MCUN0GPIO94,GPIO94 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x24 29. "MCUN0GPIO93,GPIO93 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x24 28. "MCUN0GPIO92,GPIO92 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x24 27. "MCUN0GPIO91,GPIO91 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x24 26. "MCUN0GPIO90,GPIO90 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x24 25. "MCUN0GPIO89,GPIO89 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x24 24. "MCUN0GPIO88,GPIO88 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x24 23. "MCUN0GPIO87,GPIO87 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x24 22. "MCUN0GPIO86,GPIO86 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x24 21. "MCUN0GPIO85,GPIO85 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x24 20. "MCUN0GPIO84,GPIO84 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x24 19. "MCUN0GPIO83,GPIO83 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x24 18. "MCUN0GPIO82,GPIO82 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x24 17. "MCUN0GPIO81,GPIO81 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x24 16. "MCUN0GPIO80,GPIO80 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x24 15. "MCUN0GPIO79,GPIO79 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x24 14. "MCUN0GPIO78,GPIO78 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x24 13. "MCUN0GPIO77,GPIO77 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x24 12. "MCUN0GPIO76,GPIO76 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x24 11. "MCUN0GPIO75,GPIO75 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x24 10. "MCUN0GPIO74,GPIO74 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x24 9. "MCUN0GPIO73,GPIO73 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x24 8. "MCUN0GPIO72,GPIO72 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x24 7. "MCUN0GPIO71,GPIO71 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x24 6. "MCUN0GPIO70,GPIO70 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x24 5. "MCUN0GPIO69,GPIO69 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x24 4. "MCUN0GPIO68,GPIO68 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x24 3. "MCUN0GPIO67,GPIO67 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x24 2. "MCUN0GPIO66,GPIO66 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x24 1. "MCUN0GPIO65,GPIO65 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x24 0. "MCUN0GPIO64,GPIO64 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x28 "MCUN0INT2CLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x28 31. "MCUN0GPIO95,GPIO95 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x28 30. "MCUN0GPIO94,GPIO94 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x28 29. "MCUN0GPIO93,GPIO93 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x28 28. "MCUN0GPIO92,GPIO92 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x28 27. "MCUN0GPIO91,GPIO91 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x28 26. "MCUN0GPIO90,GPIO90 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x28 25. "MCUN0GPIO89,GPIO89 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x28 24. "MCUN0GPIO88,GPIO88 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x28 23. "MCUN0GPIO87,GPIO87 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x28 22. "MCUN0GPIO86,GPIO86 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x28 21. "MCUN0GPIO85,GPIO85 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x28 20. "MCUN0GPIO84,GPIO84 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x28 19. "MCUN0GPIO83,GPIO83 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x28 18. "MCUN0GPIO82,GPIO82 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x28 17. "MCUN0GPIO81,GPIO81 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x28 16. "MCUN0GPIO80,GPIO80 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x28 15. "MCUN0GPIO79,GPIO79 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x28 14. "MCUN0GPIO78,GPIO78 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x28 13. "MCUN0GPIO77,GPIO77 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x28 12. "MCUN0GPIO76,GPIO76 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x28 11. "MCUN0GPIO75,GPIO75 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x28 10. "MCUN0GPIO74,GPIO74 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x28 9. "MCUN0GPIO73,GPIO73 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x28 8. "MCUN0GPIO72,GPIO72 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x28 7. "MCUN0GPIO71,GPIO71 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x28 6. "MCUN0GPIO70,GPIO70 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x28 5. "MCUN0GPIO69,GPIO69 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x28 4. "MCUN0GPIO68,GPIO68 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x28 3. "MCUN0GPIO67,GPIO67 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x28 2. "MCUN0GPIO66,GPIO66 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x28 1. "MCUN0GPIO65,GPIO65 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x28 0. "MCUN0GPIO64,GPIO64 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x2C "MCUN0INT2SET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0x2C 31. "MCUN0GPIO95,GPIO95 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x2C 30. "MCUN0GPIO94,GPIO94 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x2C 29. "MCUN0GPIO93,GPIO93 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x2C 28. "MCUN0GPIO92,GPIO92 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x2C 27. "MCUN0GPIO91,GPIO91 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x2C 26. "MCUN0GPIO90,GPIO90 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x2C 25. "MCUN0GPIO89,GPIO89 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x2C 24. "MCUN0GPIO88,GPIO88 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x2C 23. "MCUN0GPIO87,GPIO87 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x2C 22. "MCUN0GPIO86,GPIO86 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x2C 21. "MCUN0GPIO85,GPIO85 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x2C 20. "MCUN0GPIO84,GPIO84 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x2C 19. "MCUN0GPIO83,GPIO83 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x2C 18. "MCUN0GPIO82,GPIO82 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x2C 17. "MCUN0GPIO81,GPIO81 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x2C 16. "MCUN0GPIO80,GPIO80 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x2C 15. "MCUN0GPIO79,GPIO79 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x2C 14. "MCUN0GPIO78,GPIO78 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x2C 13. "MCUN0GPIO77,GPIO77 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x2C 12. "MCUN0GPIO76,GPIO76 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x2C 11. "MCUN0GPIO75,GPIO75 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x2C 10. "MCUN0GPIO74,GPIO74 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x2C 9. "MCUN0GPIO73,GPIO73 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x2C 8. "MCUN0GPIO72,GPIO72 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x2C 7. "MCUN0GPIO71,GPIO71 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x2C 6. "MCUN0GPIO70,GPIO70 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x2C 5. "MCUN0GPIO69,GPIO69 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x2C 4. "MCUN0GPIO68,GPIO68 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x2C 3. "MCUN0GPIO67,GPIO67 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x2C 2. "MCUN0GPIO66,GPIO66 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x2C 1. "MCUN0GPIO65,GPIO65 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x2C 0. "MCUN0GPIO64,GPIO64 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x30 "MCUN0INT3EN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x30 31. "MCUN0GPIO127,GPIO127 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x30 30. "MCUN0GPIO126,GPIO126 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x30 29. "MCUN0GPIO125,GPIO125 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x30 28. "MCUN0GPIO124,GPIO124 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x30 27. "MCUN0GPIO123,GPIO123 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x30 26. "MCUN0GPIO122,GPIO122 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x30 25. "MCUN0GPIO121,GPIO121 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x30 24. "MCUN0GPIO120,GPIO120 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x30 23. "MCUN0GPIO119,GPIO119 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x30 22. "MCUN0GPIO118,GPIO118 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x30 21. "MCUN0GPIO117,GPIO117 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x30 20. "MCUN0GPIO116,GPIO116 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x30 19. "MCUN0GPIO115,GPIO115 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x30 18. "MCUN0GPIO114,GPIO114 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x30 17. "MCUN0GPIO113,GPIO113 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x30 16. "MCUN0GPIO112,GPIO112 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x30 15. "MCUN0GPIO111,GPIO111 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x30 14. "MCUN0GPIO110,GPIO110 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x30 13. "MCUN0GPIO109,GPIO109 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x30 12. "MCUN0GPIO108,GPIO108 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x30 11. "MCUN0GPIO107,GPIO107 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x30 10. "MCUN0GPIO106,GPIO106 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x30 9. "MCUN0GPIO105,GPIO105 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x30 8. "MCUN0GPIO104,GPIO104 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x30 7. "MCUN0GPIO103,GPIO103 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x30 6. "MCUN0GPIO102,GPIO102 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x30 5. "MCUN0GPIO101,GPIO101 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x30 4. "MCUN0GPIO100,GPIO100 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x30 3. "MCUN0GPIO99,GPIO99 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x30 2. "MCUN0GPIO98,GPIO98 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x30 1. "MCUN0GPIO97,GPIO97 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x30 0. "MCUN0GPIO96,GPIO96 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x34 "MCUN0INT3STAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x34 31. "MCUN0GPIO127,GPIO127 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x34 30. "MCUN0GPIO126,GPIO126 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x34 29. "MCUN0GPIO125,GPIO125 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x34 28. "MCUN0GPIO124,GPIO124 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x34 27. "MCUN0GPIO123,GPIO123 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x34 26. "MCUN0GPIO122,GPIO122 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x34 25. "MCUN0GPIO121,GPIO121 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x34 24. "MCUN0GPIO120,GPIO120 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x34 23. "MCUN0GPIO119,GPIO119 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x34 22. "MCUN0GPIO118,GPIO118 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x34 21. "MCUN0GPIO117,GPIO117 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x34 20. "MCUN0GPIO116,GPIO116 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x34 19. "MCUN0GPIO115,GPIO115 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x34 18. "MCUN0GPIO114,GPIO114 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x34 17. "MCUN0GPIO113,GPIO113 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x34 16. "MCUN0GPIO112,GPIO112 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x34 15. "MCUN0GPIO111,GPIO111 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x34 14. "MCUN0GPIO110,GPIO110 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x34 13. "MCUN0GPIO109,GPIO109 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x34 12. "MCUN0GPIO108,GPIO108 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x34 11. "MCUN0GPIO107,GPIO107 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x34 10. "MCUN0GPIO106,GPIO106 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x34 9. "MCUN0GPIO105,GPIO105 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x34 8. "MCUN0GPIO104,GPIO104 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x34 7. "MCUN0GPIO103,GPIO103 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x34 6. "MCUN0GPIO102,GPIO102 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x34 5. "MCUN0GPIO101,GPIO101 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x34 4. "MCUN0GPIO100,GPIO100 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x34 3. "MCUN0GPIO99,GPIO99 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x34 2. "MCUN0GPIO98,GPIO98 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x34 1. "MCUN0GPIO97,GPIO97 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x34 0. "MCUN0GPIO96,GPIO96 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x38 "MCUN0INT3CLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x38 31. "MCUN0GPIO127,GPIO127 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x38 30. "MCUN0GPIO126,GPIO126 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x38 29. "MCUN0GPIO125,GPIO125 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x38 28. "MCUN0GPIO124,GPIO124 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x38 27. "MCUN0GPIO123,GPIO123 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x38 26. "MCUN0GPIO122,GPIO122 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x38 25. "MCUN0GPIO121,GPIO121 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x38 24. "MCUN0GPIO120,GPIO120 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x38 23. "MCUN0GPIO119,GPIO119 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x38 22. "MCUN0GPIO118,GPIO118 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x38 21. "MCUN0GPIO117,GPIO117 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x38 20. "MCUN0GPIO116,GPIO116 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x38 19. "MCUN0GPIO115,GPIO115 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x38 18. "MCUN0GPIO114,GPIO114 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x38 17. "MCUN0GPIO113,GPIO113 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x38 16. "MCUN0GPIO112,GPIO112 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x38 15. "MCUN0GPIO111,GPIO111 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x38 14. "MCUN0GPIO110,GPIO110 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x38 13. "MCUN0GPIO109,GPIO109 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x38 12. "MCUN0GPIO108,GPIO108 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x38 11. "MCUN0GPIO107,GPIO107 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x38 10. "MCUN0GPIO106,GPIO106 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x38 9. "MCUN0GPIO105,GPIO105 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x38 8. "MCUN0GPIO104,GPIO104 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x38 7. "MCUN0GPIO103,GPIO103 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x38 6. "MCUN0GPIO102,GPIO102 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x38 5. "MCUN0GPIO101,GPIO101 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x38 4. "MCUN0GPIO100,GPIO100 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x38 3. "MCUN0GPIO99,GPIO99 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x38 2. "MCUN0GPIO98,GPIO98 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x38 1. "MCUN0GPIO97,GPIO97 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x38 0. "MCUN0GPIO96,GPIO96 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x3C "MCUN0INT3SET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0x3C 31. "MCUN0GPIO127,GPIO127 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x3C 30. "MCUN0GPIO126,GPIO126 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x3C 29. "MCUN0GPIO125,GPIO125 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x3C 28. "MCUN0GPIO124,GPIO124 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x3C 27. "MCUN0GPIO123,GPIO123 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x3C 26. "MCUN0GPIO122,GPIO122 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x3C 25. "MCUN0GPIO121,GPIO121 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x3C 24. "MCUN0GPIO120,GPIO120 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x3C 23. "MCUN0GPIO119,GPIO119 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x3C 22. "MCUN0GPIO118,GPIO118 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x3C 21. "MCUN0GPIO117,GPIO117 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x3C 20. "MCUN0GPIO116,GPIO116 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x3C 19. "MCUN0GPIO115,GPIO115 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x3C 18. "MCUN0GPIO114,GPIO114 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x3C 17. "MCUN0GPIO113,GPIO113 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x3C 16. "MCUN0GPIO112,GPIO112 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x3C 15. "MCUN0GPIO111,GPIO111 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x3C 14. "MCUN0GPIO110,GPIO110 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x3C 13. "MCUN0GPIO109,GPIO109 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x3C 12. "MCUN0GPIO108,GPIO108 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x3C 11. "MCUN0GPIO107,GPIO107 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x3C 10. "MCUN0GPIO106,GPIO106 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x3C 9. "MCUN0GPIO105,GPIO105 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x3C 8. "MCUN0GPIO104,GPIO104 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x3C 7. "MCUN0GPIO103,GPIO103 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x3C 6. "MCUN0GPIO102,GPIO102 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x3C 5. "MCUN0GPIO101,GPIO101 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x3C 4. "MCUN0GPIO100,GPIO100 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x3C 3. "MCUN0GPIO99,GPIO99 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x3C 2. "MCUN0GPIO98,GPIO98 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x3C 1. "MCUN0GPIO97,GPIO97 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x3C 0. "MCUN0GPIO96,GPIO96 MCU N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x40 "MCUN1INT0EN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x40 31. "MCUN1GPIO31,GPIO31 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x40 30. "MCUN1GPIO30,GPIO30 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x40 29. "MCUN1GPIO29,GPIO29 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x40 28. "MCUN1GPIO28,GPIO28 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x40 27. "MCUN1GPIO27,GPIO27 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x40 26. "MCUN1GPIO26,GPIO26 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x40 25. "MCUN1GPIO25,GPIO25 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x40 24. "MCUN1GPIO24,GPIO24 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x40 23. "MCUN1GPIO23,GPIO23 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x40 22. "MCUN1GPIO22,GPIO22 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x40 21. "MCUN1GPIO21,GPIO21 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x40 20. "MCUN1GPIO20,GPIO20 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x40 19. "MCUN1GPIO19,GPIO19 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x40 18. "MCUN1GPIO18,GPIO18 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x40 17. "MCUN1GPIO17,GPIO17 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x40 16. "MCUN1GPIO16,GPIO16 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x40 15. "MCUN1GPIO15,GPIO15 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x40 14. "MCUN1GPIO14,GPIO14 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x40 13. "MCUN1GPIO13,GPIO13 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x40 12. "MCUN1GPIO12,GPIO12 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x40 11. "MCUN1GPIO11,GPIO11 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x40 10. "MCUN1GPIO10,GPIO10 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x40 9. "MCUN1GPIO9,GPIO9 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x40 8. "MCUN1GPIO8,GPIO8 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x40 7. "MCUN1GPIO7,GPIO7 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x40 6. "MCUN1GPIO6,GPIO6 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x40 5. "MCUN1GPIO5,GPIO5 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x40 4. "MCUN1GPIO4,GPIO4 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x40 3. "MCUN1GPIO3,GPIO3 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x40 2. "MCUN1GPIO2,GPIO2 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x40 1. "MCUN1GPIO1,GPIO1 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x40 0. "MCUN1GPIO0,GPIO0 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
line.long 0x44 "MCUN1INT0STAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x44 31. "MCUN1GPIO31,GPIO31 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x44 30. "MCUN1GPIO30,GPIO30 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x44 29. "MCUN1GPIO29,GPIO29 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x44 28. "MCUN1GPIO28,GPIO28 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x44 27. "MCUN1GPIO27,GPIO27 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x44 26. "MCUN1GPIO26,GPIO26 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x44 25. "MCUN1GPIO25,GPIO25 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x44 24. "MCUN1GPIO24,GPIO24 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x44 23. "MCUN1GPIO23,GPIO23 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x44 22. "MCUN1GPIO22,GPIO22 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x44 21. "MCUN1GPIO21,GPIO21 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x44 20. "MCUN1GPIO20,GPIO20 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x44 19. "MCUN1GPIO19,GPIO19 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x44 18. "MCUN1GPIO18,GPIO18 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x44 17. "MCUN1GPIO17,GPIO17 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x44 16. "MCUN1GPIO16,GPIO16 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x44 15. "MCUN1GPIO15,GPIO15 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x44 14. "MCUN1GPIO14,GPIO14 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x44 13. "MCUN1GPIO13,GPIO13 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x44 12. "MCUN1GPIO12,GPIO12 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x44 11. "MCUN1GPIO11,GPIO11 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x44 10. "MCUN1GPIO10,GPIO10 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x44 9. "MCUN1GPIO9,GPIO9 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x44 8. "MCUN1GPIO8,GPIO8 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x44 7. "MCUN1GPIO7,GPIO7 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x44 6. "MCUN1GPIO6,GPIO6 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x44 5. "MCUN1GPIO5,GPIO5 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x44 4. "MCUN1GPIO4,GPIO4 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x44 3. "MCUN1GPIO3,GPIO3 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x44 2. "MCUN1GPIO2,GPIO2 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x44 1. "MCUN1GPIO1,GPIO1 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x44 0. "MCUN1GPIO0,GPIO0 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
line.long 0x48 "MCUN1INT0CLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x48 31. "MCUN1GPIO31,GPIO31 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x48 30. "MCUN1GPIO30,GPIO30 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x48 29. "MCUN1GPIO29,GPIO29 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x48 28. "MCUN1GPIO28,GPIO28 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x48 27. "MCUN1GPIO27,GPIO27 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x48 26. "MCUN1GPIO26,GPIO26 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x48 25. "MCUN1GPIO25,GPIO25 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x48 24. "MCUN1GPIO24,GPIO24 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x48 23. "MCUN1GPIO23,GPIO23 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x48 22. "MCUN1GPIO22,GPIO22 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x48 21. "MCUN1GPIO21,GPIO21 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x48 20. "MCUN1GPIO20,GPIO20 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x48 19. "MCUN1GPIO19,GPIO19 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x48 18. "MCUN1GPIO18,GPIO18 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x48 17. "MCUN1GPIO17,GPIO17 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x48 16. "MCUN1GPIO16,GPIO16 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x48 15. "MCUN1GPIO15,GPIO15 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x48 14. "MCUN1GPIO14,GPIO14 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x48 13. "MCUN1GPIO13,GPIO13 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x48 12. "MCUN1GPIO12,GPIO12 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x48 11. "MCUN1GPIO11,GPIO11 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x48 10. "MCUN1GPIO10,GPIO10 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x48 9. "MCUN1GPIO9,GPIO9 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x48 8. "MCUN1GPIO8,GPIO8 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x48 7. "MCUN1GPIO7,GPIO7 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x48 6. "MCUN1GPIO6,GPIO6 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x48 5. "MCUN1GPIO5,GPIO5 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x48 4. "MCUN1GPIO4,GPIO4 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x48 3. "MCUN1GPIO3,GPIO3 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x48 2. "MCUN1GPIO2,GPIO2 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x48 1. "MCUN1GPIO1,GPIO1 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x48 0. "MCUN1GPIO0,GPIO0 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
line.long 0x4C "MCUN1INT0SET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0x4C 31. "MCUN1GPIO31,GPIO31 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x4C 30. "MCUN1GPIO30,GPIO30 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x4C 29. "MCUN1GPIO29,GPIO29 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x4C 28. "MCUN1GPIO28,GPIO28 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x4C 27. "MCUN1GPIO27,GPIO27 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x4C 26. "MCUN1GPIO26,GPIO26 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x4C 25. "MCUN1GPIO25,GPIO25 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x4C 24. "MCUN1GPIO24,GPIO24 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x4C 23. "MCUN1GPIO23,GPIO23 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x4C 22. "MCUN1GPIO22,GPIO22 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x4C 21. "MCUN1GPIO21,GPIO21 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x4C 20. "MCUN1GPIO20,GPIO20 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x4C 19. "MCUN1GPIO19,GPIO19 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x4C 18. "MCUN1GPIO18,GPIO18 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x4C 17. "MCUN1GPIO17,GPIO17 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x4C 16. "MCUN1GPIO16,GPIO16 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x4C 15. "MCUN1GPIO15,GPIO15 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x4C 14. "MCUN1GPIO14,GPIO14 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x4C 13. "MCUN1GPIO13,GPIO13 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x4C 12. "MCUN1GPIO12,GPIO12 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x4C 11. "MCUN1GPIO11,GPIO11 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x4C 10. "MCUN1GPIO10,GPIO10 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x4C 9. "MCUN1GPIO9,GPIO9 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x4C 8. "MCUN1GPIO8,GPIO8 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x4C 7. "MCUN1GPIO7,GPIO7 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x4C 6. "MCUN1GPIO6,GPIO6 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x4C 5. "MCUN1GPIO5,GPIO5 MCU N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x4C 4. "MCUN1GPIO4,GPIO4 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x4C 3. "MCUN1GPIO3,GPIO3 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x4C 2. "MCUN1GPIO2,GPIO2 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x4C 1. "MCUN1GPIO1,GPIO1 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x4C 0. "MCUN1GPIO0,GPIO0 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
line.long 0x50 "MCUN1INT1EN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x50 31. "MCUN1GPIO63,GPIO63 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x50 30. "MCUN1GPIO62,GPIO62 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x50 29. "MCUN1GPIO61,GPIO61 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x50 28. "MCUN1GPIO60,GPIO60 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x50 27. "MCUN1GPIO59,GPIO59 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x50 26. "MCUN1GPIO58,GPIO58 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x50 25. "MCUN1GPIO57,GPIO57 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x50 24. "MCUN1GPIO56,GPIO56 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x50 23. "MCUN1GPIO55,GPIO55 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x50 22. "MCUN1GPIO54,GPIO54 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x50 21. "MCUN1GPIO53,GPIO53 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x50 20. "MCUN1GPIO52,GPIO52 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x50 19. "MCUN1GPIO51,GPIO51 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x50 18. "MCUN1GPIO50,GPIO50 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x50 17. "MCUN1GPIO49,GPIO49 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x50 16. "MCUN1GPIO48,GPIO48 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x50 15. "MCUN1GPIO47,GPIO47 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x50 14. "MCUN1GPIO46,GPIO46 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x50 13. "MCUN1GPIO45,GPIO45 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x50 12. "MCUN1GPIO44,GPIO44 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x50 11. "MCUN1GPIO43,GPIO43 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x50 10. "MCUN1GPIO42,GPIO42 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x50 9. "MCUN1GPIO41,GPIO41 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x50 8. "MCUN1GPIO40,GPIO40 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x50 7. "MCUN1GPIO39,GPIO39 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x50 6. "MCUN1GPIO38,GPIO38 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x50 5. "MCUN1GPIO37,GPIO37 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x50 4. "MCUN1GPIO36,GPIO36 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x50 3. "MCUN1GPIO35,GPIO35 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x50 2. "MCUN1GPIO34,GPIO34 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x50 1. "MCUN1GPIO33,GPIO33 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x50 0. "MCUN1GPIO32,GPIO32 MCU N1-priority interrupt." "?,1: priority interrupt"
|
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line.long 0x54 "MCUN1INT1STAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x54 31. "MCUN1GPIO63,GPIO63 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x54 30. "MCUN1GPIO62,GPIO62 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x54 29. "MCUN1GPIO61,GPIO61 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x54 28. "MCUN1GPIO60,GPIO60 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x54 27. "MCUN1GPIO59,GPIO59 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x54 26. "MCUN1GPIO58,GPIO58 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x54 25. "MCUN1GPIO57,GPIO57 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x54 24. "MCUN1GPIO56,GPIO56 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x54 23. "MCUN1GPIO55,GPIO55 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x54 22. "MCUN1GPIO54,GPIO54 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x54 21. "MCUN1GPIO53,GPIO53 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x54 20. "MCUN1GPIO52,GPIO52 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x54 19. "MCUN1GPIO51,GPIO51 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x54 18. "MCUN1GPIO50,GPIO50 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x54 17. "MCUN1GPIO49,GPIO49 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x54 16. "MCUN1GPIO48,GPIO48 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x54 15. "MCUN1GPIO47,GPIO47 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x54 14. "MCUN1GPIO46,GPIO46 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x54 13. "MCUN1GPIO45,GPIO45 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x54 12. "MCUN1GPIO44,GPIO44 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x54 11. "MCUN1GPIO43,GPIO43 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x54 10. "MCUN1GPIO42,GPIO42 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x54 9. "MCUN1GPIO41,GPIO41 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x54 8. "MCUN1GPIO40,GPIO40 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x54 7. "MCUN1GPIO39,GPIO39 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x54 6. "MCUN1GPIO38,GPIO38 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x54 5. "MCUN1GPIO37,GPIO37 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x54 4. "MCUN1GPIO36,GPIO36 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x54 3. "MCUN1GPIO35,GPIO35 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x54 2. "MCUN1GPIO34,GPIO34 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x54 1. "MCUN1GPIO33,GPIO33 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x54 0. "MCUN1GPIO32,GPIO32 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
line.long 0x58 "MCUN1INT1CLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x58 31. "MCUN1GPIO63,GPIO63 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x58 30. "MCUN1GPIO62,GPIO62 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x58 29. "MCUN1GPIO61,GPIO61 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x58 28. "MCUN1GPIO60,GPIO60 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x58 27. "MCUN1GPIO59,GPIO59 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x58 26. "MCUN1GPIO58,GPIO58 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x58 25. "MCUN1GPIO57,GPIO57 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x58 24. "MCUN1GPIO56,GPIO56 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x58 23. "MCUN1GPIO55,GPIO55 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x58 22. "MCUN1GPIO54,GPIO54 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x58 21. "MCUN1GPIO53,GPIO53 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x58 20. "MCUN1GPIO52,GPIO52 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x58 19. "MCUN1GPIO51,GPIO51 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x58 18. "MCUN1GPIO50,GPIO50 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x58 17. "MCUN1GPIO49,GPIO49 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x58 16. "MCUN1GPIO48,GPIO48 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x58 15. "MCUN1GPIO47,GPIO47 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x58 14. "MCUN1GPIO46,GPIO46 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x58 13. "MCUN1GPIO45,GPIO45 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x58 12. "MCUN1GPIO44,GPIO44 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x58 11. "MCUN1GPIO43,GPIO43 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x58 10. "MCUN1GPIO42,GPIO42 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x58 9. "MCUN1GPIO41,GPIO41 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x58 8. "MCUN1GPIO40,GPIO40 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x58 7. "MCUN1GPIO39,GPIO39 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x58 6. "MCUN1GPIO38,GPIO38 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x58 5. "MCUN1GPIO37,GPIO37 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x58 4. "MCUN1GPIO36,GPIO36 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x58 3. "MCUN1GPIO35,GPIO35 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x58 2. "MCUN1GPIO34,GPIO34 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x58 1. "MCUN1GPIO33,GPIO33 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x58 0. "MCUN1GPIO32,GPIO32 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
line.long 0x5C "MCUN1INT1SET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0x5C 31. "MCUN1GPIO63,GPIO63 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x5C 30. "MCUN1GPIO62,GPIO62 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x5C 29. "MCUN1GPIO61,GPIO61 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x5C 28. "MCUN1GPIO60,GPIO60 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x5C 27. "MCUN1GPIO59,GPIO59 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x5C 26. "MCUN1GPIO58,GPIO58 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x5C 25. "MCUN1GPIO57,GPIO57 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x5C 24. "MCUN1GPIO56,GPIO56 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x5C 23. "MCUN1GPIO55,GPIO55 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x5C 22. "MCUN1GPIO54,GPIO54 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x5C 21. "MCUN1GPIO53,GPIO53 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x5C 20. "MCUN1GPIO52,GPIO52 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x5C 19. "MCUN1GPIO51,GPIO51 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x5C 18. "MCUN1GPIO50,GPIO50 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x5C 17. "MCUN1GPIO49,GPIO49 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x5C 16. "MCUN1GPIO48,GPIO48 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x5C 15. "MCUN1GPIO47,GPIO47 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x5C 14. "MCUN1GPIO46,GPIO46 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x5C 13. "MCUN1GPIO45,GPIO45 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x5C 12. "MCUN1GPIO44,GPIO44 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x5C 11. "MCUN1GPIO43,GPIO43 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x5C 10. "MCUN1GPIO42,GPIO42 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x5C 9. "MCUN1GPIO41,GPIO41 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x5C 8. "MCUN1GPIO40,GPIO40 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x5C 7. "MCUN1GPIO39,GPIO39 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x5C 6. "MCUN1GPIO38,GPIO38 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x5C 5. "MCUN1GPIO37,GPIO37 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x5C 4. "MCUN1GPIO36,GPIO36 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x5C 3. "MCUN1GPIO35,GPIO35 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x5C 2. "MCUN1GPIO34,GPIO34 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x5C 1. "MCUN1GPIO33,GPIO33 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x5C 0. "MCUN1GPIO32,GPIO32 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
line.long 0x60 "MCUN1INT2EN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x60 31. "MCUN1GPIO95,GPIO95 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x60 30. "MCUN1GPIO94,GPIO94 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x60 29. "MCUN1GPIO93,GPIO93 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x60 28. "MCUN1GPIO92,GPIO92 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x60 27. "MCUN1GPIO91,GPIO91 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x60 26. "MCUN1GPIO90,GPIO90 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x60 25. "MCUN1GPIO89,GPIO89 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x60 24. "MCUN1GPIO88,GPIO88 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x60 23. "MCUN1GPIO87,GPIO87 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x60 22. "MCUN1GPIO86,GPIO86 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x60 21. "MCUN1GPIO85,GPIO85 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x60 20. "MCUN1GPIO84,GPIO84 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x60 19. "MCUN1GPIO83,GPIO83 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x60 18. "MCUN1GPIO82,GPIO82 MCU N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0x60 17. "MCUN1GPIO81,GPIO81 MCU N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x60 16. "MCUN1GPIO80,GPIO80 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x60 15. "MCUN1GPIO79,GPIO79 MCU N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x60 14. "MCUN1GPIO78,GPIO78 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x60 13. "MCUN1GPIO77,GPIO77 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x60 12. "MCUN1GPIO76,GPIO76 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x60 11. "MCUN1GPIO75,GPIO75 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x60 10. "MCUN1GPIO74,GPIO74 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x60 9. "MCUN1GPIO73,GPIO73 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x60 8. "MCUN1GPIO72,GPIO72 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x60 7. "MCUN1GPIO71,GPIO71 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x60 6. "MCUN1GPIO70,GPIO70 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x60 5. "MCUN1GPIO69,GPIO69 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x60 4. "MCUN1GPIO68,GPIO68 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x60 3. "MCUN1GPIO67,GPIO67 MCU N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x60 2. "MCUN1GPIO66,GPIO66 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x60 1. "MCUN1GPIO65,GPIO65 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x60 0. "MCUN1GPIO64,GPIO64 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
line.long 0x64 "MCUN1INT2STAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x64 31. "MCUN1GPIO95,GPIO95 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x64 30. "MCUN1GPIO94,GPIO94 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x64 29. "MCUN1GPIO93,GPIO93 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x64 28. "MCUN1GPIO92,GPIO92 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x64 27. "MCUN1GPIO91,GPIO91 MCU N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x64 26. "MCUN1GPIO90,GPIO90 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x64 25. "MCUN1GPIO89,GPIO89 MCU N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x64 24. "MCUN1GPIO88,GPIO88 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x64 23. "MCUN1GPIO87,GPIO87 MCU N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x64 22. "MCUN1GPIO86,GPIO86 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x64 21. "MCUN1GPIO85,GPIO85 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x64 20. "MCUN1GPIO84,GPIO84 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x64 19. "MCUN1GPIO83,GPIO83 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x64 18. "MCUN1GPIO82,GPIO82 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x64 17. "MCUN1GPIO81,GPIO81 MCU N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x64 16. "MCUN1GPIO80,GPIO80 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x64 15. "MCUN1GPIO79,GPIO79 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x64 14. "MCUN1GPIO78,GPIO78 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x64 13. "MCUN1GPIO77,GPIO77 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x64 12. "MCUN1GPIO76,GPIO76 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x64 11. "MCUN1GPIO75,GPIO75 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x64 10. "MCUN1GPIO74,GPIO74 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x64 9. "MCUN1GPIO73,GPIO73 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x64 8. "MCUN1GPIO72,GPIO72 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x64 7. "MCUN1GPIO71,GPIO71 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x64 6. "MCUN1GPIO70,GPIO70 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x64 5. "MCUN1GPIO69,GPIO69 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x64 4. "MCUN1GPIO68,GPIO68 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x64 3. "MCUN1GPIO67,GPIO67 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x64 2. "MCUN1GPIO66,GPIO66 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x64 1. "MCUN1GPIO65,GPIO65 MCU N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x64 0. "MCUN1GPIO64,GPIO64 MCU N1-priority interrupt." "?,1: priority interrupt"
|
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line.long 0x68 "MCUN1INT2CLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
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bitfld.long 0x68 31. "MCUN1GPIO95,GPIO95 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x68 30. "MCUN1GPIO94,GPIO94 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x68 29. "MCUN1GPIO93,GPIO93 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x68 28. "MCUN1GPIO92,GPIO92 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x68 27. "MCUN1GPIO91,GPIO91 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x68 26. "MCUN1GPIO90,GPIO90 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x68 25. "MCUN1GPIO89,GPIO89 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x68 24. "MCUN1GPIO88,GPIO88 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x68 23. "MCUN1GPIO87,GPIO87 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x68 22. "MCUN1GPIO86,GPIO86 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x68 21. "MCUN1GPIO85,GPIO85 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x68 20. "MCUN1GPIO84,GPIO84 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x68 19. "MCUN1GPIO83,GPIO83 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x68 18. "MCUN1GPIO82,GPIO82 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x68 17. "MCUN1GPIO81,GPIO81 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x68 16. "MCUN1GPIO80,GPIO80 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x68 15. "MCUN1GPIO79,GPIO79 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x68 14. "MCUN1GPIO78,GPIO78 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x68 13. "MCUN1GPIO77,GPIO77 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x68 12. "MCUN1GPIO76,GPIO76 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x68 11. "MCUN1GPIO75,GPIO75 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x68 10. "MCUN1GPIO74,GPIO74 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x68 9. "MCUN1GPIO73,GPIO73 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x68 8. "MCUN1GPIO72,GPIO72 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x68 7. "MCUN1GPIO71,GPIO71 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x68 6. "MCUN1GPIO70,GPIO70 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x68 5. "MCUN1GPIO69,GPIO69 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x68 4. "MCUN1GPIO68,GPIO68 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x68 3. "MCUN1GPIO67,GPIO67 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x68 2. "MCUN1GPIO66,GPIO66 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x68 1. "MCUN1GPIO65,GPIO65 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x68 0. "MCUN1GPIO64,GPIO64 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
line.long 0x6C "MCUN1INT2SET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0x6C 31. "MCUN1GPIO95,GPIO95 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x6C 30. "MCUN1GPIO94,GPIO94 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x6C 29. "MCUN1GPIO93,GPIO93 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x6C 28. "MCUN1GPIO92,GPIO92 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x6C 27. "MCUN1GPIO91,GPIO91 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x6C 26. "MCUN1GPIO90,GPIO90 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x6C 25. "MCUN1GPIO89,GPIO89 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x6C 24. "MCUN1GPIO88,GPIO88 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x6C 23. "MCUN1GPIO87,GPIO87 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x6C 22. "MCUN1GPIO86,GPIO86 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x6C 21. "MCUN1GPIO85,GPIO85 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x6C 20. "MCUN1GPIO84,GPIO84 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x6C 19. "MCUN1GPIO83,GPIO83 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x6C 18. "MCUN1GPIO82,GPIO82 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x6C 17. "MCUN1GPIO81,GPIO81 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x6C 16. "MCUN1GPIO80,GPIO80 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x6C 15. "MCUN1GPIO79,GPIO79 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x6C 14. "MCUN1GPIO78,GPIO78 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x6C 13. "MCUN1GPIO77,GPIO77 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x6C 12. "MCUN1GPIO76,GPIO76 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x6C 11. "MCUN1GPIO75,GPIO75 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x6C 10. "MCUN1GPIO74,GPIO74 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x6C 9. "MCUN1GPIO73,GPIO73 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x6C 8. "MCUN1GPIO72,GPIO72 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x6C 7. "MCUN1GPIO71,GPIO71 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x6C 6. "MCUN1GPIO70,GPIO70 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x6C 5. "MCUN1GPIO69,GPIO69 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x6C 4. "MCUN1GPIO68,GPIO68 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x6C 3. "MCUN1GPIO67,GPIO67 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x6C 2. "MCUN1GPIO66,GPIO66 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x6C 1. "MCUN1GPIO65,GPIO65 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x6C 0. "MCUN1GPIO64,GPIO64 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
line.long 0x70 "MCUN1INT3EN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x70 31. "MCUN1GPIO127,GPIO127 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x70 30. "MCUN1GPIO126,GPIO126 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x70 29. "MCUN1GPIO125,GPIO125 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x70 28. "MCUN1GPIO124,GPIO124 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x70 27. "MCUN1GPIO123,GPIO123 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x70 26. "MCUN1GPIO122,GPIO122 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x70 25. "MCUN1GPIO121,GPIO121 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x70 24. "MCUN1GPIO120,GPIO120 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x70 23. "MCUN1GPIO119,GPIO119 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x70 22. "MCUN1GPIO118,GPIO118 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x70 21. "MCUN1GPIO117,GPIO117 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x70 20. "MCUN1GPIO116,GPIO116 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x70 19. "MCUN1GPIO115,GPIO115 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x70 18. "MCUN1GPIO114,GPIO114 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x70 17. "MCUN1GPIO113,GPIO113 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x70 16. "MCUN1GPIO112,GPIO112 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x70 15. "MCUN1GPIO111,GPIO111 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x70 14. "MCUN1GPIO110,GPIO110 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x70 13. "MCUN1GPIO109,GPIO109 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x70 12. "MCUN1GPIO108,GPIO108 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x70 11. "MCUN1GPIO107,GPIO107 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x70 10. "MCUN1GPIO106,GPIO106 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x70 9. "MCUN1GPIO105,GPIO105 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x70 8. "MCUN1GPIO104,GPIO104 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x70 7. "MCUN1GPIO103,GPIO103 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x70 6. "MCUN1GPIO102,GPIO102 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x70 5. "MCUN1GPIO101,GPIO101 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x70 4. "MCUN1GPIO100,GPIO100 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x70 3. "MCUN1GPIO99,GPIO99 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x70 2. "MCUN1GPIO98,GPIO98 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x70 1. "MCUN1GPIO97,GPIO97 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x70 0. "MCUN1GPIO96,GPIO96 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
line.long 0x74 "MCUN1INT3STAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x74 31. "MCUN1GPIO127,GPIO127 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x74 30. "MCUN1GPIO126,GPIO126 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x74 29. "MCUN1GPIO125,GPIO125 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x74 28. "MCUN1GPIO124,GPIO124 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x74 27. "MCUN1GPIO123,GPIO123 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x74 26. "MCUN1GPIO122,GPIO122 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x74 25. "MCUN1GPIO121,GPIO121 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x74 24. "MCUN1GPIO120,GPIO120 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x74 23. "MCUN1GPIO119,GPIO119 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x74 22. "MCUN1GPIO118,GPIO118 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x74 21. "MCUN1GPIO117,GPIO117 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x74 20. "MCUN1GPIO116,GPIO116 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x74 19. "MCUN1GPIO115,GPIO115 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x74 18. "MCUN1GPIO114,GPIO114 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x74 17. "MCUN1GPIO113,GPIO113 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x74 16. "MCUN1GPIO112,GPIO112 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x74 15. "MCUN1GPIO111,GPIO111 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x74 14. "MCUN1GPIO110,GPIO110 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x74 13. "MCUN1GPIO109,GPIO109 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x74 12. "MCUN1GPIO108,GPIO108 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x74 11. "MCUN1GPIO107,GPIO107 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x74 10. "MCUN1GPIO106,GPIO106 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x74 9. "MCUN1GPIO105,GPIO105 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x74 8. "MCUN1GPIO104,GPIO104 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x74 7. "MCUN1GPIO103,GPIO103 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x74 6. "MCUN1GPIO102,GPIO102 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x74 5. "MCUN1GPIO101,GPIO101 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x74 4. "MCUN1GPIO100,GPIO100 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x74 3. "MCUN1GPIO99,GPIO99 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x74 2. "MCUN1GPIO98,GPIO98 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x74 1. "MCUN1GPIO97,GPIO97 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x74 0. "MCUN1GPIO96,GPIO96 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
line.long 0x78 "MCUN1INT3CLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
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bitfld.long 0x78 31. "MCUN1GPIO127,GPIO127 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x78 30. "MCUN1GPIO126,GPIO126 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x78 29. "MCUN1GPIO125,GPIO125 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x78 28. "MCUN1GPIO124,GPIO124 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x78 27. "MCUN1GPIO123,GPIO123 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x78 26. "MCUN1GPIO122,GPIO122 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x78 25. "MCUN1GPIO121,GPIO121 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x78 24. "MCUN1GPIO120,GPIO120 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x78 23. "MCUN1GPIO119,GPIO119 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x78 22. "MCUN1GPIO118,GPIO118 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x78 21. "MCUN1GPIO117,GPIO117 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x78 20. "MCUN1GPIO116,GPIO116 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x78 19. "MCUN1GPIO115,GPIO115 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x78 18. "MCUN1GPIO114,GPIO114 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x78 17. "MCUN1GPIO113,GPIO113 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x78 16. "MCUN1GPIO112,GPIO112 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x78 15. "MCUN1GPIO111,GPIO111 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x78 14. "MCUN1GPIO110,GPIO110 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x78 13. "MCUN1GPIO109,GPIO109 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x78 12. "MCUN1GPIO108,GPIO108 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x78 11. "MCUN1GPIO107,GPIO107 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x78 10. "MCUN1GPIO106,GPIO106 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x78 9. "MCUN1GPIO105,GPIO105 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x78 8. "MCUN1GPIO104,GPIO104 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x78 7. "MCUN1GPIO103,GPIO103 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x78 6. "MCUN1GPIO102,GPIO102 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x78 5. "MCUN1GPIO101,GPIO101 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x78 4. "MCUN1GPIO100,GPIO100 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x78 3. "MCUN1GPIO99,GPIO99 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x78 2. "MCUN1GPIO98,GPIO98 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x78 1. "MCUN1GPIO97,GPIO97 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x78 0. "MCUN1GPIO96,GPIO96 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
line.long 0x7C "MCUN1INT3SET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0x7C 31. "MCUN1GPIO127,GPIO127 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x7C 30. "MCUN1GPIO126,GPIO126 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x7C 29. "MCUN1GPIO125,GPIO125 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x7C 28. "MCUN1GPIO124,GPIO124 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x7C 27. "MCUN1GPIO123,GPIO123 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x7C 26. "MCUN1GPIO122,GPIO122 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x7C 25. "MCUN1GPIO121,GPIO121 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x7C 24. "MCUN1GPIO120,GPIO120 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x7C 23. "MCUN1GPIO119,GPIO119 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x7C 22. "MCUN1GPIO118,GPIO118 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x7C 21. "MCUN1GPIO117,GPIO117 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x7C 20. "MCUN1GPIO116,GPIO116 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x7C 19. "MCUN1GPIO115,GPIO115 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x7C 18. "MCUN1GPIO114,GPIO114 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x7C 17. "MCUN1GPIO113,GPIO113 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x7C 16. "MCUN1GPIO112,GPIO112 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x7C 15. "MCUN1GPIO111,GPIO111 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x7C 14. "MCUN1GPIO110,GPIO110 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x7C 13. "MCUN1GPIO109,GPIO109 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x7C 12. "MCUN1GPIO108,GPIO108 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x7C 11. "MCUN1GPIO107,GPIO107 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x7C 10. "MCUN1GPIO106,GPIO106 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x7C 9. "MCUN1GPIO105,GPIO105 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x7C 8. "MCUN1GPIO104,GPIO104 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x7C 7. "MCUN1GPIO103,GPIO103 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x7C 6. "MCUN1GPIO102,GPIO102 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x7C 5. "MCUN1GPIO101,GPIO101 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x7C 4. "MCUN1GPIO100,GPIO100 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x7C 3. "MCUN1GPIO99,GPIO99 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x7C 2. "MCUN1GPIO98,GPIO98 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x7C 1. "MCUN1GPIO97,GPIO97 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x7C 0. "MCUN1GPIO96,GPIO96 MCU N1-priority interrupt." "?,1: priority interrupt"
|
|
line.long 0x80 "DSP0N0INT0EN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x80 31. "DSP0N0GPIO31,GPIO31 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x80 30. "DSP0N0GPIO30,GPIO30 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x80 29. "DSP0N0GPIO29,GPIO29 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x80 28. "DSP0N0GPIO28,GPIO28 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x80 27. "DSP0N0GPIO27,GPIO27 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x80 26. "DSP0N0GPIO26,GPIO26 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x80 25. "DSP0N0GPIO25,GPIO25 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x80 24. "DSP0N0GPIO24,GPIO24 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x80 23. "DSP0N0GPIO23,GPIO23 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x80 22. "DSP0N0GPIO22,GPIO22 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x80 21. "DSP0N0GPIO21,GPIO21 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x80 20. "DSP0N0GPIO20,GPIO20 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x80 19. "DSP0N0GPIO19,GPIO19 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x80 18. "DSP0N0GPIO18,GPIO18 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x80 17. "DSP0N0GPIO17,GPIO17 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x80 16. "DSP0N0GPIO16,GPIO16 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x80 15. "DSP0N0GPIO15,GPIO15 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x80 14. "DSP0N0GPIO14,GPIO14 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x80 13. "DSP0N0GPIO13,GPIO13 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x80 12. "DSP0N0GPIO12,GPIO12 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x80 11. "DSP0N0GPIO11,GPIO11 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x80 10. "DSP0N0GPIO10,GPIO10 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x80 9. "DSP0N0GPIO9,GPIO9 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x80 8. "DSP0N0GPIO8,GPIO8 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x80 7. "DSP0N0GPIO7,GPIO7 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x80 6. "DSP0N0GPIO6,GPIO6 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x80 5. "DSP0N0GPIO5,GPIO5 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x80 4. "DSP0N0GPIO4,GPIO4 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x80 3. "DSP0N0GPIO3,GPIO3 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x80 2. "DSP0N0GPIO2,GPIO2 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x80 1. "DSP0N0GPIO1,GPIO1 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x80 0. "DSP0N0GPIO0,GPIO0 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x84 "DSP0N0INT0STAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x84 31. "DSP0N0GPIO31,GPIO31 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x84 30. "DSP0N0GPIO30,GPIO30 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x84 29. "DSP0N0GPIO29,GPIO29 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x84 28. "DSP0N0GPIO28,GPIO28 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x84 27. "DSP0N0GPIO27,GPIO27 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x84 26. "DSP0N0GPIO26,GPIO26 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x84 25. "DSP0N0GPIO25,GPIO25 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x84 24. "DSP0N0GPIO24,GPIO24 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x84 23. "DSP0N0GPIO23,GPIO23 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x84 22. "DSP0N0GPIO22,GPIO22 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x84 21. "DSP0N0GPIO21,GPIO21 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x84 20. "DSP0N0GPIO20,GPIO20 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x84 19. "DSP0N0GPIO19,GPIO19 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x84 18. "DSP0N0GPIO18,GPIO18 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x84 17. "DSP0N0GPIO17,GPIO17 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x84 16. "DSP0N0GPIO16,GPIO16 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x84 15. "DSP0N0GPIO15,GPIO15 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x84 14. "DSP0N0GPIO14,GPIO14 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x84 13. "DSP0N0GPIO13,GPIO13 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x84 12. "DSP0N0GPIO12,GPIO12 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x84 11. "DSP0N0GPIO11,GPIO11 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x84 10. "DSP0N0GPIO10,GPIO10 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x84 9. "DSP0N0GPIO9,GPIO9 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x84 8. "DSP0N0GPIO8,GPIO8 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x84 7. "DSP0N0GPIO7,GPIO7 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x84 6. "DSP0N0GPIO6,GPIO6 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x84 5. "DSP0N0GPIO5,GPIO5 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x84 4. "DSP0N0GPIO4,GPIO4 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x84 3. "DSP0N0GPIO3,GPIO3 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x84 2. "DSP0N0GPIO2,GPIO2 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x84 1. "DSP0N0GPIO1,GPIO1 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x84 0. "DSP0N0GPIO0,GPIO0 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x88 "DSP0N0INT0CLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x88 31. "DSP0N0GPIO31,GPIO31 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x88 30. "DSP0N0GPIO30,GPIO30 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x88 29. "DSP0N0GPIO29,GPIO29 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x88 28. "DSP0N0GPIO28,GPIO28 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x88 27. "DSP0N0GPIO27,GPIO27 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x88 26. "DSP0N0GPIO26,GPIO26 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x88 25. "DSP0N0GPIO25,GPIO25 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x88 24. "DSP0N0GPIO24,GPIO24 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x88 23. "DSP0N0GPIO23,GPIO23 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x88 22. "DSP0N0GPIO22,GPIO22 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x88 21. "DSP0N0GPIO21,GPIO21 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x88 20. "DSP0N0GPIO20,GPIO20 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x88 19. "DSP0N0GPIO19,GPIO19 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x88 18. "DSP0N0GPIO18,GPIO18 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x88 17. "DSP0N0GPIO17,GPIO17 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x88 16. "DSP0N0GPIO16,GPIO16 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x88 15. "DSP0N0GPIO15,GPIO15 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x88 14. "DSP0N0GPIO14,GPIO14 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x88 13. "DSP0N0GPIO13,GPIO13 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x88 12. "DSP0N0GPIO12,GPIO12 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x88 11. "DSP0N0GPIO11,GPIO11 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x88 10. "DSP0N0GPIO10,GPIO10 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x88 9. "DSP0N0GPIO9,GPIO9 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x88 8. "DSP0N0GPIO8,GPIO8 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x88 7. "DSP0N0GPIO7,GPIO7 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x88 6. "DSP0N0GPIO6,GPIO6 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x88 5. "DSP0N0GPIO5,GPIO5 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x88 4. "DSP0N0GPIO4,GPIO4 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x88 3. "DSP0N0GPIO3,GPIO3 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x88 2. "DSP0N0GPIO2,GPIO2 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x88 1. "DSP0N0GPIO1,GPIO1 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x88 0. "DSP0N0GPIO0,GPIO0 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x8C "DSP0N0INT0SET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0x8C 31. "DSP0N0GPIO31,GPIO31 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x8C 30. "DSP0N0GPIO30,GPIO30 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x8C 29. "DSP0N0GPIO29,GPIO29 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x8C 28. "DSP0N0GPIO28,GPIO28 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x8C 27. "DSP0N0GPIO27,GPIO27 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x8C 26. "DSP0N0GPIO26,GPIO26 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x8C 25. "DSP0N0GPIO25,GPIO25 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x8C 24. "DSP0N0GPIO24,GPIO24 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x8C 23. "DSP0N0GPIO23,GPIO23 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x8C 22. "DSP0N0GPIO22,GPIO22 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x8C 21. "DSP0N0GPIO21,GPIO21 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x8C 20. "DSP0N0GPIO20,GPIO20 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x8C 19. "DSP0N0GPIO19,GPIO19 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x8C 18. "DSP0N0GPIO18,GPIO18 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x8C 17. "DSP0N0GPIO17,GPIO17 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x8C 16. "DSP0N0GPIO16,GPIO16 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x8C 15. "DSP0N0GPIO15,GPIO15 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x8C 14. "DSP0N0GPIO14,GPIO14 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x8C 13. "DSP0N0GPIO13,GPIO13 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x8C 12. "DSP0N0GPIO12,GPIO12 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x8C 11. "DSP0N0GPIO11,GPIO11 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x8C 10. "DSP0N0GPIO10,GPIO10 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x8C 9. "DSP0N0GPIO9,GPIO9 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x8C 8. "DSP0N0GPIO8,GPIO8 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x8C 7. "DSP0N0GPIO7,GPIO7 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x8C 6. "DSP0N0GPIO6,GPIO6 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x8C 5. "DSP0N0GPIO5,GPIO5 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x8C 4. "DSP0N0GPIO4,GPIO4 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x8C 3. "DSP0N0GPIO3,GPIO3 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x8C 2. "DSP0N0GPIO2,GPIO2 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x8C 1. "DSP0N0GPIO1,GPIO1 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x8C 0. "DSP0N0GPIO0,GPIO0 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x90 "DSP0N0INT1EN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x90 31. "DSP0N0GPIO63,GPIO63 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x90 30. "DSP0N0GPIO62,GPIO62 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x90 29. "DSP0N0GPIO61,GPIO61 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x90 28. "DSP0N0GPIO60,GPIO60 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x90 27. "DSP0N0GPIO59,GPIO59 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x90 26. "DSP0N0GPIO58,GPIO58 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x90 25. "DSP0N0GPIO57,GPIO57 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x90 24. "DSP0N0GPIO56,GPIO56 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x90 23. "DSP0N0GPIO55,GPIO55 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x90 22. "DSP0N0GPIO54,GPIO54 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x90 21. "DSP0N0GPIO53,GPIO53 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x90 20. "DSP0N0GPIO52,GPIO52 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x90 19. "DSP0N0GPIO51,GPIO51 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x90 18. "DSP0N0GPIO50,GPIO50 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x90 17. "DSP0N0GPIO49,GPIO49 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x90 16. "DSP0N0GPIO48,GPIO48 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x90 15. "DSP0N0GPIO47,GPIO47 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x90 14. "DSP0N0GPIO46,GPIO46 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x90 13. "DSP0N0GPIO45,GPIO45 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x90 12. "DSP0N0GPIO44,GPIO44 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x90 11. "DSP0N0GPIO43,GPIO43 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x90 10. "DSP0N0GPIO42,GPIO42 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x90 9. "DSP0N0GPIO41,GPIO41 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x90 8. "DSP0N0GPIO40,GPIO40 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x90 7. "DSP0N0GPIO39,GPIO39 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x90 6. "DSP0N0GPIO38,GPIO38 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x90 5. "DSP0N0GPIO37,GPIO37 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x90 4. "DSP0N0GPIO36,GPIO36 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x90 3. "DSP0N0GPIO35,GPIO35 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x90 2. "DSP0N0GPIO34,GPIO34 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x90 1. "DSP0N0GPIO33,GPIO33 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x90 0. "DSP0N0GPIO32,GPIO32 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x94 "DSP0N0INT1STAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x94 31. "DSP0N0GPIO63,GPIO63 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x94 30. "DSP0N0GPIO62,GPIO62 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x94 29. "DSP0N0GPIO61,GPIO61 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x94 28. "DSP0N0GPIO60,GPIO60 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x94 27. "DSP0N0GPIO59,GPIO59 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x94 26. "DSP0N0GPIO58,GPIO58 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x94 25. "DSP0N0GPIO57,GPIO57 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x94 24. "DSP0N0GPIO56,GPIO56 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x94 23. "DSP0N0GPIO55,GPIO55 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x94 22. "DSP0N0GPIO54,GPIO54 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x94 21. "DSP0N0GPIO53,GPIO53 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x94 20. "DSP0N0GPIO52,GPIO52 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x94 19. "DSP0N0GPIO51,GPIO51 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x94 18. "DSP0N0GPIO50,GPIO50 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x94 17. "DSP0N0GPIO49,GPIO49 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x94 16. "DSP0N0GPIO48,GPIO48 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x94 15. "DSP0N0GPIO47,GPIO47 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x94 14. "DSP0N0GPIO46,GPIO46 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x94 13. "DSP0N0GPIO45,GPIO45 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x94 12. "DSP0N0GPIO44,GPIO44 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x94 11. "DSP0N0GPIO43,GPIO43 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x94 10. "DSP0N0GPIO42,GPIO42 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x94 9. "DSP0N0GPIO41,GPIO41 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x94 8. "DSP0N0GPIO40,GPIO40 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x94 7. "DSP0N0GPIO39,GPIO39 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x94 6. "DSP0N0GPIO38,GPIO38 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x94 5. "DSP0N0GPIO37,GPIO37 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x94 4. "DSP0N0GPIO36,GPIO36 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x94 3. "DSP0N0GPIO35,GPIO35 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x94 2. "DSP0N0GPIO34,GPIO34 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x94 1. "DSP0N0GPIO33,GPIO33 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x94 0. "DSP0N0GPIO32,GPIO32 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x98 "DSP0N0INT1CLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x98 31. "DSP0N0GPIO63,GPIO63 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x98 30. "DSP0N0GPIO62,GPIO62 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x98 29. "DSP0N0GPIO61,GPIO61 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x98 28. "DSP0N0GPIO60,GPIO60 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x98 27. "DSP0N0GPIO59,GPIO59 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x98 26. "DSP0N0GPIO58,GPIO58 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x98 25. "DSP0N0GPIO57,GPIO57 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x98 24. "DSP0N0GPIO56,GPIO56 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x98 23. "DSP0N0GPIO55,GPIO55 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x98 22. "DSP0N0GPIO54,GPIO54 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x98 21. "DSP0N0GPIO53,GPIO53 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x98 20. "DSP0N0GPIO52,GPIO52 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x98 19. "DSP0N0GPIO51,GPIO51 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x98 18. "DSP0N0GPIO50,GPIO50 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x98 17. "DSP0N0GPIO49,GPIO49 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x98 16. "DSP0N0GPIO48,GPIO48 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x98 15. "DSP0N0GPIO47,GPIO47 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x98 14. "DSP0N0GPIO46,GPIO46 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x98 13. "DSP0N0GPIO45,GPIO45 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x98 12. "DSP0N0GPIO44,GPIO44 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x98 11. "DSP0N0GPIO43,GPIO43 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x98 10. "DSP0N0GPIO42,GPIO42 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x98 9. "DSP0N0GPIO41,GPIO41 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x98 8. "DSP0N0GPIO40,GPIO40 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x98 7. "DSP0N0GPIO39,GPIO39 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x98 6. "DSP0N0GPIO38,GPIO38 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x98 5. "DSP0N0GPIO37,GPIO37 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x98 4. "DSP0N0GPIO36,GPIO36 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x98 3. "DSP0N0GPIO35,GPIO35 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x98 2. "DSP0N0GPIO34,GPIO34 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x98 1. "DSP0N0GPIO33,GPIO33 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x98 0. "DSP0N0GPIO32,GPIO32 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x9C "DSP0N0INT1SET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0x9C 31. "DSP0N0GPIO63,GPIO63 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x9C 30. "DSP0N0GPIO62,GPIO62 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x9C 29. "DSP0N0GPIO61,GPIO61 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x9C 28. "DSP0N0GPIO60,GPIO60 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x9C 27. "DSP0N0GPIO59,GPIO59 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x9C 26. "DSP0N0GPIO58,GPIO58 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x9C 25. "DSP0N0GPIO57,GPIO57 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x9C 24. "DSP0N0GPIO56,GPIO56 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x9C 23. "DSP0N0GPIO55,GPIO55 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x9C 22. "DSP0N0GPIO54,GPIO54 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x9C 21. "DSP0N0GPIO53,GPIO53 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x9C 20. "DSP0N0GPIO52,GPIO52 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x9C 19. "DSP0N0GPIO51,GPIO51 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x9C 18. "DSP0N0GPIO50,GPIO50 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x9C 17. "DSP0N0GPIO49,GPIO49 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x9C 16. "DSP0N0GPIO48,GPIO48 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x9C 15. "DSP0N0GPIO47,GPIO47 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x9C 14. "DSP0N0GPIO46,GPIO46 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x9C 13. "DSP0N0GPIO45,GPIO45 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x9C 12. "DSP0N0GPIO44,GPIO44 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x9C 11. "DSP0N0GPIO43,GPIO43 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x9C 10. "DSP0N0GPIO42,GPIO42 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x9C 9. "DSP0N0GPIO41,GPIO41 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x9C 8. "DSP0N0GPIO40,GPIO40 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x9C 7. "DSP0N0GPIO39,GPIO39 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x9C 6. "DSP0N0GPIO38,GPIO38 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x9C 5. "DSP0N0GPIO37,GPIO37 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x9C 4. "DSP0N0GPIO36,GPIO36 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x9C 3. "DSP0N0GPIO35,GPIO35 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x9C 2. "DSP0N0GPIO34,GPIO34 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x9C 1. "DSP0N0GPIO33,GPIO33 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x9C 0. "DSP0N0GPIO32,GPIO32 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0xA0 "DSP0N0INT2EN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0xA0 31. "DSP0N0GPIO95,GPIO95 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA0 30. "DSP0N0GPIO94,GPIO94 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA0 29. "DSP0N0GPIO93,GPIO93 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA0 28. "DSP0N0GPIO92,GPIO92 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA0 27. "DSP0N0GPIO91,GPIO91 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA0 26. "DSP0N0GPIO90,GPIO90 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA0 25. "DSP0N0GPIO89,GPIO89 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA0 24. "DSP0N0GPIO88,GPIO88 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA0 23. "DSP0N0GPIO87,GPIO87 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA0 22. "DSP0N0GPIO86,GPIO86 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA0 21. "DSP0N0GPIO85,GPIO85 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA0 20. "DSP0N0GPIO84,GPIO84 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA0 19. "DSP0N0GPIO83,GPIO83 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA0 18. "DSP0N0GPIO82,GPIO82 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA0 17. "DSP0N0GPIO81,GPIO81 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA0 16. "DSP0N0GPIO80,GPIO80 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA0 15. "DSP0N0GPIO79,GPIO79 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA0 14. "DSP0N0GPIO78,GPIO78 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA0 13. "DSP0N0GPIO77,GPIO77 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA0 12. "DSP0N0GPIO76,GPIO76 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA0 11. "DSP0N0GPIO75,GPIO75 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA0 10. "DSP0N0GPIO74,GPIO74 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA0 9. "DSP0N0GPIO73,GPIO73 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA0 8. "DSP0N0GPIO72,GPIO72 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA0 7. "DSP0N0GPIO71,GPIO71 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA0 6. "DSP0N0GPIO70,GPIO70 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA0 5. "DSP0N0GPIO69,GPIO69 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA0 4. "DSP0N0GPIO68,GPIO68 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA0 3. "DSP0N0GPIO67,GPIO67 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA0 2. "DSP0N0GPIO66,GPIO66 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA0 1. "DSP0N0GPIO65,GPIO65 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA0 0. "DSP0N0GPIO64,GPIO64 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0xA4 "DSP0N0INT2STAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0xA4 31. "DSP0N0GPIO95,GPIO95 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA4 30. "DSP0N0GPIO94,GPIO94 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA4 29. "DSP0N0GPIO93,GPIO93 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA4 28. "DSP0N0GPIO92,GPIO92 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA4 27. "DSP0N0GPIO91,GPIO91 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA4 26. "DSP0N0GPIO90,GPIO90 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA4 25. "DSP0N0GPIO89,GPIO89 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA4 24. "DSP0N0GPIO88,GPIO88 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA4 23. "DSP0N0GPIO87,GPIO87 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA4 22. "DSP0N0GPIO86,GPIO86 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA4 21. "DSP0N0GPIO85,GPIO85 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA4 20. "DSP0N0GPIO84,GPIO84 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA4 19. "DSP0N0GPIO83,GPIO83 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA4 18. "DSP0N0GPIO82,GPIO82 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA4 17. "DSP0N0GPIO81,GPIO81 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA4 16. "DSP0N0GPIO80,GPIO80 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA4 15. "DSP0N0GPIO79,GPIO79 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA4 14. "DSP0N0GPIO78,GPIO78 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA4 13. "DSP0N0GPIO77,GPIO77 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA4 12. "DSP0N0GPIO76,GPIO76 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA4 11. "DSP0N0GPIO75,GPIO75 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA4 10. "DSP0N0GPIO74,GPIO74 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA4 9. "DSP0N0GPIO73,GPIO73 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA4 8. "DSP0N0GPIO72,GPIO72 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA4 7. "DSP0N0GPIO71,GPIO71 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA4 6. "DSP0N0GPIO70,GPIO70 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA4 5. "DSP0N0GPIO69,GPIO69 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA4 4. "DSP0N0GPIO68,GPIO68 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA4 3. "DSP0N0GPIO67,GPIO67 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA4 2. "DSP0N0GPIO66,GPIO66 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA4 1. "DSP0N0GPIO65,GPIO65 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA4 0. "DSP0N0GPIO64,GPIO64 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0xA8 "DSP0N0INT2CLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0xA8 31. "DSP0N0GPIO95,GPIO95 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA8 30. "DSP0N0GPIO94,GPIO94 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA8 29. "DSP0N0GPIO93,GPIO93 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA8 28. "DSP0N0GPIO92,GPIO92 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA8 27. "DSP0N0GPIO91,GPIO91 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA8 26. "DSP0N0GPIO90,GPIO90 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA8 25. "DSP0N0GPIO89,GPIO89 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA8 24. "DSP0N0GPIO88,GPIO88 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA8 23. "DSP0N0GPIO87,GPIO87 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA8 22. "DSP0N0GPIO86,GPIO86 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA8 21. "DSP0N0GPIO85,GPIO85 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA8 20. "DSP0N0GPIO84,GPIO84 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA8 19. "DSP0N0GPIO83,GPIO83 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA8 18. "DSP0N0GPIO82,GPIO82 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA8 17. "DSP0N0GPIO81,GPIO81 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA8 16. "DSP0N0GPIO80,GPIO80 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA8 15. "DSP0N0GPIO79,GPIO79 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA8 14. "DSP0N0GPIO78,GPIO78 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA8 13. "DSP0N0GPIO77,GPIO77 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA8 12. "DSP0N0GPIO76,GPIO76 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA8 11. "DSP0N0GPIO75,GPIO75 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA8 10. "DSP0N0GPIO74,GPIO74 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA8 9. "DSP0N0GPIO73,GPIO73 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA8 8. "DSP0N0GPIO72,GPIO72 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA8 7. "DSP0N0GPIO71,GPIO71 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA8 6. "DSP0N0GPIO70,GPIO70 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA8 5. "DSP0N0GPIO69,GPIO69 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA8 4. "DSP0N0GPIO68,GPIO68 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA8 3. "DSP0N0GPIO67,GPIO67 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA8 2. "DSP0N0GPIO66,GPIO66 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xA8 1. "DSP0N0GPIO65,GPIO65 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xA8 0. "DSP0N0GPIO64,GPIO64 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0xAC "DSP0N0INT2SET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xAC 31. "DSP0N0GPIO95,GPIO95 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xAC 30. "DSP0N0GPIO94,GPIO94 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xAC 29. "DSP0N0GPIO93,GPIO93 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xAC 28. "DSP0N0GPIO92,GPIO92 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xAC 27. "DSP0N0GPIO91,GPIO91 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xAC 26. "DSP0N0GPIO90,GPIO90 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xAC 25. "DSP0N0GPIO89,GPIO89 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xAC 24. "DSP0N0GPIO88,GPIO88 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xAC 23. "DSP0N0GPIO87,GPIO87 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xAC 22. "DSP0N0GPIO86,GPIO86 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xAC 21. "DSP0N0GPIO85,GPIO85 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xAC 20. "DSP0N0GPIO84,GPIO84 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xAC 19. "DSP0N0GPIO83,GPIO83 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xAC 18. "DSP0N0GPIO82,GPIO82 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xAC 17. "DSP0N0GPIO81,GPIO81 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xAC 16. "DSP0N0GPIO80,GPIO80 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xAC 15. "DSP0N0GPIO79,GPIO79 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xAC 14. "DSP0N0GPIO78,GPIO78 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xAC 13. "DSP0N0GPIO77,GPIO77 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xAC 12. "DSP0N0GPIO76,GPIO76 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xAC 11. "DSP0N0GPIO75,GPIO75 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xAC 10. "DSP0N0GPIO74,GPIO74 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xAC 9. "DSP0N0GPIO73,GPIO73 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xAC 8. "DSP0N0GPIO72,GPIO72 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xAC 7. "DSP0N0GPIO71,GPIO71 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xAC 6. "DSP0N0GPIO70,GPIO70 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xAC 5. "DSP0N0GPIO69,GPIO69 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xAC 4. "DSP0N0GPIO68,GPIO68 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xAC 3. "DSP0N0GPIO67,GPIO67 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xAC 2. "DSP0N0GPIO66,GPIO66 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xAC 1. "DSP0N0GPIO65,GPIO65 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xAC 0. "DSP0N0GPIO64,GPIO64 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0xB0 "DSP0N0INT3EN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0xB0 31. "DSP0N0GPIO127,GPIO127 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB0 30. "DSP0N0GPIO126,GPIO126 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB0 29. "DSP0N0GPIO125,GPIO125 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB0 28. "DSP0N0GPIO124,GPIO124 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB0 27. "DSP0N0GPIO123,GPIO123 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB0 26. "DSP0N0GPIO122,GPIO122 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB0 25. "DSP0N0GPIO121,GPIO121 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB0 24. "DSP0N0GPIO120,GPIO120 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB0 23. "DSP0N0GPIO119,GPIO119 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB0 22. "DSP0N0GPIO118,GPIO118 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB0 21. "DSP0N0GPIO117,GPIO117 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB0 20. "DSP0N0GPIO116,GPIO116 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB0 19. "DSP0N0GPIO115,GPIO115 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB0 18. "DSP0N0GPIO114,GPIO114 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB0 17. "DSP0N0GPIO113,GPIO113 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB0 16. "DSP0N0GPIO112,GPIO112 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB0 15. "DSP0N0GPIO111,GPIO111 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB0 14. "DSP0N0GPIO110,GPIO110 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB0 13. "DSP0N0GPIO109,GPIO109 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB0 12. "DSP0N0GPIO108,GPIO108 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB0 11. "DSP0N0GPIO107,GPIO107 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB0 10. "DSP0N0GPIO106,GPIO106 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB0 9. "DSP0N0GPIO105,GPIO105 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB0 8. "DSP0N0GPIO104,GPIO104 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB0 7. "DSP0N0GPIO103,GPIO103 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB0 6. "DSP0N0GPIO102,GPIO102 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB0 5. "DSP0N0GPIO101,GPIO101 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB0 4. "DSP0N0GPIO100,GPIO100 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB0 3. "DSP0N0GPIO99,GPIO99 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB0 2. "DSP0N0GPIO98,GPIO98 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB0 1. "DSP0N0GPIO97,GPIO97 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB0 0. "DSP0N0GPIO96,GPIO96 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0xB4 "DSP0N0INT3STAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0xB4 31. "DSP0N0GPIO127,GPIO127 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB4 30. "DSP0N0GPIO126,GPIO126 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB4 29. "DSP0N0GPIO125,GPIO125 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB4 28. "DSP0N0GPIO124,GPIO124 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB4 27. "DSP0N0GPIO123,GPIO123 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB4 26. "DSP0N0GPIO122,GPIO122 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB4 25. "DSP0N0GPIO121,GPIO121 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB4 24. "DSP0N0GPIO120,GPIO120 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB4 23. "DSP0N0GPIO119,GPIO119 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB4 22. "DSP0N0GPIO118,GPIO118 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB4 21. "DSP0N0GPIO117,GPIO117 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB4 20. "DSP0N0GPIO116,GPIO116 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB4 19. "DSP0N0GPIO115,GPIO115 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB4 18. "DSP0N0GPIO114,GPIO114 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB4 17. "DSP0N0GPIO113,GPIO113 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB4 16. "DSP0N0GPIO112,GPIO112 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0xB4 15. "DSP0N0GPIO111,GPIO111 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB4 14. "DSP0N0GPIO110,GPIO110 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0xB4 13. "DSP0N0GPIO109,GPIO109 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB4 12. "DSP0N0GPIO108,GPIO108 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB4 11. "DSP0N0GPIO107,GPIO107 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB4 10. "DSP0N0GPIO106,GPIO106 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB4 9. "DSP0N0GPIO105,GPIO105 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB4 8. "DSP0N0GPIO104,GPIO104 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB4 7. "DSP0N0GPIO103,GPIO103 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB4 6. "DSP0N0GPIO102,GPIO102 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0xB4 5. "DSP0N0GPIO101,GPIO101 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB4 4. "DSP0N0GPIO100,GPIO100 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB4 3. "DSP0N0GPIO99,GPIO99 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB4 2. "DSP0N0GPIO98,GPIO98 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB4 1. "DSP0N0GPIO97,GPIO97 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB4 0. "DSP0N0GPIO96,GPIO96 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0xB8 "DSP0N0INT3CLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0xB8 31. "DSP0N0GPIO127,GPIO127 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB8 30. "DSP0N0GPIO126,GPIO126 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB8 29. "DSP0N0GPIO125,GPIO125 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB8 28. "DSP0N0GPIO124,GPIO124 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB8 27. "DSP0N0GPIO123,GPIO123 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB8 26. "DSP0N0GPIO122,GPIO122 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB8 25. "DSP0N0GPIO121,GPIO121 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB8 24. "DSP0N0GPIO120,GPIO120 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB8 23. "DSP0N0GPIO119,GPIO119 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB8 22. "DSP0N0GPIO118,GPIO118 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB8 21. "DSP0N0GPIO117,GPIO117 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB8 20. "DSP0N0GPIO116,GPIO116 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB8 19. "DSP0N0GPIO115,GPIO115 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB8 18. "DSP0N0GPIO114,GPIO114 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB8 17. "DSP0N0GPIO113,GPIO113 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB8 16. "DSP0N0GPIO112,GPIO112 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB8 15. "DSP0N0GPIO111,GPIO111 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB8 14. "DSP0N0GPIO110,GPIO110 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB8 13. "DSP0N0GPIO109,GPIO109 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB8 12. "DSP0N0GPIO108,GPIO108 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB8 11. "DSP0N0GPIO107,GPIO107 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB8 10. "DSP0N0GPIO106,GPIO106 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB8 9. "DSP0N0GPIO105,GPIO105 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB8 8. "DSP0N0GPIO104,GPIO104 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB8 7. "DSP0N0GPIO103,GPIO103 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB8 6. "DSP0N0GPIO102,GPIO102 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB8 5. "DSP0N0GPIO101,GPIO101 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB8 4. "DSP0N0GPIO100,GPIO100 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB8 3. "DSP0N0GPIO99,GPIO99 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB8 2. "DSP0N0GPIO98,GPIO98 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xB8 1. "DSP0N0GPIO97,GPIO97 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xB8 0. "DSP0N0GPIO96,GPIO96 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0xBC "DSP0N0INT3SET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xBC 31. "DSP0N0GPIO127,GPIO127 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xBC 30. "DSP0N0GPIO126,GPIO126 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xBC 29. "DSP0N0GPIO125,GPIO125 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xBC 28. "DSP0N0GPIO124,GPIO124 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xBC 27. "DSP0N0GPIO123,GPIO123 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xBC 26. "DSP0N0GPIO122,GPIO122 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xBC 25. "DSP0N0GPIO121,GPIO121 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xBC 24. "DSP0N0GPIO120,GPIO120 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xBC 23. "DSP0N0GPIO119,GPIO119 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xBC 22. "DSP0N0GPIO118,GPIO118 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xBC 21. "DSP0N0GPIO117,GPIO117 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xBC 20. "DSP0N0GPIO116,GPIO116 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xBC 19. "DSP0N0GPIO115,GPIO115 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xBC 18. "DSP0N0GPIO114,GPIO114 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xBC 17. "DSP0N0GPIO113,GPIO113 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xBC 16. "DSP0N0GPIO112,GPIO112 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xBC 15. "DSP0N0GPIO111,GPIO111 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xBC 14. "DSP0N0GPIO110,GPIO110 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xBC 13. "DSP0N0GPIO109,GPIO109 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xBC 12. "DSP0N0GPIO108,GPIO108 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xBC 11. "DSP0N0GPIO107,GPIO107 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xBC 10. "DSP0N0GPIO106,GPIO106 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xBC 9. "DSP0N0GPIO105,GPIO105 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xBC 8. "DSP0N0GPIO104,GPIO104 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xBC 7. "DSP0N0GPIO103,GPIO103 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xBC 6. "DSP0N0GPIO102,GPIO102 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xBC 5. "DSP0N0GPIO101,GPIO101 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xBC 4. "DSP0N0GPIO100,GPIO100 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xBC 3. "DSP0N0GPIO99,GPIO99 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xBC 2. "DSP0N0GPIO98,GPIO98 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0xBC 1. "DSP0N0GPIO97,GPIO97 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0xBC 0. "DSP0N0GPIO96,GPIO96 DSP0 N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0xC0 "DSP0N1INT0EN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0xC0 31. "DSP0N1GPIO31,GPIO31 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xC0 30. "DSP0N1GPIO30,GPIO30 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xC0 29. "DSP0N1GPIO29,GPIO29 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xC0 28. "DSP0N1GPIO28,GPIO28 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xC0 27. "DSP0N1GPIO27,GPIO27 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xC0 26. "DSP0N1GPIO26,GPIO26 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xC0 25. "DSP0N1GPIO25,GPIO25 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xC0 24. "DSP0N1GPIO24,GPIO24 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xC0 23. "DSP0N1GPIO23,GPIO23 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xC0 22. "DSP0N1GPIO22,GPIO22 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xC0 21. "DSP0N1GPIO21,GPIO21 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xC0 20. "DSP0N1GPIO20,GPIO20 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xC0 19. "DSP0N1GPIO19,GPIO19 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xC0 18. "DSP0N1GPIO18,GPIO18 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xC0 17. "DSP0N1GPIO17,GPIO17 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xC0 16. "DSP0N1GPIO16,GPIO16 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xC0 15. "DSP0N1GPIO15,GPIO15 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xC0 14. "DSP0N1GPIO14,GPIO14 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xC0 13. "DSP0N1GPIO13,GPIO13 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xC0 12. "DSP0N1GPIO12,GPIO12 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xC0 11. "DSP0N1GPIO11,GPIO11 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xC0 10. "DSP0N1GPIO10,GPIO10 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xC0 9. "DSP0N1GPIO9,GPIO9 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xC0 8. "DSP0N1GPIO8,GPIO8 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xC0 7. "DSP0N1GPIO7,GPIO7 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xC0 6. "DSP0N1GPIO6,GPIO6 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xC0 5. "DSP0N1GPIO5,GPIO5 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xC0 4. "DSP0N1GPIO4,GPIO4 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xC0 3. "DSP0N1GPIO3,GPIO3 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xC0 2. "DSP0N1GPIO2,GPIO2 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xC0 1. "DSP0N1GPIO1,GPIO1 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xC0 0. "DSP0N1GPIO0,GPIO0 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
line.long 0xC4 "DSP0N1INT0STAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0xC4 31. "DSP0N1GPIO31,GPIO31 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xC4 30. "DSP0N1GPIO30,GPIO30 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xC4 29. "DSP0N1GPIO29,GPIO29 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xC4 28. "DSP0N1GPIO28,GPIO28 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xC4 27. "DSP0N1GPIO27,GPIO27 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xC4 26. "DSP0N1GPIO26,GPIO26 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xC4 25. "DSP0N1GPIO25,GPIO25 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xC4 24. "DSP0N1GPIO24,GPIO24 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xC4 23. "DSP0N1GPIO23,GPIO23 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xC4 22. "DSP0N1GPIO22,GPIO22 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xC4 21. "DSP0N1GPIO21,GPIO21 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0xC4 20. "DSP0N1GPIO20,GPIO20 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0xC4 19. "DSP0N1GPIO19,GPIO19 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xC4 18. "DSP0N1GPIO18,GPIO18 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0xC4 17. "DSP0N1GPIO17,GPIO17 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xC4 16. "DSP0N1GPIO16,GPIO16 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0xC4 15. "DSP0N1GPIO15,GPIO15 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0xC4 14. "DSP0N1GPIO14,GPIO14 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0xC4 13. "DSP0N1GPIO13,GPIO13 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xC4 12. "DSP0N1GPIO12,GPIO12 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0xC4 11. "DSP0N1GPIO11,GPIO11 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xC4 10. "DSP0N1GPIO10,GPIO10 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0xC4 9. "DSP0N1GPIO9,GPIO9 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xC4 8. "DSP0N1GPIO8,GPIO8 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0xC4 7. "DSP0N1GPIO7,GPIO7 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xC4 6. "DSP0N1GPIO6,GPIO6 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0xC4 5. "DSP0N1GPIO5,GPIO5 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xC4 4. "DSP0N1GPIO4,GPIO4 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0xC4 3. "DSP0N1GPIO3,GPIO3 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0xC4 2. "DSP0N1GPIO2,GPIO2 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0xC4 1. "DSP0N1GPIO1,GPIO1 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0xC4 0. "DSP0N1GPIO0,GPIO0 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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line.long 0xC8 "DSP0N1INT0CLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
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bitfld.long 0xC8 31. "DSP0N1GPIO31,GPIO31 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0xC8 30. "DSP0N1GPIO30,GPIO30 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0xC8 29. "DSP0N1GPIO29,GPIO29 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0xC8 28. "DSP0N1GPIO28,GPIO28 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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|
newline
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bitfld.long 0xC8 27. "DSP0N1GPIO27,GPIO27 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xC8 26. "DSP0N1GPIO26,GPIO26 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0xC8 25. "DSP0N1GPIO25,GPIO25 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0xC8 24. "DSP0N1GPIO24,GPIO24 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0xC8 23. "DSP0N1GPIO23,GPIO23 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xC8 22. "DSP0N1GPIO22,GPIO22 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0xC8 21. "DSP0N1GPIO21,GPIO21 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xC8 20. "DSP0N1GPIO20,GPIO20 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0xC8 19. "DSP0N1GPIO19,GPIO19 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xC8 18. "DSP0N1GPIO18,GPIO18 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0xC8 17. "DSP0N1GPIO17,GPIO17 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xC8 16. "DSP0N1GPIO16,GPIO16 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0xC8 15. "DSP0N1GPIO15,GPIO15 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0xC8 14. "DSP0N1GPIO14,GPIO14 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0xC8 13. "DSP0N1GPIO13,GPIO13 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xC8 12. "DSP0N1GPIO12,GPIO12 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0xC8 11. "DSP0N1GPIO11,GPIO11 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xC8 10. "DSP0N1GPIO10,GPIO10 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0xC8 9. "DSP0N1GPIO9,GPIO9 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xC8 8. "DSP0N1GPIO8,GPIO8 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0xC8 7. "DSP0N1GPIO7,GPIO7 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0xC8 6. "DSP0N1GPIO6,GPIO6 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0xC8 5. "DSP0N1GPIO5,GPIO5 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xC8 4. "DSP0N1GPIO4,GPIO4 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0xC8 3. "DSP0N1GPIO3,GPIO3 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xC8 2. "DSP0N1GPIO2,GPIO2 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0xC8 1. "DSP0N1GPIO1,GPIO1 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0xC8 0. "DSP0N1GPIO0,GPIO0 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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line.long 0xCC "DSP0N1INT0SET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
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bitfld.long 0xCC 31. "DSP0N1GPIO31,GPIO31 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xCC 30. "DSP0N1GPIO30,GPIO30 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0xCC 29. "DSP0N1GPIO29,GPIO29 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xCC 28. "DSP0N1GPIO28,GPIO28 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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|
newline
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bitfld.long 0xCC 27. "DSP0N1GPIO27,GPIO27 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xCC 26. "DSP0N1GPIO26,GPIO26 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0xCC 25. "DSP0N1GPIO25,GPIO25 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xCC 24. "DSP0N1GPIO24,GPIO24 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0xCC 23. "DSP0N1GPIO23,GPIO23 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xCC 22. "DSP0N1GPIO22,GPIO22 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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|
newline
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bitfld.long 0xCC 21. "DSP0N1GPIO21,GPIO21 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xCC 20. "DSP0N1GPIO20,GPIO20 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0xCC 19. "DSP0N1GPIO19,GPIO19 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0xCC 18. "DSP0N1GPIO18,GPIO18 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0xCC 17. "DSP0N1GPIO17,GPIO17 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0xCC 16. "DSP0N1GPIO16,GPIO16 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0xCC 15. "DSP0N1GPIO15,GPIO15 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0xCC 14. "DSP0N1GPIO14,GPIO14 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0xCC 13. "DSP0N1GPIO13,GPIO13 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0xCC 12. "DSP0N1GPIO12,GPIO12 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0xCC 11. "DSP0N1GPIO11,GPIO11 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0xCC 10. "DSP0N1GPIO10,GPIO10 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0xCC 9. "DSP0N1GPIO9,GPIO9 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0xCC 8. "DSP0N1GPIO8,GPIO8 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0xCC 7. "DSP0N1GPIO7,GPIO7 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0xCC 6. "DSP0N1GPIO6,GPIO6 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0xCC 5. "DSP0N1GPIO5,GPIO5 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0xCC 4. "DSP0N1GPIO4,GPIO4 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0xCC 3. "DSP0N1GPIO3,GPIO3 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0xCC 2. "DSP0N1GPIO2,GPIO2 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0xCC 1. "DSP0N1GPIO1,GPIO1 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0xCC 0. "DSP0N1GPIO0,GPIO0 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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line.long 0xD0 "DSP0N1INT1EN,Set bits in this register to allow this module to generate the corresponding interrupt."
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bitfld.long 0xD0 31. "DSP0N1GPIO63,GPIO63 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0xD0 30. "DSP0N1GPIO62,GPIO62 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0xD0 29. "DSP0N1GPIO61,GPIO61 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xD0 28. "DSP0N1GPIO60,GPIO60 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0xD0 27. "DSP0N1GPIO59,GPIO59 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xD0 26. "DSP0N1GPIO58,GPIO58 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0xD0 25. "DSP0N1GPIO57,GPIO57 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xD0 24. "DSP0N1GPIO56,GPIO56 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0xD0 23. "DSP0N1GPIO55,GPIO55 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xD0 22. "DSP0N1GPIO54,GPIO54 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0xD0 21. "DSP0N1GPIO53,GPIO53 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0xD0 20. "DSP0N1GPIO52,GPIO52 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0xD0 19. "DSP0N1GPIO51,GPIO51 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xD0 18. "DSP0N1GPIO50,GPIO50 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0xD0 17. "DSP0N1GPIO49,GPIO49 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xD0 16. "DSP0N1GPIO48,GPIO48 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0xD0 15. "DSP0N1GPIO47,GPIO47 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xD0 14. "DSP0N1GPIO46,GPIO46 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0xD0 13. "DSP0N1GPIO45,GPIO45 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xD0 12. "DSP0N1GPIO44,GPIO44 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
|
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bitfld.long 0xD0 11. "DSP0N1GPIO43,GPIO43 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xD0 10. "DSP0N1GPIO42,GPIO42 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
|
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bitfld.long 0xD0 9. "DSP0N1GPIO41,GPIO41 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xD0 8. "DSP0N1GPIO40,GPIO40 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
|
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bitfld.long 0xD0 7. "DSP0N1GPIO39,GPIO39 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xD0 6. "DSP0N1GPIO38,GPIO38 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0xD0 5. "DSP0N1GPIO37,GPIO37 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xD0 4. "DSP0N1GPIO36,GPIO36 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0xD0 3. "DSP0N1GPIO35,GPIO35 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xD0 2. "DSP0N1GPIO34,GPIO34 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
|
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bitfld.long 0xD0 1. "DSP0N1GPIO33,GPIO33 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xD0 0. "DSP0N1GPIO32,GPIO32 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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line.long 0xD4 "DSP0N1INT1STAT,Read bits from this register to discover the cause of a recent interrupt."
|
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bitfld.long 0xD4 31. "DSP0N1GPIO63,GPIO63 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xD4 30. "DSP0N1GPIO62,GPIO62 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
|
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bitfld.long 0xD4 29. "DSP0N1GPIO61,GPIO61 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xD4 28. "DSP0N1GPIO60,GPIO60 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
|
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bitfld.long 0xD4 27. "DSP0N1GPIO59,GPIO59 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xD4 26. "DSP0N1GPIO58,GPIO58 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
|
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bitfld.long 0xD4 25. "DSP0N1GPIO57,GPIO57 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xD4 24. "DSP0N1GPIO56,GPIO56 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xD4 23. "DSP0N1GPIO55,GPIO55 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xD4 22. "DSP0N1GPIO54,GPIO54 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xD4 21. "DSP0N1GPIO53,GPIO53 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xD4 20. "DSP0N1GPIO52,GPIO52 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xD4 19. "DSP0N1GPIO51,GPIO51 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xD4 18. "DSP0N1GPIO50,GPIO50 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xD4 17. "DSP0N1GPIO49,GPIO49 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xD4 16. "DSP0N1GPIO48,GPIO48 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
|
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bitfld.long 0xD4 15. "DSP0N1GPIO47,GPIO47 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xD4 14. "DSP0N1GPIO46,GPIO46 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
|
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bitfld.long 0xD4 13. "DSP0N1GPIO45,GPIO45 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xD4 12. "DSP0N1GPIO44,GPIO44 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xD4 11. "DSP0N1GPIO43,GPIO43 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xD4 10. "DSP0N1GPIO42,GPIO42 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xD4 9. "DSP0N1GPIO41,GPIO41 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xD4 8. "DSP0N1GPIO40,GPIO40 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xD4 7. "DSP0N1GPIO39,GPIO39 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xD4 6. "DSP0N1GPIO38,GPIO38 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xD4 5. "DSP0N1GPIO37,GPIO37 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xD4 4. "DSP0N1GPIO36,GPIO36 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xD4 3. "DSP0N1GPIO35,GPIO35 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xD4 2. "DSP0N1GPIO34,GPIO34 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xD4 1. "DSP0N1GPIO33,GPIO33 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xD4 0. "DSP0N1GPIO32,GPIO32 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
line.long 0xD8 "DSP0N1INT1CLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0xD8 31. "DSP0N1GPIO63,GPIO63 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xD8 30. "DSP0N1GPIO62,GPIO62 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xD8 29. "DSP0N1GPIO61,GPIO61 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xD8 28. "DSP0N1GPIO60,GPIO60 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xD8 27. "DSP0N1GPIO59,GPIO59 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xD8 26. "DSP0N1GPIO58,GPIO58 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xD8 25. "DSP0N1GPIO57,GPIO57 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xD8 24. "DSP0N1GPIO56,GPIO56 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xD8 23. "DSP0N1GPIO55,GPIO55 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xD8 22. "DSP0N1GPIO54,GPIO54 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xD8 21. "DSP0N1GPIO53,GPIO53 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xD8 20. "DSP0N1GPIO52,GPIO52 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xD8 19. "DSP0N1GPIO51,GPIO51 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xD8 18. "DSP0N1GPIO50,GPIO50 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xD8 17. "DSP0N1GPIO49,GPIO49 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xD8 16. "DSP0N1GPIO48,GPIO48 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0xD8 15. "DSP0N1GPIO47,GPIO47 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xD8 14. "DSP0N1GPIO46,GPIO46 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0xD8 13. "DSP0N1GPIO45,GPIO45 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xD8 12. "DSP0N1GPIO44,GPIO44 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0xD8 11. "DSP0N1GPIO43,GPIO43 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xD8 10. "DSP0N1GPIO42,GPIO42 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xD8 9. "DSP0N1GPIO41,GPIO41 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xD8 8. "DSP0N1GPIO40,GPIO40 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0xD8 7. "DSP0N1GPIO39,GPIO39 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xD8 6. "DSP0N1GPIO38,GPIO38 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0xD8 5. "DSP0N1GPIO37,GPIO37 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xD8 4. "DSP0N1GPIO36,GPIO36 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0xD8 3. "DSP0N1GPIO35,GPIO35 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xD8 2. "DSP0N1GPIO34,GPIO34 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0xD8 1. "DSP0N1GPIO33,GPIO33 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xD8 0. "DSP0N1GPIO32,GPIO32 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
line.long 0xDC "DSP0N1INT1SET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
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bitfld.long 0xDC 31. "DSP0N1GPIO63,GPIO63 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xDC 30. "DSP0N1GPIO62,GPIO62 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0xDC 29. "DSP0N1GPIO61,GPIO61 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xDC 28. "DSP0N1GPIO60,GPIO60 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0xDC 27. "DSP0N1GPIO59,GPIO59 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xDC 26. "DSP0N1GPIO58,GPIO58 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xDC 25. "DSP0N1GPIO57,GPIO57 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xDC 24. "DSP0N1GPIO56,GPIO56 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0xDC 23. "DSP0N1GPIO55,GPIO55 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xDC 22. "DSP0N1GPIO54,GPIO54 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xDC 21. "DSP0N1GPIO53,GPIO53 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xDC 20. "DSP0N1GPIO52,GPIO52 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xDC 19. "DSP0N1GPIO51,GPIO51 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xDC 18. "DSP0N1GPIO50,GPIO50 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xDC 17. "DSP0N1GPIO49,GPIO49 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xDC 16. "DSP0N1GPIO48,GPIO48 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0xDC 15. "DSP0N1GPIO47,GPIO47 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xDC 14. "DSP0N1GPIO46,GPIO46 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0xDC 13. "DSP0N1GPIO45,GPIO45 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xDC 12. "DSP0N1GPIO44,GPIO44 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0xDC 11. "DSP0N1GPIO43,GPIO43 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xDC 10. "DSP0N1GPIO42,GPIO42 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xDC 9. "DSP0N1GPIO41,GPIO41 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xDC 8. "DSP0N1GPIO40,GPIO40 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xDC 7. "DSP0N1GPIO39,GPIO39 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xDC 6. "DSP0N1GPIO38,GPIO38 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0xDC 5. "DSP0N1GPIO37,GPIO37 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xDC 4. "DSP0N1GPIO36,GPIO36 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0xDC 3. "DSP0N1GPIO35,GPIO35 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xDC 2. "DSP0N1GPIO34,GPIO34 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0xDC 1. "DSP0N1GPIO33,GPIO33 DSP0 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0xDC 0. "DSP0N1GPIO32,GPIO32 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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line.long 0xE0 "DSP0N1INT2EN,Set bits in this register to allow this module to generate the corresponding interrupt."
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bitfld.long 0xE0 31. "DSP0N1GPIO95,GPIO95 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xE0 30. "DSP0N1GPIO94,GPIO94 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xE0 29. "DSP0N1GPIO93,GPIO93 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xE0 28. "DSP0N1GPIO92,GPIO92 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xE0 27. "DSP0N1GPIO91,GPIO91 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xE0 26. "DSP0N1GPIO90,GPIO90 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xE0 25. "DSP0N1GPIO89,GPIO89 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xE0 24. "DSP0N1GPIO88,GPIO88 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xE0 23. "DSP0N1GPIO87,GPIO87 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xE0 22. "DSP0N1GPIO86,GPIO86 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xE0 21. "DSP0N1GPIO85,GPIO85 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xE0 20. "DSP0N1GPIO84,GPIO84 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xE0 19. "DSP0N1GPIO83,GPIO83 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xE0 18. "DSP0N1GPIO82,GPIO82 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xE0 17. "DSP0N1GPIO81,GPIO81 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xE0 16. "DSP0N1GPIO80,GPIO80 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xE0 15. "DSP0N1GPIO79,GPIO79 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xE0 14. "DSP0N1GPIO78,GPIO78 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xE0 13. "DSP0N1GPIO77,GPIO77 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xE0 12. "DSP0N1GPIO76,GPIO76 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xE0 11. "DSP0N1GPIO75,GPIO75 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xE0 10. "DSP0N1GPIO74,GPIO74 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xE0 9. "DSP0N1GPIO73,GPIO73 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xE0 8. "DSP0N1GPIO72,GPIO72 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xE0 7. "DSP0N1GPIO71,GPIO71 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xE0 6. "DSP0N1GPIO70,GPIO70 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xE0 5. "DSP0N1GPIO69,GPIO69 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xE0 4. "DSP0N1GPIO68,GPIO68 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xE0 3. "DSP0N1GPIO67,GPIO67 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xE0 2. "DSP0N1GPIO66,GPIO66 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xE0 1. "DSP0N1GPIO65,GPIO65 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xE0 0. "DSP0N1GPIO64,GPIO64 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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line.long 0xE4 "DSP0N1INT2STAT,Read bits from this register to discover the cause of a recent interrupt."
|
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bitfld.long 0xE4 31. "DSP0N1GPIO95,GPIO95 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xE4 30. "DSP0N1GPIO94,GPIO94 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xE4 29. "DSP0N1GPIO93,GPIO93 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xE4 28. "DSP0N1GPIO92,GPIO92 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xE4 27. "DSP0N1GPIO91,GPIO91 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xE4 26. "DSP0N1GPIO90,GPIO90 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xE4 25. "DSP0N1GPIO89,GPIO89 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xE4 24. "DSP0N1GPIO88,GPIO88 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xE4 23. "DSP0N1GPIO87,GPIO87 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xE4 22. "DSP0N1GPIO86,GPIO86 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xE4 21. "DSP0N1GPIO85,GPIO85 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xE4 20. "DSP0N1GPIO84,GPIO84 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xE4 19. "DSP0N1GPIO83,GPIO83 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xE4 18. "DSP0N1GPIO82,GPIO82 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xE4 17. "DSP0N1GPIO81,GPIO81 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xE4 16. "DSP0N1GPIO80,GPIO80 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xE4 15. "DSP0N1GPIO79,GPIO79 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xE4 14. "DSP0N1GPIO78,GPIO78 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xE4 13. "DSP0N1GPIO77,GPIO77 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xE4 12. "DSP0N1GPIO76,GPIO76 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xE4 11. "DSP0N1GPIO75,GPIO75 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xE4 10. "DSP0N1GPIO74,GPIO74 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xE4 9. "DSP0N1GPIO73,GPIO73 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xE4 8. "DSP0N1GPIO72,GPIO72 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xE4 7. "DSP0N1GPIO71,GPIO71 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xE4 6. "DSP0N1GPIO70,GPIO70 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xE4 5. "DSP0N1GPIO69,GPIO69 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xE4 4. "DSP0N1GPIO68,GPIO68 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xE4 3. "DSP0N1GPIO67,GPIO67 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xE4 2. "DSP0N1GPIO66,GPIO66 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xE4 1. "DSP0N1GPIO65,GPIO65 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xE4 0. "DSP0N1GPIO64,GPIO64 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
line.long 0xE8 "DSP0N1INT2CLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0xE8 31. "DSP0N1GPIO95,GPIO95 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xE8 30. "DSP0N1GPIO94,GPIO94 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xE8 29. "DSP0N1GPIO93,GPIO93 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xE8 28. "DSP0N1GPIO92,GPIO92 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xE8 27. "DSP0N1GPIO91,GPIO91 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xE8 26. "DSP0N1GPIO90,GPIO90 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xE8 25. "DSP0N1GPIO89,GPIO89 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xE8 24. "DSP0N1GPIO88,GPIO88 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xE8 23. "DSP0N1GPIO87,GPIO87 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xE8 22. "DSP0N1GPIO86,GPIO86 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xE8 21. "DSP0N1GPIO85,GPIO85 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xE8 20. "DSP0N1GPIO84,GPIO84 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xE8 19. "DSP0N1GPIO83,GPIO83 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xE8 18. "DSP0N1GPIO82,GPIO82 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xE8 17. "DSP0N1GPIO81,GPIO81 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xE8 16. "DSP0N1GPIO80,GPIO80 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xE8 15. "DSP0N1GPIO79,GPIO79 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xE8 14. "DSP0N1GPIO78,GPIO78 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xE8 13. "DSP0N1GPIO77,GPIO77 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xE8 12. "DSP0N1GPIO76,GPIO76 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xE8 11. "DSP0N1GPIO75,GPIO75 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xE8 10. "DSP0N1GPIO74,GPIO74 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xE8 9. "DSP0N1GPIO73,GPIO73 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xE8 8. "DSP0N1GPIO72,GPIO72 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xE8 7. "DSP0N1GPIO71,GPIO71 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xE8 6. "DSP0N1GPIO70,GPIO70 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xE8 5. "DSP0N1GPIO69,GPIO69 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xE8 4. "DSP0N1GPIO68,GPIO68 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xE8 3. "DSP0N1GPIO67,GPIO67 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xE8 2. "DSP0N1GPIO66,GPIO66 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xE8 1. "DSP0N1GPIO65,GPIO65 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xE8 0. "DSP0N1GPIO64,GPIO64 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
line.long 0xEC "DSP0N1INT2SET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xEC 31. "DSP0N1GPIO95,GPIO95 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xEC 30. "DSP0N1GPIO94,GPIO94 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xEC 29. "DSP0N1GPIO93,GPIO93 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xEC 28. "DSP0N1GPIO92,GPIO92 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xEC 27. "DSP0N1GPIO91,GPIO91 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xEC 26. "DSP0N1GPIO90,GPIO90 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xEC 25. "DSP0N1GPIO89,GPIO89 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xEC 24. "DSP0N1GPIO88,GPIO88 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xEC 23. "DSP0N1GPIO87,GPIO87 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xEC 22. "DSP0N1GPIO86,GPIO86 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xEC 21. "DSP0N1GPIO85,GPIO85 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xEC 20. "DSP0N1GPIO84,GPIO84 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xEC 19. "DSP0N1GPIO83,GPIO83 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xEC 18. "DSP0N1GPIO82,GPIO82 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xEC 17. "DSP0N1GPIO81,GPIO81 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xEC 16. "DSP0N1GPIO80,GPIO80 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0xEC 15. "DSP0N1GPIO79,GPIO79 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xEC 14. "DSP0N1GPIO78,GPIO78 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xEC 13. "DSP0N1GPIO77,GPIO77 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xEC 12. "DSP0N1GPIO76,GPIO76 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0xEC 11. "DSP0N1GPIO75,GPIO75 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xEC 10. "DSP0N1GPIO74,GPIO74 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xEC 9. "DSP0N1GPIO73,GPIO73 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xEC 8. "DSP0N1GPIO72,GPIO72 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0xEC 7. "DSP0N1GPIO71,GPIO71 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xEC 6. "DSP0N1GPIO70,GPIO70 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0xEC 5. "DSP0N1GPIO69,GPIO69 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xEC 4. "DSP0N1GPIO68,GPIO68 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0xEC 3. "DSP0N1GPIO67,GPIO67 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xEC 2. "DSP0N1GPIO66,GPIO66 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0xEC 1. "DSP0N1GPIO65,GPIO65 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xEC 0. "DSP0N1GPIO64,GPIO64 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
line.long 0xF0 "DSP0N1INT3EN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
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bitfld.long 0xF0 31. "DSP0N1GPIO127,GPIO127 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF0 30. "DSP0N1GPIO126,GPIO126 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0xF0 29. "DSP0N1GPIO125,GPIO125 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF0 28. "DSP0N1GPIO124,GPIO124 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xF0 27. "DSP0N1GPIO123,GPIO123 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF0 26. "DSP0N1GPIO122,GPIO122 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xF0 25. "DSP0N1GPIO121,GPIO121 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF0 24. "DSP0N1GPIO120,GPIO120 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xF0 23. "DSP0N1GPIO119,GPIO119 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF0 22. "DSP0N1GPIO118,GPIO118 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xF0 21. "DSP0N1GPIO117,GPIO117 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF0 20. "DSP0N1GPIO116,GPIO116 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xF0 19. "DSP0N1GPIO115,GPIO115 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF0 18. "DSP0N1GPIO114,GPIO114 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xF0 17. "DSP0N1GPIO113,GPIO113 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF0 16. "DSP0N1GPIO112,GPIO112 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0xF0 15. "DSP0N1GPIO111,GPIO111 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0xF0 14. "DSP0N1GPIO110,GPIO110 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xF0 13. "DSP0N1GPIO109,GPIO109 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF0 12. "DSP0N1GPIO108,GPIO108 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xF0 11. "DSP0N1GPIO107,GPIO107 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF0 10. "DSP0N1GPIO106,GPIO106 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xF0 9. "DSP0N1GPIO105,GPIO105 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF0 8. "DSP0N1GPIO104,GPIO104 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xF0 7. "DSP0N1GPIO103,GPIO103 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF0 6. "DSP0N1GPIO102,GPIO102 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xF0 5. "DSP0N1GPIO101,GPIO101 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF0 4. "DSP0N1GPIO100,GPIO100 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xF0 3. "DSP0N1GPIO99,GPIO99 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF0 2. "DSP0N1GPIO98,GPIO98 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xF0 1. "DSP0N1GPIO97,GPIO97 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF0 0. "DSP0N1GPIO96,GPIO96 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
line.long 0xF4 "DSP0N1INT3STAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0xF4 31. "DSP0N1GPIO127,GPIO127 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF4 30. "DSP0N1GPIO126,GPIO126 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xF4 29. "DSP0N1GPIO125,GPIO125 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF4 28. "DSP0N1GPIO124,GPIO124 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xF4 27. "DSP0N1GPIO123,GPIO123 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF4 26. "DSP0N1GPIO122,GPIO122 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xF4 25. "DSP0N1GPIO121,GPIO121 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF4 24. "DSP0N1GPIO120,GPIO120 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xF4 23. "DSP0N1GPIO119,GPIO119 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF4 22. "DSP0N1GPIO118,GPIO118 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xF4 21. "DSP0N1GPIO117,GPIO117 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF4 20. "DSP0N1GPIO116,GPIO116 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xF4 19. "DSP0N1GPIO115,GPIO115 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF4 18. "DSP0N1GPIO114,GPIO114 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xF4 17. "DSP0N1GPIO113,GPIO113 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF4 16. "DSP0N1GPIO112,GPIO112 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xF4 15. "DSP0N1GPIO111,GPIO111 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF4 14. "DSP0N1GPIO110,GPIO110 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xF4 13. "DSP0N1GPIO109,GPIO109 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF4 12. "DSP0N1GPIO108,GPIO108 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xF4 11. "DSP0N1GPIO107,GPIO107 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF4 10. "DSP0N1GPIO106,GPIO106 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xF4 9. "DSP0N1GPIO105,GPIO105 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF4 8. "DSP0N1GPIO104,GPIO104 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xF4 7. "DSP0N1GPIO103,GPIO103 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF4 6. "DSP0N1GPIO102,GPIO102 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xF4 5. "DSP0N1GPIO101,GPIO101 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF4 4. "DSP0N1GPIO100,GPIO100 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xF4 3. "DSP0N1GPIO99,GPIO99 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF4 2. "DSP0N1GPIO98,GPIO98 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xF4 1. "DSP0N1GPIO97,GPIO97 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF4 0. "DSP0N1GPIO96,GPIO96 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
line.long 0xF8 "DSP0N1INT3CLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0xF8 31. "DSP0N1GPIO127,GPIO127 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF8 30. "DSP0N1GPIO126,GPIO126 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xF8 29. "DSP0N1GPIO125,GPIO125 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF8 28. "DSP0N1GPIO124,GPIO124 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xF8 27. "DSP0N1GPIO123,GPIO123 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF8 26. "DSP0N1GPIO122,GPIO122 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xF8 25. "DSP0N1GPIO121,GPIO121 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF8 24. "DSP0N1GPIO120,GPIO120 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xF8 23. "DSP0N1GPIO119,GPIO119 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF8 22. "DSP0N1GPIO118,GPIO118 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xF8 21. "DSP0N1GPIO117,GPIO117 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF8 20. "DSP0N1GPIO116,GPIO116 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xF8 19. "DSP0N1GPIO115,GPIO115 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF8 18. "DSP0N1GPIO114,GPIO114 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xF8 17. "DSP0N1GPIO113,GPIO113 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF8 16. "DSP0N1GPIO112,GPIO112 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xF8 15. "DSP0N1GPIO111,GPIO111 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF8 14. "DSP0N1GPIO110,GPIO110 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xF8 13. "DSP0N1GPIO109,GPIO109 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF8 12. "DSP0N1GPIO108,GPIO108 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xF8 11. "DSP0N1GPIO107,GPIO107 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF8 10. "DSP0N1GPIO106,GPIO106 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xF8 9. "DSP0N1GPIO105,GPIO105 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF8 8. "DSP0N1GPIO104,GPIO104 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xF8 7. "DSP0N1GPIO103,GPIO103 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF8 6. "DSP0N1GPIO102,GPIO102 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xF8 5. "DSP0N1GPIO101,GPIO101 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF8 4. "DSP0N1GPIO100,GPIO100 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xF8 3. "DSP0N1GPIO99,GPIO99 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF8 2. "DSP0N1GPIO98,GPIO98 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xF8 1. "DSP0N1GPIO97,GPIO97 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xF8 0. "DSP0N1GPIO96,GPIO96 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
line.long 0xFC "DSP0N1INT3SET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xFC 31. "DSP0N1GPIO127,GPIO127 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xFC 30. "DSP0N1GPIO126,GPIO126 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xFC 29. "DSP0N1GPIO125,GPIO125 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xFC 28. "DSP0N1GPIO124,GPIO124 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xFC 27. "DSP0N1GPIO123,GPIO123 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xFC 26. "DSP0N1GPIO122,GPIO122 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xFC 25. "DSP0N1GPIO121,GPIO121 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xFC 24. "DSP0N1GPIO120,GPIO120 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xFC 23. "DSP0N1GPIO119,GPIO119 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xFC 22. "DSP0N1GPIO118,GPIO118 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xFC 21. "DSP0N1GPIO117,GPIO117 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xFC 20. "DSP0N1GPIO116,GPIO116 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xFC 19. "DSP0N1GPIO115,GPIO115 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xFC 18. "DSP0N1GPIO114,GPIO114 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xFC 17. "DSP0N1GPIO113,GPIO113 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xFC 16. "DSP0N1GPIO112,GPIO112 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xFC 15. "DSP0N1GPIO111,GPIO111 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xFC 14. "DSP0N1GPIO110,GPIO110 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xFC 13. "DSP0N1GPIO109,GPIO109 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xFC 12. "DSP0N1GPIO108,GPIO108 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xFC 11. "DSP0N1GPIO107,GPIO107 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xFC 10. "DSP0N1GPIO106,GPIO106 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xFC 9. "DSP0N1GPIO105,GPIO105 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xFC 8. "DSP0N1GPIO104,GPIO104 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xFC 7. "DSP0N1GPIO103,GPIO103 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xFC 6. "DSP0N1GPIO102,GPIO102 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xFC 5. "DSP0N1GPIO101,GPIO101 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xFC 4. "DSP0N1GPIO100,GPIO100 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0xFC 3. "DSP0N1GPIO99,GPIO99 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xFC 2. "DSP0N1GPIO98,GPIO98 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0xFC 1. "DSP0N1GPIO97,GPIO97 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0xFC 0. "DSP0N1GPIO96,GPIO96 DSP0 N1-priority interrupt." "?,1: priority interrupt"
|
|
line.long 0x100 "DSP1N0INT0EN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x100 31. "DSP1N0GPIO31,GPIO31 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x100 30. "DSP1N0GPIO30,GPIO30 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x100 29. "DSP1N0GPIO29,GPIO29 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x100 28. "DSP1N0GPIO28,GPIO28 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x100 27. "DSP1N0GPIO27,GPIO27 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x100 26. "DSP1N0GPIO26,GPIO26 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x100 25. "DSP1N0GPIO25,GPIO25 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x100 24. "DSP1N0GPIO24,GPIO24 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x100 23. "DSP1N0GPIO23,GPIO23 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x100 22. "DSP1N0GPIO22,GPIO22 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x100 21. "DSP1N0GPIO21,GPIO21 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x100 20. "DSP1N0GPIO20,GPIO20 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x100 19. "DSP1N0GPIO19,GPIO19 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x100 18. "DSP1N0GPIO18,GPIO18 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x100 17. "DSP1N0GPIO17,GPIO17 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x100 16. "DSP1N0GPIO16,GPIO16 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x100 15. "DSP1N0GPIO15,GPIO15 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x100 14. "DSP1N0GPIO14,GPIO14 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x100 13. "DSP1N0GPIO13,GPIO13 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x100 12. "DSP1N0GPIO12,GPIO12 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x100 11. "DSP1N0GPIO11,GPIO11 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x100 10. "DSP1N0GPIO10,GPIO10 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x100 9. "DSP1N0GPIO9,GPIO9 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x100 8. "DSP1N0GPIO8,GPIO8 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x100 7. "DSP1N0GPIO7,GPIO7 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x100 6. "DSP1N0GPIO6,GPIO6 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x100 5. "DSP1N0GPIO5,GPIO5 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x100 4. "DSP1N0GPIO4,GPIO4 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x100 3. "DSP1N0GPIO3,GPIO3 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x100 2. "DSP1N0GPIO2,GPIO2 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x100 1. "DSP1N0GPIO1,GPIO1 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x100 0. "DSP1N0GPIO0,GPIO0 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x104 "DSP1N0INT0STAT,Read bits from this register to discover the cause of a recent interrupt."
|
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bitfld.long 0x104 31. "DSP1N0GPIO31,GPIO31 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x104 30. "DSP1N0GPIO30,GPIO30 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x104 29. "DSP1N0GPIO29,GPIO29 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x104 28. "DSP1N0GPIO28,GPIO28 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x104 27. "DSP1N0GPIO27,GPIO27 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x104 26. "DSP1N0GPIO26,GPIO26 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x104 25. "DSP1N0GPIO25,GPIO25 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x104 24. "DSP1N0GPIO24,GPIO24 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x104 23. "DSP1N0GPIO23,GPIO23 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x104 22. "DSP1N0GPIO22,GPIO22 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x104 21. "DSP1N0GPIO21,GPIO21 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x104 20. "DSP1N0GPIO20,GPIO20 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x104 19. "DSP1N0GPIO19,GPIO19 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x104 18. "DSP1N0GPIO18,GPIO18 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x104 17. "DSP1N0GPIO17,GPIO17 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x104 16. "DSP1N0GPIO16,GPIO16 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x104 15. "DSP1N0GPIO15,GPIO15 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x104 14. "DSP1N0GPIO14,GPIO14 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x104 13. "DSP1N0GPIO13,GPIO13 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x104 12. "DSP1N0GPIO12,GPIO12 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x104 11. "DSP1N0GPIO11,GPIO11 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x104 10. "DSP1N0GPIO10,GPIO10 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x104 9. "DSP1N0GPIO9,GPIO9 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x104 8. "DSP1N0GPIO8,GPIO8 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x104 7. "DSP1N0GPIO7,GPIO7 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x104 6. "DSP1N0GPIO6,GPIO6 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x104 5. "DSP1N0GPIO5,GPIO5 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x104 4. "DSP1N0GPIO4,GPIO4 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x104 3. "DSP1N0GPIO3,GPIO3 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x104 2. "DSP1N0GPIO2,GPIO2 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x104 1. "DSP1N0GPIO1,GPIO1 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x104 0. "DSP1N0GPIO0,GPIO0 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x108 "DSP1N0INT0CLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x108 31. "DSP1N0GPIO31,GPIO31 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x108 30. "DSP1N0GPIO30,GPIO30 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x108 29. "DSP1N0GPIO29,GPIO29 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x108 28. "DSP1N0GPIO28,GPIO28 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x108 27. "DSP1N0GPIO27,GPIO27 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x108 26. "DSP1N0GPIO26,GPIO26 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x108 25. "DSP1N0GPIO25,GPIO25 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x108 24. "DSP1N0GPIO24,GPIO24 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x108 23. "DSP1N0GPIO23,GPIO23 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x108 22. "DSP1N0GPIO22,GPIO22 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x108 21. "DSP1N0GPIO21,GPIO21 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x108 20. "DSP1N0GPIO20,GPIO20 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x108 19. "DSP1N0GPIO19,GPIO19 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x108 18. "DSP1N0GPIO18,GPIO18 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x108 17. "DSP1N0GPIO17,GPIO17 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x108 16. "DSP1N0GPIO16,GPIO16 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x108 15. "DSP1N0GPIO15,GPIO15 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x108 14. "DSP1N0GPIO14,GPIO14 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x108 13. "DSP1N0GPIO13,GPIO13 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x108 12. "DSP1N0GPIO12,GPIO12 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x108 11. "DSP1N0GPIO11,GPIO11 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x108 10. "DSP1N0GPIO10,GPIO10 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x108 9. "DSP1N0GPIO9,GPIO9 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x108 8. "DSP1N0GPIO8,GPIO8 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x108 7. "DSP1N0GPIO7,GPIO7 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x108 6. "DSP1N0GPIO6,GPIO6 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x108 5. "DSP1N0GPIO5,GPIO5 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x108 4. "DSP1N0GPIO4,GPIO4 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x108 3. "DSP1N0GPIO3,GPIO3 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x108 2. "DSP1N0GPIO2,GPIO2 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x108 1. "DSP1N0GPIO1,GPIO1 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x108 0. "DSP1N0GPIO0,GPIO0 DSP1 N0-priority interrupt." "0: priority interrupt,?"
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|
line.long 0x10C "DSP1N0INT0SET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
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bitfld.long 0x10C 31. "DSP1N0GPIO31,GPIO31 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x10C 30. "DSP1N0GPIO30,GPIO30 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x10C 29. "DSP1N0GPIO29,GPIO29 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x10C 28. "DSP1N0GPIO28,GPIO28 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x10C 27. "DSP1N0GPIO27,GPIO27 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x10C 26. "DSP1N0GPIO26,GPIO26 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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newline
|
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bitfld.long 0x10C 25. "DSP1N0GPIO25,GPIO25 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x10C 24. "DSP1N0GPIO24,GPIO24 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x10C 23. "DSP1N0GPIO23,GPIO23 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x10C 22. "DSP1N0GPIO22,GPIO22 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x10C 21. "DSP1N0GPIO21,GPIO21 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x10C 20. "DSP1N0GPIO20,GPIO20 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x10C 19. "DSP1N0GPIO19,GPIO19 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x10C 18. "DSP1N0GPIO18,GPIO18 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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newline
|
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bitfld.long 0x10C 17. "DSP1N0GPIO17,GPIO17 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x10C 16. "DSP1N0GPIO16,GPIO16 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x10C 15. "DSP1N0GPIO15,GPIO15 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x10C 14. "DSP1N0GPIO14,GPIO14 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x10C 13. "DSP1N0GPIO13,GPIO13 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x10C 12. "DSP1N0GPIO12,GPIO12 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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newline
|
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bitfld.long 0x10C 11. "DSP1N0GPIO11,GPIO11 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x10C 10. "DSP1N0GPIO10,GPIO10 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x10C 9. "DSP1N0GPIO9,GPIO9 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x10C 8. "DSP1N0GPIO8,GPIO8 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x10C 7. "DSP1N0GPIO7,GPIO7 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x10C 6. "DSP1N0GPIO6,GPIO6 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x10C 5. "DSP1N0GPIO5,GPIO5 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x10C 4. "DSP1N0GPIO4,GPIO4 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x10C 3. "DSP1N0GPIO3,GPIO3 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x10C 2. "DSP1N0GPIO2,GPIO2 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x10C 1. "DSP1N0GPIO1,GPIO1 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x10C 0. "DSP1N0GPIO0,GPIO0 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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line.long 0x110 "DSP1N0INT1EN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x110 31. "DSP1N0GPIO63,GPIO63 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x110 30. "DSP1N0GPIO62,GPIO62 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x110 29. "DSP1N0GPIO61,GPIO61 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x110 28. "DSP1N0GPIO60,GPIO60 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x110 27. "DSP1N0GPIO59,GPIO59 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x110 26. "DSP1N0GPIO58,GPIO58 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x110 25. "DSP1N0GPIO57,GPIO57 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x110 24. "DSP1N0GPIO56,GPIO56 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x110 23. "DSP1N0GPIO55,GPIO55 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x110 22. "DSP1N0GPIO54,GPIO54 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x110 21. "DSP1N0GPIO53,GPIO53 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x110 20. "DSP1N0GPIO52,GPIO52 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x110 19. "DSP1N0GPIO51,GPIO51 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x110 18. "DSP1N0GPIO50,GPIO50 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x110 17. "DSP1N0GPIO49,GPIO49 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x110 16. "DSP1N0GPIO48,GPIO48 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x110 15. "DSP1N0GPIO47,GPIO47 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x110 14. "DSP1N0GPIO46,GPIO46 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x110 13. "DSP1N0GPIO45,GPIO45 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x110 12. "DSP1N0GPIO44,GPIO44 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x110 11. "DSP1N0GPIO43,GPIO43 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x110 10. "DSP1N0GPIO42,GPIO42 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x110 9. "DSP1N0GPIO41,GPIO41 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x110 8. "DSP1N0GPIO40,GPIO40 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x110 7. "DSP1N0GPIO39,GPIO39 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x110 6. "DSP1N0GPIO38,GPIO38 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x110 5. "DSP1N0GPIO37,GPIO37 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x110 4. "DSP1N0GPIO36,GPIO36 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x110 3. "DSP1N0GPIO35,GPIO35 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x110 2. "DSP1N0GPIO34,GPIO34 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x110 1. "DSP1N0GPIO33,GPIO33 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x110 0. "DSP1N0GPIO32,GPIO32 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x114 "DSP1N0INT1STAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x114 31. "DSP1N0GPIO63,GPIO63 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x114 30. "DSP1N0GPIO62,GPIO62 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x114 29. "DSP1N0GPIO61,GPIO61 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x114 28. "DSP1N0GPIO60,GPIO60 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x114 27. "DSP1N0GPIO59,GPIO59 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x114 26. "DSP1N0GPIO58,GPIO58 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x114 25. "DSP1N0GPIO57,GPIO57 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x114 24. "DSP1N0GPIO56,GPIO56 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x114 23. "DSP1N0GPIO55,GPIO55 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x114 22. "DSP1N0GPIO54,GPIO54 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x114 21. "DSP1N0GPIO53,GPIO53 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x114 20. "DSP1N0GPIO52,GPIO52 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x114 19. "DSP1N0GPIO51,GPIO51 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x114 18. "DSP1N0GPIO50,GPIO50 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x114 17. "DSP1N0GPIO49,GPIO49 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x114 16. "DSP1N0GPIO48,GPIO48 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x114 15. "DSP1N0GPIO47,GPIO47 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x114 14. "DSP1N0GPIO46,GPIO46 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x114 13. "DSP1N0GPIO45,GPIO45 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x114 12. "DSP1N0GPIO44,GPIO44 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x114 11. "DSP1N0GPIO43,GPIO43 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x114 10. "DSP1N0GPIO42,GPIO42 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x114 9. "DSP1N0GPIO41,GPIO41 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x114 8. "DSP1N0GPIO40,GPIO40 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x114 7. "DSP1N0GPIO39,GPIO39 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x114 6. "DSP1N0GPIO38,GPIO38 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x114 5. "DSP1N0GPIO37,GPIO37 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x114 4. "DSP1N0GPIO36,GPIO36 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x114 3. "DSP1N0GPIO35,GPIO35 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x114 2. "DSP1N0GPIO34,GPIO34 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x114 1. "DSP1N0GPIO33,GPIO33 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x114 0. "DSP1N0GPIO32,GPIO32 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x118 "DSP1N0INT1CLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x118 31. "DSP1N0GPIO63,GPIO63 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x118 30. "DSP1N0GPIO62,GPIO62 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x118 29. "DSP1N0GPIO61,GPIO61 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x118 28. "DSP1N0GPIO60,GPIO60 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x118 27. "DSP1N0GPIO59,GPIO59 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x118 26. "DSP1N0GPIO58,GPIO58 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x118 25. "DSP1N0GPIO57,GPIO57 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x118 24. "DSP1N0GPIO56,GPIO56 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x118 23. "DSP1N0GPIO55,GPIO55 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x118 22. "DSP1N0GPIO54,GPIO54 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x118 21. "DSP1N0GPIO53,GPIO53 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x118 20. "DSP1N0GPIO52,GPIO52 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x118 19. "DSP1N0GPIO51,GPIO51 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x118 18. "DSP1N0GPIO50,GPIO50 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x118 17. "DSP1N0GPIO49,GPIO49 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x118 16. "DSP1N0GPIO48,GPIO48 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x118 15. "DSP1N0GPIO47,GPIO47 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x118 14. "DSP1N0GPIO46,GPIO46 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x118 13. "DSP1N0GPIO45,GPIO45 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x118 12. "DSP1N0GPIO44,GPIO44 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x118 11. "DSP1N0GPIO43,GPIO43 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x118 10. "DSP1N0GPIO42,GPIO42 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x118 9. "DSP1N0GPIO41,GPIO41 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x118 8. "DSP1N0GPIO40,GPIO40 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x118 7. "DSP1N0GPIO39,GPIO39 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x118 6. "DSP1N0GPIO38,GPIO38 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x118 5. "DSP1N0GPIO37,GPIO37 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x118 4. "DSP1N0GPIO36,GPIO36 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x118 3. "DSP1N0GPIO35,GPIO35 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x118 2. "DSP1N0GPIO34,GPIO34 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x118 1. "DSP1N0GPIO33,GPIO33 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x118 0. "DSP1N0GPIO32,GPIO32 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x11C "DSP1N0INT1SET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
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bitfld.long 0x11C 31. "DSP1N0GPIO63,GPIO63 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x11C 30. "DSP1N0GPIO62,GPIO62 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x11C 29. "DSP1N0GPIO61,GPIO61 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x11C 28. "DSP1N0GPIO60,GPIO60 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x11C 27. "DSP1N0GPIO59,GPIO59 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x11C 26. "DSP1N0GPIO58,GPIO58 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x11C 25. "DSP1N0GPIO57,GPIO57 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x11C 24. "DSP1N0GPIO56,GPIO56 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x11C 23. "DSP1N0GPIO55,GPIO55 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x11C 22. "DSP1N0GPIO54,GPIO54 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x11C 21. "DSP1N0GPIO53,GPIO53 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x11C 20. "DSP1N0GPIO52,GPIO52 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x11C 19. "DSP1N0GPIO51,GPIO51 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x11C 18. "DSP1N0GPIO50,GPIO50 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x11C 17. "DSP1N0GPIO49,GPIO49 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x11C 16. "DSP1N0GPIO48,GPIO48 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x11C 15. "DSP1N0GPIO47,GPIO47 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x11C 14. "DSP1N0GPIO46,GPIO46 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x11C 13. "DSP1N0GPIO45,GPIO45 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x11C 12. "DSP1N0GPIO44,GPIO44 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x11C 11. "DSP1N0GPIO43,GPIO43 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x11C 10. "DSP1N0GPIO42,GPIO42 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x11C 9. "DSP1N0GPIO41,GPIO41 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x11C 8. "DSP1N0GPIO40,GPIO40 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x11C 7. "DSP1N0GPIO39,GPIO39 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x11C 6. "DSP1N0GPIO38,GPIO38 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x11C 5. "DSP1N0GPIO37,GPIO37 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x11C 4. "DSP1N0GPIO36,GPIO36 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x11C 3. "DSP1N0GPIO35,GPIO35 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x11C 2. "DSP1N0GPIO34,GPIO34 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x11C 1. "DSP1N0GPIO33,GPIO33 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x11C 0. "DSP1N0GPIO32,GPIO32 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x120 "DSP1N0INT2EN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x120 31. "DSP1N0GPIO95,GPIO95 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x120 30. "DSP1N0GPIO94,GPIO94 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x120 29. "DSP1N0GPIO93,GPIO93 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x120 28. "DSP1N0GPIO92,GPIO92 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x120 27. "DSP1N0GPIO91,GPIO91 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x120 26. "DSP1N0GPIO90,GPIO90 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x120 25. "DSP1N0GPIO89,GPIO89 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x120 24. "DSP1N0GPIO88,GPIO88 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x120 23. "DSP1N0GPIO87,GPIO87 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x120 22. "DSP1N0GPIO86,GPIO86 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x120 21. "DSP1N0GPIO85,GPIO85 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x120 20. "DSP1N0GPIO84,GPIO84 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x120 19. "DSP1N0GPIO83,GPIO83 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x120 18. "DSP1N0GPIO82,GPIO82 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x120 17. "DSP1N0GPIO81,GPIO81 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x120 16. "DSP1N0GPIO80,GPIO80 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x120 15. "DSP1N0GPIO79,GPIO79 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x120 14. "DSP1N0GPIO78,GPIO78 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x120 13. "DSP1N0GPIO77,GPIO77 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x120 12. "DSP1N0GPIO76,GPIO76 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x120 11. "DSP1N0GPIO75,GPIO75 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x120 10. "DSP1N0GPIO74,GPIO74 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x120 9. "DSP1N0GPIO73,GPIO73 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x120 8. "DSP1N0GPIO72,GPIO72 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x120 7. "DSP1N0GPIO71,GPIO71 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x120 6. "DSP1N0GPIO70,GPIO70 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x120 5. "DSP1N0GPIO69,GPIO69 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x120 4. "DSP1N0GPIO68,GPIO68 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x120 3. "DSP1N0GPIO67,GPIO67 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x120 2. "DSP1N0GPIO66,GPIO66 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x120 1. "DSP1N0GPIO65,GPIO65 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x120 0. "DSP1N0GPIO64,GPIO64 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x124 "DSP1N0INT2STAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x124 31. "DSP1N0GPIO95,GPIO95 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x124 30. "DSP1N0GPIO94,GPIO94 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x124 29. "DSP1N0GPIO93,GPIO93 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x124 28. "DSP1N0GPIO92,GPIO92 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x124 27. "DSP1N0GPIO91,GPIO91 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x124 26. "DSP1N0GPIO90,GPIO90 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x124 25. "DSP1N0GPIO89,GPIO89 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x124 24. "DSP1N0GPIO88,GPIO88 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x124 23. "DSP1N0GPIO87,GPIO87 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x124 22. "DSP1N0GPIO86,GPIO86 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x124 21. "DSP1N0GPIO85,GPIO85 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x124 20. "DSP1N0GPIO84,GPIO84 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x124 19. "DSP1N0GPIO83,GPIO83 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x124 18. "DSP1N0GPIO82,GPIO82 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x124 17. "DSP1N0GPIO81,GPIO81 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x124 16. "DSP1N0GPIO80,GPIO80 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x124 15. "DSP1N0GPIO79,GPIO79 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x124 14. "DSP1N0GPIO78,GPIO78 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x124 13. "DSP1N0GPIO77,GPIO77 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x124 12. "DSP1N0GPIO76,GPIO76 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x124 11. "DSP1N0GPIO75,GPIO75 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x124 10. "DSP1N0GPIO74,GPIO74 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x124 9. "DSP1N0GPIO73,GPIO73 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x124 8. "DSP1N0GPIO72,GPIO72 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x124 7. "DSP1N0GPIO71,GPIO71 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x124 6. "DSP1N0GPIO70,GPIO70 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x124 5. "DSP1N0GPIO69,GPIO69 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x124 4. "DSP1N0GPIO68,GPIO68 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x124 3. "DSP1N0GPIO67,GPIO67 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x124 2. "DSP1N0GPIO66,GPIO66 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x124 1. "DSP1N0GPIO65,GPIO65 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x124 0. "DSP1N0GPIO64,GPIO64 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x128 "DSP1N0INT2CLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x128 31. "DSP1N0GPIO95,GPIO95 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x128 30. "DSP1N0GPIO94,GPIO94 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x128 29. "DSP1N0GPIO93,GPIO93 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x128 28. "DSP1N0GPIO92,GPIO92 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x128 27. "DSP1N0GPIO91,GPIO91 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x128 26. "DSP1N0GPIO90,GPIO90 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x128 25. "DSP1N0GPIO89,GPIO89 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x128 24. "DSP1N0GPIO88,GPIO88 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x128 23. "DSP1N0GPIO87,GPIO87 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x128 22. "DSP1N0GPIO86,GPIO86 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x128 21. "DSP1N0GPIO85,GPIO85 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x128 20. "DSP1N0GPIO84,GPIO84 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x128 19. "DSP1N0GPIO83,GPIO83 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x128 18. "DSP1N0GPIO82,GPIO82 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x128 17. "DSP1N0GPIO81,GPIO81 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x128 16. "DSP1N0GPIO80,GPIO80 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x128 15. "DSP1N0GPIO79,GPIO79 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x128 14. "DSP1N0GPIO78,GPIO78 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x128 13. "DSP1N0GPIO77,GPIO77 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x128 12. "DSP1N0GPIO76,GPIO76 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x128 11. "DSP1N0GPIO75,GPIO75 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x128 10. "DSP1N0GPIO74,GPIO74 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x128 9. "DSP1N0GPIO73,GPIO73 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x128 8. "DSP1N0GPIO72,GPIO72 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x128 7. "DSP1N0GPIO71,GPIO71 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x128 6. "DSP1N0GPIO70,GPIO70 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x128 5. "DSP1N0GPIO69,GPIO69 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x128 4. "DSP1N0GPIO68,GPIO68 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x128 3. "DSP1N0GPIO67,GPIO67 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x128 2. "DSP1N0GPIO66,GPIO66 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x128 1. "DSP1N0GPIO65,GPIO65 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x128 0. "DSP1N0GPIO64,GPIO64 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x12C "DSP1N0INT2SET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0x12C 31. "DSP1N0GPIO95,GPIO95 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x12C 30. "DSP1N0GPIO94,GPIO94 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x12C 29. "DSP1N0GPIO93,GPIO93 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x12C 28. "DSP1N0GPIO92,GPIO92 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x12C 27. "DSP1N0GPIO91,GPIO91 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x12C 26. "DSP1N0GPIO90,GPIO90 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x12C 25. "DSP1N0GPIO89,GPIO89 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x12C 24. "DSP1N0GPIO88,GPIO88 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x12C 23. "DSP1N0GPIO87,GPIO87 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x12C 22. "DSP1N0GPIO86,GPIO86 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x12C 21. "DSP1N0GPIO85,GPIO85 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x12C 20. "DSP1N0GPIO84,GPIO84 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x12C 19. "DSP1N0GPIO83,GPIO83 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x12C 18. "DSP1N0GPIO82,GPIO82 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x12C 17. "DSP1N0GPIO81,GPIO81 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x12C 16. "DSP1N0GPIO80,GPIO80 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x12C 15. "DSP1N0GPIO79,GPIO79 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x12C 14. "DSP1N0GPIO78,GPIO78 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x12C 13. "DSP1N0GPIO77,GPIO77 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x12C 12. "DSP1N0GPIO76,GPIO76 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x12C 11. "DSP1N0GPIO75,GPIO75 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x12C 10. "DSP1N0GPIO74,GPIO74 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x12C 9. "DSP1N0GPIO73,GPIO73 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x12C 8. "DSP1N0GPIO72,GPIO72 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x12C 7. "DSP1N0GPIO71,GPIO71 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x12C 6. "DSP1N0GPIO70,GPIO70 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x12C 5. "DSP1N0GPIO69,GPIO69 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x12C 4. "DSP1N0GPIO68,GPIO68 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
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bitfld.long 0x12C 3. "DSP1N0GPIO67,GPIO67 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x12C 2. "DSP1N0GPIO66,GPIO66 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x12C 1. "DSP1N0GPIO65,GPIO65 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x12C 0. "DSP1N0GPIO64,GPIO64 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x130 "DSP1N0INT3EN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x130 31. "DSP1N0GPIO127,GPIO127 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x130 30. "DSP1N0GPIO126,GPIO126 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x130 29. "DSP1N0GPIO125,GPIO125 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x130 28. "DSP1N0GPIO124,GPIO124 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x130 27. "DSP1N0GPIO123,GPIO123 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x130 26. "DSP1N0GPIO122,GPIO122 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x130 25. "DSP1N0GPIO121,GPIO121 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x130 24. "DSP1N0GPIO120,GPIO120 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x130 23. "DSP1N0GPIO119,GPIO119 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x130 22. "DSP1N0GPIO118,GPIO118 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x130 21. "DSP1N0GPIO117,GPIO117 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x130 20. "DSP1N0GPIO116,GPIO116 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x130 19. "DSP1N0GPIO115,GPIO115 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x130 18. "DSP1N0GPIO114,GPIO114 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x130 17. "DSP1N0GPIO113,GPIO113 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x130 16. "DSP1N0GPIO112,GPIO112 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x130 15. "DSP1N0GPIO111,GPIO111 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x130 14. "DSP1N0GPIO110,GPIO110 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x130 13. "DSP1N0GPIO109,GPIO109 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x130 12. "DSP1N0GPIO108,GPIO108 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x130 11. "DSP1N0GPIO107,GPIO107 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x130 10. "DSP1N0GPIO106,GPIO106 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x130 9. "DSP1N0GPIO105,GPIO105 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x130 8. "DSP1N0GPIO104,GPIO104 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x130 7. "DSP1N0GPIO103,GPIO103 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x130 6. "DSP1N0GPIO102,GPIO102 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x130 5. "DSP1N0GPIO101,GPIO101 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x130 4. "DSP1N0GPIO100,GPIO100 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x130 3. "DSP1N0GPIO99,GPIO99 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x130 2. "DSP1N0GPIO98,GPIO98 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x130 1. "DSP1N0GPIO97,GPIO97 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x130 0. "DSP1N0GPIO96,GPIO96 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x134 "DSP1N0INT3STAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x134 31. "DSP1N0GPIO127,GPIO127 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x134 30. "DSP1N0GPIO126,GPIO126 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x134 29. "DSP1N0GPIO125,GPIO125 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x134 28. "DSP1N0GPIO124,GPIO124 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x134 27. "DSP1N0GPIO123,GPIO123 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x134 26. "DSP1N0GPIO122,GPIO122 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x134 25. "DSP1N0GPIO121,GPIO121 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x134 24. "DSP1N0GPIO120,GPIO120 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x134 23. "DSP1N0GPIO119,GPIO119 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x134 22. "DSP1N0GPIO118,GPIO118 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x134 21. "DSP1N0GPIO117,GPIO117 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x134 20. "DSP1N0GPIO116,GPIO116 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x134 19. "DSP1N0GPIO115,GPIO115 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x134 18. "DSP1N0GPIO114,GPIO114 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x134 17. "DSP1N0GPIO113,GPIO113 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x134 16. "DSP1N0GPIO112,GPIO112 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x134 15. "DSP1N0GPIO111,GPIO111 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x134 14. "DSP1N0GPIO110,GPIO110 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x134 13. "DSP1N0GPIO109,GPIO109 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x134 12. "DSP1N0GPIO108,GPIO108 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x134 11. "DSP1N0GPIO107,GPIO107 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x134 10. "DSP1N0GPIO106,GPIO106 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x134 9. "DSP1N0GPIO105,GPIO105 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x134 8. "DSP1N0GPIO104,GPIO104 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x134 7. "DSP1N0GPIO103,GPIO103 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x134 6. "DSP1N0GPIO102,GPIO102 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x134 5. "DSP1N0GPIO101,GPIO101 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x134 4. "DSP1N0GPIO100,GPIO100 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x134 3. "DSP1N0GPIO99,GPIO99 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x134 2. "DSP1N0GPIO98,GPIO98 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x134 1. "DSP1N0GPIO97,GPIO97 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x134 0. "DSP1N0GPIO96,GPIO96 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x138 "DSP1N0INT3CLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x138 31. "DSP1N0GPIO127,GPIO127 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x138 30. "DSP1N0GPIO126,GPIO126 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x138 29. "DSP1N0GPIO125,GPIO125 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x138 28. "DSP1N0GPIO124,GPIO124 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x138 27. "DSP1N0GPIO123,GPIO123 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x138 26. "DSP1N0GPIO122,GPIO122 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x138 25. "DSP1N0GPIO121,GPIO121 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x138 24. "DSP1N0GPIO120,GPIO120 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x138 23. "DSP1N0GPIO119,GPIO119 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x138 22. "DSP1N0GPIO118,GPIO118 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x138 21. "DSP1N0GPIO117,GPIO117 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x138 20. "DSP1N0GPIO116,GPIO116 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x138 19. "DSP1N0GPIO115,GPIO115 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x138 18. "DSP1N0GPIO114,GPIO114 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x138 17. "DSP1N0GPIO113,GPIO113 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x138 16. "DSP1N0GPIO112,GPIO112 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x138 15. "DSP1N0GPIO111,GPIO111 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x138 14. "DSP1N0GPIO110,GPIO110 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x138 13. "DSP1N0GPIO109,GPIO109 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x138 12. "DSP1N0GPIO108,GPIO108 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x138 11. "DSP1N0GPIO107,GPIO107 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x138 10. "DSP1N0GPIO106,GPIO106 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x138 9. "DSP1N0GPIO105,GPIO105 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x138 8. "DSP1N0GPIO104,GPIO104 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x138 7. "DSP1N0GPIO103,GPIO103 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x138 6. "DSP1N0GPIO102,GPIO102 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x138 5. "DSP1N0GPIO101,GPIO101 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x138 4. "DSP1N0GPIO100,GPIO100 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x138 3. "DSP1N0GPIO99,GPIO99 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x138 2. "DSP1N0GPIO98,GPIO98 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x138 1. "DSP1N0GPIO97,GPIO97 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x138 0. "DSP1N0GPIO96,GPIO96 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
line.long 0x13C "DSP1N0INT3SET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0x13C 31. "DSP1N0GPIO127,GPIO127 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x13C 30. "DSP1N0GPIO126,GPIO126 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x13C 29. "DSP1N0GPIO125,GPIO125 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x13C 28. "DSP1N0GPIO124,GPIO124 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x13C 27. "DSP1N0GPIO123,GPIO123 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x13C 26. "DSP1N0GPIO122,GPIO122 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x13C 25. "DSP1N0GPIO121,GPIO121 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
bitfld.long 0x13C 24. "DSP1N0GPIO120,GPIO120 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
|
|
bitfld.long 0x13C 23. "DSP1N0GPIO119,GPIO119 DSP1 N0-priority interrupt." "0: priority interrupt,?"
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bitfld.long 0x13C 22. "DSP1N0GPIO118,GPIO118 DSP1 N0-priority interrupt." "0: priority interrupt,?"
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newline
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bitfld.long 0x13C 21. "DSP1N0GPIO117,GPIO117 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x13C 20. "DSP1N0GPIO116,GPIO116 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
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bitfld.long 0x13C 19. "DSP1N0GPIO115,GPIO115 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x13C 18. "DSP1N0GPIO114,GPIO114 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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newline
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bitfld.long 0x13C 17. "DSP1N0GPIO113,GPIO113 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x13C 16. "DSP1N0GPIO112,GPIO112 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
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bitfld.long 0x13C 15. "DSP1N0GPIO111,GPIO111 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x13C 14. "DSP1N0GPIO110,GPIO110 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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newline
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bitfld.long 0x13C 13. "DSP1N0GPIO109,GPIO109 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x13C 12. "DSP1N0GPIO108,GPIO108 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
|
newline
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bitfld.long 0x13C 11. "DSP1N0GPIO107,GPIO107 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x13C 10. "DSP1N0GPIO106,GPIO106 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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newline
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bitfld.long 0x13C 9. "DSP1N0GPIO105,GPIO105 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x13C 8. "DSP1N0GPIO104,GPIO104 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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newline
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bitfld.long 0x13C 7. "DSP1N0GPIO103,GPIO103 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x13C 6. "DSP1N0GPIO102,GPIO102 DSP1 N0-priority interrupt." "0: priority interrupt,?"
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newline
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bitfld.long 0x13C 5. "DSP1N0GPIO101,GPIO101 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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bitfld.long 0x13C 4. "DSP1N0GPIO100,GPIO100 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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newline
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bitfld.long 0x13C 3. "DSP1N0GPIO99,GPIO99 DSP1 N0-priority interrupt." "0: priority interrupt,?"
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bitfld.long 0x13C 2. "DSP1N0GPIO98,GPIO98 DSP1 N0-priority interrupt." "0: priority interrupt,?"
|
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newline
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bitfld.long 0x13C 1. "DSP1N0GPIO97,GPIO97 DSP1 N0-priority interrupt." "0: priority interrupt,?"
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bitfld.long 0x13C 0. "DSP1N0GPIO96,GPIO96 DSP1 N0-priority interrupt." "0: priority interrupt,?"
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line.long 0x140 "DSP1N1INT0EN,Set bits in this register to allow this module to generate the corresponding interrupt."
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bitfld.long 0x140 31. "DSP1N1GPIO31,GPIO31 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0x140 30. "DSP1N1GPIO30,GPIO30 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0x140 29. "DSP1N1GPIO29,GPIO29 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0x140 28. "DSP1N1GPIO28,GPIO28 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0x140 27. "DSP1N1GPIO27,GPIO27 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x140 26. "DSP1N1GPIO26,GPIO26 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0x140 25. "DSP1N1GPIO25,GPIO25 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0x140 24. "DSP1N1GPIO24,GPIO24 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0x140 23. "DSP1N1GPIO23,GPIO23 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x140 22. "DSP1N1GPIO22,GPIO22 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0x140 21. "DSP1N1GPIO21,GPIO21 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0x140 20. "DSP1N1GPIO20,GPIO20 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0x140 19. "DSP1N1GPIO19,GPIO19 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0x140 18. "DSP1N1GPIO18,GPIO18 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0x140 17. "DSP1N1GPIO17,GPIO17 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0x140 16. "DSP1N1GPIO16,GPIO16 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0x140 15. "DSP1N1GPIO15,GPIO15 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0x140 14. "DSP1N1GPIO14,GPIO14 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0x140 13. "DSP1N1GPIO13,GPIO13 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x140 12. "DSP1N1GPIO12,GPIO12 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0x140 11. "DSP1N1GPIO11,GPIO11 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x140 10. "DSP1N1GPIO10,GPIO10 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0x140 9. "DSP1N1GPIO9,GPIO9 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x140 8. "DSP1N1GPIO8,GPIO8 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0x140 7. "DSP1N1GPIO7,GPIO7 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x140 6. "DSP1N1GPIO6,GPIO6 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0x140 5. "DSP1N1GPIO5,GPIO5 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x140 4. "DSP1N1GPIO4,GPIO4 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0x140 3. "DSP1N1GPIO3,GPIO3 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x140 2. "DSP1N1GPIO2,GPIO2 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0x140 1. "DSP1N1GPIO1,GPIO1 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0x140 0. "DSP1N1GPIO0,GPIO0 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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line.long 0x144 "DSP1N1INT0STAT,Read bits from this register to discover the cause of a recent interrupt."
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bitfld.long 0x144 31. "DSP1N1GPIO31,GPIO31 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x144 30. "DSP1N1GPIO30,GPIO30 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0x144 29. "DSP1N1GPIO29,GPIO29 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x144 28. "DSP1N1GPIO28,GPIO28 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0x144 27. "DSP1N1GPIO27,GPIO27 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x144 26. "DSP1N1GPIO26,GPIO26 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0x144 25. "DSP1N1GPIO25,GPIO25 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x144 24. "DSP1N1GPIO24,GPIO24 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0x144 23. "DSP1N1GPIO23,GPIO23 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x144 22. "DSP1N1GPIO22,GPIO22 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0x144 21. "DSP1N1GPIO21,GPIO21 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0x144 20. "DSP1N1GPIO20,GPIO20 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0x144 19. "DSP1N1GPIO19,GPIO19 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0x144 18. "DSP1N1GPIO18,GPIO18 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0x144 17. "DSP1N1GPIO17,GPIO17 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0x144 16. "DSP1N1GPIO16,GPIO16 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0x144 15. "DSP1N1GPIO15,GPIO15 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0x144 14. "DSP1N1GPIO14,GPIO14 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0x144 13. "DSP1N1GPIO13,GPIO13 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0x144 12. "DSP1N1GPIO12,GPIO12 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0x144 11. "DSP1N1GPIO11,GPIO11 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0x144 10. "DSP1N1GPIO10,GPIO10 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0x144 9. "DSP1N1GPIO9,GPIO9 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0x144 8. "DSP1N1GPIO8,GPIO8 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0x144 7. "DSP1N1GPIO7,GPIO7 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x144 6. "DSP1N1GPIO6,GPIO6 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0x144 5. "DSP1N1GPIO5,GPIO5 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0x144 4. "DSP1N1GPIO4,GPIO4 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0x144 3. "DSP1N1GPIO3,GPIO3 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0x144 2. "DSP1N1GPIO2,GPIO2 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0x144 1. "DSP1N1GPIO1,GPIO1 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0x144 0. "DSP1N1GPIO0,GPIO0 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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line.long 0x148 "DSP1N1INT0CLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
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bitfld.long 0x148 31. "DSP1N1GPIO31,GPIO31 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0x148 30. "DSP1N1GPIO30,GPIO30 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0x148 29. "DSP1N1GPIO29,GPIO29 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0x148 28. "DSP1N1GPIO28,GPIO28 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0x148 27. "DSP1N1GPIO27,GPIO27 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x148 26. "DSP1N1GPIO26,GPIO26 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0x148 25. "DSP1N1GPIO25,GPIO25 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x148 24. "DSP1N1GPIO24,GPIO24 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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newline
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bitfld.long 0x148 23. "DSP1N1GPIO23,GPIO23 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x148 22. "DSP1N1GPIO22,GPIO22 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0x148 21. "DSP1N1GPIO21,GPIO21 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x148 20. "DSP1N1GPIO20,GPIO20 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0x148 19. "DSP1N1GPIO19,GPIO19 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x148 18. "DSP1N1GPIO18,GPIO18 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0x148 17. "DSP1N1GPIO17,GPIO17 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x148 16. "DSP1N1GPIO16,GPIO16 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0x148 15. "DSP1N1GPIO15,GPIO15 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x148 14. "DSP1N1GPIO14,GPIO14 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0x148 13. "DSP1N1GPIO13,GPIO13 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x148 12. "DSP1N1GPIO12,GPIO12 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0x148 11. "DSP1N1GPIO11,GPIO11 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x148 10. "DSP1N1GPIO10,GPIO10 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x148 9. "DSP1N1GPIO9,GPIO9 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x148 8. "DSP1N1GPIO8,GPIO8 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x148 7. "DSP1N1GPIO7,GPIO7 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x148 6. "DSP1N1GPIO6,GPIO6 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
|
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bitfld.long 0x148 5. "DSP1N1GPIO5,GPIO5 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x148 4. "DSP1N1GPIO4,GPIO4 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x148 3. "DSP1N1GPIO3,GPIO3 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x148 2. "DSP1N1GPIO2,GPIO2 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
|
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bitfld.long 0x148 1. "DSP1N1GPIO1,GPIO1 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x148 0. "DSP1N1GPIO0,GPIO0 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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line.long 0x14C "DSP1N1INT0SET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
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bitfld.long 0x14C 31. "DSP1N1GPIO31,GPIO31 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x14C 30. "DSP1N1GPIO30,GPIO30 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
|
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bitfld.long 0x14C 29. "DSP1N1GPIO29,GPIO29 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x14C 28. "DSP1N1GPIO28,GPIO28 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
|
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bitfld.long 0x14C 27. "DSP1N1GPIO27,GPIO27 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x14C 26. "DSP1N1GPIO26,GPIO26 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
|
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bitfld.long 0x14C 25. "DSP1N1GPIO25,GPIO25 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x14C 24. "DSP1N1GPIO24,GPIO24 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
|
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bitfld.long 0x14C 23. "DSP1N1GPIO23,GPIO23 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x14C 22. "DSP1N1GPIO22,GPIO22 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
|
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bitfld.long 0x14C 21. "DSP1N1GPIO21,GPIO21 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x14C 20. "DSP1N1GPIO20,GPIO20 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
|
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bitfld.long 0x14C 19. "DSP1N1GPIO19,GPIO19 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x14C 18. "DSP1N1GPIO18,GPIO18 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
|
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bitfld.long 0x14C 17. "DSP1N1GPIO17,GPIO17 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x14C 16. "DSP1N1GPIO16,GPIO16 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
|
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bitfld.long 0x14C 15. "DSP1N1GPIO15,GPIO15 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x14C 14. "DSP1N1GPIO14,GPIO14 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x14C 13. "DSP1N1GPIO13,GPIO13 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x14C 12. "DSP1N1GPIO12,GPIO12 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x14C 11. "DSP1N1GPIO11,GPIO11 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x14C 10. "DSP1N1GPIO10,GPIO10 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x14C 9. "DSP1N1GPIO9,GPIO9 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x14C 8. "DSP1N1GPIO8,GPIO8 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x14C 7. "DSP1N1GPIO7,GPIO7 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x14C 6. "DSP1N1GPIO6,GPIO6 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x14C 5. "DSP1N1GPIO5,GPIO5 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x14C 4. "DSP1N1GPIO4,GPIO4 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x14C 3. "DSP1N1GPIO3,GPIO3 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x14C 2. "DSP1N1GPIO2,GPIO2 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x14C 1. "DSP1N1GPIO1,GPIO1 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x14C 0. "DSP1N1GPIO0,GPIO0 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
line.long 0x150 "DSP1N1INT1EN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x150 31. "DSP1N1GPIO63,GPIO63 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x150 30. "DSP1N1GPIO62,GPIO62 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x150 29. "DSP1N1GPIO61,GPIO61 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x150 28. "DSP1N1GPIO60,GPIO60 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x150 27. "DSP1N1GPIO59,GPIO59 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x150 26. "DSP1N1GPIO58,GPIO58 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x150 25. "DSP1N1GPIO57,GPIO57 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x150 24. "DSP1N1GPIO56,GPIO56 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x150 23. "DSP1N1GPIO55,GPIO55 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x150 22. "DSP1N1GPIO54,GPIO54 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x150 21. "DSP1N1GPIO53,GPIO53 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x150 20. "DSP1N1GPIO52,GPIO52 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x150 19. "DSP1N1GPIO51,GPIO51 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x150 18. "DSP1N1GPIO50,GPIO50 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0x150 17. "DSP1N1GPIO49,GPIO49 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x150 16. "DSP1N1GPIO48,GPIO48 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0x150 15. "DSP1N1GPIO47,GPIO47 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x150 14. "DSP1N1GPIO46,GPIO46 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x150 13. "DSP1N1GPIO45,GPIO45 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x150 12. "DSP1N1GPIO44,GPIO44 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x150 11. "DSP1N1GPIO43,GPIO43 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x150 10. "DSP1N1GPIO42,GPIO42 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x150 9. "DSP1N1GPIO41,GPIO41 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x150 8. "DSP1N1GPIO40,GPIO40 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0x150 7. "DSP1N1GPIO39,GPIO39 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x150 6. "DSP1N1GPIO38,GPIO38 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x150 5. "DSP1N1GPIO37,GPIO37 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x150 4. "DSP1N1GPIO36,GPIO36 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x150 3. "DSP1N1GPIO35,GPIO35 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x150 2. "DSP1N1GPIO34,GPIO34 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x150 1. "DSP1N1GPIO33,GPIO33 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x150 0. "DSP1N1GPIO32,GPIO32 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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line.long 0x154 "DSP1N1INT1STAT,Read bits from this register to discover the cause of a recent interrupt."
|
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bitfld.long 0x154 31. "DSP1N1GPIO63,GPIO63 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x154 30. "DSP1N1GPIO62,GPIO62 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x154 29. "DSP1N1GPIO61,GPIO61 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x154 28. "DSP1N1GPIO60,GPIO60 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x154 27. "DSP1N1GPIO59,GPIO59 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x154 26. "DSP1N1GPIO58,GPIO58 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x154 25. "DSP1N1GPIO57,GPIO57 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x154 24. "DSP1N1GPIO56,GPIO56 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x154 23. "DSP1N1GPIO55,GPIO55 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x154 22. "DSP1N1GPIO54,GPIO54 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x154 21. "DSP1N1GPIO53,GPIO53 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x154 20. "DSP1N1GPIO52,GPIO52 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0x154 19. "DSP1N1GPIO51,GPIO51 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x154 18. "DSP1N1GPIO50,GPIO50 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0x154 17. "DSP1N1GPIO49,GPIO49 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x154 16. "DSP1N1GPIO48,GPIO48 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0x154 15. "DSP1N1GPIO47,GPIO47 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x154 14. "DSP1N1GPIO46,GPIO46 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x154 13. "DSP1N1GPIO45,GPIO45 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x154 12. "DSP1N1GPIO44,GPIO44 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x154 11. "DSP1N1GPIO43,GPIO43 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x154 10. "DSP1N1GPIO42,GPIO42 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x154 9. "DSP1N1GPIO41,GPIO41 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x154 8. "DSP1N1GPIO40,GPIO40 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x154 7. "DSP1N1GPIO39,GPIO39 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x154 6. "DSP1N1GPIO38,GPIO38 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x154 5. "DSP1N1GPIO37,GPIO37 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x154 4. "DSP1N1GPIO36,GPIO36 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0x154 3. "DSP1N1GPIO35,GPIO35 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x154 2. "DSP1N1GPIO34,GPIO34 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0x154 1. "DSP1N1GPIO33,GPIO33 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x154 0. "DSP1N1GPIO32,GPIO32 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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line.long 0x158 "DSP1N1INT1CLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
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bitfld.long 0x158 31. "DSP1N1GPIO63,GPIO63 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x158 30. "DSP1N1GPIO62,GPIO62 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x158 29. "DSP1N1GPIO61,GPIO61 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x158 28. "DSP1N1GPIO60,GPIO60 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x158 27. "DSP1N1GPIO59,GPIO59 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x158 26. "DSP1N1GPIO58,GPIO58 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x158 25. "DSP1N1GPIO57,GPIO57 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x158 24. "DSP1N1GPIO56,GPIO56 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x158 23. "DSP1N1GPIO55,GPIO55 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x158 22. "DSP1N1GPIO54,GPIO54 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x158 21. "DSP1N1GPIO53,GPIO53 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x158 20. "DSP1N1GPIO52,GPIO52 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x158 19. "DSP1N1GPIO51,GPIO51 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x158 18. "DSP1N1GPIO50,GPIO50 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0x158 17. "DSP1N1GPIO49,GPIO49 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x158 16. "DSP1N1GPIO48,GPIO48 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x158 15. "DSP1N1GPIO47,GPIO47 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x158 14. "DSP1N1GPIO46,GPIO46 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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|
newline
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bitfld.long 0x158 13. "DSP1N1GPIO45,GPIO45 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x158 12. "DSP1N1GPIO44,GPIO44 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x158 11. "DSP1N1GPIO43,GPIO43 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x158 10. "DSP1N1GPIO42,GPIO42 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x158 9. "DSP1N1GPIO41,GPIO41 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x158 8. "DSP1N1GPIO40,GPIO40 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x158 7. "DSP1N1GPIO39,GPIO39 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x158 6. "DSP1N1GPIO38,GPIO38 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x158 5. "DSP1N1GPIO37,GPIO37 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x158 4. "DSP1N1GPIO36,GPIO36 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x158 3. "DSP1N1GPIO35,GPIO35 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x158 2. "DSP1N1GPIO34,GPIO34 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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|
newline
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bitfld.long 0x158 1. "DSP1N1GPIO33,GPIO33 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x158 0. "DSP1N1GPIO32,GPIO32 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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line.long 0x15C "DSP1N1INT1SET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
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bitfld.long 0x15C 31. "DSP1N1GPIO63,GPIO63 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x15C 30. "DSP1N1GPIO62,GPIO62 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0x15C 29. "DSP1N1GPIO61,GPIO61 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x15C 28. "DSP1N1GPIO60,GPIO60 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0x15C 27. "DSP1N1GPIO59,GPIO59 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x15C 26. "DSP1N1GPIO58,GPIO58 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x15C 25. "DSP1N1GPIO57,GPIO57 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x15C 24. "DSP1N1GPIO56,GPIO56 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
|
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bitfld.long 0x15C 23. "DSP1N1GPIO55,GPIO55 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x15C 22. "DSP1N1GPIO54,GPIO54 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0x15C 21. "DSP1N1GPIO53,GPIO53 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x15C 20. "DSP1N1GPIO52,GPIO52 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
|
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bitfld.long 0x15C 19. "DSP1N1GPIO51,GPIO51 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x15C 18. "DSP1N1GPIO50,GPIO50 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
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bitfld.long 0x15C 17. "DSP1N1GPIO49,GPIO49 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x15C 16. "DSP1N1GPIO48,GPIO48 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
|
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bitfld.long 0x15C 15. "DSP1N1GPIO47,GPIO47 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x15C 14. "DSP1N1GPIO46,GPIO46 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
|
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bitfld.long 0x15C 13. "DSP1N1GPIO45,GPIO45 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x15C 12. "DSP1N1GPIO44,GPIO44 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x15C 11. "DSP1N1GPIO43,GPIO43 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x15C 10. "DSP1N1GPIO42,GPIO42 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x15C 9. "DSP1N1GPIO41,GPIO41 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x15C 8. "DSP1N1GPIO40,GPIO40 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x15C 7. "DSP1N1GPIO39,GPIO39 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x15C 6. "DSP1N1GPIO38,GPIO38 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x15C 5. "DSP1N1GPIO37,GPIO37 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x15C 4. "DSP1N1GPIO36,GPIO36 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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newline
|
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bitfld.long 0x15C 3. "DSP1N1GPIO35,GPIO35 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x15C 2. "DSP1N1GPIO34,GPIO34 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x15C 1. "DSP1N1GPIO33,GPIO33 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x15C 0. "DSP1N1GPIO32,GPIO32 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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line.long 0x160 "DSP1N1INT2EN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
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bitfld.long 0x160 31. "DSP1N1GPIO95,GPIO95 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x160 30. "DSP1N1GPIO94,GPIO94 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x160 29. "DSP1N1GPIO93,GPIO93 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x160 28. "DSP1N1GPIO92,GPIO92 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x160 27. "DSP1N1GPIO91,GPIO91 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x160 26. "DSP1N1GPIO90,GPIO90 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x160 25. "DSP1N1GPIO89,GPIO89 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x160 24. "DSP1N1GPIO88,GPIO88 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x160 23. "DSP1N1GPIO87,GPIO87 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x160 22. "DSP1N1GPIO86,GPIO86 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x160 21. "DSP1N1GPIO85,GPIO85 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x160 20. "DSP1N1GPIO84,GPIO84 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x160 19. "DSP1N1GPIO83,GPIO83 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x160 18. "DSP1N1GPIO82,GPIO82 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x160 17. "DSP1N1GPIO81,GPIO81 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x160 16. "DSP1N1GPIO80,GPIO80 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x160 15. "DSP1N1GPIO79,GPIO79 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x160 14. "DSP1N1GPIO78,GPIO78 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x160 13. "DSP1N1GPIO77,GPIO77 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x160 12. "DSP1N1GPIO76,GPIO76 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x160 11. "DSP1N1GPIO75,GPIO75 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x160 10. "DSP1N1GPIO74,GPIO74 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x160 9. "DSP1N1GPIO73,GPIO73 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x160 8. "DSP1N1GPIO72,GPIO72 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x160 7. "DSP1N1GPIO71,GPIO71 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x160 6. "DSP1N1GPIO70,GPIO70 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x160 5. "DSP1N1GPIO69,GPIO69 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x160 4. "DSP1N1GPIO68,GPIO68 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x160 3. "DSP1N1GPIO67,GPIO67 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x160 2. "DSP1N1GPIO66,GPIO66 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x160 1. "DSP1N1GPIO65,GPIO65 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x160 0. "DSP1N1GPIO64,GPIO64 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
line.long 0x164 "DSP1N1INT2STAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x164 31. "DSP1N1GPIO95,GPIO95 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x164 30. "DSP1N1GPIO94,GPIO94 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x164 29. "DSP1N1GPIO93,GPIO93 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x164 28. "DSP1N1GPIO92,GPIO92 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x164 27. "DSP1N1GPIO91,GPIO91 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x164 26. "DSP1N1GPIO90,GPIO90 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x164 25. "DSP1N1GPIO89,GPIO89 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x164 24. "DSP1N1GPIO88,GPIO88 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x164 23. "DSP1N1GPIO87,GPIO87 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x164 22. "DSP1N1GPIO86,GPIO86 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x164 21. "DSP1N1GPIO85,GPIO85 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x164 20. "DSP1N1GPIO84,GPIO84 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x164 19. "DSP1N1GPIO83,GPIO83 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x164 18. "DSP1N1GPIO82,GPIO82 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x164 17. "DSP1N1GPIO81,GPIO81 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x164 16. "DSP1N1GPIO80,GPIO80 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x164 15. "DSP1N1GPIO79,GPIO79 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x164 14. "DSP1N1GPIO78,GPIO78 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x164 13. "DSP1N1GPIO77,GPIO77 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x164 12. "DSP1N1GPIO76,GPIO76 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x164 11. "DSP1N1GPIO75,GPIO75 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x164 10. "DSP1N1GPIO74,GPIO74 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x164 9. "DSP1N1GPIO73,GPIO73 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x164 8. "DSP1N1GPIO72,GPIO72 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x164 7. "DSP1N1GPIO71,GPIO71 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x164 6. "DSP1N1GPIO70,GPIO70 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x164 5. "DSP1N1GPIO69,GPIO69 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x164 4. "DSP1N1GPIO68,GPIO68 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x164 3. "DSP1N1GPIO67,GPIO67 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0x164 2. "DSP1N1GPIO66,GPIO66 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x164 1. "DSP1N1GPIO65,GPIO65 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x164 0. "DSP1N1GPIO64,GPIO64 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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line.long 0x168 "DSP1N1INT2CLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
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bitfld.long 0x168 31. "DSP1N1GPIO95,GPIO95 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0x168 30. "DSP1N1GPIO94,GPIO94 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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|
newline
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bitfld.long 0x168 29. "DSP1N1GPIO93,GPIO93 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x168 28. "DSP1N1GPIO92,GPIO92 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x168 27. "DSP1N1GPIO91,GPIO91 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x168 26. "DSP1N1GPIO90,GPIO90 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x168 25. "DSP1N1GPIO89,GPIO89 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x168 24. "DSP1N1GPIO88,GPIO88 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x168 23. "DSP1N1GPIO87,GPIO87 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x168 22. "DSP1N1GPIO86,GPIO86 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x168 21. "DSP1N1GPIO85,GPIO85 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x168 20. "DSP1N1GPIO84,GPIO84 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x168 19. "DSP1N1GPIO83,GPIO83 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x168 18. "DSP1N1GPIO82,GPIO82 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x168 17. "DSP1N1GPIO81,GPIO81 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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bitfld.long 0x168 16. "DSP1N1GPIO80,GPIO80 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x168 15. "DSP1N1GPIO79,GPIO79 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x168 14. "DSP1N1GPIO78,GPIO78 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x168 13. "DSP1N1GPIO77,GPIO77 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x168 12. "DSP1N1GPIO76,GPIO76 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x168 11. "DSP1N1GPIO75,GPIO75 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x168 10. "DSP1N1GPIO74,GPIO74 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x168 9. "DSP1N1GPIO73,GPIO73 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x168 8. "DSP1N1GPIO72,GPIO72 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x168 7. "DSP1N1GPIO71,GPIO71 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x168 6. "DSP1N1GPIO70,GPIO70 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x168 5. "DSP1N1GPIO69,GPIO69 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x168 4. "DSP1N1GPIO68,GPIO68 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x168 3. "DSP1N1GPIO67,GPIO67 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x168 2. "DSP1N1GPIO66,GPIO66 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x168 1. "DSP1N1GPIO65,GPIO65 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x168 0. "DSP1N1GPIO64,GPIO64 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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line.long 0x16C "DSP1N1INT2SET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
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bitfld.long 0x16C 31. "DSP1N1GPIO95,GPIO95 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x16C 30. "DSP1N1GPIO94,GPIO94 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x16C 29. "DSP1N1GPIO93,GPIO93 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x16C 28. "DSP1N1GPIO92,GPIO92 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x16C 27. "DSP1N1GPIO91,GPIO91 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x16C 26. "DSP1N1GPIO90,GPIO90 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x16C 25. "DSP1N1GPIO89,GPIO89 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x16C 24. "DSP1N1GPIO88,GPIO88 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x16C 23. "DSP1N1GPIO87,GPIO87 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x16C 22. "DSP1N1GPIO86,GPIO86 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x16C 21. "DSP1N1GPIO85,GPIO85 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x16C 20. "DSP1N1GPIO84,GPIO84 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x16C 19. "DSP1N1GPIO83,GPIO83 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x16C 18. "DSP1N1GPIO82,GPIO82 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
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bitfld.long 0x16C 17. "DSP1N1GPIO81,GPIO81 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x16C 16. "DSP1N1GPIO80,GPIO80 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x16C 15. "DSP1N1GPIO79,GPIO79 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x16C 14. "DSP1N1GPIO78,GPIO78 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x16C 13. "DSP1N1GPIO77,GPIO77 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x16C 12. "DSP1N1GPIO76,GPIO76 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x16C 11. "DSP1N1GPIO75,GPIO75 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x16C 10. "DSP1N1GPIO74,GPIO74 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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|
newline
|
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bitfld.long 0x16C 9. "DSP1N1GPIO73,GPIO73 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x16C 8. "DSP1N1GPIO72,GPIO72 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x16C 7. "DSP1N1GPIO71,GPIO71 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x16C 6. "DSP1N1GPIO70,GPIO70 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x16C 5. "DSP1N1GPIO69,GPIO69 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x16C 4. "DSP1N1GPIO68,GPIO68 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x16C 3. "DSP1N1GPIO67,GPIO67 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x16C 2. "DSP1N1GPIO66,GPIO66 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x16C 1. "DSP1N1GPIO65,GPIO65 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x16C 0. "DSP1N1GPIO64,GPIO64 DSP1 N1-priority interrupt." "?,1: priority interrupt"
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line.long 0x170 "DSP1N1INT3EN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
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bitfld.long 0x170 31. "DSP1N1GPIO127,GPIO127 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x170 30. "DSP1N1GPIO126,GPIO126 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x170 29. "DSP1N1GPIO125,GPIO125 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
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bitfld.long 0x170 28. "DSP1N1GPIO124,GPIO124 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x170 27. "DSP1N1GPIO123,GPIO123 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x170 26. "DSP1N1GPIO122,GPIO122 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x170 25. "DSP1N1GPIO121,GPIO121 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x170 24. "DSP1N1GPIO120,GPIO120 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x170 23. "DSP1N1GPIO119,GPIO119 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x170 22. "DSP1N1GPIO118,GPIO118 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x170 21. "DSP1N1GPIO117,GPIO117 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x170 20. "DSP1N1GPIO116,GPIO116 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x170 19. "DSP1N1GPIO115,GPIO115 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x170 18. "DSP1N1GPIO114,GPIO114 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x170 17. "DSP1N1GPIO113,GPIO113 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x170 16. "DSP1N1GPIO112,GPIO112 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x170 15. "DSP1N1GPIO111,GPIO111 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x170 14. "DSP1N1GPIO110,GPIO110 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x170 13. "DSP1N1GPIO109,GPIO109 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x170 12. "DSP1N1GPIO108,GPIO108 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x170 11. "DSP1N1GPIO107,GPIO107 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x170 10. "DSP1N1GPIO106,GPIO106 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x170 9. "DSP1N1GPIO105,GPIO105 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x170 8. "DSP1N1GPIO104,GPIO104 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x170 7. "DSP1N1GPIO103,GPIO103 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x170 6. "DSP1N1GPIO102,GPIO102 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x170 5. "DSP1N1GPIO101,GPIO101 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x170 4. "DSP1N1GPIO100,GPIO100 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x170 3. "DSP1N1GPIO99,GPIO99 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x170 2. "DSP1N1GPIO98,GPIO98 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x170 1. "DSP1N1GPIO97,GPIO97 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x170 0. "DSP1N1GPIO96,GPIO96 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
line.long 0x174 "DSP1N1INT3STAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x174 31. "DSP1N1GPIO127,GPIO127 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x174 30. "DSP1N1GPIO126,GPIO126 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x174 29. "DSP1N1GPIO125,GPIO125 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x174 28. "DSP1N1GPIO124,GPIO124 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x174 27. "DSP1N1GPIO123,GPIO123 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x174 26. "DSP1N1GPIO122,GPIO122 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x174 25. "DSP1N1GPIO121,GPIO121 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x174 24. "DSP1N1GPIO120,GPIO120 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x174 23. "DSP1N1GPIO119,GPIO119 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x174 22. "DSP1N1GPIO118,GPIO118 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x174 21. "DSP1N1GPIO117,GPIO117 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x174 20. "DSP1N1GPIO116,GPIO116 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x174 19. "DSP1N1GPIO115,GPIO115 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x174 18. "DSP1N1GPIO114,GPIO114 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x174 17. "DSP1N1GPIO113,GPIO113 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x174 16. "DSP1N1GPIO112,GPIO112 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
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bitfld.long 0x174 15. "DSP1N1GPIO111,GPIO111 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x174 14. "DSP1N1GPIO110,GPIO110 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x174 13. "DSP1N1GPIO109,GPIO109 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x174 12. "DSP1N1GPIO108,GPIO108 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x174 11. "DSP1N1GPIO107,GPIO107 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x174 10. "DSP1N1GPIO106,GPIO106 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x174 9. "DSP1N1GPIO105,GPIO105 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x174 8. "DSP1N1GPIO104,GPIO104 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x174 7. "DSP1N1GPIO103,GPIO103 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x174 6. "DSP1N1GPIO102,GPIO102 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x174 5. "DSP1N1GPIO101,GPIO101 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x174 4. "DSP1N1GPIO100,GPIO100 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x174 3. "DSP1N1GPIO99,GPIO99 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x174 2. "DSP1N1GPIO98,GPIO98 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x174 1. "DSP1N1GPIO97,GPIO97 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x174 0. "DSP1N1GPIO96,GPIO96 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
line.long 0x178 "DSP1N1INT3CLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x178 31. "DSP1N1GPIO127,GPIO127 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x178 30. "DSP1N1GPIO126,GPIO126 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x178 29. "DSP1N1GPIO125,GPIO125 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x178 28. "DSP1N1GPIO124,GPIO124 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x178 27. "DSP1N1GPIO123,GPIO123 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x178 26. "DSP1N1GPIO122,GPIO122 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x178 25. "DSP1N1GPIO121,GPIO121 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x178 24. "DSP1N1GPIO120,GPIO120 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x178 23. "DSP1N1GPIO119,GPIO119 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x178 22. "DSP1N1GPIO118,GPIO118 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x178 21. "DSP1N1GPIO117,GPIO117 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x178 20. "DSP1N1GPIO116,GPIO116 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x178 19. "DSP1N1GPIO115,GPIO115 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x178 18. "DSP1N1GPIO114,GPIO114 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x178 17. "DSP1N1GPIO113,GPIO113 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x178 16. "DSP1N1GPIO112,GPIO112 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x178 15. "DSP1N1GPIO111,GPIO111 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x178 14. "DSP1N1GPIO110,GPIO110 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x178 13. "DSP1N1GPIO109,GPIO109 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x178 12. "DSP1N1GPIO108,GPIO108 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x178 11. "DSP1N1GPIO107,GPIO107 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x178 10. "DSP1N1GPIO106,GPIO106 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x178 9. "DSP1N1GPIO105,GPIO105 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x178 8. "DSP1N1GPIO104,GPIO104 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x178 7. "DSP1N1GPIO103,GPIO103 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x178 6. "DSP1N1GPIO102,GPIO102 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x178 5. "DSP1N1GPIO101,GPIO101 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x178 4. "DSP1N1GPIO100,GPIO100 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x178 3. "DSP1N1GPIO99,GPIO99 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x178 2. "DSP1N1GPIO98,GPIO98 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x178 1. "DSP1N1GPIO97,GPIO97 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x178 0. "DSP1N1GPIO96,GPIO96 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
line.long 0x17C "DSP1N1INT3SET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0x17C 31. "DSP1N1GPIO127,GPIO127 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x17C 30. "DSP1N1GPIO126,GPIO126 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x17C 29. "DSP1N1GPIO125,GPIO125 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x17C 28. "DSP1N1GPIO124,GPIO124 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x17C 27. "DSP1N1GPIO123,GPIO123 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x17C 26. "DSP1N1GPIO122,GPIO122 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x17C 25. "DSP1N1GPIO121,GPIO121 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x17C 24. "DSP1N1GPIO120,GPIO120 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x17C 23. "DSP1N1GPIO119,GPIO119 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x17C 22. "DSP1N1GPIO118,GPIO118 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x17C 21. "DSP1N1GPIO117,GPIO117 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x17C 20. "DSP1N1GPIO116,GPIO116 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x17C 19. "DSP1N1GPIO115,GPIO115 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x17C 18. "DSP1N1GPIO114,GPIO114 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x17C 17. "DSP1N1GPIO113,GPIO113 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x17C 16. "DSP1N1GPIO112,GPIO112 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x17C 15. "DSP1N1GPIO111,GPIO111 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x17C 14. "DSP1N1GPIO110,GPIO110 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x17C 13. "DSP1N1GPIO109,GPIO109 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x17C 12. "DSP1N1GPIO108,GPIO108 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x17C 11. "DSP1N1GPIO107,GPIO107 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x17C 10. "DSP1N1GPIO106,GPIO106 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x17C 9. "DSP1N1GPIO105,GPIO105 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x17C 8. "DSP1N1GPIO104,GPIO104 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x17C 7. "DSP1N1GPIO103,GPIO103 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x17C 6. "DSP1N1GPIO102,GPIO102 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x17C 5. "DSP1N1GPIO101,GPIO101 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x17C 4. "DSP1N1GPIO100,GPIO100 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x17C 3. "DSP1N1GPIO99,GPIO99 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x17C 2. "DSP1N1GPIO98,GPIO98 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
newline
|
|
bitfld.long 0x17C 1. "DSP1N1GPIO97,GPIO97 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
bitfld.long 0x17C 0. "DSP1N1GPIO96,GPIO96 DSP1 N1-priority interrupt." "?,1: priority interrupt"
|
|
tree.end
|
|
tree "GPU (Graphics Processing Unit)"
|
|
base ad:0x40090000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "TEX0BASE,Base address of the drawing surface 0 (must be word aligned)."
|
|
hexmask.long 0x0 0.--31. 1. "Base,Address 0: base address of the drawing surface 0 (must be word aligned)."
|
|
line.long 0x4 "TEX0STRIDE,Image 0 mode and stride."
|
|
hexmask.long.byte 0x4 24.--31. 1. "IMGFMT,Image Format"
|
|
hexmask.long.byte 0x4 16.--23. 1. "IMGMODE,Image Mode"
|
|
hexmask.long.word 0x4 0.--15. 1. "IMGSTRD,image stride (signed) distance in bytes from one scanline to another"
|
|
line.long 0x8 "TEX0RES,Image 0 resolution."
|
|
hexmask.long.word 0x8 16.--31. 1. "RESY,resolution Y size"
|
|
hexmask.long.word 0x8 0.--15. 1. "RESX,resolution X size"
|
|
group.long 0x10++0x1B
|
|
line.long 0x0 "TEX1BASE,Base address of the drawing surface 1 (must be word aligned)."
|
|
hexmask.long 0x0 0.--31. 1. "Base,address 1: base address of the drawing surface 1 (must be word aligned)."
|
|
line.long 0x4 "TEX1STRIDE,Image 1 mode and stride."
|
|
hexmask.long.byte 0x4 24.--31. 1. "IMGFMT,Image Format"
|
|
hexmask.long.byte 0x4 16.--23. 1. "IMGMODE,Image Mode"
|
|
hexmask.long.word 0x4 0.--15. 1. "IMGSTRD,image stride (signed) distance in bytes from one scanline to another"
|
|
line.long 0x8 "TEX1RES,Image 1 resolution."
|
|
hexmask.long.word 0x8 16.--31. 1. "RESY,resolution Y size"
|
|
hexmask.long.word 0x8 0.--15. 1. "RESX,resolution X size"
|
|
line.long 0xC "TEX1COLOR,Texture maps default color.Used with luminance and alpha-only color formats."
|
|
hexmask.long.byte 0xC 24.--31. 1. "ALPHA,alpha value"
|
|
hexmask.long.byte 0xC 16.--23. 1. "BLUE,blue value"
|
|
hexmask.long.byte 0xC 8.--15. 1. "GREEN,green value"
|
|
hexmask.long.byte 0xC 0.--7. 1. "RED,red value"
|
|
line.long 0x10 "TEX2BASE,Base address of the drawing surface 2 (must be word aligned)."
|
|
hexmask.long 0x10 0.--31. 1. "Drawing,surface 2 Base address of the drawing surface 2"
|
|
line.long 0x14 "TEX2STRIDE,Image 2 mode and stride."
|
|
hexmask.long.byte 0x14 24.--31. 1. "IMGFMT,image format"
|
|
hexmask.long.byte 0x14 16.--23. 1. "IMGMODE,image mode"
|
|
hexmask.long.word 0x14 0.--15. 1. "IMGSTRD,image stride (signed) distance in bytes from one scanline to another"
|
|
line.long 0x18 "TEX2RES,Image 2 resolution."
|
|
hexmask.long.word 0x18 16.--31. 1. "RESY,resolution Y size"
|
|
hexmask.long.word 0x18 0.--15. 1. "RESX,resolution X size"
|
|
group.long 0x30++0xB
|
|
line.long 0x0 "TEX3BASE,Base address of the drawing surface 3 (must be word aligned)."
|
|
hexmask.long 0x0 0.--31. 1. "Image,3 Base address of the drawing surface"
|
|
line.long 0x4 "TEX3STRIDE,mode and stride."
|
|
hexmask.long.byte 0x4 24.--31. 1. "IMGFMT,image format"
|
|
hexmask.long.byte 0x4 16.--23. 1. "IMGMODE,image mode"
|
|
hexmask.long.word 0x4 0.--15. 1. "IMGSTRD,image stride (signed) distance in bytes from one scanline to another"
|
|
line.long 0x8 "TEX3RES,Image 3 resolution."
|
|
hexmask.long.word 0x8 16.--31. 1. "RESY,resolution Y size"
|
|
hexmask.long.word 0x8 0.--15. 1. "RESX,resolution X size"
|
|
group.long 0x90++0xF
|
|
line.long 0x0 "CGCMD,Clock gating enable"
|
|
bitfld.long 0x0 1. "START,start clock" "0,1"
|
|
bitfld.long 0x0 0. "STOP,stop clock" "0,1"
|
|
line.long 0x4 "CGCTRL,CGCTRL register description needed here."
|
|
bitfld.long 0x4 30.--31. "DISCLKMOD,disable clock gating for all modules (MISTAKE ?)" "0,1,2,3"
|
|
hexmask.long.byte 0x4 24.--29. 1. "RSVD1,This bitfield is reserved."
|
|
bitfld.long 0x4 23. "DISCLKCORE,disable clock gating for core 0" "0,1"
|
|
hexmask.long.tbyte 0x4 4.--22. 1. "RSVD0,This bitfield is reserved."
|
|
newline
|
|
bitfld.long 0x4 2.--3. "DISCLKFRAME,disable clock gating for framebuffer 0 (MISTAKE ?)" "0,1,2,3"
|
|
bitfld.long 0x4 1. "DISCLKCFG,disable clock gating for configuration file" "0,1"
|
|
bitfld.long 0x4 0. "DISCLKPROC,disable clock gating for command list processor" "0,1"
|
|
line.long 0x8 "DIRTYTRIGMIN,Resets dirty region to resolution size when written."
|
|
hexmask.long 0x8 0.--31. 1. "DRTYREG,Resets dirty region to resolution size when written."
|
|
line.long 0xC "DIRTYTRIGMAX,Resets dirty region to resolution size when written."
|
|
hexmask.long 0xC 0.--31. 1. "DRTYREG,Resets dirty region to resolution size when written."
|
|
group.long 0xB0++0x3
|
|
line.long 0x0 "STATUS,On read. returns GPU status (CHECK address!!)."
|
|
bitfld.long 0x0 31. "SYSBSY,system busy" "0,1"
|
|
bitfld.long 0x0 30. "MEMBSY,memory system busy" "0,1"
|
|
bitfld.long 0x0 29. "CLBSY,command list bus busy" "0,1"
|
|
bitfld.long 0x0 28. "CLPBSY,command list processor busy" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--27. 1. "RASTBSY,rasterizer busy"
|
|
hexmask.long.byte 0x0 16.--19. 1. "DEPTHFIFOBSY,depth buffer busy (Cores 3-0)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "RENDERBSY,render output unit busy (Cores 3-0)"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TEXTMAPBSY,texture map busy (Cores 3-0)"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "PIPEBSY,pipeline busy (Cores 3-0)"
|
|
hexmask.long.byte 0x0 0.--3. 1. "COREBSY,processing core busy (Cores 3-0)"
|
|
group.long 0xC0++0xF
|
|
line.long 0x0 "BUSCTRL,Bus Control"
|
|
hexmask.long 0x0 0.--31. 1. "BUSCTRL,Bus Control"
|
|
line.long 0x4 "IMEMLDIADDR,Load shader instruction memory address."
|
|
hexmask.long 0x4 0.--31. 1. "IMEM,ADDR Load shader. Load shader instruction memory address."
|
|
line.long 0x8 "IMEMLDIDATAHL,Load shader instruction Memory data (31:0)."
|
|
hexmask.long 0x8 0.--31. 1. "IMEM,DATA Load shader. Load shader instruction Memory data (31:0)."
|
|
line.long 0xC "IMEMLDIDATAHH,Load shader instruction Memory data (63:32)."
|
|
hexmask.long 0xC 0.--31. 1. "IMEM,DATA Load shader. Load shader instruction Memory data (63:32)."
|
|
group.long 0xE8++0x23
|
|
line.long 0x0 "CMDLISTSTATUS,On read. returns command list processor status; On write. resets command list processor."
|
|
bitfld.long 0x0 0. "LIST,processor status" "0,1"
|
|
line.long 0x4 "CMDLISTRINGSTOP,Updates GPU command list pointer to stop executing."
|
|
hexmask.long 0x4 0.--31. 1. "UPDATEPRT,Updates GPU command list pointer to stop executing."
|
|
line.long 0x8 "CMDLISTADDR,Command list base pointer."
|
|
hexmask.long 0x8 0.--31. 1. "BASEPTR,Command list base pointer."
|
|
line.long 0xC "CMDLISTSIZE,Command list length in words."
|
|
hexmask.long 0xC 0.--31. 1. "LISTWORDS,Command list length in words."
|
|
line.long 0x10 "INTERRUPTCTRL,On write. clears the IRQ (CHECK address!)."
|
|
bitfld.long 0x10 30.--31. "CHANGEFREQ,change frequency of asynchronous clock" "0,1,2,3"
|
|
hexmask.long 0x10 4.--29. 1. "RSVD,This bitfield is reserved."
|
|
bitfld.long 0x10 3. "AUTOCLR,if set auto clears interrupt" "0,1"
|
|
bitfld.long 0x10 2. "INTDRAWEND,if set signals interrupt at the end of drawing command" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "INTCMDEND,if set signals interrupt at the end of command list" "0,1"
|
|
bitfld.long 0x10 0. "IRQACTIVE,if set to zero IRQ is active high if set to one IRQ is active low" "0,1"
|
|
line.long 0x14 "SYSCLEAR,On write. resets the GPU (CHECK address!)."
|
|
hexmask.long 0x14 0.--31. 1. "RESETGPU,On write resets the GPU (CHECK address!)."
|
|
line.long 0x18 "DRAWCMD,Rasterizer drawing command."
|
|
hexmask.long 0x18 3.--31. 1. "RSVD,This bitfield is reserved."
|
|
bitfld.long 0x18 0.--2. "START,Start the draw command" "0: draw pixel using STARTXY,1: draw line from STARTXY to ENDXY,2: fill rectangle from STARTXY to ENDXY,3: draw triangle (if enabled),4: draw quadrilateral (if enabled),?,?,?"
|
|
line.long 0x1C "DRAWPT0,Stores only integer values. For greater accurancy DRAWPT0X and DRAWPT0Y registers are used which are 16. 16 fixed point."
|
|
hexmask.long.word 0x1C 16.--31. 1. "COORDY,vertex 0 Y coordinate (integer value)"
|
|
hexmask.long.word 0x1C 0.--15. 1. "COORDX,vertex 0 X coordinate (integer value)"
|
|
line.long 0x20 "DRAWPT1,Stores only integer values. Vertex 1 drawing primitive. Stores only integer values. For greater accurancy DRAWPT1X and DRAWPT1Y registers are used which are 16. 16 fixed point."
|
|
hexmask.long.word 0x20 16.--31. 1. "COORDY,vertex 0 Y coordinate (integer value)"
|
|
hexmask.long.word 0x20 0.--15. 1. "COORDX,vertex 0 X coordinate (integer value)"
|
|
group.long 0x110++0x2B
|
|
line.long 0x0 "CLIPMIN,Clipping rectangle upper left vertex."
|
|
hexmask.long.word 0x0 16.--31. 1. "COORDY,upper left Y coordinate"
|
|
hexmask.long.word 0x0 0.--15. 1. "COORDX,upper left X coordinate"
|
|
line.long 0x4 "CLIPMAX,Clipping rectangle bottom right vertex."
|
|
hexmask.long.word 0x4 16.--31. 1. "COORDY,bottom right Y coordinate"
|
|
hexmask.long.word 0x4 0.--15. 1. "COORDX,bottom right X coordinate"
|
|
line.long 0x8 "RASTCTRL,Rasterizer matrix multiplication control"
|
|
bitfld.long 0x8 30.--31. "PERSP,when set to 0 is in perspective mode (MISTAKE IN DOC?)" "0,1,2,3"
|
|
bitfld.long 0x8 29. "ADD,adds 0.5 to X and Y" "0,1"
|
|
bitfld.long 0x8 28. "BYPASS,tells module to bypass calculations" "0,1"
|
|
hexmask.long 0x8 0.--27. 1. "RSVD,This bitfield is reserved."
|
|
line.long 0xC "DRAWCODEPTR,DRAWCODEPTR register description needed here."
|
|
hexmask.long.word 0xC 16.--31. 1. "BKGND,the pointer for the instruction that will be executed for background pixel"
|
|
hexmask.long.word 0xC 0.--15. 1. "FRGND,the pointer for the instruction that will be executed for foreground pixel"
|
|
line.long 0x10 "DRAWPT0X,X coordinate of Vertex 0 drawing primitive 16. 16 fixed point."
|
|
hexmask.long 0x10 0.--31. 1. "DRAW0X,X coordinate"
|
|
line.long 0x14 "DRAWPT0Y,Y coordinate of Vertex 0 drawing primitive 16. 16 fixed point."
|
|
hexmask.long 0x14 0.--31. 1. "DRAW0Y,Y coordinate"
|
|
line.long 0x18 "DRAWPT0Z,DRAWPTOX register description needed here."
|
|
hexmask.long 0x18 0.--31. 1. "DRAW0Z,This bitfield is reserved."
|
|
line.long 0x1C "DRAWCOLOR,DRAWCOLOR register description needed here."
|
|
hexmask.long 0x1C 0.--31. 1. "RASTPRIM,Rasterizer drawing"
|
|
line.long 0x20 "DRAWPT1X,X coordinate of Vertex 1 drawing primitive 16. 16 fixed point."
|
|
hexmask.long 0x20 0.--31. 1. "DRAW1X,X coordinate"
|
|
line.long 0x24 "DRAWPT1Y,Y coordinate of Vertex 1 drawing primitive 16. 16 fixed point."
|
|
hexmask.long 0x24 0.--31. 1. "DRAW1Y,Y coordinate"
|
|
line.long 0x28 "DRAWPT1Z,DRAWPT1Z register description needed here."
|
|
hexmask.long 0x28 0.--31. 1. "DRAW1Z,This bitfield is reserved."
|
|
group.long 0x140++0xB
|
|
line.long 0x0 "DRAWPT2X,X coordinate of Vertex 2 drawing primitive 16. 16 fixed point."
|
|
hexmask.long 0x0 0.--31. 1. "DRAW2X,X coordinate"
|
|
line.long 0x4 "DRAWPT2Y,Y coordinate of Vertex 2 drawing primitive 16. 16 fixed point."
|
|
hexmask.long 0x4 0.--31. 1. "DRAW2Y,Y coordinate"
|
|
line.long 0x8 "DRAWPT2Z,DRAWPT2Z register description needed here."
|
|
hexmask.long 0x8 0.--31. 1. "RSVD,This bitfield is reserved."
|
|
group.long 0x150++0xB
|
|
line.long 0x0 "DRAWPT3X,X coordinate of Vertex 3 drawing primitive 16. 16 fixed point."
|
|
hexmask.long 0x0 0.--31. 1. "DRAW3X,X coordinate"
|
|
line.long 0x4 "DRAWPT3Y,Y coordinate of Vertex 3 drawing primitive 16. 16 fixed point."
|
|
hexmask.long 0x4 0.--31. 1. "DRAW3Y,Y coordinate."
|
|
line.long 0x8 "DRAWPT3Z,Fixed value (not accessible). Registers 0x160-0x180 are the elements of the 3x3 transformation matrix used for homogeneous conversion from screen coordinates to texture coordinates; the elements are floating points"
|
|
hexmask.long 0x8 0.--31. 1. "DRAW3Z,Fixed value (not accessible)"
|
|
group.long 0x160++0x3B
|
|
line.long 0x0 "MM00,matrix floating point element."
|
|
hexmask.long 0x0 0.--31. 1. "MTX,(0 0). matrix floating point element."
|
|
line.long 0x4 "MM01,matrix floating point element."
|
|
hexmask.long 0x4 0.--31. 1. "MTX,(0 1). matrix floating point element."
|
|
line.long 0x8 "MM02,matrix floating point element; sets to unit matrix if previously written element is MM12."
|
|
hexmask.long 0x8 0.--31. 1. "MTX,(0 2). matrix floating point element."
|
|
line.long 0xC "MM10,matrix floating point element."
|
|
hexmask.long 0xC 0.--31. 1. "MTX,(1 0). matrix floating point element."
|
|
line.long 0x10 "MM11,matrix floating point element."
|
|
hexmask.long 0x10 0.--31. 1. "MTX,(1 1). matrix floating point element"
|
|
line.long 0x14 "MM12,matrix floating point element."
|
|
hexmask.long 0x14 0.--31. 1. "MTX,(1 2). matrix floating point element."
|
|
line.long 0x18 "MM20,matrix floating point element."
|
|
hexmask.long 0x18 0.--31. 1. "MTX,(2 0). matrix floating point element."
|
|
line.long 0x1C "MM21,matrix floating point element."
|
|
hexmask.long 0x1C 0.--31. 1. "MTX,(2 1). matrix floating point element."
|
|
line.long 0x20 "MM22,matrix floating point element."
|
|
hexmask.long 0x20 0.--31. 1. "MTX,(2 2). matrix floating point element"
|
|
line.long 0x24 "DEPTHSTARTL,Depth value of START pixel. (32 low bits fractional.)"
|
|
hexmask.long 0x24 0.--31. 1. "DEPTH32LO,Depth value of START pixel"
|
|
line.long 0x28 "DEPTHSTARTH,Depth value of START pixel. (32 high bits integral.)"
|
|
hexmask.long 0x28 0.--31. 1. "DEPTH32HI,Depth value of START pixel"
|
|
line.long 0x2C "DEPTHDXL,Added depth value for each step at x-axis (32 low bits fractional.)"
|
|
hexmask.long 0x2C 0.--31. 1. "XAXISLO,Added depth value for each step at x-axis"
|
|
line.long 0x30 "DEPTHDXH,Added depth value for each step at x-axis (32 high bits integral.)"
|
|
hexmask.long 0x30 0.--31. 1. "XAXISHI,Added depth value for each step at x-axis"
|
|
line.long 0x34 "DEPTHDYL,Added depth value for each step at y-axis (32 low bits fractional.)"
|
|
hexmask.long 0x34 0.--31. 1. "YAXISLO,Added depth value for each step at y-axis"
|
|
line.long 0x38 "DEPTHDYH,Added depth value for each step at y-axis (32 high bits integral.)"
|
|
hexmask.long 0x38 0.--31. 1. "YAXISHI,Added depth value for each step at y-axis"
|
|
group.long 0x1A0++0x2F
|
|
line.long 0x0 "REDX,Added red value for each step at x-axis. (16. 16 fixed point)"
|
|
hexmask.long 0x0 0.--31. 1. "REDX,Added red value for each step at x-axis"
|
|
line.long 0x4 "REDY,Added red value for each step at y-axis. (16. 16 fixed point)"
|
|
hexmask.long 0x4 0.--31. 1. "REDY,red value for each step at y-axis"
|
|
line.long 0x8 "GREENX,Added green value for each step at x-axis. (16. 16 fixed point)"
|
|
hexmask.long 0x8 0.--31. 1. "GREENX,Added green value for each step at x-axis"
|
|
line.long 0xC "GREENY,Added green value for each step at y-axis. (16. 16 fixed point)"
|
|
hexmask.long 0xC 0.--31. 1. "GREENY,Added green value for each step at y-axis"
|
|
line.long 0x10 "BLUEX,Added blue value for each step at x-axis. (16. 16 fixed point)"
|
|
hexmask.long 0x10 0.--31. 1. "BLUEX,Added blue value for each step at x-axis"
|
|
line.long 0x14 "BLUEY,Added blue value for each step at y-axis. (16. 16 fixed point)"
|
|
hexmask.long 0x14 0.--31. 1. "BLUEY,Added blue value for each step at y-axis"
|
|
line.long 0x18 "ALFX,Added alfa value for each step at x-axis. (16. 16 fixed point)"
|
|
hexmask.long 0x18 0.--31. 1. "ALFX,Added alfa value for each step at x-axis"
|
|
line.long 0x1C "ALFY,Added alfa value for each step at y-axis. (16. 16 fixed point)"
|
|
hexmask.long 0x1C 0.--31. 1. "ALFY,Added alfa value for each step at y-axis"
|
|
line.long 0x20 "REDINIT,Red value of STARTXY pixel. (16. 16 fixed point)"
|
|
hexmask.long 0x20 0.--31. 1. "REDXY,Red value of STARTXY pixel"
|
|
line.long 0x24 "GREINIT,Green value of STARTXY pixel. (16. 16 fixed point)"
|
|
hexmask.long 0x24 0.--31. 1. "GREENXY,Green value of STARTXY pixel"
|
|
line.long 0x28 "BLUINIT,Blue value of STARTXY pixel. (16. 16 fixed point)"
|
|
hexmask.long 0x28 0.--31. 1. "BLUEXY,Blue value of STARTXY pixel"
|
|
line.long 0x2C "ALFINIT,Alfa value of STARTXY pixel. (16. 16 fixed point) Shader Registers"
|
|
hexmask.long 0x2C 0.--31. 1. "ALFXY,Alfa value of STARTXY pixel"
|
|
group.long 0x1EC++0x7
|
|
line.long 0x0 "IDREG,Fixed value"
|
|
hexmask.long 0x0 0.--31. 1. "GPUID,Fixed value for GPU ID"
|
|
line.long 0x4 "LOADCTRL,Load Control"
|
|
hexmask.long 0x4 0.--31. 1. "LOADCTRL,Load Control"
|
|
group.long 0x200++0xF
|
|
line.long 0x0 "C0REG,Shader constant register 0."
|
|
hexmask.long 0x0 0.--31. 1. "C0SHADER,Shader constant register 0."
|
|
line.long 0x4 "C1REG,Shader constant register 1."
|
|
hexmask.long 0x4 0.--31. 1. "C1SHADER,Shader constant register 1."
|
|
line.long 0x8 "C2REG,Shader constant register 2."
|
|
hexmask.long 0x8 0.--31. 1. "C2SHADER,Shader constant register 2"
|
|
line.long 0xC "C3REG,Shader constant register 3. the dirty Region Register"
|
|
hexmask.long 0xC 0.--31. 1. "C3SHADER,Shader constant register 3"
|
|
group.long 0xFF0++0x3
|
|
line.long 0x0 "IRQID,Signals interrupt when set (CHECK address!)."
|
|
hexmask.long 0x0 0.--31. 1. "IRQID,Signals interrupt when set (CHECK address!"
|
|
tree.end
|
|
tree "I2S (Inter-IC Sound)"
|
|
base ad:0x0
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMA4B2KP")||cpuis("AMAP42KK")||cpuis("AMAP42KP"))
|
|
tree "I2S0"
|
|
base ad:0x40208000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "RXDATA,Read only access to the i2S receive data"
|
|
hexmask.long 0x0 0.--31. 1. "RXSAMPLE,32b audio sample from the internal receive FIFO. MSB is always in bit 31"
|
|
line.long 0x4 "RXCHANID,Read only received channel identification register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXCHANID,Channel ID value 0-255."
|
|
line.long 0x8 "RXFIFOSTATUS,Holds the number of samples currently in the receive FIFO. and the empty condition flag"
|
|
bitfld.long 0x8 28. "RXEMPTY,Receive FIFO empty bit. a 1 indicates the receive FIFO is empty." "0,1"
|
|
hexmask.long 0x8 0.--27. 1. "RXSAMPLECNT,The count of the number of samples currently in the receive FIFO."
|
|
line.long 0xC "RXFIFOSIZE,Holds the size of the receive FIFO in samples"
|
|
hexmask.long 0xC 0.--31. 1. "SIZE,Size of the receive FIFO in units of i2S samples. Read only value."
|
|
line.long 0x10 "RXUPPERLIMIT,The number of samples required to be in the RX FIFO before asserting the RX_FFi interrupt bit"
|
|
hexmask.long 0x10 0.--31. 1. "SIZE,When the I2S sample count stored within the receive FIFO reaches this value or is larger the interrupt RX_FFi bit is asserted."
|
|
group.long 0x20++0x13
|
|
line.long 0x0 "TXDATA,Write only register to hold the i2S sample to transmit via the write FIFO"
|
|
hexmask.long 0x0 0.--31. 1. "TXSAMPLE,32b I2S sample to send out of the I2S module via the external pins. All sample have the MSB in bit 31 regardless of number of bits per sample and data justification"
|
|
line.long 0x4 "TXCHANID,Channel ID used for the next audio sample to be written to the data transmission register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "TXCHANID,Channel ID value 0-255."
|
|
line.long 0x8 "TXFIFOSTATUS,Holds the number of samples currently in the transmit FIFO. and the full condition flag"
|
|
bitfld.long 0x8 28. "TXFIFOFULL,Transmit FIFO full bit. a 1 indicates the transmit FIFO is full." "0,1"
|
|
hexmask.long 0x8 0.--27. 1. "TXFIFOCNT,The count of the number of samples currently in the transmit FIFO."
|
|
line.long 0xC "TXFIFOSIZE,Holds the size of the transmit FIFO in samples"
|
|
hexmask.long 0xC 0.--31. 1. "SIZE,Size of the transmit FIFO in units of I2S samples. Read only value."
|
|
line.long 0x10 "TXLOWERLIMIT,Minimum number of samples have been reached in the transmit FIFO."
|
|
hexmask.long 0x10 0.--31. 1. "SIZE,When the number of sample in the TX FIFO goes below this value the interrupt TX_FFi bit is asserted."
|
|
group.long 0x40++0x17
|
|
line.long 0x0 "I2SDATACFG,Specifies the data format of I2S sub frames"
|
|
bitfld.long 0x0 31. "PH,Read Phase Bit. 0: Single Phase frame; 1: Dual-Phase frame." "0: Single Phase frame;,1: Dual-Phase frame"
|
|
hexmask.long.byte 0x0 24.--30. 1. "FRLEN2,Number of channels in phase 2; 0: 1 Channel in phase 2 .. 0x7: 8 channels in phase 2"
|
|
newline
|
|
bitfld.long 0x0 21.--23. "WDLEN2,Receive channel length in bits for phase 2. 0: 8b 2: 16b 4: 24b 5: 32b 1 3 6 7: Reserved" "0: Receive channel length is 8 bits for phase 2.,?,2: Receive channel length is 16 bits for phase 2.,?,4: Receive channel length is 24 bits for phase 2.,5: Receive channel length is 32 bits for phase 2.,?,7: Reserved"
|
|
bitfld.long 0x0 19.--20. "DATADLY,Receive data delay bit count. Valid values are 0-2 3 is reserved." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 16.--18. "SSZ2,Receive audio sample length for phase 2. 0: 8b 2: 16b 4: 24b 5: 32b 1 3 6 7: Reserved" "0: Receive audio sample length is 8 bits for phase 2.,?,2: Receive audio sample length is 16 bits for phase..,?,4: Receive audio sample length is 24 bits for phase..,5: Receive audio sample length is 32 bits for phase..,?,7: Reserved"
|
|
hexmask.long.byte 0x0 8.--14. 1. "FRLEN1,Number of channels in phase 1; 0: 1 Channel in phase 2 .. 0x7: 8 channels in phase 1"
|
|
newline
|
|
bitfld.long 0x0 5.--7. "WDLEN1,Receive channel length in bits for phase 1. 0: 8b 2: 16b 4: 24b 5: 32b 1 3 6 7: Reserved" "0: Receive channel length is 8 bits for phase 1.,?,2: Receive channel length is 16 bits for phase 1.,?,4: Receive channel length is 24 bits for phase 1.,5: Receive channel length is 32 bits for phase 1.,?,7: Reserved"
|
|
bitfld.long 0x0 3. "JUST,Audio sample justification. 0: Left-justified 1: Right-justified" "0: Left-justified,1: Right-justified"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "SSZ1,Receive audio sample length for phase 1. 0: 8b 2: 16b 4: 24b 5: 32b 1 3 6 7: Reserved" "0: Receive audio sample length is 8 bits for phase 1.,?,2: Receive audio sample length is 16 bits for phase..,?,4: Receive audio sample length is 24 bits for phase..,5: Receive audio sample length is 32 bits for phase..,?,7: Reserved"
|
|
line.long 0x4 "I2SIOCFG,Specified polarity and clock configuration of the I2S IPB clocks and IO signals"
|
|
hexmask.long.byte 0x4 20.--27. 1. "FWID,period of fsync/lr_clk in units of sclks"
|
|
bitfld.long 0x4 19. "PRx,Receive clock edge polarity bit. 0: sdata is sampled on the rising edge of sclk. 1: sdata is sampled on the falling edge of sclk." "0: sdata is sampled on the rising edge of sclk,1: sdata is sampled on the falling edge of sclk"
|
|
newline
|
|
bitfld.long 0x4 18. "MSL,Master/Slave clock configuration. 0: External clock(sclk and lr_clk provided externally). 1: Internal clock (sclk and lr_clk sourced internally)." "0: External clock,1: Internal clock"
|
|
bitfld.long 0x4 17. "PRTX,Transmit clock edge polarity bit. 0: sdata is transmitted starting from the falling edge of sclk. 1: sdata is transmitted starting from the rising edge of sclk." "0: sdata is transmitted starting from the falling..,1: sdata is transmitted starting from the rising.."
|
|
newline
|
|
bitfld.long 0x4 16. "FSP,Polarity of fsync/lr_clk signal. 0: Active high. 1: Active low" "0: Active high,1: Active low"
|
|
hexmask.long.word 0x4 4.--15. 1. "FPER,Frame period in units of sclk. Period is FPER + 1 sclks in length. 0: 1 sclk 0x3F: 64 sclks"
|
|
newline
|
|
bitfld.long 0x4 0. "OEN,Output enable for SDATA output" "0,1"
|
|
line.long 0x8 "I2SCTL,Specified polarity and clock configuration of the I2S IPB clocks and IO signals"
|
|
bitfld.long 0x8 31. "I2SVAL,I2S validity bit mode. 1: RX data stored only when validity mask condition is asserted. 0: No validity mask conditions checking is done." "0: No validity mask conditions checking is done,1: RX data stored only when validity mask condition.."
|
|
bitfld.long 0x8 5. "RXRST,Active high receiver reset signal. 1: Flush the RX FIFO" "?,1: Flush the RX FIFO"
|
|
newline
|
|
bitfld.long 0x8 4. "RXEN,Receive enable control. 1: Enables capture of serial audio starting with first channel. 0: No receive data captured. For Full duplex operation RXEN and TXEN MUST be set in a single register write access or the Slave FSM may ignore one of the.." "0: No receive data captured,1: Enables capture of serial audio"
|
|
bitfld.long 0x8 1. "TXRST,Transmit reset signal. 1 will reset the TX side registers and flush the TX FIFO." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TXEN,Transmit enable signal. 1 will enable the transmission of serial audio. For Full duplex operation RXEN and TXEN MUST be set in a single register write access or the Slave FSM may ignore one of the bit-field read-modify-write accesses. TXRST and.." "0,1"
|
|
line.long 0xC "IPBIRPT,Additional mask and status registers for the IPB core."
|
|
bitfld.long 0xC 21. "TXDMAI,TX dma interrupt" "0,1"
|
|
bitfld.long 0xC 20. "RXDMAI,RX dma interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "TXEI,TX Empty interrupt. TX unit attempted to read an empty FIFO" "0,1"
|
|
bitfld.long 0xC 18. "RXFI,RX Full interrupt. RX unit attempted to write to a full FIFO" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "TXFFI,Transmit fifo low limit interrupt" "0,1"
|
|
bitfld.long 0xC 16. "RXFFI,Receive fifo high limit interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "TXDMAM,Transmit FIFO interrupt mask. Will assert interrupt when = 1 and cimdmareq_tx is asserted" "0,1"
|
|
bitfld.long 0xC 4. "RXDMAM,Receive FIFO interrupt mask. Will assert interrupt when = 1 and cimdmareq_rx is asserted" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "TXEM,Transmit FIFO interrupt mask. Will assert interrupt when = 1 and TXEI is asserted" "0,1"
|
|
bitfld.long 0xC 2. "RXFM,Receive FIFO interrupt mask. Will assert interrupt when = 1 and RXFI is asserted" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "TXFFM,Transmit FIFO interrupt mask. Will assert interrupt when = 1 and TXFFI is asserted" "0,1"
|
|
bitfld.long 0xC 0. "RXFFM,Receive FIFO interrupt mask. Will assert interrupt when = 1 and RXFFI is asserted" "0,1"
|
|
line.long 0x10 "IPCOREID,Returns the core ID of the IPB core. and used to write the I2S validity mask."
|
|
hexmask.long.byte 0x10 24.--31. 1. "COREFAM,Core Family. Also bit 31 is used to set the I2S validity bit when a write is done."
|
|
hexmask.long.byte 0x10 16.--23. 1. "COREID,Core ID of the IPB core"
|
|
line.long 0x14 "AMQCFG,Control the enablement of the ASRC module and the source of the MCLK used in the IPB core."
|
|
bitfld.long 0x14 1. "ASRCEN,ASRC sub module enable. 0: Enabled. 1: Disabled/Bypassed" "0: Enabled,1: Disabled/Bypassed"
|
|
bitfld.long 0x14 0. "MCLKSRC,MCLK source. 1: Output of nco_clk divider. 0: MCLK from ambiq clock configuration directly" "0: MCLK from ambiq clock configuration directly,1: Output of nco_clk divider"
|
|
group.long 0x60++0x7
|
|
line.long 0x0 "INTDIV,Integer divide value for the nco_clk divider"
|
|
hexmask.long 0x0 0.--31. 1. "INTDIV,Integer divide value for internal clock divider"
|
|
line.long 0x4 "FRACDIV,Fractional divide value for the nco_clk divider"
|
|
hexmask.long 0x4 0.--31. 1. "FRACDIV,Fractional divide value for internal clock divider"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "CLKCFG,Provides clock selection and control for I2S clocks"
|
|
bitfld.long 0x0 20. "DIV3,0: no change to the clock selected by FSEL 1: frequency divide-by-3 of the clock selected by FSEL" "0: no change to the clock selected by FSEL,1: frequency divide-by-3 of the clock selected by.."
|
|
bitfld.long 0x0 16.--17. "REFFSEL,FUTURE USE Select the input clock frequency for the ref_clk. 0: HFRC_48MHz 1: HFRC_48MHz_GATED 2: XT_24MHz 3: HFRC2_48MHz" "0: HFRC_48MHz,1: HFRC_48MHz_GATED,2: XT_24MHz,3: HFRC2_48MHz"
|
|
newline
|
|
bitfld.long 0x0 12. "REFCLKEN,FUTURE USE Enable for the reference clock" "0,1"
|
|
hexmask.long.byte 0x0 4.--8. 1. "FSEL,Select the input clock frequency for the MCLK.Whenever changing the clock source here the MISC_HFRC2FRC bit in the CLKGEN module must first be set. The sequence for changing the clock source regardless of clock selection is to first force HFRC2 on.."
|
|
newline
|
|
bitfld.long 0x0 0. "MCLKEN,Enable for the master audio clock." "0,1"
|
|
group.long 0x200++0x1B
|
|
line.long 0x0 "DMACFG,Configuration control of the DMA process. including the direction of DMA. and enablement of DMA"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RXREQCNT,Number of blocks of samples transferred before asserting the RXREQCNT interrupt signal. A block is 8 samples. The interrupt will assert if enabled and after RXREQCNT blocks of data has been transferred from the I2S into the device. A value of 0.."
|
|
hexmask.long.byte 0x0 8.--15. 1. "TXREQCNT,Number of blocks of samples transferred before asserting the TXREQCNT interrupt signal. A block is 8 samples. The interrupt will assert if enabled and after TXREQCNT blocks of data has been transferred to the I2S module from the device. A value.."
|
|
newline
|
|
bitfld.long 0x0 5. "TXDMAPRI,Sets the Priority of the TXDMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
|
|
bitfld.long 0x0 4. "TXDMAEN,DMA Enable for TX channel. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable TXDMA Function,1: Enable TXDMA Function"
|
|
newline
|
|
bitfld.long 0x0 1. "RXDMAPRI,Sets the Priority of the RXDMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
|
|
bitfld.long 0x0 0. "RXDMAEN,DMA Enable for RX channel. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable RXDMA Function,1: Enable RXDMA Function"
|
|
line.long 0x4 "RXDMATOTCNT,Contains the total count of samples to be stored for the current RX DMA operation. This register is updated as DMA beats complete."
|
|
hexmask.long.word 0x4 0.--11. 1. "RXTOTCNT,Number of 32b audio samples to transfer for RX DMA."
|
|
line.long 0x8 "RXDMAADDR,The address which the DMA operation will store the incoming audio samples. This address is updated as the samples are stored."
|
|
hexmask.long 0x8 0.--31. 1. "RXTARGADDR,Address bits of the target byte address for source of RX write DMA."
|
|
line.long 0xC "RXDMASTAT,Status of the RX DMA operation currently in progress."
|
|
bitfld.long 0xC 2. "RXDMAERR,RX DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set this bit will remain set until cleared by software." "0,1"
|
|
bitfld.long 0xC 1. "RXDMACPL,RX DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0 and will also be cleared when a new DMA is started." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "RXDMATIP,RX DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
|
|
line.long 0x10 "TXDMATOTCNT,Contains the total count of samples to be read and transmitted for the current TX DMA operation. This register is updated as DMA beats complete."
|
|
hexmask.long.word 0x10 0.--11. 1. "TXTOTCNT,Number of 32b audio samples to transmit"
|
|
line.long 0x14 "TXDMAADDR,The address which the DMA operation will fetch the audio samples. This address is updated as the samples are stored."
|
|
hexmask.long 0x14 0.--31. 1. "TXTARGADDR,Address bits of the target byte address for source of TX write DMA."
|
|
line.long 0x18 "TXDMASTAT,Status of the TX DMA operation currently in progress."
|
|
bitfld.long 0x18 2. "TXDMAERR,TX DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set this bit will remain set until cleared by software." "0,1"
|
|
bitfld.long 0x18 1. "TXDMACPL,TX DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0 and will also be cleared when a new DMA is started." "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXDMATIP,TX DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
|
|
group.long 0x230++0x3
|
|
line.long 0x0 "STATUS,I2S Module Status"
|
|
bitfld.long 0x0 0. "TBD,To Be determined." "0,1"
|
|
group.long 0x300++0xF
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 4. "RXDMACPL,A RX dma operation has completed" "0,1"
|
|
bitfld.long 0x0 3. "TXDMACPL,A TX dma operation has completed" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXREQCNT,The I2S module has asserted the dma read request based on TX fifo level." "0,1"
|
|
bitfld.long 0x0 1. "RXREQCNT,The I2S module has completed RXREQCNT number of DMA transfers of size 8 samples. This interrupt allows servicing of buffers at a programmable location within the overall DMA transfer." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IPB,Interrupt from I2S module" "0,1"
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 4. "RXDMACPL,A RX dma operation has completed" "0,1"
|
|
bitfld.long 0x4 3. "TXDMACPL,A TX dma operation has completed" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXREQCNT,The I2S module has asserted the dma read request based on TX fifo level." "0,1"
|
|
bitfld.long 0x4 1. "RXREQCNT,The I2S module has completed RXREQCNT number of DMA transfers of size 8 samples. This interrupt allows servicing of buffers at a programmable location within the overall DMA transfer." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IPB,Interrupt from I2S module" "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 4. "RXDMACPL,A RX dma operation has completed" "0,1"
|
|
bitfld.long 0x8 3. "TXDMACPL,A TX dma operation has completed" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "TXREQCNT,The I2S module has asserted the dma read request based on TX fifo level." "0,1"
|
|
bitfld.long 0x8 1. "RXREQCNT,The I2S module has completed RXREQCNT number of DMA transfers of size 8 samples. This interrupt allows servicing of buffers at a programmable location within the overall DMA transfer." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "IPB,Interrupt from I2S module" "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 4. "RXDMACPL,A RX dma operation has completed" "0,1"
|
|
bitfld.long 0xC 3. "TXDMACPL,A TX dma operation has completed" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "TXREQCNT,The I2S module has asserted the dma read request based on TX fifo level." "0,1"
|
|
bitfld.long 0xC 1. "RXREQCNT,The I2S module has completed RXREQCNT number of DMA transfers of size 8 samples. This interrupt allows servicing of buffers at a programmable location within the overall DMA transfer." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "IPB,Interrupt from I2S module" "0,1"
|
|
group.long 0x400++0x3
|
|
line.long 0x0 "I2SDBG,Debug control"
|
|
hexmask.long 0x0 3.--31. 1. "DBGDATA,Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers."
|
|
bitfld.long 0x0 2. "APBCLKON,APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MCLKON,MCLK debug clock control. Enable MCLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
|
|
bitfld.long 0x0 0. "DBGEN,Debug Enable. Setting bit will enable the update of data within this register otherwise it is clock gated for power savings" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMA4B2KP")||cpuis("AMAP42KK")||cpuis("AMAP42KP"))
|
|
tree "I2S1"
|
|
base ad:0x40209000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "RXDATA,Read only access to the i2S receive data"
|
|
hexmask.long 0x0 0.--31. 1. "RXSAMPLE,32b audio sample from the internal receive FIFO. MSB is always in bit 31"
|
|
line.long 0x4 "RXCHANID,Read only received channel identification register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXCHANID,Channel ID value 0-255."
|
|
line.long 0x8 "RXFIFOSTATUS,Holds the number of samples currently in the receive FIFO. and the empty condition flag"
|
|
bitfld.long 0x8 28. "RXEMPTY,Receive FIFO empty bit. a 1 indicates the receive FIFO is empty." "0,1"
|
|
hexmask.long 0x8 0.--27. 1. "RXSAMPLECNT,The count of the number of samples currently in the receive FIFO."
|
|
line.long 0xC "RXFIFOSIZE,Holds the size of the receive FIFO in samples"
|
|
hexmask.long 0xC 0.--31. 1. "SIZE,Size of the receive FIFO in units of i2S samples. Read only value."
|
|
line.long 0x10 "RXUPPERLIMIT,The number of samples required to be in the RX FIFO before asserting the RX_FFi interrupt bit"
|
|
hexmask.long 0x10 0.--31. 1. "SIZE,When the I2S sample count stored within the receive FIFO reaches this value or is larger the interrupt RX_FFi bit is asserted."
|
|
group.long 0x20++0x13
|
|
line.long 0x0 "TXDATA,Write only register to hold the i2S sample to transmit via the write FIFO"
|
|
hexmask.long 0x0 0.--31. 1. "TXSAMPLE,32b I2S sample to send out of the I2S module via the external pins. All sample have the MSB in bit 31 regardless of number of bits per sample and data justification"
|
|
line.long 0x4 "TXCHANID,Channel ID used for the next audio sample to be written to the data transmission register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "TXCHANID,Channel ID value 0-255."
|
|
line.long 0x8 "TXFIFOSTATUS,Holds the number of samples currently in the transmit FIFO. and the full condition flag"
|
|
bitfld.long 0x8 28. "TXFIFOFULL,Transmit FIFO full bit. a 1 indicates the transmit FIFO is full." "0,1"
|
|
hexmask.long 0x8 0.--27. 1. "TXFIFOCNT,The count of the number of samples currently in the transmit FIFO."
|
|
line.long 0xC "TXFIFOSIZE,Holds the size of the transmit FIFO in samples"
|
|
hexmask.long 0xC 0.--31. 1. "SIZE,Size of the transmit FIFO in units of I2S samples. Read only value."
|
|
line.long 0x10 "TXLOWERLIMIT,Minimum number of samples have been reached in the transmit FIFO."
|
|
hexmask.long 0x10 0.--31. 1. "SIZE,When the number of sample in the TX FIFO goes below this value the interrupt TX_FFi bit is asserted."
|
|
group.long 0x40++0x17
|
|
line.long 0x0 "I2SDATACFG,Specifies the data format of I2S sub frames"
|
|
bitfld.long 0x0 31. "PH,Read Phase Bit. 0: Single Phase frame; 1: Dual-Phase frame." "0: Single Phase frame;,1: Dual-Phase frame"
|
|
hexmask.long.byte 0x0 24.--30. 1. "FRLEN2,Number of channels in phase 2; 0: 1 Channel in phase 2 .. 0x7: 8 channels in phase 2"
|
|
newline
|
|
bitfld.long 0x0 21.--23. "WDLEN2,Receive channel length in bits for phase 2. 0: 8b 2: 16b 4: 24b 5: 32b 1 3 6 7: Reserved" "0: Receive channel length is 8 bits for phase 2.,?,2: Receive channel length is 16 bits for phase 2.,?,4: Receive channel length is 24 bits for phase 2.,5: Receive channel length is 32 bits for phase 2.,?,7: Reserved"
|
|
bitfld.long 0x0 19.--20. "DATADLY,Receive data delay bit count. Valid values are 0-2 3 is reserved." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 16.--18. "SSZ2,Receive audio sample length for phase 2. 0: 8b 2: 16b 4: 24b 5: 32b 1 3 6 7: Reserved" "0: Receive audio sample length is 8 bits for phase 2.,?,2: Receive audio sample length is 16 bits for phase..,?,4: Receive audio sample length is 24 bits for phase..,5: Receive audio sample length is 32 bits for phase..,?,7: Reserved"
|
|
hexmask.long.byte 0x0 8.--14. 1. "FRLEN1,Number of channels in phase 1; 0: 1 Channel in phase 2 .. 0x7: 8 channels in phase 1"
|
|
newline
|
|
bitfld.long 0x0 5.--7. "WDLEN1,Receive channel length in bits for phase 1. 0: 8b 2: 16b 4: 24b 5: 32b 1 3 6 7: Reserved" "0: Receive channel length is 8 bits for phase 1.,?,2: Receive channel length is 16 bits for phase 1.,?,4: Receive channel length is 24 bits for phase 1.,5: Receive channel length is 32 bits for phase 1.,?,7: Reserved"
|
|
bitfld.long 0x0 3. "JUST,Audio sample justification. 0: Left-justified 1: Right-justified" "0: Left-justified,1: Right-justified"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "SSZ1,Receive audio sample length for phase 1. 0: 8b 2: 16b 4: 24b 5: 32b 1 3 6 7: Reserved" "0: Receive audio sample length is 8 bits for phase 1.,?,2: Receive audio sample length is 16 bits for phase..,?,4: Receive audio sample length is 24 bits for phase..,5: Receive audio sample length is 32 bits for phase..,?,7: Reserved"
|
|
line.long 0x4 "I2SIOCFG,Specified polarity and clock configuration of the I2S IPB clocks and IO signals"
|
|
hexmask.long.byte 0x4 20.--27. 1. "FWID,period of fsync/lr_clk in units of sclks"
|
|
bitfld.long 0x4 19. "PRx,Receive clock edge polarity bit. 0: sdata is sampled on the rising edge of sclk. 1: sdata is sampled on the falling edge of sclk." "0: sdata is sampled on the rising edge of sclk,1: sdata is sampled on the falling edge of sclk"
|
|
newline
|
|
bitfld.long 0x4 18. "MSL,Master/Slave clock configuration. 0: External clock(sclk and lr_clk provided externally). 1: Internal clock (sclk and lr_clk sourced internally)." "0: External clock,1: Internal clock"
|
|
bitfld.long 0x4 17. "PRTX,Transmit clock edge polarity bit. 0: sdata is transmitted starting from the falling edge of sclk. 1: sdata is transmitted starting from the rising edge of sclk." "0: sdata is transmitted starting from the falling..,1: sdata is transmitted starting from the rising.."
|
|
newline
|
|
bitfld.long 0x4 16. "FSP,Polarity of fsync/lr_clk signal. 0: Active high. 1: Active low" "0: Active high,1: Active low"
|
|
hexmask.long.word 0x4 4.--15. 1. "FPER,Frame period in units of sclk. Period is FPER + 1 sclks in length. 0: 1 sclk 0x3F: 64 sclks"
|
|
newline
|
|
bitfld.long 0x4 0. "OEN,Output enable for SDATA output" "0,1"
|
|
line.long 0x8 "I2SCTL,Specified polarity and clock configuration of the I2S IPB clocks and IO signals"
|
|
bitfld.long 0x8 31. "I2SVAL,I2S validity bit mode. 1: RX data stored only when validity mask condition is asserted. 0: No validity mask conditions checking is done." "0: No validity mask conditions checking is done,1: RX data stored only when validity mask condition.."
|
|
bitfld.long 0x8 5. "RXRST,Active high receiver reset signal. 1: Flush the RX FIFO" "?,1: Flush the RX FIFO"
|
|
newline
|
|
bitfld.long 0x8 4. "RXEN,Receive enable control. 1: Enables capture of serial audio starting with first channel. 0: No receive data captured. For Full duplex operation RXEN and TXEN MUST be set in a single register write access or the Slave FSM may ignore one of the.." "0: No receive data captured,1: Enables capture of serial audio"
|
|
bitfld.long 0x8 1. "TXRST,Transmit reset signal. 1 will reset the TX side registers and flush the TX FIFO." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TXEN,Transmit enable signal. 1 will enable the transmission of serial audio. For Full duplex operation RXEN and TXEN MUST be set in a single register write access or the Slave FSM may ignore one of the bit-field read-modify-write accesses. TXRST and.." "0,1"
|
|
line.long 0xC "IPBIRPT,Additional mask and status registers for the IPB core."
|
|
bitfld.long 0xC 21. "TXDMAI,TX dma interrupt" "0,1"
|
|
bitfld.long 0xC 20. "RXDMAI,RX dma interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "TXEI,TX Empty interrupt. TX unit attempted to read an empty FIFO" "0,1"
|
|
bitfld.long 0xC 18. "RXFI,RX Full interrupt. RX unit attempted to write to a full FIFO" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "TXFFI,Transmit fifo low limit interrupt" "0,1"
|
|
bitfld.long 0xC 16. "RXFFI,Receive fifo high limit interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "TXDMAM,Transmit FIFO interrupt mask. Will assert interrupt when = 1 and cimdmareq_tx is asserted" "0,1"
|
|
bitfld.long 0xC 4. "RXDMAM,Receive FIFO interrupt mask. Will assert interrupt when = 1 and cimdmareq_rx is asserted" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "TXEM,Transmit FIFO interrupt mask. Will assert interrupt when = 1 and TXEI is asserted" "0,1"
|
|
bitfld.long 0xC 2. "RXFM,Receive FIFO interrupt mask. Will assert interrupt when = 1 and RXFI is asserted" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "TXFFM,Transmit FIFO interrupt mask. Will assert interrupt when = 1 and TXFFI is asserted" "0,1"
|
|
bitfld.long 0xC 0. "RXFFM,Receive FIFO interrupt mask. Will assert interrupt when = 1 and RXFFI is asserted" "0,1"
|
|
line.long 0x10 "IPCOREID,Returns the core ID of the IPB core. and used to write the I2S validity mask."
|
|
hexmask.long.byte 0x10 24.--31. 1. "COREFAM,Core Family. Also bit 31 is used to set the I2S validity bit when a write is done."
|
|
hexmask.long.byte 0x10 16.--23. 1. "COREID,Core ID of the IPB core"
|
|
line.long 0x14 "AMQCFG,Control the enablement of the ASRC module and the source of the MCLK used in the IPB core."
|
|
bitfld.long 0x14 1. "ASRCEN,ASRC sub module enable. 0: Enabled. 1: Disabled/Bypassed" "0: Enabled,1: Disabled/Bypassed"
|
|
bitfld.long 0x14 0. "MCLKSRC,MCLK source. 1: Output of nco_clk divider. 0: MCLK from ambiq clock configuration directly" "0: MCLK from ambiq clock configuration directly,1: Output of nco_clk divider"
|
|
group.long 0x60++0x7
|
|
line.long 0x0 "INTDIV,Integer divide value for the nco_clk divider"
|
|
hexmask.long 0x0 0.--31. 1. "INTDIV,Integer divide value for internal clock divider"
|
|
line.long 0x4 "FRACDIV,Fractional divide value for the nco_clk divider"
|
|
hexmask.long 0x4 0.--31. 1. "FRACDIV,Fractional divide value for internal clock divider"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "CLKCFG,Provides clock selection and control for I2S clocks"
|
|
bitfld.long 0x0 20. "DIV3,0: no change to the clock selected by FSEL 1: frequency divide-by-3 of the clock selected by FSEL" "0: no change to the clock selected by FSEL,1: frequency divide-by-3 of the clock selected by.."
|
|
bitfld.long 0x0 16.--17. "REFFSEL,FUTURE USE Select the input clock frequency for the ref_clk. 0: HFRC_48MHz 1: HFRC_48MHz_GATED 2: XT_24MHz 3: HFRC2_48MHz" "0: HFRC_48MHz,1: HFRC_48MHz_GATED,2: XT_24MHz,3: HFRC2_48MHz"
|
|
newline
|
|
bitfld.long 0x0 12. "REFCLKEN,FUTURE USE Enable for the reference clock" "0,1"
|
|
hexmask.long.byte 0x0 4.--8. 1. "FSEL,Select the input clock frequency for the MCLK.Whenever changing the clock source here the MISC_HFRC2FRC bit in the CLKGEN module must first be set. The sequence for changing the clock source regardless of clock selection is to first force HFRC2 on.."
|
|
newline
|
|
bitfld.long 0x0 0. "MCLKEN,Enable for the master audio clock." "0,1"
|
|
group.long 0x200++0x1B
|
|
line.long 0x0 "DMACFG,Configuration control of the DMA process. including the direction of DMA. and enablement of DMA"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RXREQCNT,Number of blocks of samples transferred before asserting the RXREQCNT interrupt signal. A block is 8 samples. The interrupt will assert if enabled and after RXREQCNT blocks of data has been transferred from the I2S into the device. A value of 0.."
|
|
hexmask.long.byte 0x0 8.--15. 1. "TXREQCNT,Number of blocks of samples transferred before asserting the TXREQCNT interrupt signal. A block is 8 samples. The interrupt will assert if enabled and after TXREQCNT blocks of data has been transferred to the I2S module from the device. A value.."
|
|
newline
|
|
bitfld.long 0x0 5. "TXDMAPRI,Sets the Priority of the TXDMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
|
|
bitfld.long 0x0 4. "TXDMAEN,DMA Enable for TX channel. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable TXDMA Function,1: Enable TXDMA Function"
|
|
newline
|
|
bitfld.long 0x0 1. "RXDMAPRI,Sets the Priority of the RXDMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
|
|
bitfld.long 0x0 0. "RXDMAEN,DMA Enable for RX channel. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable RXDMA Function,1: Enable RXDMA Function"
|
|
line.long 0x4 "RXDMATOTCNT,Contains the total count of samples to be stored for the current RX DMA operation. This register is updated as DMA beats complete."
|
|
hexmask.long.word 0x4 0.--11. 1. "RXTOTCNT,Number of 32b audio samples to transfer for RX DMA."
|
|
line.long 0x8 "RXDMAADDR,The address which the DMA operation will store the incoming audio samples. This address is updated as the samples are stored."
|
|
hexmask.long 0x8 0.--31. 1. "RXTARGADDR,Address bits of the target byte address for source of RX write DMA."
|
|
line.long 0xC "RXDMASTAT,Status of the RX DMA operation currently in progress."
|
|
bitfld.long 0xC 2. "RXDMAERR,RX DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set this bit will remain set until cleared by software." "0,1"
|
|
bitfld.long 0xC 1. "RXDMACPL,RX DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0 and will also be cleared when a new DMA is started." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "RXDMATIP,RX DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
|
|
line.long 0x10 "TXDMATOTCNT,Contains the total count of samples to be read and transmitted for the current TX DMA operation. This register is updated as DMA beats complete."
|
|
hexmask.long.word 0x10 0.--11. 1. "TXTOTCNT,Number of 32b audio samples to transmit"
|
|
line.long 0x14 "TXDMAADDR,The address which the DMA operation will fetch the audio samples. This address is updated as the samples are stored."
|
|
hexmask.long 0x14 0.--31. 1. "TXTARGADDR,Address bits of the target byte address for source of TX write DMA."
|
|
line.long 0x18 "TXDMASTAT,Status of the TX DMA operation currently in progress."
|
|
bitfld.long 0x18 2. "TXDMAERR,TX DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set this bit will remain set until cleared by software." "0,1"
|
|
bitfld.long 0x18 1. "TXDMACPL,TX DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0 and will also be cleared when a new DMA is started." "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXDMATIP,TX DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
|
|
group.long 0x230++0x3
|
|
line.long 0x0 "STATUS,I2S Module Status"
|
|
bitfld.long 0x0 0. "TBD,To Be determined." "0,1"
|
|
group.long 0x300++0xF
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 4. "RXDMACPL,A RX dma operation has completed" "0,1"
|
|
bitfld.long 0x0 3. "TXDMACPL,A TX dma operation has completed" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXREQCNT,The I2S module has asserted the dma read request based on TX fifo level." "0,1"
|
|
bitfld.long 0x0 1. "RXREQCNT,The I2S module has completed RXREQCNT number of DMA transfers of size 8 samples. This interrupt allows servicing of buffers at a programmable location within the overall DMA transfer." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IPB,Interrupt from I2S module" "0,1"
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 4. "RXDMACPL,A RX dma operation has completed" "0,1"
|
|
bitfld.long 0x4 3. "TXDMACPL,A TX dma operation has completed" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXREQCNT,The I2S module has asserted the dma read request based on TX fifo level." "0,1"
|
|
bitfld.long 0x4 1. "RXREQCNT,The I2S module has completed RXREQCNT number of DMA transfers of size 8 samples. This interrupt allows servicing of buffers at a programmable location within the overall DMA transfer." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IPB,Interrupt from I2S module" "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 4. "RXDMACPL,A RX dma operation has completed" "0,1"
|
|
bitfld.long 0x8 3. "TXDMACPL,A TX dma operation has completed" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "TXREQCNT,The I2S module has asserted the dma read request based on TX fifo level." "0,1"
|
|
bitfld.long 0x8 1. "RXREQCNT,The I2S module has completed RXREQCNT number of DMA transfers of size 8 samples. This interrupt allows servicing of buffers at a programmable location within the overall DMA transfer." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "IPB,Interrupt from I2S module" "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 4. "RXDMACPL,A RX dma operation has completed" "0,1"
|
|
bitfld.long 0xC 3. "TXDMACPL,A TX dma operation has completed" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "TXREQCNT,The I2S module has asserted the dma read request based on TX fifo level." "0,1"
|
|
bitfld.long 0xC 1. "RXREQCNT,The I2S module has completed RXREQCNT number of DMA transfers of size 8 samples. This interrupt allows servicing of buffers at a programmable location within the overall DMA transfer." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "IPB,Interrupt from I2S module" "0,1"
|
|
group.long 0x400++0x3
|
|
line.long 0x0 "I2SDBG,Debug control"
|
|
hexmask.long 0x0 3.--31. 1. "DBGDATA,Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers."
|
|
bitfld.long 0x0 2. "APBCLKON,APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MCLKON,MCLK debug clock control. Enable MCLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
|
|
bitfld.long 0x0 0. "DBGEN,Debug Enable. Setting bit will enable the update of data within this register otherwise it is clock gated for power savings" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("AMAP42KL")||cpuis("AMA4B2KL"))
|
|
tree "I2S0"
|
|
base ad:0x40208000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "RXDATA,Read only access to the i2S receive data"
|
|
hexmask.long 0x0 0.--31. 1. "RXSAMPLE,32b audio sample from the internal receive FIFO. MSB is always in bit 31"
|
|
line.long 0x4 "RXCHANID,Read only received channel identification register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXCHANID,Channel ID value 0-255."
|
|
line.long 0x8 "RXFIFOSTATUS,Holds the number of samples currently in the receive FIFO. and the empty condition flag"
|
|
bitfld.long 0x8 28. "RXEMPTY,Receive FIFO empty bit. a 1 indicates the receive FIFO is empty." "0,1"
|
|
hexmask.long 0x8 0.--27. 1. "RXSAMPLECNT,The count of the number of samples currently in the receive FIFO."
|
|
line.long 0xC "RXFIFOSIZE,Holds the size of the receive FIFO in samples"
|
|
hexmask.long 0xC 0.--31. 1. "SIZE,Size of the receive FIFO in units of i2S samples. Read only value."
|
|
line.long 0x10 "RXUPPERLIMIT,The number of samples required to be in the RX FIFO before asserting the RX_FFi interrupt bit"
|
|
hexmask.long 0x10 0.--31. 1. "SIZE,When the I2S sample count stored within the receive FIFO reaches this value or is larger the interrupt RX_FFi bit is asserted."
|
|
group.long 0x20++0x13
|
|
line.long 0x0 "TXDATA,Write only register to hold the i2S sample to transmit via the write FIFO"
|
|
hexmask.long 0x0 0.--31. 1. "TXSAMPLE,32b I2S sample to send out of the I2S module via the external pins. All sample have the MSB in bit 31 regardless of number of bits per sample and data justification"
|
|
line.long 0x4 "TXCHANID,Channel ID used for the next audio sample to be written to the data transmission register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "TXCHANID,Channel ID value 0-255."
|
|
line.long 0x8 "TXFIFOSTATUS,Holds the number of samples currently in the transmit FIFO. and the full condition flag"
|
|
bitfld.long 0x8 29. "TXFIFOFULL,Transmit FIFO full bit. a 1 indicates the transmit FIFO is full." "0,1"
|
|
hexmask.long 0x8 0.--27. 1. "TXFIFOCNT,The count of the number of samples currently in the transmit FIFO."
|
|
line.long 0xC "TXFIFOSIZE,Holds the size of the transmit FIFO in samples"
|
|
hexmask.long 0xC 0.--31. 1. "SIZE,Size of the transmit FIFO in units of I2S samples. Read only value."
|
|
line.long 0x10 "TXLOWERLIMIT,Minimum number of samples have been reached in the transmit FIFO."
|
|
hexmask.long 0x10 0.--31. 1. "SIZE,When the number of sample in the TX FIFO goes below this value the interrupt TX_FFi bit is asserted."
|
|
group.long 0x40++0x17
|
|
line.long 0x0 "I2SDATACFG,Specifies the data format of I2S sub frames"
|
|
bitfld.long 0x0 31. "PH,Read Phase Bit. 0: Single Phase frame; 1: Dual-Phase frame." "0: Single Phase frame;,1: Dual-Phase frame"
|
|
hexmask.long.byte 0x0 24.--30. 1. "FRLEN2,Number of channels in phase 2; 0: 1 Channel in phase 2 .. 0x7: 8 channels in phase 2"
|
|
newline
|
|
bitfld.long 0x0 21.--23. "WDLEN2,Receive channel length in bits for phase 2. 0: 8b 2: 16b 4: 24b 5: 32b 1 3 6 7: Reserved" "0: Receive channel length is 8 bits for phase 2.,?,2: Receive channel length is 16 bits for phase 2.,?,4: Receive channel length is 24 bits for phase 2.,5: Receive channel length is 32 bits for phase 2.,?,7: Reserved"
|
|
bitfld.long 0x0 19.--20. "DATADLY,Receive data delay bit count. Valid values are 0-2 3 is reserved." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 16.--18. "SSZ2,Receive audio sample length for phase 2. 0: 8b 2: 16b 4: 24b 5: 32b 1 3 6 7: Reserved" "0: Receive audio sample length is 8 bits for phase 2.,?,2: Receive audio sample length is 16 bits for phase..,?,4: Receive audio sample length is 24 bits for phase..,5: Receive audio sample length is 32 bits for phase..,?,7: Reserved"
|
|
hexmask.long.byte 0x0 8.--14. 1. "FRLEN1,Number of channels in phase 1; 0: 1 Channel in phase 2 .. 0x7: 8 channels in phase 1"
|
|
newline
|
|
bitfld.long 0x0 5.--7. "WDLEN1,Receive channel length in bits for phase 1. 0: 8b 2: 16b 4: 24b 5: 32b 1 3 6 7: Reserved" "0: Receive channel length is 8 bits for phase 1.,?,2: Receive channel length is 16 bits for phase 1.,?,4: Receive channel length is 24 bits for phase 1.,5: Receive channel length is 32 bits for phase 1.,?,7: Reserved"
|
|
bitfld.long 0x0 3. "JUST,Audio sample justification. 0: Left-justified 1: Right-justified" "0: Left-justified,1: Right-justified"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "SSZ1,Receive audio sample length for phase 1. 0: 8b 2: 16b 4: 24b 5: 32b 1 3 6 7: Reserved" "0: Receive audio sample length is 8 bits for phase 1.,?,2: Receive audio sample length is 16 bits for phase..,?,4: Receive audio sample length is 24 bits for phase..,5: Receive audio sample length is 32 bits for phase..,?,7: Reserved"
|
|
line.long 0x4 "I2SIOCFG,Specified polarity and clock configuration of the I2S IPB clocks and IO signals"
|
|
hexmask.long.byte 0x4 20.--27. 1. "FWID,period of fsync/lr_clk in units of sclks"
|
|
bitfld.long 0x4 19. "PRx,Receive clock edge polarity bit. 0: sdata is sampled on the rising edge of sclk. 1: sdata is sampled on the falling edge of sclk." "0: sdata is sampled on the rising edge of sclk,1: sdata is sampled on the falling edge of sclk"
|
|
newline
|
|
bitfld.long 0x4 18. "MSL,Master/Slave clock configuration. 0: External clock(sclk and lr_clk provided externally). 1: Internal clock (sclk and lr_clk sourced internally)." "0: External clock,1: Internal clock"
|
|
bitfld.long 0x4 17. "PRTX,Transmit clock edge polarity bit. 0: sdata is transmitted starting from the falling edge of sclk. 1: sdata is transmitted starting from the rising edge of sclk." "0: sdata is transmitted starting from the falling..,1: sdata is transmitted starting from the rising.."
|
|
newline
|
|
bitfld.long 0x4 16. "FSP,Polarity of fsync/lr_clk signal. 0: Active high. 1: Active low" "0: Active high,1: Active low"
|
|
hexmask.long.word 0x4 4.--15. 1. "FPER,Frame period in units of sclk. Period is FPER + 1 sclks in length. 0: 1 sclk 0x3F: 64 sclks"
|
|
newline
|
|
bitfld.long 0x4 0. "OEN,Output enable for SDATA output" "0,1"
|
|
line.long 0x8 "I2SCTL,Specified polarity and clock configuration of the I2S IPB clocks and IO signals"
|
|
bitfld.long 0x8 31. "I2SVAL,I2S validity bit mode. 1: RX data stored only when validity mask condition is asserted. 0: No validity mask conditions checking is done." "0: No validity mask conditions checking is done,1: RX data stored only when validity mask condition.."
|
|
bitfld.long 0x8 5. "RXRST,Active high receiver reset signal. 1: Flush the RX FIFO" "?,1: Flush the RX FIFO"
|
|
newline
|
|
bitfld.long 0x8 4. "RXEN,Receive enable control. 1: Enables capture of serial audio starting with first channel. 0: No receive data captured. For Full duplex operation RXEN and TXEN MUST be set in a single register write access or the Slave FSM may ignore one of the.." "0: No receive data captured,1: Enables capture of serial audio"
|
|
bitfld.long 0x8 1. "TXRST,Transmit reset signal. 1 will reset the TX side registers and flush the TX FIFO." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TXEN,Transmit enable signal. 1 will enable the transmission of serial audio. For Full duplex operation RXEN and TXEN MUST be set in a single register write access or the Slave FSM may ignore one of the bit-field read-modify-write accesses. TXRST and.." "0,1"
|
|
line.long 0xC "IPBIRPT,Additional mask and status registers for the IPB core."
|
|
bitfld.long 0xC 21. "TXDMAI,TX dma interrupt" "0,1"
|
|
bitfld.long 0xC 20. "RXDMAI,RX dma interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "TXEI,TX Empty interrupt. TX unit attempted to read an empty FIFO" "0,1"
|
|
bitfld.long 0xC 18. "RXFI,RX Full interrupt. RX unit attempted to write to a full FIFO" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "TXFFI,Transmit fifo low limit interrupt" "0,1"
|
|
bitfld.long 0xC 16. "RXFFI,Receive fifo high limit interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "TXDMAM,Transmit FIFO interrupt mask. Will assert interrupt when = 1 and cimdmareq_tx is asserted" "0,1"
|
|
bitfld.long 0xC 4. "RXDMAM,Receive FIFO interrupt mask. Will assert interrupt when = 1 and cimdmareq_rx is asserted" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "TXEM,Transmit FIFO interrupt mask. Will assert interrupt when = 1 and TXEI is asserted" "0,1"
|
|
bitfld.long 0xC 2. "RXFM,Receive FIFO interrupt mask. Will assert interrupt when = 1 and RXFI is asserted" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "TXFFM,Transmit FIFO interrupt mask. Will assert interrupt when = 1 and TXFFI is asserted" "0,1"
|
|
bitfld.long 0xC 0. "RXFFM,Receive FIFO interrupt mask. Will assert interrupt when = 1 and RXFFI is asserted" "0,1"
|
|
line.long 0x10 "IPCOREID,Returns the core ID of the IPB core. and used to write the I2S validity mask."
|
|
hexmask.long.byte 0x10 24.--31. 1. "COREFAM,Core Family. Also bit 31 is used to set the I2S validity bit when a write is done."
|
|
hexmask.long.byte 0x10 16.--23. 1. "COREID,Core ID of the IPB core"
|
|
line.long 0x14 "AMQCFG,Control the enablement of the ASRC module and the source of the MCLK used in the IPB core."
|
|
bitfld.long 0x14 0. "MCLKSRC,MCLK source. 1: Output of nco_clk divider. 0: MCLK from ambiq clock configuration directly" "0: MCLK from ambiq clock configuration directly,1: Output of nco_clk divider"
|
|
group.long 0x60++0x7
|
|
line.long 0x0 "INTDIV,Integer divide value for the nco_clk divider"
|
|
hexmask.long 0x0 0.--31. 1. "INTDIV,Integer divide value for internal clock divider"
|
|
line.long 0x4 "FRACDIV,Fractional divide value for the nco_clk divider"
|
|
hexmask.long 0x4 0.--31. 1. "FRACDIV,Fractional divide value for internal clock divider"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "CLKCFG,Provides clock selection and control for I2S clocks"
|
|
bitfld.long 0x0 20. "DIV3,0: no change to the clock selected by FSEL 1: frequency divide-by-3 of the clock selected by FSEL" "0: no change to the clock selected by FSEL,1: frequency divide-by-3 of the clock selected by.."
|
|
bitfld.long 0x0 16.--17. "REFFSEL,FUTURE USE Select the input clock frequency for the ref_clk. 0: HFRC_48MHz 1: HFRC_48MHz_GATED 2: XT_24MHz 3: HFRC2_48MHz" "0: HFRC_48MHz,1: HFRC_48MHz_GATED,2: XT_24MHz,3: HFRC2_48MHz"
|
|
newline
|
|
bitfld.long 0x0 12. "REFCLKEN,FUTURE USE Enable for the reference clock" "0,1"
|
|
hexmask.long.byte 0x0 4.--8. 1. "FSEL,Select the input clock frequency for the MCLK.Whenever changing the clock source here the MISC_HFRC2FRC bit in the CLKGEN module must first be set. The sequence for changing the clock source regardless of clock selection is to first force HFRC2 on.."
|
|
newline
|
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bitfld.long 0x0 0. "MCLKEN,Enable for the master audio clock." "0,1"
|
|
group.long 0x200++0x1B
|
|
line.long 0x0 "DMACFG,Configuration control of the DMA process. including the direction of DMA. and enablement of DMA"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RXREQCNT,Number of blocks of samples transferred before asserting the RXREQCNT interrupt signal. A block is 8 samples. The interrupt will assert if enabled and after RXREQCNT blocks of data has been transferred from the I2S into the device. A value of 0.."
|
|
hexmask.long.byte 0x0 8.--15. 1. "TXREQCNT,Number of blocks of samples transferred before asserting the TXREQCNT interrupt signal. A block is 8 samples. The interrupt will assert if enabled and after TXREQCNT blocks of data has been transferred to the I2S module from the device. A value.."
|
|
newline
|
|
bitfld.long 0x0 5. "TXDMAPRI,Sets the Priority of the TXDMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
|
|
bitfld.long 0x0 4. "TXDMAEN,DMA Enable for TX channel. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable TXDMA Function,1: Enable TXDMA Function"
|
|
newline
|
|
bitfld.long 0x0 1. "RXDMAPRI,Sets the Priority of the RXDMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
|
|
bitfld.long 0x0 0. "RXDMAEN,DMA Enable for RX channel. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable RXDMA Function,1: Enable RXDMA Function"
|
|
line.long 0x4 "RXDMATOTCNT,Contains the total count of samples to be stored for the current RX DMA operation. This register is updated as DMA beats complete."
|
|
hexmask.long.word 0x4 0.--11. 1. "RXTOTCNT,Number of 32b audio samples to transfer for RX DMA."
|
|
line.long 0x8 "RXDMAADDR,The address which the DMA operation will store the incoming audio samples. This address is updated as the samples are stored."
|
|
hexmask.long 0x8 0.--31. 1. "RXTARGADDR,Address bits of the target byte address for source of RX write DMA."
|
|
line.long 0xC "RXDMASTAT,Status of the RX DMA operation currently in progress."
|
|
bitfld.long 0xC 2. "RXDMAERR,RX DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set this bit will remain set until cleared by software." "0,1"
|
|
bitfld.long 0xC 1. "RXDMACPL,RX DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0 and will also be cleared when a new DMA is started." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "RXDMATIP,RX DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
|
|
line.long 0x10 "TXDMATOTCNT,Contains the total count of samples to be read and transmitted for the current TX DMA operation. This register is updated as DMA beats complete."
|
|
hexmask.long.word 0x10 0.--11. 1. "TXTOTCNT,Number of 32b audio samples to transmit"
|
|
line.long 0x14 "TXDMAADDR,The address which the DMA operation will fetch the audio samples. This address is updated as the samples are stored."
|
|
hexmask.long 0x14 0.--31. 1. "TXTARGADDR,Address bits of the target byte address for source of TX write DMA."
|
|
line.long 0x18 "TXDMASTAT,Status of the TX DMA operation currently in progress."
|
|
bitfld.long 0x18 2. "TXDMAERR,TX DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set this bit will remain set until cleared by software." "0,1"
|
|
bitfld.long 0x18 1. "TXDMACPL,TX DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0 and will also be cleared when a new DMA is started." "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXDMATIP,TX DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
|
|
group.long 0x230++0x3
|
|
line.long 0x0 "STATUS,I2S Module Status"
|
|
bitfld.long 0x0 0. "TBD,To Be determined." "0,1"
|
|
group.long 0x300++0xF
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 4. "RXDMACPL,A RX dma operation has completed" "0,1"
|
|
bitfld.long 0x0 3. "TXDMACPL,A TX dma operation has completed" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXREQCNT,The I2S module has asserted the dma read request based on TX fifo level." "0,1"
|
|
bitfld.long 0x0 1. "RXREQCNT,The I2S module has completed RXREQCNT number of DMA transfers of size 8 samples. This interrupt allows servicing of buffers at a programmable location within the overall DMA transfer." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IPB,Interrupt from I2S module" "0,1"
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 4. "RXDMACPL,A RX dma operation has completed" "0,1"
|
|
bitfld.long 0x4 3. "TXDMACPL,A TX dma operation has completed" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXREQCNT,The I2S module has asserted the dma read request based on TX fifo level." "0,1"
|
|
bitfld.long 0x4 1. "RXREQCNT,The I2S module has completed RXREQCNT number of DMA transfers of size 8 samples. This interrupt allows servicing of buffers at a programmable location within the overall DMA transfer." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IPB,Interrupt from I2S module" "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 4. "RXDMACPL,A RX dma operation has completed" "0,1"
|
|
bitfld.long 0x8 3. "TXDMACPL,A TX dma operation has completed" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "TXREQCNT,The I2S module has asserted the dma read request based on TX fifo level." "0,1"
|
|
bitfld.long 0x8 1. "RXREQCNT,The I2S module has completed RXREQCNT number of DMA transfers of size 8 samples. This interrupt allows servicing of buffers at a programmable location within the overall DMA transfer." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "IPB,Interrupt from I2S module" "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 4. "RXDMACPL,A RX dma operation has completed" "0,1"
|
|
bitfld.long 0xC 3. "TXDMACPL,A TX dma operation has completed" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "TXREQCNT,The I2S module has asserted the dma read request based on TX fifo level." "0,1"
|
|
bitfld.long 0xC 1. "RXREQCNT,The I2S module has completed RXREQCNT number of DMA transfers of size 8 samples. This interrupt allows servicing of buffers at a programmable location within the overall DMA transfer." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "IPB,Interrupt from I2S module" "0,1"
|
|
group.long 0x400++0x3
|
|
line.long 0x0 "I2SDBG,Debug control"
|
|
hexmask.long 0x0 3.--31. 1. "DBGDATA,Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers."
|
|
bitfld.long 0x0 2. "APBCLKON,APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MCLKON,MCLK debug clock control. Enable MCLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
|
|
bitfld.long 0x0 0. "DBGEN,Debug Enable. Setting bit will enable the update of data within this register otherwise it is clock gated for power savings" "0,1"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "IOM (IO Peripheral Master)"
|
|
base ad:0x0
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
tree "IOM0"
|
|
base ad:0x40050000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FIFO,Provides direct random access to both input and output fifos. The state of the FIFO is not distured by reading these locations (ie no POP will be done). FIFO0 is accessible from addresses 0x0 - 0x1C. and is used for data outuput from the IOM to.."
|
|
hexmask.long 0x0 0.--31. 1. "FIFO,FIFO direct access. Only locations 0 - 3F will return valid information."
|
|
group.long 0x100++0x2F
|
|
line.long 0x0 "FIFOPTR,Provides the current valid byte count of data within the FIFO as seen from the internal state machines. FIFO0 is dedicated to outgoing transactions and FIFO1 is dedicated to incoming transactions. All counts are specified in units of bytes."
|
|
hexmask.long.byte 0x0 24.--31. 1. "FIFO1REM,The number of remaining data bytes slots currently in FIFO 1 (written by interface read by MCU)"
|
|
hexmask.long.byte 0x0 16.--23. 1. "FIFO1SIZ,The number of valid data bytes currently in FIFO 1 (written by interface read by MCU)"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "FIFO0REM,The number of remaining data bytes slots currently in FIFO 0 (written by MCU read by interface)"
|
|
hexmask.long.byte 0x0 0.--7. 1. "FIFO0SIZ,The number of valid data bytes currently in the FIFO 0 (written by MCU read by interface)"
|
|
line.long 0x4 "FIFOTHR,Sets the threshold values for incoming and outgoing transactions. The threshold values are used to assert the interrupt if enabled. and also used during DMA to set the transfer size as a result of DMATHR trigger."
|
|
hexmask.long.byte 0x4 8.--13. 1. "FIFOWTHR,FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the write fifo contains FIFOWTHR free bytes as.."
|
|
hexmask.long.byte 0x4 0.--5. 1. "FIFORTHR,FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the read fifo contains FIFORTHR valid bytes of data as.."
|
|
line.long 0x8 "FIFOPOP,Will advance the internal read pointer of the incoming FIFO (FIFO1) when read. if POPWR is not active. If POPWR is active. a write to this register is needed to advance the internal FIFO pointer."
|
|
hexmask.long 0x8 0.--31. 1. "FIFODOUT,This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0) the fifo read pointer will be advanced by one word as a result of the read."
|
|
line.long 0xC "FIFOPUSH,Will write new data into the outgoing FIFO and advance the internal write pointer."
|
|
hexmask.long 0xC 0.--31. 1. "FIFODIN,This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes)."
|
|
line.long 0x10 "FIFOCTRL,Provides controls for the operation of the internal FIFOs. Contains fields used to control the operation of the POP register. and also controls to reset the internal pointers of the FIFOs."
|
|
bitfld.long 0x10 1. "FIFORSTN,Active low manual reset of the fifo. Write to 0 to reset fifo and then write to 1 to remove the reset." "0,1"
|
|
bitfld.long 0x10 0. "POPWR,Selects the mode in which 'pop' events are done for the fifo read operations. A value of '1' will prevent a pop event on a read operation and will require a write to the FIFOPOP register to create a pop event." "0,1"
|
|
line.long 0x14 "FIFOLOC,Provides a read only value of the current read and write pointers. This register is read only and can be used alogn with the FIFO direct access method to determine the next data to be used for input and output functions."
|
|
hexmask.long.byte 0x14 8.--11. 1. "FIFORPTR,Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1) which is used to store read data returned from external devices during a read operation."
|
|
hexmask.long.byte 0x14 0.--3. 1. "FIFOWPTR,Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0) which is used during write operations to external devices."
|
|
line.long 0x18 "CLKCFG,Provides clock related controls used internal to the BLEIF module. and enablement of 32KHz clock to the BLE Core module. The internal clock sourced is selected via the FSEL and can be further divided by 3 using the DIV3 control."
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hexmask.long.byte 0x18 24.--31. 1. "TOTPER,Clock total clock count minus 1. This provides the total period of the divided clock -1 when the DIVEN is active. The"
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hexmask.long.byte 0x18 16.--23. 1. "LOWPER,Clock low clock count minus 1. This provides the number of clocks the divided clock will be low when the DIVEN = 1."
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bitfld.long 0x18 12. "DIVEN,Enable clock division by TOTPER and LOWPER" "0: Disable TOTPER division.,1: Enable TOTPER division."
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bitfld.long 0x18 11. "DIV3,Enable divide by 3 of the source IOCLK. Division by 3 is done before the DIVEN programmable divider and if enabled" "0: Select divide by 1.,1: Select divide by 3."
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bitfld.long 0x18 8.--10. "FSEL,Select the input clock frequency." "0: Selects the minimum power clock. This setting..,1: Selects static 0 as the input clock. Previously..,2: Selects the HFRC 48MHz as the input clock.,3: Selects the HFRC 24MHz as the input clock.,4: Selects the HFRC 12MHz as the input clock.,5: Selects the HFRC 6MHz as the input clock.,6: Selects the HFRC 3MHz as the input clock.,7: Selects the HFRC 1.5MHz as the input clock."
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bitfld.long 0x18 0. "IOCLKEN,Enable for the interface clock. Must be enabled prior to executing any IO operations." "0,1"
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line.long 0x1C "SUBMODCTRL,Provides enable for each submodule. Only a sigle submodule can be enabled at one time."
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bitfld.long 0x1C 9.--11. "SMOD2TYPE,Submodule 2 module type. This is the I2S Master/Slave interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,4: Master/Slave submodule,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 8. "SMOD2EN,Submodule 2 enable (1) or disable (0)" "0,1"
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bitfld.long 0x1C 5.--7. "SMOD1TYPE,Submodule 1 module type. This is the I2C Master interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,4: Master/Slave submodule,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 4. "SMOD1EN,Submodule 1 enable (1) or disable (0)" "0,1"
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bitfld.long 0x1C 1.--3. "SMOD0TYPE,Submodule 0 module type. This is the SPI Master interface." "0: MSPI submodule,1: I2C Master submodule,2: I2S Master/Slave Module,?,?,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 0. "SMOD0EN,Submodule 0 enable (1) or disable (0)" "0,1"
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line.long 0x20 "CMD,Writes to this register will start an IO transaction. as well as set various parameters for the command itself. Reads will return the command value written to the CMD register."
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hexmask.long.byte 0x20 24.--31. 1. "OFFSETLO,This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command."
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bitfld.long 0x20 20.--21. "CMDSEL,Command Specific selection information. Not used in Master I2C. Used as CEn select for Master SPI transactions" "0,1,2,3"
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hexmask.long.word 0x20 8.--19. 1. "TSIZE,Defines the transaction size in bytes. The offset transfer is not included in this size."
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bitfld.long 0x20 7. "CONT,Contine to hold the bus after the current transaction if set to a 1 with a new command issued." "0,1"
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bitfld.long 0x20 4.--6. "OFFSETCNT,Number of offset bytes to use for the command - 0 1 2 3 4 5 are valid selections. The second (byte 1) third (byte 2) and forth (byte 3) are read from the OFFSETHI register and the low order byte is pulled from this register in the.." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x20 0.--3. 1. "CMD,Command for submodule."
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line.long 0x24 "DCXCTRL,Enables transmission of DCX signal with SPI transactions and selects which CE signals will be used to transmit the DCX signal."
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bitfld.long 0x24 4. "DCXEN,Global enable of the DCX function. Setting to 1 will enable the generation of the DCX signal which will assert when sending the offset bytes of the SPI transaction." "0,1"
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hexmask.long.byte 0x24 0.--3. 1. "DCXSEL,Selects the CE channel used to convey the DCX function. The select is bitwise encoded with bit 0 = 1 enabling CE0 for DCX transmission bit 1 = 1 enableing CE1 for DCX transmission etc. If the CE used for the SPI transaction is set it will be.."
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line.long 0x28 "OFFSETHI,High order bytes of offset for IO transaction"
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hexmask.long 0x28 0.--31. 1. "OFFSETHI,Holds the high order bytes of the byte addressing/offset field to use with IO commands. The number of offset bytes to use is specified in the command register"
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line.long 0x2C "CMDSTAT,Provides staus on the execution of the command currently in progress. The fields in this register will reflect the real time status of the internal state machines and data transfers within the IOM."
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hexmask.long.word 0x2C 8.--19. 1. "CTSIZE,The current number of bytes still to be transferred with this command. This field will count down to zero."
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bitfld.long 0x2C 5.--7. "CMDSTAT,The current status of the command execution." "?,1: Error encountered with command,2: Actively processing command,?,4: Idle state no active command no error,?,6: Command in progress but waiting on data from host,?"
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hexmask.long.byte 0x2C 0.--4. 1. "CCMD,Current command that is being executed; This will update based on the phase of the I2C and will indicate a write operation during transmission of the offset "
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group.long 0x200++0x4B
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line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
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bitfld.long 0x0 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x0 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x0 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x0 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x0 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x0 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. Also asserted during I2C write operations when value of 1 expected on bus but 0 is observed. When asserted the I2C state machine will.." "0,1"
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bitfld.long 0x0 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x0 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x0 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x0 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x0 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x0 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0x0 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0x0 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x0 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
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bitfld.long 0x4 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x4 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x4 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x4 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x4 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x4 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. Also asserted during I2C write operations when value of 1 expected on bus but 0 is observed. When asserted the I2C state machine will.." "0,1"
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bitfld.long 0x4 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x4 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x4 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x4 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x4 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x4 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0x4 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0x4 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x4 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
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bitfld.long 0x8 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x8 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x8 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x8 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x8 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x8 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. Also asserted during I2C write operations when value of 1 expected on bus but 0 is observed. When asserted the I2C state machine will.." "0,1"
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bitfld.long 0x8 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x8 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x8 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x8 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x8 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x8 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0x8 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0x8 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x8 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
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bitfld.long 0xC 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0xC 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0xC 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0xC 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0xC 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0xC 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. Also asserted during I2C write operations when value of 1 expected on bus but 0 is observed. When asserted the I2C state machine will.." "0,1"
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bitfld.long 0xC 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0xC 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0xC 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0xC 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0xC 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0xC 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0xC 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0xC 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0xC 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x10 "DMATRIGEN,Provides control on which event will trigger the DMA transfer after the DMA operation is setup and enabled. The trigger event will cause a number of bytes (depending on trigger event) to be"
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bitfld.long 0x10 1. "DTHREN,Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes) the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO and will transfer (WTHR/4) number of words" "0,1"
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bitfld.long 0x10 0. "DCMDCMPEN,Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered the number of words transferred will be the lesser of the remaining TOTCOUNT bytes or" "0,1"
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line.long 0x14 "DMATRIGSTAT,Provides the status of trigger events that have occurred for the transaction. Some of the bits are read only and some can be reset via a write of 0."
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bitfld.long 0x14 2. "DTOTCMP,DMA triggered when DCMDCMP = 0 and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is" "0,1"
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bitfld.long 0x14 1. "DTHR,Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA." "0,1"
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bitfld.long 0x14 0. "DCMDCMP,Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA." "0,1"
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line.long 0x18 "DMACFG,Configuration control of the DMA process. including the direction of DMA. and enablement of DMA"
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bitfld.long 0x18 9. "DPWROFF,Power off module after DMA is complete. If this bit is active the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain power down will not be performed." "0: Power off disabled,1: Power off enabled"
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bitfld.long 0x18 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x18 1. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction. To be..,1: Memory to Peripheral transaction. To be set when.."
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bitfld.long 0x18 0. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable DMA Function,1: Enable DMA Function"
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line.long 0x1C "DMATOTCOUNT,Contains the number of bytes to be transferred for this DMA transaction. This register is decremented as the data is transferred. and will be 0 at the completion of the DMA operation."
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hexmask.long.word 0x1C 0.--11. 1. "TOTCOUNT,Triggered DMA from Command complete event occured. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."
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line.long 0x20 "DMATARGADDR,The source or destination address internal the SRAM for the DMA data. For write operations. this can only be SRAM data (ADDR bit 28 = 1); For read operations. this can ve either SRAM or FLASH (ADDR bit 28 = 0)"
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hexmask.long 0x20 0.--28. 1. "TARGADDR,Bits [28:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment and does not have to be word aligned. In cases of non-word aligned addresses the DMA logic will take care for ensuring only.."
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line.long 0x24 "DMASTAT,Status of the DMA operation currently in progress."
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bitfld.long 0x24 2. "DMAERR,DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set this bit will remain set until cleared by software." "0,1"
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bitfld.long 0x24 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0 and will also be cleared when a new DMA is started." "0,1"
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bitfld.long 0x24 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
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line.long 0x28 "CQCFG,Controls parameters and options for execution of the command queue operation. To enable command queue. create this in memory. set the address. and enable it with a write to CQEN"
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bitfld.long 0x28 2.--3. "MSPIFLGSEL,Selects the MPSI modules used for sourcing the CQFLAG [11:8]." "0: Selects MPSI0 as source of signals used in..,1: Selects MPSI1 as source of signals used in..,2: Selects MPSI2 as source of signals used in..,?"
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bitfld.long 0x28 1. "CQPRI,Sets the Priority of the command queue dma request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x28 0. "CQEN,Command queue enable. When set will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled" "0: Disable CQ Function,1: Enable CQ Function"
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line.long 0x2C "CQADDR,The SRAM address which will be fetched next execution of the CQ operation. This register is updated as the CQ operation progresses. and is the live version of the register. The register can also be"
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hexmask.long 0x2C 2.--28. 1. "CQADDR,Bits 28:2 of target byte address for source of CQ . The buffer must be aligned on a word boundary"
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line.long 0x30 "CQSTAT,Provides the status of the command queue operation. If the command queue is disabled. these bits will be cleared. The bits are read only"
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bitfld.long 0x30 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
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bitfld.long 0x30 1. "CQPAUSED,Command queue operation is currently paused." "0,1"
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bitfld.long 0x30 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
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line.long 0x34 "CQFLAGS,Command Queue Flag"
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hexmask.long.word 0x34 16.--31. 1. "CQIRQMASK,Mask the bits used to generate the command queue interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE"
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hexmask.long.word 0x34 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
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line.long 0x38 "CQSETCLEAR,Set/Clear the command queue software pause flags on a per-bit basis. Contains 3 fields. allowing for setting. clearing or toggling the value in the software flags. Priority when the same bit"
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hexmask.long.byte 0x38 16.--23. 1. "CQFCLR,Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x38 8.--15. 1. "CQFTGL,Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x38 0.--7. 1. "CQFSET,Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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line.long 0x3C "CQPAUSEEN,Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the CQFLAG register is '1'. CQ processing will halt until either value is changed to '0'."
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hexmask.long.word 0x3C 0.--15. 1. "CQPEN,Enables the specified event to pause command processing when active"
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line.long 0x40 "CQCURIDX,Current index value. targeted to be written by register write operations within the command queue. This is compared to the CQENDIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and"
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hexmask.long.byte 0x40 0.--7. 1. "CQCURIDX,Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x44 "CQENDIDX,End index value. targeted to be written by software to indicate the last valid register pair contained within the command queue. rgister write operations within the command queue."
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hexmask.long.byte 0x44 0.--7. 1. "CQENDIDX,Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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|
line.long 0x48 "STATUS,IOM Module Status"
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|
bitfld.long 0x48 2. "IDLEST,indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to holdoffs from data availability or as the command gets propagated into the logic from the registers." "?,1: The I/O state machine is in the idle state."
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bitfld.long 0x48 1. "CMDACT,Indicates if the active I/O Command is currently processing a transaction or command is complete but the FIFO pointers are still syncronizing internally. This bit will go high at" "?,1: An I/O command is active. Indicates the active.."
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|
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bitfld.long 0x48 0. "ERR,Bit has been deprecated. Please refer to the other error indicators. This will always return 0." "?,1: Bit has been deprecated and will always return 0."
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|
group.long 0x280++0x3
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|
line.long 0x0 "MSPICFG,Controls the configuration of the SPI master module. including POL/PHA. LSB. flow control. and delays for MISO and MOSI"
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bitfld.long 0x0 30. "MSPIRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 27.--29. "DOUTDLY,Delay tap to use for the output signal (MOSI). This give more hold time on the output data" "0,1,2,3,4,5,6,7"
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|
newline
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bitfld.long 0x0 24.--26. "DINDLY,Delay tap to use for the input signal (MISO). This gives more hold time on the input data." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "SPILSB,Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first." "0: Send and receive MSB bit first,1: Send and receive LSB bit first"
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newline
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bitfld.long 0x0 22. "RDFCPOL,Selects the read flow control signal polarity." "0: Flow control signal high creates flow control.,1: Flow control signal low creates flow control."
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bitfld.long 0x0 21. "WTFCPOL,selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 will allow a IRQ=1 to pause transfers)." "0: Flow control signal high(1) creates flow control..,1: Flow control signal low(0) creates flow control.."
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newline
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bitfld.long 0x0 20. "WTFCIRQ,Selects the write mode flow control signal." "0: MISO is used as the write mode flow control..,1: IRQ is used as the write mode flow control signal."
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bitfld.long 0x0 18. "MOSIINV,Inverts MOSI when flow control is enabled." "0: MOSI is set to 0 in read mode and 1 in write mode.,1: MOSI is set to 1 in read mode and 0 in write mode."
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newline
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bitfld.long 0x0 17. "RDFC,Enables read mode flow control." "0: Read mode flow control disabled.,1: Read mode flow control enabled."
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bitfld.long 0x0 16. "WTFC,enables write mode flow control." "0: Write mode flow control disabled.,1: Write mode flow control enabled."
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newline
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bitfld.long 0x0 2. "FULLDUP,Enables full duplex mode for Master SPI write operations. Data will be captured simultaneously into the read fifo" "0,1"
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bitfld.long 0x0 1. "SPHA,Selects SPI phase.IMPORTANT NOTICE: Due to the susceptibility of creating a clock glitch which could cause register corruption changing SPHA and SPOL bits should be done in separate writes to this register." "0: Sample on the leading (first) clock edge.,1: Sample on the trailing (second) clock edge."
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newline
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bitfld.long 0x0 0. "SPOL,Selects SPI polarity.IMPORTANT NOTICE: Due to the susceptibility of creating a clock glitch which could cause register corruption changing SPHA and SPOL bits should be done in separate writes to this register." "0: The base value of the clock is 0.,1: The base value of the clock is 1."
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group.long 0x2C0++0x7
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line.long 0x0 "MI2CCFG,Controls the configuration of the I2C bus master."
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bitfld.long 0x0 24. "STRDIS,Disable detection of clock stretch events smaller than 1 cycle" "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "SMPCNT,Number of Base clk cycles to wait before sampling the SCL clock to determine if a clock stretch event has occured"
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newline
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hexmask.long.byte 0x0 12.--15. 1. "SDAENDLY,Number of IOCLK cycles to delay the SDA output en (all transitions affected). Used to delay data relative to clock"
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hexmask.long.byte 0x0 8.--11. 1. "SCLENDLY,Number of IOCLK cycles to delay the rising edge of the SCL output en (clock will go low on this edge). Used to allow clock shaping."
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newline
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bitfld.long 0x0 6. "MI2CRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 4.--5. "SDADLY,Delay to enable on the SDA output. Values are 0x0-0x3." "0,1,2,3"
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newline
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bitfld.long 0x0 2. "ARBEN,Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master this function can be disabled to save clock cycles on I2C transactions" "0: Disable multi-master bus arbitration support for..,1: Enable multi-master bus arbitration support for.."
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bitfld.long 0x0 1. "I2CLSB,Direction of data transmit and receive MSB(0) or LSB(1) first. Default per I2C specification is MSB first. This applies to both read and write data and read data will be bit" "0: Byte data is transmitted MSB first onto the..,1: Byte data is transmitted LSB first onto the.."
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newline
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bitfld.long 0x0 0. "ADDRSZ,Sets the I2C master device address size to either 7b (0) or 10b (1)." "0: Use 7b addressing for I2C master transactions,1: Use 10b addressing for I2C master transactions"
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line.long 0x4 "DEVCFG,Contains the I2C device address."
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hexmask.long.word 0x4 0.--9. 1. "DEVADDR,I2C address of the device that the Master will use to target for read/write operations. This can be either a 7b or 10b address."
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group.long 0x388++0x3
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line.long 0x0 "IOMDBG,Debug control"
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hexmask.long 0x0 3.--31. 1. "DBGDATA,Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers."
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bitfld.long 0x0 2. "APBCLKON,APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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newline
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bitfld.long 0x0 1. "IOCLKON,IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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bitfld.long 0x0 0. "DBGEN,Debug Enable. Setting bit will enable the update of data within this register otherwise it is clock gated for power savings" "0,1"
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|
tree.end
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
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tree "IOM1"
|
|
base ad:0x40051000
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|
group.long 0x0++0x3
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|
line.long 0x0 "FIFO,Provides direct random access to both input and output fifos. The state of the FIFO is not distured by reading these locations (ie no POP will be done). FIFO0 is accessible from addresses 0x0 - 0x1C. and is used for data outuput from the IOM to.."
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hexmask.long 0x0 0.--31. 1. "FIFO,FIFO direct access. Only locations 0 - 3F will return valid information."
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group.long 0x100++0x2F
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line.long 0x0 "FIFOPTR,Provides the current valid byte count of data within the FIFO as seen from the internal state machines. FIFO0 is dedicated to outgoing transactions and FIFO1 is dedicated to incoming transactions. All counts are specified in units of bytes."
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hexmask.long.byte 0x0 24.--31. 1. "FIFO1REM,The number of remaining data bytes slots currently in FIFO 1 (written by interface read by MCU)"
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hexmask.long.byte 0x0 16.--23. 1. "FIFO1SIZ,The number of valid data bytes currently in FIFO 1 (written by interface read by MCU)"
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|
newline
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hexmask.long.byte 0x0 8.--15. 1. "FIFO0REM,The number of remaining data bytes slots currently in FIFO 0 (written by MCU read by interface)"
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|
hexmask.long.byte 0x0 0.--7. 1. "FIFO0SIZ,The number of valid data bytes currently in the FIFO 0 (written by MCU read by interface)"
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|
line.long 0x4 "FIFOTHR,Sets the threshold values for incoming and outgoing transactions. The threshold values are used to assert the interrupt if enabled. and also used during DMA to set the transfer size as a result of DMATHR trigger."
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hexmask.long.byte 0x4 8.--13. 1. "FIFOWTHR,FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the write fifo contains FIFOWTHR free bytes as.."
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|
hexmask.long.byte 0x4 0.--5. 1. "FIFORTHR,FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the read fifo contains FIFORTHR valid bytes of data as.."
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line.long 0x8 "FIFOPOP,Will advance the internal read pointer of the incoming FIFO (FIFO1) when read. if POPWR is not active. If POPWR is active. a write to this register is needed to advance the internal FIFO pointer."
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hexmask.long 0x8 0.--31. 1. "FIFODOUT,This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0) the fifo read pointer will be advanced by one word as a result of the read."
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|
line.long 0xC "FIFOPUSH,Will write new data into the outgoing FIFO and advance the internal write pointer."
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hexmask.long 0xC 0.--31. 1. "FIFODIN,This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes)."
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line.long 0x10 "FIFOCTRL,Provides controls for the operation of the internal FIFOs. Contains fields used to control the operation of the POP register. and also controls to reset the internal pointers of the FIFOs."
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bitfld.long 0x10 1. "FIFORSTN,Active low manual reset of the fifo. Write to 0 to reset fifo and then write to 1 to remove the reset." "0,1"
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bitfld.long 0x10 0. "POPWR,Selects the mode in which 'pop' events are done for the fifo read operations. A value of '1' will prevent a pop event on a read operation and will require a write to the FIFOPOP register to create a pop event." "0,1"
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line.long 0x14 "FIFOLOC,Provides a read only value of the current read and write pointers. This register is read only and can be used alogn with the FIFO direct access method to determine the next data to be used for input and output functions."
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hexmask.long.byte 0x14 8.--11. 1. "FIFORPTR,Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1) which is used to store read data returned from external devices during a read operation."
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hexmask.long.byte 0x14 0.--3. 1. "FIFOWPTR,Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0) which is used during write operations to external devices."
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line.long 0x18 "CLKCFG,Provides clock related controls used internal to the BLEIF module. and enablement of 32KHz clock to the BLE Core module. The internal clock sourced is selected via the FSEL and can be further divided by 3 using the DIV3 control."
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hexmask.long.byte 0x18 24.--31. 1. "TOTPER,Clock total clock count minus 1. This provides the total period of the divided clock -1 when the DIVEN is active. The"
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hexmask.long.byte 0x18 16.--23. 1. "LOWPER,Clock low clock count minus 1. This provides the number of clocks the divided clock will be low when the DIVEN = 1."
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newline
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bitfld.long 0x18 12. "DIVEN,Enable clock division by TOTPER and LOWPER" "0: Disable TOTPER division.,1: Enable TOTPER division."
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bitfld.long 0x18 11. "DIV3,Enable divide by 3 of the source IOCLK. Division by 3 is done before the DIVEN programmable divider and if enabled" "0: Select divide by 1.,1: Select divide by 3."
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newline
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bitfld.long 0x18 8.--10. "FSEL,Select the input clock frequency." "0: Selects the minimum power clock. This setting..,1: Selects static 0 as the input clock. Previously..,2: Selects the HFRC 48MHz as the input clock.,3: Selects the HFRC 24MHz as the input clock.,4: Selects the HFRC 12MHz as the input clock.,5: Selects the HFRC 6MHz as the input clock.,6: Selects the HFRC 3MHz as the input clock.,7: Selects the HFRC 1.5MHz as the input clock."
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bitfld.long 0x18 0. "IOCLKEN,Enable for the interface clock. Must be enabled prior to executing any IO operations." "0,1"
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line.long 0x1C "SUBMODCTRL,Provides enable for each submodule. Only a sigle submodule can be enabled at one time."
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bitfld.long 0x1C 9.--11. "SMOD2TYPE,Submodule 2 module type. This is the I2S Master/Slave interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,4: Master/Slave submodule,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 8. "SMOD2EN,Submodule 2 enable (1) or disable (0)" "0,1"
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newline
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bitfld.long 0x1C 5.--7. "SMOD1TYPE,Submodule 1 module type. This is the I2C Master interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,4: Master/Slave submodule,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 4. "SMOD1EN,Submodule 1 enable (1) or disable (0)" "0,1"
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newline
|
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bitfld.long 0x1C 1.--3. "SMOD0TYPE,Submodule 0 module type. This is the SPI Master interface." "0: MSPI submodule,1: I2C Master submodule,2: I2S Master/Slave Module,?,?,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 0. "SMOD0EN,Submodule 0 enable (1) or disable (0)" "0,1"
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line.long 0x20 "CMD,Writes to this register will start an IO transaction. as well as set various parameters for the command itself. Reads will return the command value written to the CMD register."
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hexmask.long.byte 0x20 24.--31. 1. "OFFSETLO,This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command."
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bitfld.long 0x20 20.--21. "CMDSEL,Command Specific selection information. Not used in Master I2C. Used as CEn select for Master SPI transactions" "0,1,2,3"
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newline
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hexmask.long.word 0x20 8.--19. 1. "TSIZE,Defines the transaction size in bytes. The offset transfer is not included in this size."
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|
bitfld.long 0x20 7. "CONT,Contine to hold the bus after the current transaction if set to a 1 with a new command issued." "0,1"
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newline
|
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bitfld.long 0x20 4.--6. "OFFSETCNT,Number of offset bytes to use for the command - 0 1 2 3 4 5 are valid selections. The second (byte 1) third (byte 2) and forth (byte 3) are read from the OFFSETHI register and the low order byte is pulled from this register in the.." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x20 0.--3. 1. "CMD,Command for submodule."
|
|
line.long 0x24 "DCXCTRL,Enables transmission of DCX signal with SPI transactions and selects which CE signals will be used to transmit the DCX signal."
|
|
bitfld.long 0x24 4. "DCXEN,Global enable of the DCX function. Setting to 1 will enable the generation of the DCX signal which will assert when sending the offset bytes of the SPI transaction." "0,1"
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hexmask.long.byte 0x24 0.--3. 1. "DCXSEL,Selects the CE channel used to convey the DCX function. The select is bitwise encoded with bit 0 = 1 enabling CE0 for DCX transmission bit 1 = 1 enableing CE1 for DCX transmission etc. If the CE used for the SPI transaction is set it will be.."
|
|
line.long 0x28 "OFFSETHI,High order bytes of offset for IO transaction"
|
|
hexmask.long 0x28 0.--31. 1. "OFFSETHI,Holds the high order bytes of the byte addressing/offset field to use with IO commands. The number of offset bytes to use is specified in the command register"
|
|
line.long 0x2C "CMDSTAT,Provides staus on the execution of the command currently in progress. The fields in this register will reflect the real time status of the internal state machines and data transfers within the IOM."
|
|
hexmask.long.word 0x2C 8.--19. 1. "CTSIZE,The current number of bytes still to be transferred with this command. This field will count down to zero."
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|
bitfld.long 0x2C 5.--7. "CMDSTAT,The current status of the command execution." "?,1: Error encountered with command,2: Actively processing command,?,4: Idle state no active command no error,?,6: Command in progress but waiting on data from host,?"
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|
newline
|
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hexmask.long.byte 0x2C 0.--4. 1. "CCMD,Current command that is being executed; This will update based on the phase of the I2C and will indicate a write operation during transmission of the offset "
|
|
group.long 0x200++0x4B
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
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|
bitfld.long 0x0 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x0 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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newline
|
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bitfld.long 0x0 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x0 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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newline
|
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bitfld.long 0x0 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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|
bitfld.long 0x0 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. Also asserted during I2C write operations when value of 1 expected on bus but 0 is observed. When asserted the I2C state machine will.." "0,1"
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newline
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bitfld.long 0x0 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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|
bitfld.long 0x0 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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|
newline
|
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bitfld.long 0x0 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x0 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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newline
|
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bitfld.long 0x0 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x0 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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newline
|
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bitfld.long 0x0 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0x0 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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newline
|
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bitfld.long 0x0 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
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bitfld.long 0x4 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x4 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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newline
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bitfld.long 0x4 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x4 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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newline
|
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bitfld.long 0x4 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0x4 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. Also asserted during I2C write operations when value of 1 expected on bus but 0 is observed. When asserted the I2C state machine will.." "0,1"
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newline
|
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bitfld.long 0x4 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x4 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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|
newline
|
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bitfld.long 0x4 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x4 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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|
newline
|
|
bitfld.long 0x4 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0x4 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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|
newline
|
|
bitfld.long 0x4 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
|
|
bitfld.long 0x4 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 14. "CQERR,Error during command queue operations" "0,1"
|
|
bitfld.long 0x8 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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|
newline
|
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bitfld.long 0x8 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
|
|
bitfld.long 0x8 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0x8 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. Also asserted during I2C write operations when value of 1 expected on bus but 0 is observed. When asserted the I2C state machine will.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x8 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
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bitfld.long 0x8 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x8 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x8 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0x8 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0x8 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x8 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
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bitfld.long 0xC 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0xC 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0xC 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0xC 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0xC 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0xC 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. Also asserted during I2C write operations when value of 1 expected on bus but 0 is observed. When asserted the I2C state machine will.." "0,1"
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bitfld.long 0xC 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0xC 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0xC 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0xC 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0xC 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0xC 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0xC 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0xC 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0xC 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x10 "DMATRIGEN,Provides control on which event will trigger the DMA transfer after the DMA operation is setup and enabled. The trigger event will cause a number of bytes (depending on trigger event) to be"
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bitfld.long 0x10 1. "DTHREN,Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes) the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO and will transfer (WTHR/4) number of words" "0,1"
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bitfld.long 0x10 0. "DCMDCMPEN,Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered the number of words transferred will be the lesser of the remaining TOTCOUNT bytes or" "0,1"
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line.long 0x14 "DMATRIGSTAT,Provides the status of trigger events that have occurred for the transaction. Some of the bits are read only and some can be reset via a write of 0."
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bitfld.long 0x14 2. "DTOTCMP,DMA triggered when DCMDCMP = 0 and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is" "0,1"
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bitfld.long 0x14 1. "DTHR,Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA." "0,1"
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bitfld.long 0x14 0. "DCMDCMP,Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA." "0,1"
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line.long 0x18 "DMACFG,Configuration control of the DMA process. including the direction of DMA. and enablement of DMA"
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bitfld.long 0x18 9. "DPWROFF,Power off module after DMA is complete. If this bit is active the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain power down will not be performed." "0: Power off disabled,1: Power off enabled"
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bitfld.long 0x18 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x18 1. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction. To be..,1: Memory to Peripheral transaction. To be set when.."
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bitfld.long 0x18 0. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable DMA Function,1: Enable DMA Function"
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line.long 0x1C "DMATOTCOUNT,Contains the number of bytes to be transferred for this DMA transaction. This register is decremented as the data is transferred. and will be 0 at the completion of the DMA operation."
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hexmask.long.word 0x1C 0.--11. 1. "TOTCOUNT,Triggered DMA from Command complete event occured. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."
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line.long 0x20 "DMATARGADDR,The source or destination address internal the SRAM for the DMA data. For write operations. this can only be SRAM data (ADDR bit 28 = 1); For read operations. this can ve either SRAM or FLASH (ADDR bit 28 = 0)"
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hexmask.long 0x20 0.--28. 1. "TARGADDR,Bits [28:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment and does not have to be word aligned. In cases of non-word aligned addresses the DMA logic will take care for ensuring only.."
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line.long 0x24 "DMASTAT,Status of the DMA operation currently in progress."
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bitfld.long 0x24 2. "DMAERR,DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set this bit will remain set until cleared by software." "0,1"
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bitfld.long 0x24 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0 and will also be cleared when a new DMA is started." "0,1"
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bitfld.long 0x24 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
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line.long 0x28 "CQCFG,Controls parameters and options for execution of the command queue operation. To enable command queue. create this in memory. set the address. and enable it with a write to CQEN"
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bitfld.long 0x28 2.--3. "MSPIFLGSEL,Selects the MPSI modules used for sourcing the CQFLAG [11:8]." "0: Selects MPSI0 as source of signals used in..,1: Selects MPSI1 as source of signals used in..,2: Selects MPSI2 as source of signals used in..,?"
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bitfld.long 0x28 1. "CQPRI,Sets the Priority of the command queue dma request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x28 0. "CQEN,Command queue enable. When set will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled" "0: Disable CQ Function,1: Enable CQ Function"
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line.long 0x2C "CQADDR,The SRAM address which will be fetched next execution of the CQ operation. This register is updated as the CQ operation progresses. and is the live version of the register. The register can also be"
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hexmask.long 0x2C 2.--28. 1. "CQADDR,Bits 28:2 of target byte address for source of CQ . The buffer must be aligned on a word boundary"
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line.long 0x30 "CQSTAT,Provides the status of the command queue operation. If the command queue is disabled. these bits will be cleared. The bits are read only"
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bitfld.long 0x30 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
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bitfld.long 0x30 1. "CQPAUSED,Command queue operation is currently paused." "0,1"
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bitfld.long 0x30 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
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line.long 0x34 "CQFLAGS,Command Queue Flag"
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hexmask.long.word 0x34 16.--31. 1. "CQIRQMASK,Mask the bits used to generate the command queue interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE"
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hexmask.long.word 0x34 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
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line.long 0x38 "CQSETCLEAR,Set/Clear the command queue software pause flags on a per-bit basis. Contains 3 fields. allowing for setting. clearing or toggling the value in the software flags. Priority when the same bit"
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hexmask.long.byte 0x38 16.--23. 1. "CQFCLR,Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x38 8.--15. 1. "CQFTGL,Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x38 0.--7. 1. "CQFSET,Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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line.long 0x3C "CQPAUSEEN,Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the CQFLAG register is '1'. CQ processing will halt until either value is changed to '0'."
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hexmask.long.word 0x3C 0.--15. 1. "CQPEN,Enables the specified event to pause command processing when active"
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line.long 0x40 "CQCURIDX,Current index value. targeted to be written by register write operations within the command queue. This is compared to the CQENDIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and"
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hexmask.long.byte 0x40 0.--7. 1. "CQCURIDX,Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x44 "CQENDIDX,End index value. targeted to be written by software to indicate the last valid register pair contained within the command queue. rgister write operations within the command queue."
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hexmask.long.byte 0x44 0.--7. 1. "CQENDIDX,Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x48 "STATUS,IOM Module Status"
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bitfld.long 0x48 2. "IDLEST,indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to holdoffs from data availability or as the command gets propagated into the logic from the registers." "?,1: The I/O state machine is in the idle state."
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bitfld.long 0x48 1. "CMDACT,Indicates if the active I/O Command is currently processing a transaction or command is complete but the FIFO pointers are still syncronizing internally. This bit will go high at" "?,1: An I/O command is active. Indicates the active.."
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bitfld.long 0x48 0. "ERR,Bit has been deprecated. Please refer to the other error indicators. This will always return 0." "?,1: Bit has been deprecated and will always return 0."
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group.long 0x280++0x3
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line.long 0x0 "MSPICFG,Controls the configuration of the SPI master module. including POL/PHA. LSB. flow control. and delays for MISO and MOSI"
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bitfld.long 0x0 30. "MSPIRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 27.--29. "DOUTDLY,Delay tap to use for the output signal (MOSI). This give more hold time on the output data" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 24.--26. "DINDLY,Delay tap to use for the input signal (MISO). This gives more hold time on the input data." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "SPILSB,Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first." "0: Send and receive MSB bit first,1: Send and receive LSB bit first"
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bitfld.long 0x0 22. "RDFCPOL,Selects the read flow control signal polarity." "0: Flow control signal high creates flow control.,1: Flow control signal low creates flow control."
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bitfld.long 0x0 21. "WTFCPOL,selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 will allow a IRQ=1 to pause transfers)." "0: Flow control signal high(1) creates flow control..,1: Flow control signal low(0) creates flow control.."
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bitfld.long 0x0 20. "WTFCIRQ,Selects the write mode flow control signal." "0: MISO is used as the write mode flow control..,1: IRQ is used as the write mode flow control signal."
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bitfld.long 0x0 18. "MOSIINV,Inverts MOSI when flow control is enabled." "0: MOSI is set to 0 in read mode and 1 in write mode.,1: MOSI is set to 1 in read mode and 0 in write mode."
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bitfld.long 0x0 17. "RDFC,Enables read mode flow control." "0: Read mode flow control disabled.,1: Read mode flow control enabled."
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bitfld.long 0x0 16. "WTFC,enables write mode flow control." "0: Write mode flow control disabled.,1: Write mode flow control enabled."
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bitfld.long 0x0 2. "FULLDUP,Enables full duplex mode for Master SPI write operations. Data will be captured simultaneously into the read fifo" "0,1"
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bitfld.long 0x0 1. "SPHA,Selects SPI phase.IMPORTANT NOTICE: Due to the susceptibility of creating a clock glitch which could cause register corruption changing SPHA and SPOL bits should be done in separate writes to this register." "0: Sample on the leading (first) clock edge.,1: Sample on the trailing (second) clock edge."
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newline
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bitfld.long 0x0 0. "SPOL,Selects SPI polarity.IMPORTANT NOTICE: Due to the susceptibility of creating a clock glitch which could cause register corruption changing SPHA and SPOL bits should be done in separate writes to this register." "0: The base value of the clock is 0.,1: The base value of the clock is 1."
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group.long 0x2C0++0x7
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line.long 0x0 "MI2CCFG,Controls the configuration of the I2C bus master."
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bitfld.long 0x0 24. "STRDIS,Disable detection of clock stretch events smaller than 1 cycle" "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "SMPCNT,Number of Base clk cycles to wait before sampling the SCL clock to determine if a clock stretch event has occured"
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hexmask.long.byte 0x0 12.--15. 1. "SDAENDLY,Number of IOCLK cycles to delay the SDA output en (all transitions affected). Used to delay data relative to clock"
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hexmask.long.byte 0x0 8.--11. 1. "SCLENDLY,Number of IOCLK cycles to delay the rising edge of the SCL output en (clock will go low on this edge). Used to allow clock shaping."
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bitfld.long 0x0 6. "MI2CRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 4.--5. "SDADLY,Delay to enable on the SDA output. Values are 0x0-0x3." "0,1,2,3"
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newline
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bitfld.long 0x0 2. "ARBEN,Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master this function can be disabled to save clock cycles on I2C transactions" "0: Disable multi-master bus arbitration support for..,1: Enable multi-master bus arbitration support for.."
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bitfld.long 0x0 1. "I2CLSB,Direction of data transmit and receive MSB(0) or LSB(1) first. Default per I2C specification is MSB first. This applies to both read and write data and read data will be bit" "0: Byte data is transmitted MSB first onto the..,1: Byte data is transmitted LSB first onto the.."
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newline
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bitfld.long 0x0 0. "ADDRSZ,Sets the I2C master device address size to either 7b (0) or 10b (1)." "0: Use 7b addressing for I2C master transactions,1: Use 10b addressing for I2C master transactions"
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line.long 0x4 "DEVCFG,Contains the I2C device address."
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hexmask.long.word 0x4 0.--9. 1. "DEVADDR,I2C address of the device that the Master will use to target for read/write operations. This can be either a 7b or 10b address."
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group.long 0x388++0x3
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line.long 0x0 "IOMDBG,Debug control"
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hexmask.long 0x0 3.--31. 1. "DBGDATA,Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers."
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bitfld.long 0x0 2. "APBCLKON,APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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bitfld.long 0x0 1. "IOCLKON,IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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bitfld.long 0x0 0. "DBGEN,Debug Enable. Setting bit will enable the update of data within this register otherwise it is clock gated for power savings" "0,1"
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tree.end
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endif
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sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
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tree "IOM2"
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base ad:0x40052000
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group.long 0x0++0x3
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line.long 0x0 "FIFO,Provides direct random access to both input and output fifos. The state of the FIFO is not distured by reading these locations (ie no POP will be done). FIFO0 is accessible from addresses 0x0 - 0x1C. and is used for data outuput from the IOM to.."
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hexmask.long 0x0 0.--31. 1. "FIFO,FIFO direct access. Only locations 0 - 3F will return valid information."
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group.long 0x100++0x2F
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line.long 0x0 "FIFOPTR,Provides the current valid byte count of data within the FIFO as seen from the internal state machines. FIFO0 is dedicated to outgoing transactions and FIFO1 is dedicated to incoming transactions. All counts are specified in units of bytes."
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hexmask.long.byte 0x0 24.--31. 1. "FIFO1REM,The number of remaining data bytes slots currently in FIFO 1 (written by interface read by MCU)"
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hexmask.long.byte 0x0 16.--23. 1. "FIFO1SIZ,The number of valid data bytes currently in FIFO 1 (written by interface read by MCU)"
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hexmask.long.byte 0x0 8.--15. 1. "FIFO0REM,The number of remaining data bytes slots currently in FIFO 0 (written by MCU read by interface)"
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hexmask.long.byte 0x0 0.--7. 1. "FIFO0SIZ,The number of valid data bytes currently in the FIFO 0 (written by MCU read by interface)"
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line.long 0x4 "FIFOTHR,Sets the threshold values for incoming and outgoing transactions. The threshold values are used to assert the interrupt if enabled. and also used during DMA to set the transfer size as a result of DMATHR trigger."
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hexmask.long.byte 0x4 8.--13. 1. "FIFOWTHR,FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the write fifo contains FIFOWTHR free bytes as.."
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hexmask.long.byte 0x4 0.--5. 1. "FIFORTHR,FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the read fifo contains FIFORTHR valid bytes of data as.."
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line.long 0x8 "FIFOPOP,Will advance the internal read pointer of the incoming FIFO (FIFO1) when read. if POPWR is not active. If POPWR is active. a write to this register is needed to advance the internal FIFO pointer."
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hexmask.long 0x8 0.--31. 1. "FIFODOUT,This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0) the fifo read pointer will be advanced by one word as a result of the read."
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line.long 0xC "FIFOPUSH,Will write new data into the outgoing FIFO and advance the internal write pointer."
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hexmask.long 0xC 0.--31. 1. "FIFODIN,This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes)."
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line.long 0x10 "FIFOCTRL,Provides controls for the operation of the internal FIFOs. Contains fields used to control the operation of the POP register. and also controls to reset the internal pointers of the FIFOs."
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bitfld.long 0x10 1. "FIFORSTN,Active low manual reset of the fifo. Write to 0 to reset fifo and then write to 1 to remove the reset." "0,1"
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bitfld.long 0x10 0. "POPWR,Selects the mode in which 'pop' events are done for the fifo read operations. A value of '1' will prevent a pop event on a read operation and will require a write to the FIFOPOP register to create a pop event." "0,1"
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line.long 0x14 "FIFOLOC,Provides a read only value of the current read and write pointers. This register is read only and can be used alogn with the FIFO direct access method to determine the next data to be used for input and output functions."
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hexmask.long.byte 0x14 8.--11. 1. "FIFORPTR,Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1) which is used to store read data returned from external devices during a read operation."
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hexmask.long.byte 0x14 0.--3. 1. "FIFOWPTR,Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0) which is used during write operations to external devices."
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line.long 0x18 "CLKCFG,Provides clock related controls used internal to the BLEIF module. and enablement of 32KHz clock to the BLE Core module. The internal clock sourced is selected via the FSEL and can be further divided by 3 using the DIV3 control."
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hexmask.long.byte 0x18 24.--31. 1. "TOTPER,Clock total clock count minus 1. This provides the total period of the divided clock -1 when the DIVEN is active. The"
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hexmask.long.byte 0x18 16.--23. 1. "LOWPER,Clock low clock count minus 1. This provides the number of clocks the divided clock will be low when the DIVEN = 1."
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newline
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bitfld.long 0x18 12. "DIVEN,Enable clock division by TOTPER and LOWPER" "0: Disable TOTPER division.,1: Enable TOTPER division."
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bitfld.long 0x18 11. "DIV3,Enable divide by 3 of the source IOCLK. Division by 3 is done before the DIVEN programmable divider and if enabled" "0: Select divide by 1.,1: Select divide by 3."
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newline
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bitfld.long 0x18 8.--10. "FSEL,Select the input clock frequency." "0: Selects the minimum power clock. This setting..,1: Selects static 0 as the input clock. Previously..,2: Selects the HFRC 48MHz as the input clock.,3: Selects the HFRC 24MHz as the input clock.,4: Selects the HFRC 12MHz as the input clock.,5: Selects the HFRC 6MHz as the input clock.,6: Selects the HFRC 3MHz as the input clock.,7: Selects the HFRC 1.5MHz as the input clock."
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bitfld.long 0x18 0. "IOCLKEN,Enable for the interface clock. Must be enabled prior to executing any IO operations." "0,1"
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line.long 0x1C "SUBMODCTRL,Provides enable for each submodule. Only a sigle submodule can be enabled at one time."
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bitfld.long 0x1C 9.--11. "SMOD2TYPE,Submodule 2 module type. This is the I2S Master/Slave interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,4: Master/Slave submodule,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 8. "SMOD2EN,Submodule 2 enable (1) or disable (0)" "0,1"
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bitfld.long 0x1C 5.--7. "SMOD1TYPE,Submodule 1 module type. This is the I2C Master interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,4: Master/Slave submodule,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 4. "SMOD1EN,Submodule 1 enable (1) or disable (0)" "0,1"
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bitfld.long 0x1C 1.--3. "SMOD0TYPE,Submodule 0 module type. This is the SPI Master interface." "0: MSPI submodule,1: I2C Master submodule,2: I2S Master/Slave Module,?,?,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 0. "SMOD0EN,Submodule 0 enable (1) or disable (0)" "0,1"
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line.long 0x20 "CMD,Writes to this register will start an IO transaction. as well as set various parameters for the command itself. Reads will return the command value written to the CMD register."
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hexmask.long.byte 0x20 24.--31. 1. "OFFSETLO,This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command."
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bitfld.long 0x20 20.--21. "CMDSEL,Command Specific selection information. Not used in Master I2C. Used as CEn select for Master SPI transactions" "0,1,2,3"
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hexmask.long.word 0x20 8.--19. 1. "TSIZE,Defines the transaction size in bytes. The offset transfer is not included in this size."
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bitfld.long 0x20 7. "CONT,Contine to hold the bus after the current transaction if set to a 1 with a new command issued." "0,1"
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bitfld.long 0x20 4.--6. "OFFSETCNT,Number of offset bytes to use for the command - 0 1 2 3 4 5 are valid selections. The second (byte 1) third (byte 2) and forth (byte 3) are read from the OFFSETHI register and the low order byte is pulled from this register in the.." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x20 0.--3. 1. "CMD,Command for submodule."
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line.long 0x24 "DCXCTRL,Enables transmission of DCX signal with SPI transactions and selects which CE signals will be used to transmit the DCX signal."
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bitfld.long 0x24 4. "DCXEN,Global enable of the DCX function. Setting to 1 will enable the generation of the DCX signal which will assert when sending the offset bytes of the SPI transaction." "0,1"
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hexmask.long.byte 0x24 0.--3. 1. "DCXSEL,Selects the CE channel used to convey the DCX function. The select is bitwise encoded with bit 0 = 1 enabling CE0 for DCX transmission bit 1 = 1 enableing CE1 for DCX transmission etc. If the CE used for the SPI transaction is set it will be.."
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line.long 0x28 "OFFSETHI,High order bytes of offset for IO transaction"
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hexmask.long 0x28 0.--31. 1. "OFFSETHI,Holds the high order bytes of the byte addressing/offset field to use with IO commands. The number of offset bytes to use is specified in the command register"
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line.long 0x2C "CMDSTAT,Provides staus on the execution of the command currently in progress. The fields in this register will reflect the real time status of the internal state machines and data transfers within the IOM."
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hexmask.long.word 0x2C 8.--19. 1. "CTSIZE,The current number of bytes still to be transferred with this command. This field will count down to zero."
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bitfld.long 0x2C 5.--7. "CMDSTAT,The current status of the command execution." "?,1: Error encountered with command,2: Actively processing command,?,4: Idle state no active command no error,?,6: Command in progress but waiting on data from host,?"
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hexmask.long.byte 0x2C 0.--4. 1. "CCMD,Current command that is being executed; This will update based on the phase of the I2C and will indicate a write operation during transmission of the offset "
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group.long 0x200++0x4B
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line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
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bitfld.long 0x0 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x0 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x0 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x0 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x0 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x0 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. Also asserted during I2C write operations when value of 1 expected on bus but 0 is observed. When asserted the I2C state machine will.." "0,1"
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bitfld.long 0x0 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x0 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x0 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x0 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x0 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x0 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0x0 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0x0 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x0 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
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bitfld.long 0x4 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x4 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x4 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x4 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x4 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x4 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. Also asserted during I2C write operations when value of 1 expected on bus but 0 is observed. When asserted the I2C state machine will.." "0,1"
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bitfld.long 0x4 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x4 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x4 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x4 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x4 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x4 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0x4 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0x4 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x4 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
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bitfld.long 0x8 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x8 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x8 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x8 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x8 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x8 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. Also asserted during I2C write operations when value of 1 expected on bus but 0 is observed. When asserted the I2C state machine will.." "0,1"
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bitfld.long 0x8 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x8 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x8 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x8 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x8 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x8 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0x8 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0x8 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x8 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
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bitfld.long 0xC 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0xC 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0xC 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0xC 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0xC 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0xC 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. Also asserted during I2C write operations when value of 1 expected on bus but 0 is observed. When asserted the I2C state machine will.." "0,1"
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bitfld.long 0xC 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0xC 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0xC 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0xC 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0xC 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0xC 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0xC 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0xC 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0xC 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x10 "DMATRIGEN,Provides control on which event will trigger the DMA transfer after the DMA operation is setup and enabled. The trigger event will cause a number of bytes (depending on trigger event) to be"
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bitfld.long 0x10 1. "DTHREN,Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes) the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO and will transfer (WTHR/4) number of words" "0,1"
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bitfld.long 0x10 0. "DCMDCMPEN,Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered the number of words transferred will be the lesser of the remaining TOTCOUNT bytes or" "0,1"
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line.long 0x14 "DMATRIGSTAT,Provides the status of trigger events that have occurred for the transaction. Some of the bits are read only and some can be reset via a write of 0."
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bitfld.long 0x14 2. "DTOTCMP,DMA triggered when DCMDCMP = 0 and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is" "0,1"
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bitfld.long 0x14 1. "DTHR,Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA." "0,1"
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bitfld.long 0x14 0. "DCMDCMP,Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA." "0,1"
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line.long 0x18 "DMACFG,Configuration control of the DMA process. including the direction of DMA. and enablement of DMA"
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bitfld.long 0x18 9. "DPWROFF,Power off module after DMA is complete. If this bit is active the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain power down will not be performed." "0: Power off disabled,1: Power off enabled"
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bitfld.long 0x18 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x18 1. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction. To be..,1: Memory to Peripheral transaction. To be set when.."
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bitfld.long 0x18 0. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable DMA Function,1: Enable DMA Function"
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line.long 0x1C "DMATOTCOUNT,Contains the number of bytes to be transferred for this DMA transaction. This register is decremented as the data is transferred. and will be 0 at the completion of the DMA operation."
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hexmask.long.word 0x1C 0.--11. 1. "TOTCOUNT,Triggered DMA from Command complete event occured. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."
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line.long 0x20 "DMATARGADDR,The source or destination address internal the SRAM for the DMA data. For write operations. this can only be SRAM data (ADDR bit 28 = 1); For read operations. this can ve either SRAM or FLASH (ADDR bit 28 = 0)"
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hexmask.long 0x20 0.--28. 1. "TARGADDR,Bits [28:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment and does not have to be word aligned. In cases of non-word aligned addresses the DMA logic will take care for ensuring only.."
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line.long 0x24 "DMASTAT,Status of the DMA operation currently in progress."
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bitfld.long 0x24 2. "DMAERR,DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set this bit will remain set until cleared by software." "0,1"
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bitfld.long 0x24 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0 and will also be cleared when a new DMA is started." "0,1"
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newline
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bitfld.long 0x24 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
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line.long 0x28 "CQCFG,Controls parameters and options for execution of the command queue operation. To enable command queue. create this in memory. set the address. and enable it with a write to CQEN"
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bitfld.long 0x28 2.--3. "MSPIFLGSEL,Selects the MPSI modules used for sourcing the CQFLAG [11:8]." "0: Selects MPSI0 as source of signals used in..,1: Selects MPSI1 as source of signals used in..,2: Selects MPSI2 as source of signals used in..,?"
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bitfld.long 0x28 1. "CQPRI,Sets the Priority of the command queue dma request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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newline
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bitfld.long 0x28 0. "CQEN,Command queue enable. When set will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled" "0: Disable CQ Function,1: Enable CQ Function"
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line.long 0x2C "CQADDR,The SRAM address which will be fetched next execution of the CQ operation. This register is updated as the CQ operation progresses. and is the live version of the register. The register can also be"
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hexmask.long 0x2C 2.--28. 1. "CQADDR,Bits 28:2 of target byte address for source of CQ . The buffer must be aligned on a word boundary"
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line.long 0x30 "CQSTAT,Provides the status of the command queue operation. If the command queue is disabled. these bits will be cleared. The bits are read only"
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bitfld.long 0x30 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
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bitfld.long 0x30 1. "CQPAUSED,Command queue operation is currently paused." "0,1"
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bitfld.long 0x30 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
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line.long 0x34 "CQFLAGS,Command Queue Flag"
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hexmask.long.word 0x34 16.--31. 1. "CQIRQMASK,Mask the bits used to generate the command queue interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE"
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hexmask.long.word 0x34 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
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line.long 0x38 "CQSETCLEAR,Set/Clear the command queue software pause flags on a per-bit basis. Contains 3 fields. allowing for setting. clearing or toggling the value in the software flags. Priority when the same bit"
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hexmask.long.byte 0x38 16.--23. 1. "CQFCLR,Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x38 8.--15. 1. "CQFTGL,Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x38 0.--7. 1. "CQFSET,Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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line.long 0x3C "CQPAUSEEN,Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the CQFLAG register is '1'. CQ processing will halt until either value is changed to '0'."
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hexmask.long.word 0x3C 0.--15. 1. "CQPEN,Enables the specified event to pause command processing when active"
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line.long 0x40 "CQCURIDX,Current index value. targeted to be written by register write operations within the command queue. This is compared to the CQENDIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and"
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hexmask.long.byte 0x40 0.--7. 1. "CQCURIDX,Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x44 "CQENDIDX,End index value. targeted to be written by software to indicate the last valid register pair contained within the command queue. rgister write operations within the command queue."
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hexmask.long.byte 0x44 0.--7. 1. "CQENDIDX,Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x48 "STATUS,IOM Module Status"
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bitfld.long 0x48 2. "IDLEST,indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to holdoffs from data availability or as the command gets propagated into the logic from the registers." "?,1: The I/O state machine is in the idle state."
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bitfld.long 0x48 1. "CMDACT,Indicates if the active I/O Command is currently processing a transaction or command is complete but the FIFO pointers are still syncronizing internally. This bit will go high at" "?,1: An I/O command is active. Indicates the active.."
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bitfld.long 0x48 0. "ERR,Bit has been deprecated. Please refer to the other error indicators. This will always return 0." "?,1: Bit has been deprecated and will always return 0."
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group.long 0x280++0x3
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line.long 0x0 "MSPICFG,Controls the configuration of the SPI master module. including POL/PHA. LSB. flow control. and delays for MISO and MOSI"
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bitfld.long 0x0 30. "MSPIRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 27.--29. "DOUTDLY,Delay tap to use for the output signal (MOSI). This give more hold time on the output data" "0,1,2,3,4,5,6,7"
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|
newline
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bitfld.long 0x0 24.--26. "DINDLY,Delay tap to use for the input signal (MISO). This gives more hold time on the input data." "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x0 23. "SPILSB,Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first." "0: Send and receive MSB bit first,1: Send and receive LSB bit first"
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|
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bitfld.long 0x0 22. "RDFCPOL,Selects the read flow control signal polarity." "0: Flow control signal high creates flow control.,1: Flow control signal low creates flow control."
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|
bitfld.long 0x0 21. "WTFCPOL,selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 will allow a IRQ=1 to pause transfers)." "0: Flow control signal high(1) creates flow control..,1: Flow control signal low(0) creates flow control.."
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bitfld.long 0x0 20. "WTFCIRQ,Selects the write mode flow control signal." "0: MISO is used as the write mode flow control..,1: IRQ is used as the write mode flow control signal."
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bitfld.long 0x0 18. "MOSIINV,Inverts MOSI when flow control is enabled." "0: MOSI is set to 0 in read mode and 1 in write mode.,1: MOSI is set to 1 in read mode and 0 in write mode."
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|
newline
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bitfld.long 0x0 17. "RDFC,Enables read mode flow control." "0: Read mode flow control disabled.,1: Read mode flow control enabled."
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|
bitfld.long 0x0 16. "WTFC,enables write mode flow control." "0: Write mode flow control disabled.,1: Write mode flow control enabled."
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|
newline
|
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bitfld.long 0x0 2. "FULLDUP,Enables full duplex mode for Master SPI write operations. Data will be captured simultaneously into the read fifo" "0,1"
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|
bitfld.long 0x0 1. "SPHA,Selects SPI phase.IMPORTANT NOTICE: Due to the susceptibility of creating a clock glitch which could cause register corruption changing SPHA and SPOL bits should be done in separate writes to this register." "0: Sample on the leading (first) clock edge.,1: Sample on the trailing (second) clock edge."
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|
newline
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bitfld.long 0x0 0. "SPOL,Selects SPI polarity.IMPORTANT NOTICE: Due to the susceptibility of creating a clock glitch which could cause register corruption changing SPHA and SPOL bits should be done in separate writes to this register." "0: The base value of the clock is 0.,1: The base value of the clock is 1."
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|
group.long 0x2C0++0x7
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|
line.long 0x0 "MI2CCFG,Controls the configuration of the I2C bus master."
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|
bitfld.long 0x0 24. "STRDIS,Disable detection of clock stretch events smaller than 1 cycle" "0,1"
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|
hexmask.long.byte 0x0 16.--23. 1. "SMPCNT,Number of Base clk cycles to wait before sampling the SCL clock to determine if a clock stretch event has occured"
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|
newline
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hexmask.long.byte 0x0 12.--15. 1. "SDAENDLY,Number of IOCLK cycles to delay the SDA output en (all transitions affected). Used to delay data relative to clock"
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|
hexmask.long.byte 0x0 8.--11. 1. "SCLENDLY,Number of IOCLK cycles to delay the rising edge of the SCL output en (clock will go low on this edge). Used to allow clock shaping."
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|
newline
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bitfld.long 0x0 6. "MI2CRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 4.--5. "SDADLY,Delay to enable on the SDA output. Values are 0x0-0x3." "0,1,2,3"
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newline
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bitfld.long 0x0 2. "ARBEN,Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master this function can be disabled to save clock cycles on I2C transactions" "0: Disable multi-master bus arbitration support for..,1: Enable multi-master bus arbitration support for.."
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bitfld.long 0x0 1. "I2CLSB,Direction of data transmit and receive MSB(0) or LSB(1) first. Default per I2C specification is MSB first. This applies to both read and write data and read data will be bit" "0: Byte data is transmitted MSB first onto the..,1: Byte data is transmitted LSB first onto the.."
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newline
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bitfld.long 0x0 0. "ADDRSZ,Sets the I2C master device address size to either 7b (0) or 10b (1)." "0: Use 7b addressing for I2C master transactions,1: Use 10b addressing for I2C master transactions"
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line.long 0x4 "DEVCFG,Contains the I2C device address."
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hexmask.long.word 0x4 0.--9. 1. "DEVADDR,I2C address of the device that the Master will use to target for read/write operations. This can be either a 7b or 10b address."
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group.long 0x388++0x3
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line.long 0x0 "IOMDBG,Debug control"
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hexmask.long 0x0 3.--31. 1. "DBGDATA,Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers."
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bitfld.long 0x0 2. "APBCLKON,APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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newline
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bitfld.long 0x0 1. "IOCLKON,IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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bitfld.long 0x0 0. "DBGEN,Debug Enable. Setting bit will enable the update of data within this register otherwise it is clock gated for power savings" "0,1"
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|
tree.end
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
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|
tree "IOM3"
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|
base ad:0x40053000
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group.long 0x0++0x3
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line.long 0x0 "FIFO,Provides direct random access to both input and output fifos. The state of the FIFO is not distured by reading these locations (ie no POP will be done). FIFO0 is accessible from addresses 0x0 - 0x1C. and is used for data outuput from the IOM to.."
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|
hexmask.long 0x0 0.--31. 1. "FIFO,FIFO direct access. Only locations 0 - 3F will return valid information."
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group.long 0x100++0x2F
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line.long 0x0 "FIFOPTR,Provides the current valid byte count of data within the FIFO as seen from the internal state machines. FIFO0 is dedicated to outgoing transactions and FIFO1 is dedicated to incoming transactions. All counts are specified in units of bytes."
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hexmask.long.byte 0x0 24.--31. 1. "FIFO1REM,The number of remaining data bytes slots currently in FIFO 1 (written by interface read by MCU)"
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hexmask.long.byte 0x0 16.--23. 1. "FIFO1SIZ,The number of valid data bytes currently in FIFO 1 (written by interface read by MCU)"
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|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "FIFO0REM,The number of remaining data bytes slots currently in FIFO 0 (written by MCU read by interface)"
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hexmask.long.byte 0x0 0.--7. 1. "FIFO0SIZ,The number of valid data bytes currently in the FIFO 0 (written by MCU read by interface)"
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line.long 0x4 "FIFOTHR,Sets the threshold values for incoming and outgoing transactions. The threshold values are used to assert the interrupt if enabled. and also used during DMA to set the transfer size as a result of DMATHR trigger."
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hexmask.long.byte 0x4 8.--13. 1. "FIFOWTHR,FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the write fifo contains FIFOWTHR free bytes as.."
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|
hexmask.long.byte 0x4 0.--5. 1. "FIFORTHR,FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the read fifo contains FIFORTHR valid bytes of data as.."
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|
line.long 0x8 "FIFOPOP,Will advance the internal read pointer of the incoming FIFO (FIFO1) when read. if POPWR is not active. If POPWR is active. a write to this register is needed to advance the internal FIFO pointer."
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hexmask.long 0x8 0.--31. 1. "FIFODOUT,This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0) the fifo read pointer will be advanced by one word as a result of the read."
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|
line.long 0xC "FIFOPUSH,Will write new data into the outgoing FIFO and advance the internal write pointer."
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|
hexmask.long 0xC 0.--31. 1. "FIFODIN,This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes)."
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line.long 0x10 "FIFOCTRL,Provides controls for the operation of the internal FIFOs. Contains fields used to control the operation of the POP register. and also controls to reset the internal pointers of the FIFOs."
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|
bitfld.long 0x10 1. "FIFORSTN,Active low manual reset of the fifo. Write to 0 to reset fifo and then write to 1 to remove the reset." "0,1"
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|
bitfld.long 0x10 0. "POPWR,Selects the mode in which 'pop' events are done for the fifo read operations. A value of '1' will prevent a pop event on a read operation and will require a write to the FIFOPOP register to create a pop event." "0,1"
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|
line.long 0x14 "FIFOLOC,Provides a read only value of the current read and write pointers. This register is read only and can be used alogn with the FIFO direct access method to determine the next data to be used for input and output functions."
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hexmask.long.byte 0x14 8.--11. 1. "FIFORPTR,Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1) which is used to store read data returned from external devices during a read operation."
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hexmask.long.byte 0x14 0.--3. 1. "FIFOWPTR,Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0) which is used during write operations to external devices."
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|
line.long 0x18 "CLKCFG,Provides clock related controls used internal to the BLEIF module. and enablement of 32KHz clock to the BLE Core module. The internal clock sourced is selected via the FSEL and can be further divided by 3 using the DIV3 control."
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|
hexmask.long.byte 0x18 24.--31. 1. "TOTPER,Clock total clock count minus 1. This provides the total period of the divided clock -1 when the DIVEN is active. The"
|
|
hexmask.long.byte 0x18 16.--23. 1. "LOWPER,Clock low clock count minus 1. This provides the number of clocks the divided clock will be low when the DIVEN = 1."
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|
newline
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bitfld.long 0x18 12. "DIVEN,Enable clock division by TOTPER and LOWPER" "0: Disable TOTPER division.,1: Enable TOTPER division."
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|
bitfld.long 0x18 11. "DIV3,Enable divide by 3 of the source IOCLK. Division by 3 is done before the DIVEN programmable divider and if enabled" "0: Select divide by 1.,1: Select divide by 3."
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newline
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bitfld.long 0x18 8.--10. "FSEL,Select the input clock frequency." "0: Selects the minimum power clock. This setting..,1: Selects static 0 as the input clock. Previously..,2: Selects the HFRC 48MHz as the input clock.,3: Selects the HFRC 24MHz as the input clock.,4: Selects the HFRC 12MHz as the input clock.,5: Selects the HFRC 6MHz as the input clock.,6: Selects the HFRC 3MHz as the input clock.,7: Selects the HFRC 1.5MHz as the input clock."
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bitfld.long 0x18 0. "IOCLKEN,Enable for the interface clock. Must be enabled prior to executing any IO operations." "0,1"
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|
line.long 0x1C "SUBMODCTRL,Provides enable for each submodule. Only a sigle submodule can be enabled at one time."
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|
bitfld.long 0x1C 9.--11. "SMOD2TYPE,Submodule 2 module type. This is the I2S Master/Slave interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,4: Master/Slave submodule,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 8. "SMOD2EN,Submodule 2 enable (1) or disable (0)" "0,1"
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newline
|
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bitfld.long 0x1C 5.--7. "SMOD1TYPE,Submodule 1 module type. This is the I2C Master interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,4: Master/Slave submodule,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 4. "SMOD1EN,Submodule 1 enable (1) or disable (0)" "0,1"
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|
newline
|
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bitfld.long 0x1C 1.--3. "SMOD0TYPE,Submodule 0 module type. This is the SPI Master interface." "0: MSPI submodule,1: I2C Master submodule,2: I2S Master/Slave Module,?,?,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 0. "SMOD0EN,Submodule 0 enable (1) or disable (0)" "0,1"
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|
line.long 0x20 "CMD,Writes to this register will start an IO transaction. as well as set various parameters for the command itself. Reads will return the command value written to the CMD register."
|
|
hexmask.long.byte 0x20 24.--31. 1. "OFFSETLO,This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command."
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bitfld.long 0x20 20.--21. "CMDSEL,Command Specific selection information. Not used in Master I2C. Used as CEn select for Master SPI transactions" "0,1,2,3"
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|
newline
|
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hexmask.long.word 0x20 8.--19. 1. "TSIZE,Defines the transaction size in bytes. The offset transfer is not included in this size."
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|
bitfld.long 0x20 7. "CONT,Contine to hold the bus after the current transaction if set to a 1 with a new command issued." "0,1"
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|
newline
|
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bitfld.long 0x20 4.--6. "OFFSETCNT,Number of offset bytes to use for the command - 0 1 2 3 4 5 are valid selections. The second (byte 1) third (byte 2) and forth (byte 3) are read from the OFFSETHI register and the low order byte is pulled from this register in the.." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x20 0.--3. 1. "CMD,Command for submodule."
|
|
line.long 0x24 "DCXCTRL,Enables transmission of DCX signal with SPI transactions and selects which CE signals will be used to transmit the DCX signal."
|
|
bitfld.long 0x24 4. "DCXEN,Global enable of the DCX function. Setting to 1 will enable the generation of the DCX signal which will assert when sending the offset bytes of the SPI transaction." "0,1"
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|
hexmask.long.byte 0x24 0.--3. 1. "DCXSEL,Selects the CE channel used to convey the DCX function. The select is bitwise encoded with bit 0 = 1 enabling CE0 for DCX transmission bit 1 = 1 enableing CE1 for DCX transmission etc. If the CE used for the SPI transaction is set it will be.."
|
|
line.long 0x28 "OFFSETHI,High order bytes of offset for IO transaction"
|
|
hexmask.long 0x28 0.--31. 1. "OFFSETHI,Holds the high order bytes of the byte addressing/offset field to use with IO commands. The number of offset bytes to use is specified in the command register"
|
|
line.long 0x2C "CMDSTAT,Provides staus on the execution of the command currently in progress. The fields in this register will reflect the real time status of the internal state machines and data transfers within the IOM."
|
|
hexmask.long.word 0x2C 8.--19. 1. "CTSIZE,The current number of bytes still to be transferred with this command. This field will count down to zero."
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|
bitfld.long 0x2C 5.--7. "CMDSTAT,The current status of the command execution." "?,1: Error encountered with command,2: Actively processing command,?,4: Idle state no active command no error,?,6: Command in progress but waiting on data from host,?"
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|
newline
|
|
hexmask.long.byte 0x2C 0.--4. 1. "CCMD,Current command that is being executed; This will update based on the phase of the I2C and will indicate a write operation during transmission of the offset "
|
|
group.long 0x200++0x4B
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 14. "CQERR,Error during command queue operations" "0,1"
|
|
bitfld.long 0x0 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
|
|
newline
|
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bitfld.long 0x0 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
|
|
bitfld.long 0x0 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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|
newline
|
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bitfld.long 0x0 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0x0 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. Also asserted during I2C write operations when value of 1 expected on bus but 0 is observed. When asserted the I2C state machine will.." "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x0 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x0 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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|
newline
|
|
bitfld.long 0x0 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x0 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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|
newline
|
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bitfld.long 0x0 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
|
|
bitfld.long 0x0 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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|
newline
|
|
bitfld.long 0x0 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 14. "CQERR,Error during command queue operations" "0,1"
|
|
bitfld.long 0x4 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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newline
|
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bitfld.long 0x4 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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|
bitfld.long 0x4 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
newline
|
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bitfld.long 0x4 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0x4 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. Also asserted during I2C write operations when value of 1 expected on bus but 0 is observed. When asserted the I2C state machine will.." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x4 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x4 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0x4 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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|
newline
|
|
bitfld.long 0x4 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
|
|
bitfld.long 0x4 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 14. "CQERR,Error during command queue operations" "0,1"
|
|
bitfld.long 0x8 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
|
|
bitfld.long 0x8 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0x8 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. Also asserted during I2C write operations when value of 1 expected on bus but 0 is observed. When asserted the I2C state machine will.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x8 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x8 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0x8 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
|
|
bitfld.long 0x8 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 14. "CQERR,Error during command queue operations" "0,1"
|
|
bitfld.long 0xC 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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newline
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bitfld.long 0xC 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0xC 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0xC 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0xC 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. Also asserted during I2C write operations when value of 1 expected on bus but 0 is observed. When asserted the I2C state machine will.." "0,1"
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bitfld.long 0xC 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0xC 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0xC 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0xC 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0xC 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0xC 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0xC 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0xC 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0xC 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x10 "DMATRIGEN,Provides control on which event will trigger the DMA transfer after the DMA operation is setup and enabled. The trigger event will cause a number of bytes (depending on trigger event) to be"
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bitfld.long 0x10 1. "DTHREN,Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes) the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO and will transfer (WTHR/4) number of words" "0,1"
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bitfld.long 0x10 0. "DCMDCMPEN,Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered the number of words transferred will be the lesser of the remaining TOTCOUNT bytes or" "0,1"
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line.long 0x14 "DMATRIGSTAT,Provides the status of trigger events that have occurred for the transaction. Some of the bits are read only and some can be reset via a write of 0."
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bitfld.long 0x14 2. "DTOTCMP,DMA triggered when DCMDCMP = 0 and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is" "0,1"
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bitfld.long 0x14 1. "DTHR,Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA." "0,1"
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bitfld.long 0x14 0. "DCMDCMP,Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA." "0,1"
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line.long 0x18 "DMACFG,Configuration control of the DMA process. including the direction of DMA. and enablement of DMA"
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bitfld.long 0x18 9. "DPWROFF,Power off module after DMA is complete. If this bit is active the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain power down will not be performed." "0: Power off disabled,1: Power off enabled"
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bitfld.long 0x18 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x18 1. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction. To be..,1: Memory to Peripheral transaction. To be set when.."
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bitfld.long 0x18 0. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable DMA Function,1: Enable DMA Function"
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line.long 0x1C "DMATOTCOUNT,Contains the number of bytes to be transferred for this DMA transaction. This register is decremented as the data is transferred. and will be 0 at the completion of the DMA operation."
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hexmask.long.word 0x1C 0.--11. 1. "TOTCOUNT,Triggered DMA from Command complete event occured. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."
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line.long 0x20 "DMATARGADDR,The source or destination address internal the SRAM for the DMA data. For write operations. this can only be SRAM data (ADDR bit 28 = 1); For read operations. this can ve either SRAM or FLASH (ADDR bit 28 = 0)"
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hexmask.long 0x20 0.--28. 1. "TARGADDR,Bits [28:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment and does not have to be word aligned. In cases of non-word aligned addresses the DMA logic will take care for ensuring only.."
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line.long 0x24 "DMASTAT,Status of the DMA operation currently in progress."
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bitfld.long 0x24 2. "DMAERR,DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set this bit will remain set until cleared by software." "0,1"
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bitfld.long 0x24 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0 and will also be cleared when a new DMA is started." "0,1"
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bitfld.long 0x24 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
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line.long 0x28 "CQCFG,Controls parameters and options for execution of the command queue operation. To enable command queue. create this in memory. set the address. and enable it with a write to CQEN"
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bitfld.long 0x28 2.--3. "MSPIFLGSEL,Selects the MPSI modules used for sourcing the CQFLAG [11:8]." "0: Selects MPSI0 as source of signals used in..,1: Selects MPSI1 as source of signals used in..,2: Selects MPSI2 as source of signals used in..,?"
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bitfld.long 0x28 1. "CQPRI,Sets the Priority of the command queue dma request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x28 0. "CQEN,Command queue enable. When set will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled" "0: Disable CQ Function,1: Enable CQ Function"
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line.long 0x2C "CQADDR,The SRAM address which will be fetched next execution of the CQ operation. This register is updated as the CQ operation progresses. and is the live version of the register. The register can also be"
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hexmask.long 0x2C 2.--28. 1. "CQADDR,Bits 28:2 of target byte address for source of CQ . The buffer must be aligned on a word boundary"
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line.long 0x30 "CQSTAT,Provides the status of the command queue operation. If the command queue is disabled. these bits will be cleared. The bits are read only"
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bitfld.long 0x30 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
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bitfld.long 0x30 1. "CQPAUSED,Command queue operation is currently paused." "0,1"
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bitfld.long 0x30 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
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line.long 0x34 "CQFLAGS,Command Queue Flag"
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hexmask.long.word 0x34 16.--31. 1. "CQIRQMASK,Mask the bits used to generate the command queue interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE"
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hexmask.long.word 0x34 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
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line.long 0x38 "CQSETCLEAR,Set/Clear the command queue software pause flags on a per-bit basis. Contains 3 fields. allowing for setting. clearing or toggling the value in the software flags. Priority when the same bit"
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hexmask.long.byte 0x38 16.--23. 1. "CQFCLR,Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x38 8.--15. 1. "CQFTGL,Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x38 0.--7. 1. "CQFSET,Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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line.long 0x3C "CQPAUSEEN,Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the CQFLAG register is '1'. CQ processing will halt until either value is changed to '0'."
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hexmask.long.word 0x3C 0.--15. 1. "CQPEN,Enables the specified event to pause command processing when active"
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line.long 0x40 "CQCURIDX,Current index value. targeted to be written by register write operations within the command queue. This is compared to the CQENDIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and"
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hexmask.long.byte 0x40 0.--7. 1. "CQCURIDX,Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x44 "CQENDIDX,End index value. targeted to be written by software to indicate the last valid register pair contained within the command queue. rgister write operations within the command queue."
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hexmask.long.byte 0x44 0.--7. 1. "CQENDIDX,Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x48 "STATUS,IOM Module Status"
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bitfld.long 0x48 2. "IDLEST,indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to holdoffs from data availability or as the command gets propagated into the logic from the registers." "?,1: The I/O state machine is in the idle state."
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bitfld.long 0x48 1. "CMDACT,Indicates if the active I/O Command is currently processing a transaction or command is complete but the FIFO pointers are still syncronizing internally. This bit will go high at" "?,1: An I/O command is active. Indicates the active.."
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bitfld.long 0x48 0. "ERR,Bit has been deprecated. Please refer to the other error indicators. This will always return 0." "?,1: Bit has been deprecated and will always return 0."
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group.long 0x280++0x3
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line.long 0x0 "MSPICFG,Controls the configuration of the SPI master module. including POL/PHA. LSB. flow control. and delays for MISO and MOSI"
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bitfld.long 0x0 30. "MSPIRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 27.--29. "DOUTDLY,Delay tap to use for the output signal (MOSI). This give more hold time on the output data" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 24.--26. "DINDLY,Delay tap to use for the input signal (MISO). This gives more hold time on the input data." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "SPILSB,Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first." "0: Send and receive MSB bit first,1: Send and receive LSB bit first"
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bitfld.long 0x0 22. "RDFCPOL,Selects the read flow control signal polarity." "0: Flow control signal high creates flow control.,1: Flow control signal low creates flow control."
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bitfld.long 0x0 21. "WTFCPOL,selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 will allow a IRQ=1 to pause transfers)." "0: Flow control signal high(1) creates flow control..,1: Flow control signal low(0) creates flow control.."
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bitfld.long 0x0 20. "WTFCIRQ,Selects the write mode flow control signal." "0: MISO is used as the write mode flow control..,1: IRQ is used as the write mode flow control signal."
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bitfld.long 0x0 18. "MOSIINV,Inverts MOSI when flow control is enabled." "0: MOSI is set to 0 in read mode and 1 in write mode.,1: MOSI is set to 1 in read mode and 0 in write mode."
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bitfld.long 0x0 17. "RDFC,Enables read mode flow control." "0: Read mode flow control disabled.,1: Read mode flow control enabled."
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bitfld.long 0x0 16. "WTFC,enables write mode flow control." "0: Write mode flow control disabled.,1: Write mode flow control enabled."
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bitfld.long 0x0 2. "FULLDUP,Enables full duplex mode for Master SPI write operations. Data will be captured simultaneously into the read fifo" "0,1"
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bitfld.long 0x0 1. "SPHA,Selects SPI phase.IMPORTANT NOTICE: Due to the susceptibility of creating a clock glitch which could cause register corruption changing SPHA and SPOL bits should be done in separate writes to this register." "0: Sample on the leading (first) clock edge.,1: Sample on the trailing (second) clock edge."
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bitfld.long 0x0 0. "SPOL,Selects SPI polarity.IMPORTANT NOTICE: Due to the susceptibility of creating a clock glitch which could cause register corruption changing SPHA and SPOL bits should be done in separate writes to this register." "0: The base value of the clock is 0.,1: The base value of the clock is 1."
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group.long 0x2C0++0x7
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line.long 0x0 "MI2CCFG,Controls the configuration of the I2C bus master."
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bitfld.long 0x0 24. "STRDIS,Disable detection of clock stretch events smaller than 1 cycle" "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "SMPCNT,Number of Base clk cycles to wait before sampling the SCL clock to determine if a clock stretch event has occured"
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hexmask.long.byte 0x0 12.--15. 1. "SDAENDLY,Number of IOCLK cycles to delay the SDA output en (all transitions affected). Used to delay data relative to clock"
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hexmask.long.byte 0x0 8.--11. 1. "SCLENDLY,Number of IOCLK cycles to delay the rising edge of the SCL output en (clock will go low on this edge). Used to allow clock shaping."
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bitfld.long 0x0 6. "MI2CRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 4.--5. "SDADLY,Delay to enable on the SDA output. Values are 0x0-0x3." "0,1,2,3"
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bitfld.long 0x0 2. "ARBEN,Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master this function can be disabled to save clock cycles on I2C transactions" "0: Disable multi-master bus arbitration support for..,1: Enable multi-master bus arbitration support for.."
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bitfld.long 0x0 1. "I2CLSB,Direction of data transmit and receive MSB(0) or LSB(1) first. Default per I2C specification is MSB first. This applies to both read and write data and read data will be bit" "0: Byte data is transmitted MSB first onto the..,1: Byte data is transmitted LSB first onto the.."
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newline
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bitfld.long 0x0 0. "ADDRSZ,Sets the I2C master device address size to either 7b (0) or 10b (1)." "0: Use 7b addressing for I2C master transactions,1: Use 10b addressing for I2C master transactions"
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line.long 0x4 "DEVCFG,Contains the I2C device address."
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hexmask.long.word 0x4 0.--9. 1. "DEVADDR,I2C address of the device that the Master will use to target for read/write operations. This can be either a 7b or 10b address."
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group.long 0x388++0x3
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line.long 0x0 "IOMDBG,Debug control"
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hexmask.long 0x0 3.--31. 1. "DBGDATA,Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers."
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bitfld.long 0x0 2. "APBCLKON,APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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bitfld.long 0x0 1. "IOCLKON,IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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bitfld.long 0x0 0. "DBGEN,Debug Enable. Setting bit will enable the update of data within this register otherwise it is clock gated for power savings" "0,1"
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tree.end
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endif
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sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
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tree "IOM4"
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base ad:0x40054000
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group.long 0x0++0x3
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line.long 0x0 "FIFO,Provides direct random access to both input and output fifos. The state of the FIFO is not distured by reading these locations (ie no POP will be done). FIFO0 is accessible from addresses 0x0 - 0x1C. and is used for data outuput from the IOM to.."
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hexmask.long 0x0 0.--31. 1. "FIFO,FIFO direct access. Only locations 0 - 3F will return valid information."
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group.long 0x100++0x2F
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line.long 0x0 "FIFOPTR,Provides the current valid byte count of data within the FIFO as seen from the internal state machines. FIFO0 is dedicated to outgoing transactions and FIFO1 is dedicated to incoming transactions. All counts are specified in units of bytes."
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hexmask.long.byte 0x0 24.--31. 1. "FIFO1REM,The number of remaining data bytes slots currently in FIFO 1 (written by interface read by MCU)"
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hexmask.long.byte 0x0 16.--23. 1. "FIFO1SIZ,The number of valid data bytes currently in FIFO 1 (written by interface read by MCU)"
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hexmask.long.byte 0x0 8.--15. 1. "FIFO0REM,The number of remaining data bytes slots currently in FIFO 0 (written by MCU read by interface)"
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hexmask.long.byte 0x0 0.--7. 1. "FIFO0SIZ,The number of valid data bytes currently in the FIFO 0 (written by MCU read by interface)"
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line.long 0x4 "FIFOTHR,Sets the threshold values for incoming and outgoing transactions. The threshold values are used to assert the interrupt if enabled. and also used during DMA to set the transfer size as a result of DMATHR trigger."
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hexmask.long.byte 0x4 8.--13. 1. "FIFOWTHR,FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the write fifo contains FIFOWTHR free bytes as.."
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hexmask.long.byte 0x4 0.--5. 1. "FIFORTHR,FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the read fifo contains FIFORTHR valid bytes of data as.."
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line.long 0x8 "FIFOPOP,Will advance the internal read pointer of the incoming FIFO (FIFO1) when read. if POPWR is not active. If POPWR is active. a write to this register is needed to advance the internal FIFO pointer."
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hexmask.long 0x8 0.--31. 1. "FIFODOUT,This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0) the fifo read pointer will be advanced by one word as a result of the read."
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line.long 0xC "FIFOPUSH,Will write new data into the outgoing FIFO and advance the internal write pointer."
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hexmask.long 0xC 0.--31. 1. "FIFODIN,This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes)."
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line.long 0x10 "FIFOCTRL,Provides controls for the operation of the internal FIFOs. Contains fields used to control the operation of the POP register. and also controls to reset the internal pointers of the FIFOs."
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bitfld.long 0x10 1. "FIFORSTN,Active low manual reset of the fifo. Write to 0 to reset fifo and then write to 1 to remove the reset." "0,1"
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bitfld.long 0x10 0. "POPWR,Selects the mode in which 'pop' events are done for the fifo read operations. A value of '1' will prevent a pop event on a read operation and will require a write to the FIFOPOP register to create a pop event." "0,1"
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line.long 0x14 "FIFOLOC,Provides a read only value of the current read and write pointers. This register is read only and can be used alogn with the FIFO direct access method to determine the next data to be used for input and output functions."
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hexmask.long.byte 0x14 8.--11. 1. "FIFORPTR,Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1) which is used to store read data returned from external devices during a read operation."
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hexmask.long.byte 0x14 0.--3. 1. "FIFOWPTR,Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0) which is used during write operations to external devices."
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line.long 0x18 "CLKCFG,Provides clock related controls used internal to the BLEIF module. and enablement of 32KHz clock to the BLE Core module. The internal clock sourced is selected via the FSEL and can be further divided by 3 using the DIV3 control."
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hexmask.long.byte 0x18 24.--31. 1. "TOTPER,Clock total clock count minus 1. This provides the total period of the divided clock -1 when the DIVEN is active. The"
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hexmask.long.byte 0x18 16.--23. 1. "LOWPER,Clock low clock count minus 1. This provides the number of clocks the divided clock will be low when the DIVEN = 1."
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newline
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bitfld.long 0x18 12. "DIVEN,Enable clock division by TOTPER and LOWPER" "0: Disable TOTPER division.,1: Enable TOTPER division."
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bitfld.long 0x18 11. "DIV3,Enable divide by 3 of the source IOCLK. Division by 3 is done before the DIVEN programmable divider and if enabled" "0: Select divide by 1.,1: Select divide by 3."
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bitfld.long 0x18 8.--10. "FSEL,Select the input clock frequency." "0: Selects the minimum power clock. This setting..,1: Selects static 0 as the input clock. Previously..,2: Selects the HFRC 48MHz as the input clock.,3: Selects the HFRC 24MHz as the input clock.,4: Selects the HFRC 12MHz as the input clock.,5: Selects the HFRC 6MHz as the input clock.,6: Selects the HFRC 3MHz as the input clock.,7: Selects the HFRC 1.5MHz as the input clock."
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bitfld.long 0x18 0. "IOCLKEN,Enable for the interface clock. Must be enabled prior to executing any IO operations." "0,1"
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line.long 0x1C "SUBMODCTRL,Provides enable for each submodule. Only a sigle submodule can be enabled at one time."
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bitfld.long 0x1C 9.--11. "SMOD2TYPE,Submodule 2 module type. This is the I2S Master/Slave interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,4: Master/Slave submodule,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 8. "SMOD2EN,Submodule 2 enable (1) or disable (0)" "0,1"
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bitfld.long 0x1C 5.--7. "SMOD1TYPE,Submodule 1 module type. This is the I2C Master interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,4: Master/Slave submodule,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 4. "SMOD1EN,Submodule 1 enable (1) or disable (0)" "0,1"
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newline
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bitfld.long 0x1C 1.--3. "SMOD0TYPE,Submodule 0 module type. This is the SPI Master interface." "0: MSPI submodule,1: I2C Master submodule,2: I2S Master/Slave Module,?,?,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 0. "SMOD0EN,Submodule 0 enable (1) or disable (0)" "0,1"
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line.long 0x20 "CMD,Writes to this register will start an IO transaction. as well as set various parameters for the command itself. Reads will return the command value written to the CMD register."
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hexmask.long.byte 0x20 24.--31. 1. "OFFSETLO,This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command."
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bitfld.long 0x20 20.--21. "CMDSEL,Command Specific selection information. Not used in Master I2C. Used as CEn select for Master SPI transactions" "0,1,2,3"
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hexmask.long.word 0x20 8.--19. 1. "TSIZE,Defines the transaction size in bytes. The offset transfer is not included in this size."
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bitfld.long 0x20 7. "CONT,Contine to hold the bus after the current transaction if set to a 1 with a new command issued." "0,1"
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bitfld.long 0x20 4.--6. "OFFSETCNT,Number of offset bytes to use for the command - 0 1 2 3 4 5 are valid selections. The second (byte 1) third (byte 2) and forth (byte 3) are read from the OFFSETHI register and the low order byte is pulled from this register in the.." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x20 0.--3. 1. "CMD,Command for submodule."
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line.long 0x24 "DCXCTRL,Enables transmission of DCX signal with SPI transactions and selects which CE signals will be used to transmit the DCX signal."
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bitfld.long 0x24 4. "DCXEN,Global enable of the DCX function. Setting to 1 will enable the generation of the DCX signal which will assert when sending the offset bytes of the SPI transaction." "0,1"
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hexmask.long.byte 0x24 0.--3. 1. "DCXSEL,Selects the CE channel used to convey the DCX function. The select is bitwise encoded with bit 0 = 1 enabling CE0 for DCX transmission bit 1 = 1 enableing CE1 for DCX transmission etc. If the CE used for the SPI transaction is set it will be.."
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line.long 0x28 "OFFSETHI,High order bytes of offset for IO transaction"
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hexmask.long 0x28 0.--31. 1. "OFFSETHI,Holds the high order bytes of the byte addressing/offset field to use with IO commands. The number of offset bytes to use is specified in the command register"
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line.long 0x2C "CMDSTAT,Provides staus on the execution of the command currently in progress. The fields in this register will reflect the real time status of the internal state machines and data transfers within the IOM."
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hexmask.long.word 0x2C 8.--19. 1. "CTSIZE,The current number of bytes still to be transferred with this command. This field will count down to zero."
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bitfld.long 0x2C 5.--7. "CMDSTAT,The current status of the command execution." "?,1: Error encountered with command,2: Actively processing command,?,4: Idle state no active command no error,?,6: Command in progress but waiting on data from host,?"
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hexmask.long.byte 0x2C 0.--4. 1. "CCMD,Current command that is being executed; This will update based on the phase of the I2C and will indicate a write operation during transmission of the offset "
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group.long 0x200++0x4B
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line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
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bitfld.long 0x0 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x0 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x0 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x0 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x0 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x0 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. Also asserted during I2C write operations when value of 1 expected on bus but 0 is observed. When asserted the I2C state machine will.." "0,1"
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bitfld.long 0x0 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x0 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x0 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x0 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x0 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x0 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0x0 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0x0 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x0 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
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bitfld.long 0x4 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x4 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x4 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x4 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x4 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x4 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. Also asserted during I2C write operations when value of 1 expected on bus but 0 is observed. When asserted the I2C state machine will.." "0,1"
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bitfld.long 0x4 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x4 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x4 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x4 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x4 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x4 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0x4 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0x4 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x4 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
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bitfld.long 0x8 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x8 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x8 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x8 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x8 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x8 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. Also asserted during I2C write operations when value of 1 expected on bus but 0 is observed. When asserted the I2C state machine will.." "0,1"
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bitfld.long 0x8 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x8 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x8 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x8 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x8 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x8 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0x8 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0x8 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x8 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
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bitfld.long 0xC 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0xC 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0xC 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0xC 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0xC 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0xC 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. Also asserted during I2C write operations when value of 1 expected on bus but 0 is observed. When asserted the I2C state machine will.." "0,1"
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bitfld.long 0xC 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0xC 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0xC 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0xC 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0xC 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0xC 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0xC 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0xC 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0xC 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x10 "DMATRIGEN,Provides control on which event will trigger the DMA transfer after the DMA operation is setup and enabled. The trigger event will cause a number of bytes (depending on trigger event) to be"
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bitfld.long 0x10 1. "DTHREN,Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes) the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO and will transfer (WTHR/4) number of words" "0,1"
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bitfld.long 0x10 0. "DCMDCMPEN,Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered the number of words transferred will be the lesser of the remaining TOTCOUNT bytes or" "0,1"
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line.long 0x14 "DMATRIGSTAT,Provides the status of trigger events that have occurred for the transaction. Some of the bits are read only and some can be reset via a write of 0."
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bitfld.long 0x14 2. "DTOTCMP,DMA triggered when DCMDCMP = 0 and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is" "0,1"
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bitfld.long 0x14 1. "DTHR,Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA." "0,1"
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bitfld.long 0x14 0. "DCMDCMP,Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA." "0,1"
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line.long 0x18 "DMACFG,Configuration control of the DMA process. including the direction of DMA. and enablement of DMA"
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bitfld.long 0x18 9. "DPWROFF,Power off module after DMA is complete. If this bit is active the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain power down will not be performed." "0: Power off disabled,1: Power off enabled"
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bitfld.long 0x18 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x18 1. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction. To be..,1: Memory to Peripheral transaction. To be set when.."
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bitfld.long 0x18 0. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable DMA Function,1: Enable DMA Function"
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line.long 0x1C "DMATOTCOUNT,Contains the number of bytes to be transferred for this DMA transaction. This register is decremented as the data is transferred. and will be 0 at the completion of the DMA operation."
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hexmask.long.word 0x1C 0.--11. 1. "TOTCOUNT,Triggered DMA from Command complete event occured. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."
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line.long 0x20 "DMATARGADDR,The source or destination address internal the SRAM for the DMA data. For write operations. this can only be SRAM data (ADDR bit 28 = 1); For read operations. this can ve either SRAM or FLASH (ADDR bit 28 = 0)"
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hexmask.long 0x20 0.--28. 1. "TARGADDR,Bits [28:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment and does not have to be word aligned. In cases of non-word aligned addresses the DMA logic will take care for ensuring only.."
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line.long 0x24 "DMASTAT,Status of the DMA operation currently in progress."
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bitfld.long 0x24 2. "DMAERR,DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set this bit will remain set until cleared by software." "0,1"
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bitfld.long 0x24 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0 and will also be cleared when a new DMA is started." "0,1"
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bitfld.long 0x24 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
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line.long 0x28 "CQCFG,Controls parameters and options for execution of the command queue operation. To enable command queue. create this in memory. set the address. and enable it with a write to CQEN"
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bitfld.long 0x28 2.--3. "MSPIFLGSEL,Selects the MPSI modules used for sourcing the CQFLAG [11:8]." "0: Selects MPSI0 as source of signals used in..,1: Selects MPSI1 as source of signals used in..,2: Selects MPSI2 as source of signals used in..,?"
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bitfld.long 0x28 1. "CQPRI,Sets the Priority of the command queue dma request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x28 0. "CQEN,Command queue enable. When set will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled" "0: Disable CQ Function,1: Enable CQ Function"
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line.long 0x2C "CQADDR,The SRAM address which will be fetched next execution of the CQ operation. This register is updated as the CQ operation progresses. and is the live version of the register. The register can also be"
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hexmask.long 0x2C 2.--28. 1. "CQADDR,Bits 28:2 of target byte address for source of CQ . The buffer must be aligned on a word boundary"
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line.long 0x30 "CQSTAT,Provides the status of the command queue operation. If the command queue is disabled. these bits will be cleared. The bits are read only"
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bitfld.long 0x30 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
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bitfld.long 0x30 1. "CQPAUSED,Command queue operation is currently paused." "0,1"
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bitfld.long 0x30 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
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line.long 0x34 "CQFLAGS,Command Queue Flag"
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hexmask.long.word 0x34 16.--31. 1. "CQIRQMASK,Mask the bits used to generate the command queue interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE"
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hexmask.long.word 0x34 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
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line.long 0x38 "CQSETCLEAR,Set/Clear the command queue software pause flags on a per-bit basis. Contains 3 fields. allowing for setting. clearing or toggling the value in the software flags. Priority when the same bit"
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hexmask.long.byte 0x38 16.--23. 1. "CQFCLR,Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x38 8.--15. 1. "CQFTGL,Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x38 0.--7. 1. "CQFSET,Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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line.long 0x3C "CQPAUSEEN,Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the CQFLAG register is '1'. CQ processing will halt until either value is changed to '0'."
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hexmask.long.word 0x3C 0.--15. 1. "CQPEN,Enables the specified event to pause command processing when active"
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line.long 0x40 "CQCURIDX,Current index value. targeted to be written by register write operations within the command queue. This is compared to the CQENDIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and"
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hexmask.long.byte 0x40 0.--7. 1. "CQCURIDX,Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x44 "CQENDIDX,End index value. targeted to be written by software to indicate the last valid register pair contained within the command queue. rgister write operations within the command queue."
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hexmask.long.byte 0x44 0.--7. 1. "CQENDIDX,Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x48 "STATUS,IOM Module Status"
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bitfld.long 0x48 2. "IDLEST,indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to holdoffs from data availability or as the command gets propagated into the logic from the registers." "?,1: The I/O state machine is in the idle state."
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bitfld.long 0x48 1. "CMDACT,Indicates if the active I/O Command is currently processing a transaction or command is complete but the FIFO pointers are still syncronizing internally. This bit will go high at" "?,1: An I/O command is active. Indicates the active.."
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bitfld.long 0x48 0. "ERR,Bit has been deprecated. Please refer to the other error indicators. This will always return 0." "?,1: Bit has been deprecated and will always return 0."
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group.long 0x280++0x3
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line.long 0x0 "MSPICFG,Controls the configuration of the SPI master module. including POL/PHA. LSB. flow control. and delays for MISO and MOSI"
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bitfld.long 0x0 30. "MSPIRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 27.--29. "DOUTDLY,Delay tap to use for the output signal (MOSI). This give more hold time on the output data" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 24.--26. "DINDLY,Delay tap to use for the input signal (MISO). This gives more hold time on the input data." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "SPILSB,Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first." "0: Send and receive MSB bit first,1: Send and receive LSB bit first"
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bitfld.long 0x0 22. "RDFCPOL,Selects the read flow control signal polarity." "0: Flow control signal high creates flow control.,1: Flow control signal low creates flow control."
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bitfld.long 0x0 21. "WTFCPOL,selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 will allow a IRQ=1 to pause transfers)." "0: Flow control signal high(1) creates flow control..,1: Flow control signal low(0) creates flow control.."
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bitfld.long 0x0 20. "WTFCIRQ,Selects the write mode flow control signal." "0: MISO is used as the write mode flow control..,1: IRQ is used as the write mode flow control signal."
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bitfld.long 0x0 18. "MOSIINV,Inverts MOSI when flow control is enabled." "0: MOSI is set to 0 in read mode and 1 in write mode.,1: MOSI is set to 1 in read mode and 0 in write mode."
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bitfld.long 0x0 17. "RDFC,Enables read mode flow control." "0: Read mode flow control disabled.,1: Read mode flow control enabled."
|
|
bitfld.long 0x0 16. "WTFC,enables write mode flow control." "0: Write mode flow control disabled.,1: Write mode flow control enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "FULLDUP,Enables full duplex mode for Master SPI write operations. Data will be captured simultaneously into the read fifo" "0,1"
|
|
bitfld.long 0x0 1. "SPHA,Selects SPI phase.IMPORTANT NOTICE: Due to the susceptibility of creating a clock glitch which could cause register corruption changing SPHA and SPOL bits should be done in separate writes to this register." "0: Sample on the leading (first) clock edge.,1: Sample on the trailing (second) clock edge."
|
|
newline
|
|
bitfld.long 0x0 0. "SPOL,Selects SPI polarity.IMPORTANT NOTICE: Due to the susceptibility of creating a clock glitch which could cause register corruption changing SPHA and SPOL bits should be done in separate writes to this register." "0: The base value of the clock is 0.,1: The base value of the clock is 1."
|
|
group.long 0x2C0++0x7
|
|
line.long 0x0 "MI2CCFG,Controls the configuration of the I2C bus master."
|
|
bitfld.long 0x0 24. "STRDIS,Disable detection of clock stretch events smaller than 1 cycle" "0,1"
|
|
hexmask.long.byte 0x0 16.--23. 1. "SMPCNT,Number of Base clk cycles to wait before sampling the SCL clock to determine if a clock stretch event has occured"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "SDAENDLY,Number of IOCLK cycles to delay the SDA output en (all transitions affected). Used to delay data relative to clock"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SCLENDLY,Number of IOCLK cycles to delay the rising edge of the SCL output en (clock will go low on this edge). Used to allow clock shaping."
|
|
newline
|
|
bitfld.long 0x0 6. "MI2CRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
|
|
bitfld.long 0x0 4.--5. "SDADLY,Delay to enable on the SDA output. Values are 0x0-0x3." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 2. "ARBEN,Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master this function can be disabled to save clock cycles on I2C transactions" "0: Disable multi-master bus arbitration support for..,1: Enable multi-master bus arbitration support for.."
|
|
bitfld.long 0x0 1. "I2CLSB,Direction of data transmit and receive MSB(0) or LSB(1) first. Default per I2C specification is MSB first. This applies to both read and write data and read data will be bit" "0: Byte data is transmitted MSB first onto the..,1: Byte data is transmitted LSB first onto the.."
|
|
newline
|
|
bitfld.long 0x0 0. "ADDRSZ,Sets the I2C master device address size to either 7b (0) or 10b (1)." "0: Use 7b addressing for I2C master transactions,1: Use 10b addressing for I2C master transactions"
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|
line.long 0x4 "DEVCFG,Contains the I2C device address."
|
|
hexmask.long.word 0x4 0.--9. 1. "DEVADDR,I2C address of the device that the Master will use to target for read/write operations. This can be either a 7b or 10b address."
|
|
group.long 0x388++0x3
|
|
line.long 0x0 "IOMDBG,Debug control"
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|
hexmask.long 0x0 3.--31. 1. "DBGDATA,Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers."
|
|
bitfld.long 0x0 2. "APBCLKON,APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "IOCLKON,IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
|
|
bitfld.long 0x0 0. "DBGEN,Debug Enable. Setting bit will enable the update of data within this register otherwise it is clock gated for power savings" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
tree "IOM5"
|
|
base ad:0x40055000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FIFO,Provides direct random access to both input and output fifos. The state of the FIFO is not distured by reading these locations (ie no POP will be done). FIFO0 is accessible from addresses 0x0 - 0x1C. and is used for data outuput from the IOM to.."
|
|
hexmask.long 0x0 0.--31. 1. "FIFO,FIFO direct access. Only locations 0 - 3F will return valid information."
|
|
group.long 0x100++0x2F
|
|
line.long 0x0 "FIFOPTR,Provides the current valid byte count of data within the FIFO as seen from the internal state machines. FIFO0 is dedicated to outgoing transactions and FIFO1 is dedicated to incoming transactions. All counts are specified in units of bytes."
|
|
hexmask.long.byte 0x0 24.--31. 1. "FIFO1REM,The number of remaining data bytes slots currently in FIFO 1 (written by interface read by MCU)"
|
|
hexmask.long.byte 0x0 16.--23. 1. "FIFO1SIZ,The number of valid data bytes currently in FIFO 1 (written by interface read by MCU)"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "FIFO0REM,The number of remaining data bytes slots currently in FIFO 0 (written by MCU read by interface)"
|
|
hexmask.long.byte 0x0 0.--7. 1. "FIFO0SIZ,The number of valid data bytes currently in the FIFO 0 (written by MCU read by interface)"
|
|
line.long 0x4 "FIFOTHR,Sets the threshold values for incoming and outgoing transactions. The threshold values are used to assert the interrupt if enabled. and also used during DMA to set the transfer size as a result of DMATHR trigger."
|
|
hexmask.long.byte 0x4 8.--13. 1. "FIFOWTHR,FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the write fifo contains FIFOWTHR free bytes as.."
|
|
hexmask.long.byte 0x4 0.--5. 1. "FIFORTHR,FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the read fifo contains FIFORTHR valid bytes of data as.."
|
|
line.long 0x8 "FIFOPOP,Will advance the internal read pointer of the incoming FIFO (FIFO1) when read. if POPWR is not active. If POPWR is active. a write to this register is needed to advance the internal FIFO pointer."
|
|
hexmask.long 0x8 0.--31. 1. "FIFODOUT,This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0) the fifo read pointer will be advanced by one word as a result of the read."
|
|
line.long 0xC "FIFOPUSH,Will write new data into the outgoing FIFO and advance the internal write pointer."
|
|
hexmask.long 0xC 0.--31. 1. "FIFODIN,This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes)."
|
|
line.long 0x10 "FIFOCTRL,Provides controls for the operation of the internal FIFOs. Contains fields used to control the operation of the POP register. and also controls to reset the internal pointers of the FIFOs."
|
|
bitfld.long 0x10 1. "FIFORSTN,Active low manual reset of the fifo. Write to 0 to reset fifo and then write to 1 to remove the reset." "0,1"
|
|
bitfld.long 0x10 0. "POPWR,Selects the mode in which 'pop' events are done for the fifo read operations. A value of '1' will prevent a pop event on a read operation and will require a write to the FIFOPOP register to create a pop event." "0,1"
|
|
line.long 0x14 "FIFOLOC,Provides a read only value of the current read and write pointers. This register is read only and can be used alogn with the FIFO direct access method to determine the next data to be used for input and output functions."
|
|
hexmask.long.byte 0x14 8.--11. 1. "FIFORPTR,Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1) which is used to store read data returned from external devices during a read operation."
|
|
hexmask.long.byte 0x14 0.--3. 1. "FIFOWPTR,Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0) which is used during write operations to external devices."
|
|
line.long 0x18 "CLKCFG,Provides clock related controls used internal to the BLEIF module. and enablement of 32KHz clock to the BLE Core module. The internal clock sourced is selected via the FSEL and can be further divided by 3 using the DIV3 control."
|
|
hexmask.long.byte 0x18 24.--31. 1. "TOTPER,Clock total clock count minus 1. This provides the total period of the divided clock -1 when the DIVEN is active. The"
|
|
hexmask.long.byte 0x18 16.--23. 1. "LOWPER,Clock low clock count minus 1. This provides the number of clocks the divided clock will be low when the DIVEN = 1."
|
|
newline
|
|
bitfld.long 0x18 12. "DIVEN,Enable clock division by TOTPER and LOWPER" "0: Disable TOTPER division.,1: Enable TOTPER division."
|
|
bitfld.long 0x18 11. "DIV3,Enable divide by 3 of the source IOCLK. Division by 3 is done before the DIVEN programmable divider and if enabled" "0: Select divide by 1.,1: Select divide by 3."
|
|
newline
|
|
bitfld.long 0x18 8.--10. "FSEL,Select the input clock frequency." "0: Selects the minimum power clock. This setting..,1: Selects static 0 as the input clock. Previously..,2: Selects the HFRC 48MHz as the input clock.,3: Selects the HFRC 24MHz as the input clock.,4: Selects the HFRC 12MHz as the input clock.,5: Selects the HFRC 6MHz as the input clock.,6: Selects the HFRC 3MHz as the input clock.,7: Selects the HFRC 1.5MHz as the input clock."
|
|
bitfld.long 0x18 0. "IOCLKEN,Enable for the interface clock. Must be enabled prior to executing any IO operations." "0,1"
|
|
line.long 0x1C "SUBMODCTRL,Provides enable for each submodule. Only a sigle submodule can be enabled at one time."
|
|
bitfld.long 0x1C 9.--11. "SMOD2TYPE,Submodule 2 module type. This is the I2S Master/Slave interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,4: Master/Slave submodule,?,?,7: NOT INSTALLED"
|
|
bitfld.long 0x1C 8. "SMOD2EN,Submodule 2 enable (1) or disable (0)" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 5.--7. "SMOD1TYPE,Submodule 1 module type. This is the I2C Master interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,4: Master/Slave submodule,?,?,7: NOT INSTALLED"
|
|
bitfld.long 0x1C 4. "SMOD1EN,Submodule 1 enable (1) or disable (0)" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 1.--3. "SMOD0TYPE,Submodule 0 module type. This is the SPI Master interface." "0: MSPI submodule,1: I2C Master submodule,2: I2S Master/Slave Module,?,?,?,?,7: NOT INSTALLED"
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|
bitfld.long 0x1C 0. "SMOD0EN,Submodule 0 enable (1) or disable (0)" "0,1"
|
|
line.long 0x20 "CMD,Writes to this register will start an IO transaction. as well as set various parameters for the command itself. Reads will return the command value written to the CMD register."
|
|
hexmask.long.byte 0x20 24.--31. 1. "OFFSETLO,This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command."
|
|
bitfld.long 0x20 20.--21. "CMDSEL,Command Specific selection information. Not used in Master I2C. Used as CEn select for Master SPI transactions" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x20 8.--19. 1. "TSIZE,Defines the transaction size in bytes. The offset transfer is not included in this size."
|
|
bitfld.long 0x20 7. "CONT,Contine to hold the bus after the current transaction if set to a 1 with a new command issued." "0,1"
|
|
newline
|
|
bitfld.long 0x20 4.--6. "OFFSETCNT,Number of offset bytes to use for the command - 0 1 2 3 4 5 are valid selections. The second (byte 1) third (byte 2) and forth (byte 3) are read from the OFFSETHI register and the low order byte is pulled from this register in the.." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x20 0.--3. 1. "CMD,Command for submodule."
|
|
line.long 0x24 "DCXCTRL,Enables transmission of DCX signal with SPI transactions and selects which CE signals will be used to transmit the DCX signal."
|
|
bitfld.long 0x24 4. "DCXEN,Global enable of the DCX function. Setting to 1 will enable the generation of the DCX signal which will assert when sending the offset bytes of the SPI transaction." "0,1"
|
|
hexmask.long.byte 0x24 0.--3. 1. "DCXSEL,Selects the CE channel used to convey the DCX function. The select is bitwise encoded with bit 0 = 1 enabling CE0 for DCX transmission bit 1 = 1 enableing CE1 for DCX transmission etc. If the CE used for the SPI transaction is set it will be.."
|
|
line.long 0x28 "OFFSETHI,High order bytes of offset for IO transaction"
|
|
hexmask.long 0x28 0.--31. 1. "OFFSETHI,Holds the high order bytes of the byte addressing/offset field to use with IO commands. The number of offset bytes to use is specified in the command register"
|
|
line.long 0x2C "CMDSTAT,Provides staus on the execution of the command currently in progress. The fields in this register will reflect the real time status of the internal state machines and data transfers within the IOM."
|
|
hexmask.long.word 0x2C 8.--19. 1. "CTSIZE,The current number of bytes still to be transferred with this command. This field will count down to zero."
|
|
bitfld.long 0x2C 5.--7. "CMDSTAT,The current status of the command execution." "?,1: Error encountered with command,2: Actively processing command,?,4: Idle state no active command no error,?,6: Command in progress but waiting on data from host,?"
|
|
newline
|
|
hexmask.long.byte 0x2C 0.--4. 1. "CCMD,Current command that is being executed; This will update based on the phase of the I2C and will indicate a write operation during transmission of the offset "
|
|
group.long 0x200++0x4B
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 14. "CQERR,Error during command queue operations" "0,1"
|
|
bitfld.long 0x0 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
|
|
bitfld.long 0x0 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0x0 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. Also asserted during I2C write operations when value of 1 expected on bus but 0 is observed. When asserted the I2C state machine will.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x0 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x0 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0x0 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
|
|
bitfld.long 0x0 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 14. "CQERR,Error during command queue operations" "0,1"
|
|
bitfld.long 0x4 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
|
|
bitfld.long 0x4 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0x4 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. Also asserted during I2C write operations when value of 1 expected on bus but 0 is observed. When asserted the I2C state machine will.." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x4 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x4 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0x4 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
|
|
bitfld.long 0x4 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 14. "CQERR,Error during command queue operations" "0,1"
|
|
bitfld.long 0x8 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
|
|
bitfld.long 0x8 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0x8 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. Also asserted during I2C write operations when value of 1 expected on bus but 0 is observed. When asserted the I2C state machine will.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x8 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x8 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0x8 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
|
|
bitfld.long 0x8 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 14. "CQERR,Error during command queue operations" "0,1"
|
|
bitfld.long 0xC 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
|
|
bitfld.long 0xC 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0xC 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. Also asserted during I2C write operations when value of 1 expected on bus but 0 is observed. When asserted the I2C state machine will.." "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0xC 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0xC 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0xC 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0xC 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0xC 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0xC 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x10 "DMATRIGEN,Provides control on which event will trigger the DMA transfer after the DMA operation is setup and enabled. The trigger event will cause a number of bytes (depending on trigger event) to be"
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bitfld.long 0x10 1. "DTHREN,Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes) the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO and will transfer (WTHR/4) number of words" "0,1"
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bitfld.long 0x10 0. "DCMDCMPEN,Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered the number of words transferred will be the lesser of the remaining TOTCOUNT bytes or" "0,1"
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line.long 0x14 "DMATRIGSTAT,Provides the status of trigger events that have occurred for the transaction. Some of the bits are read only and some can be reset via a write of 0."
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bitfld.long 0x14 2. "DTOTCMP,DMA triggered when DCMDCMP = 0 and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is" "0,1"
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bitfld.long 0x14 1. "DTHR,Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA." "0,1"
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bitfld.long 0x14 0. "DCMDCMP,Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA." "0,1"
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line.long 0x18 "DMACFG,Configuration control of the DMA process. including the direction of DMA. and enablement of DMA"
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bitfld.long 0x18 9. "DPWROFF,Power off module after DMA is complete. If this bit is active the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain power down will not be performed." "0: Power off disabled,1: Power off enabled"
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bitfld.long 0x18 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x18 1. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction. To be..,1: Memory to Peripheral transaction. To be set when.."
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bitfld.long 0x18 0. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable DMA Function,1: Enable DMA Function"
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line.long 0x1C "DMATOTCOUNT,Contains the number of bytes to be transferred for this DMA transaction. This register is decremented as the data is transferred. and will be 0 at the completion of the DMA operation."
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hexmask.long.word 0x1C 0.--11. 1. "TOTCOUNT,Triggered DMA from Command complete event occured. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."
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line.long 0x20 "DMATARGADDR,The source or destination address internal the SRAM for the DMA data. For write operations. this can only be SRAM data (ADDR bit 28 = 1); For read operations. this can ve either SRAM or FLASH (ADDR bit 28 = 0)"
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hexmask.long 0x20 0.--28. 1. "TARGADDR,Bits [28:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment and does not have to be word aligned. In cases of non-word aligned addresses the DMA logic will take care for ensuring only.."
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line.long 0x24 "DMASTAT,Status of the DMA operation currently in progress."
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bitfld.long 0x24 2. "DMAERR,DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set this bit will remain set until cleared by software." "0,1"
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bitfld.long 0x24 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0 and will also be cleared when a new DMA is started." "0,1"
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bitfld.long 0x24 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
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line.long 0x28 "CQCFG,Controls parameters and options for execution of the command queue operation. To enable command queue. create this in memory. set the address. and enable it with a write to CQEN"
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bitfld.long 0x28 2.--3. "MSPIFLGSEL,Selects the MPSI modules used for sourcing the CQFLAG [11:8]." "0: Selects MPSI0 as source of signals used in..,1: Selects MPSI1 as source of signals used in..,2: Selects MPSI2 as source of signals used in..,?"
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bitfld.long 0x28 1. "CQPRI,Sets the Priority of the command queue dma request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x28 0. "CQEN,Command queue enable. When set will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled" "0: Disable CQ Function,1: Enable CQ Function"
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line.long 0x2C "CQADDR,The SRAM address which will be fetched next execution of the CQ operation. This register is updated as the CQ operation progresses. and is the live version of the register. The register can also be"
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hexmask.long 0x2C 2.--28. 1. "CQADDR,Bits 28:2 of target byte address for source of CQ . The buffer must be aligned on a word boundary"
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line.long 0x30 "CQSTAT,Provides the status of the command queue operation. If the command queue is disabled. these bits will be cleared. The bits are read only"
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bitfld.long 0x30 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
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bitfld.long 0x30 1. "CQPAUSED,Command queue operation is currently paused." "0,1"
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bitfld.long 0x30 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
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line.long 0x34 "CQFLAGS,Command Queue Flag"
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hexmask.long.word 0x34 16.--31. 1. "CQIRQMASK,Mask the bits used to generate the command queue interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE"
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hexmask.long.word 0x34 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
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line.long 0x38 "CQSETCLEAR,Set/Clear the command queue software pause flags on a per-bit basis. Contains 3 fields. allowing for setting. clearing or toggling the value in the software flags. Priority when the same bit"
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hexmask.long.byte 0x38 16.--23. 1. "CQFCLR,Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x38 8.--15. 1. "CQFTGL,Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x38 0.--7. 1. "CQFSET,Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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line.long 0x3C "CQPAUSEEN,Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the CQFLAG register is '1'. CQ processing will halt until either value is changed to '0'."
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hexmask.long.word 0x3C 0.--15. 1. "CQPEN,Enables the specified event to pause command processing when active"
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line.long 0x40 "CQCURIDX,Current index value. targeted to be written by register write operations within the command queue. This is compared to the CQENDIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and"
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hexmask.long.byte 0x40 0.--7. 1. "CQCURIDX,Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x44 "CQENDIDX,End index value. targeted to be written by software to indicate the last valid register pair contained within the command queue. rgister write operations within the command queue."
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hexmask.long.byte 0x44 0.--7. 1. "CQENDIDX,Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x48 "STATUS,IOM Module Status"
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bitfld.long 0x48 2. "IDLEST,indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to holdoffs from data availability or as the command gets propagated into the logic from the registers." "?,1: The I/O state machine is in the idle state."
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bitfld.long 0x48 1. "CMDACT,Indicates if the active I/O Command is currently processing a transaction or command is complete but the FIFO pointers are still syncronizing internally. This bit will go high at" "?,1: An I/O command is active. Indicates the active.."
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bitfld.long 0x48 0. "ERR,Bit has been deprecated. Please refer to the other error indicators. This will always return 0." "?,1: Bit has been deprecated and will always return 0."
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group.long 0x280++0x3
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line.long 0x0 "MSPICFG,Controls the configuration of the SPI master module. including POL/PHA. LSB. flow control. and delays for MISO and MOSI"
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bitfld.long 0x0 30. "MSPIRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 27.--29. "DOUTDLY,Delay tap to use for the output signal (MOSI). This give more hold time on the output data" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 24.--26. "DINDLY,Delay tap to use for the input signal (MISO). This gives more hold time on the input data." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "SPILSB,Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first." "0: Send and receive MSB bit first,1: Send and receive LSB bit first"
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bitfld.long 0x0 22. "RDFCPOL,Selects the read flow control signal polarity." "0: Flow control signal high creates flow control.,1: Flow control signal low creates flow control."
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bitfld.long 0x0 21. "WTFCPOL,selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 will allow a IRQ=1 to pause transfers)." "0: Flow control signal high(1) creates flow control..,1: Flow control signal low(0) creates flow control.."
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bitfld.long 0x0 20. "WTFCIRQ,Selects the write mode flow control signal." "0: MISO is used as the write mode flow control..,1: IRQ is used as the write mode flow control signal."
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bitfld.long 0x0 18. "MOSIINV,Inverts MOSI when flow control is enabled." "0: MOSI is set to 0 in read mode and 1 in write mode.,1: MOSI is set to 1 in read mode and 0 in write mode."
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bitfld.long 0x0 17. "RDFC,Enables read mode flow control." "0: Read mode flow control disabled.,1: Read mode flow control enabled."
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bitfld.long 0x0 16. "WTFC,enables write mode flow control." "0: Write mode flow control disabled.,1: Write mode flow control enabled."
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bitfld.long 0x0 2. "FULLDUP,Enables full duplex mode for Master SPI write operations. Data will be captured simultaneously into the read fifo" "0,1"
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bitfld.long 0x0 1. "SPHA,Selects SPI phase.IMPORTANT NOTICE: Due to the susceptibility of creating a clock glitch which could cause register corruption changing SPHA and SPOL bits should be done in separate writes to this register." "0: Sample on the leading (first) clock edge.,1: Sample on the trailing (second) clock edge."
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bitfld.long 0x0 0. "SPOL,Selects SPI polarity.IMPORTANT NOTICE: Due to the susceptibility of creating a clock glitch which could cause register corruption changing SPHA and SPOL bits should be done in separate writes to this register." "0: The base value of the clock is 0.,1: The base value of the clock is 1."
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group.long 0x2C0++0x7
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line.long 0x0 "MI2CCFG,Controls the configuration of the I2C bus master."
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bitfld.long 0x0 24. "STRDIS,Disable detection of clock stretch events smaller than 1 cycle" "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "SMPCNT,Number of Base clk cycles to wait before sampling the SCL clock to determine if a clock stretch event has occured"
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hexmask.long.byte 0x0 12.--15. 1. "SDAENDLY,Number of IOCLK cycles to delay the SDA output en (all transitions affected). Used to delay data relative to clock"
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hexmask.long.byte 0x0 8.--11. 1. "SCLENDLY,Number of IOCLK cycles to delay the rising edge of the SCL output en (clock will go low on this edge). Used to allow clock shaping."
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bitfld.long 0x0 6. "MI2CRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 4.--5. "SDADLY,Delay to enable on the SDA output. Values are 0x0-0x3." "0,1,2,3"
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bitfld.long 0x0 2. "ARBEN,Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master this function can be disabled to save clock cycles on I2C transactions" "0: Disable multi-master bus arbitration support for..,1: Enable multi-master bus arbitration support for.."
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bitfld.long 0x0 1. "I2CLSB,Direction of data transmit and receive MSB(0) or LSB(1) first. Default per I2C specification is MSB first. This applies to both read and write data and read data will be bit" "0: Byte data is transmitted MSB first onto the..,1: Byte data is transmitted LSB first onto the.."
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bitfld.long 0x0 0. "ADDRSZ,Sets the I2C master device address size to either 7b (0) or 10b (1)." "0: Use 7b addressing for I2C master transactions,1: Use 10b addressing for I2C master transactions"
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line.long 0x4 "DEVCFG,Contains the I2C device address."
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hexmask.long.word 0x4 0.--9. 1. "DEVADDR,I2C address of the device that the Master will use to target for read/write operations. This can be either a 7b or 10b address."
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group.long 0x388++0x3
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line.long 0x0 "IOMDBG,Debug control"
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hexmask.long 0x0 3.--31. 1. "DBGDATA,Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers."
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bitfld.long 0x0 2. "APBCLKON,APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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newline
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bitfld.long 0x0 1. "IOCLKON,IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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bitfld.long 0x0 0. "DBGEN,Debug Enable. Setting bit will enable the update of data within this register otherwise it is clock gated for power savings" "0,1"
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tree.end
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endif
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sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
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tree "IOM6"
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base ad:0x40056000
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group.long 0x0++0x3
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line.long 0x0 "FIFO,Provides direct random access to both input and output fifos. The state of the FIFO is not distured by reading these locations (ie no POP will be done). FIFO0 is accessible from addresses 0x0 - 0x1C. and is used for data outuput from the IOM to.."
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hexmask.long 0x0 0.--31. 1. "FIFO,FIFO direct access. Only locations 0 - 3F will return valid information."
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group.long 0x100++0x2F
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line.long 0x0 "FIFOPTR,Provides the current valid byte count of data within the FIFO as seen from the internal state machines. FIFO0 is dedicated to outgoing transactions and FIFO1 is dedicated to incoming transactions. All counts are specified in units of bytes."
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hexmask.long.byte 0x0 24.--31. 1. "FIFO1REM,The number of remaining data bytes slots currently in FIFO 1 (written by interface read by MCU)"
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hexmask.long.byte 0x0 16.--23. 1. "FIFO1SIZ,The number of valid data bytes currently in FIFO 1 (written by interface read by MCU)"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "FIFO0REM,The number of remaining data bytes slots currently in FIFO 0 (written by MCU read by interface)"
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hexmask.long.byte 0x0 0.--7. 1. "FIFO0SIZ,The number of valid data bytes currently in the FIFO 0 (written by MCU read by interface)"
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line.long 0x4 "FIFOTHR,Sets the threshold values for incoming and outgoing transactions. The threshold values are used to assert the interrupt if enabled. and also used during DMA to set the transfer size as a result of DMATHR trigger."
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hexmask.long.byte 0x4 8.--13. 1. "FIFOWTHR,FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the write fifo contains FIFOWTHR free bytes as.."
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hexmask.long.byte 0x4 0.--5. 1. "FIFORTHR,FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the read fifo contains FIFORTHR valid bytes of data as.."
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line.long 0x8 "FIFOPOP,Will advance the internal read pointer of the incoming FIFO (FIFO1) when read. if POPWR is not active. If POPWR is active. a write to this register is needed to advance the internal FIFO pointer."
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hexmask.long 0x8 0.--31. 1. "FIFODOUT,This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0) the fifo read pointer will be advanced by one word as a result of the read."
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line.long 0xC "FIFOPUSH,Will write new data into the outgoing FIFO and advance the internal write pointer."
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hexmask.long 0xC 0.--31. 1. "FIFODIN,This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes)."
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line.long 0x10 "FIFOCTRL,Provides controls for the operation of the internal FIFOs. Contains fields used to control the operation of the POP register. and also controls to reset the internal pointers of the FIFOs."
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bitfld.long 0x10 1. "FIFORSTN,Active low manual reset of the fifo. Write to 0 to reset fifo and then write to 1 to remove the reset." "0,1"
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bitfld.long 0x10 0. "POPWR,Selects the mode in which 'pop' events are done for the fifo read operations. A value of '1' will prevent a pop event on a read operation and will require a write to the FIFOPOP register to create a pop event." "0,1"
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line.long 0x14 "FIFOLOC,Provides a read only value of the current read and write pointers. This register is read only and can be used alogn with the FIFO direct access method to determine the next data to be used for input and output functions."
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hexmask.long.byte 0x14 8.--11. 1. "FIFORPTR,Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1) which is used to store read data returned from external devices during a read operation."
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hexmask.long.byte 0x14 0.--3. 1. "FIFOWPTR,Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0) which is used during write operations to external devices."
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line.long 0x18 "CLKCFG,Provides clock related controls used internal to the BLEIF module. and enablement of 32KHz clock to the BLE Core module. The internal clock sourced is selected via the FSEL and can be further divided by 3 using the DIV3 control."
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hexmask.long.byte 0x18 24.--31. 1. "TOTPER,Clock total clock count minus 1. This provides the total period of the divided clock -1 when the DIVEN is active. The"
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hexmask.long.byte 0x18 16.--23. 1. "LOWPER,Clock low clock count minus 1. This provides the number of clocks the divided clock will be low when the DIVEN = 1."
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newline
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bitfld.long 0x18 12. "DIVEN,Enable clock division by TOTPER and LOWPER" "0: Disable TOTPER division.,1: Enable TOTPER division."
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bitfld.long 0x18 11. "DIV3,Enable divide by 3 of the source IOCLK. Division by 3 is done before the DIVEN programmable divider and if enabled" "0: Select divide by 1.,1: Select divide by 3."
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newline
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bitfld.long 0x18 8.--10. "FSEL,Select the input clock frequency." "0: Selects the minimum power clock. This setting..,1: Selects static 0 as the input clock. Previously..,2: Selects the HFRC 48MHz as the input clock.,3: Selects the HFRC 24MHz as the input clock.,4: Selects the HFRC 12MHz as the input clock.,5: Selects the HFRC 6MHz as the input clock.,6: Selects the HFRC 3MHz as the input clock.,7: Selects the HFRC 1.5MHz as the input clock."
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bitfld.long 0x18 0. "IOCLKEN,Enable for the interface clock. Must be enabled prior to executing any IO operations." "0,1"
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line.long 0x1C "SUBMODCTRL,Provides enable for each submodule. Only a sigle submodule can be enabled at one time."
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bitfld.long 0x1C 9.--11. "SMOD2TYPE,Submodule 2 module type. This is the I2S Master/Slave interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,4: Master/Slave submodule,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 8. "SMOD2EN,Submodule 2 enable (1) or disable (0)" "0,1"
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newline
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bitfld.long 0x1C 5.--7. "SMOD1TYPE,Submodule 1 module type. This is the I2C Master interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,4: Master/Slave submodule,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 4. "SMOD1EN,Submodule 1 enable (1) or disable (0)" "0,1"
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newline
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bitfld.long 0x1C 1.--3. "SMOD0TYPE,Submodule 0 module type. This is the SPI Master interface." "0: MSPI submodule,1: I2C Master submodule,2: I2S Master/Slave Module,?,?,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 0. "SMOD0EN,Submodule 0 enable (1) or disable (0)" "0,1"
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line.long 0x20 "CMD,Writes to this register will start an IO transaction. as well as set various parameters for the command itself. Reads will return the command value written to the CMD register."
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hexmask.long.byte 0x20 24.--31. 1. "OFFSETLO,This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command."
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bitfld.long 0x20 20.--21. "CMDSEL,Command Specific selection information. Not used in Master I2C. Used as CEn select for Master SPI transactions" "0,1,2,3"
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hexmask.long.word 0x20 8.--19. 1. "TSIZE,Defines the transaction size in bytes. The offset transfer is not included in this size."
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|
bitfld.long 0x20 7. "CONT,Contine to hold the bus after the current transaction if set to a 1 with a new command issued." "0,1"
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newline
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bitfld.long 0x20 4.--6. "OFFSETCNT,Number of offset bytes to use for the command - 0 1 2 3 4 5 are valid selections. The second (byte 1) third (byte 2) and forth (byte 3) are read from the OFFSETHI register and the low order byte is pulled from this register in the.." "0,1,2,3,4,5,6,7"
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|
hexmask.long.byte 0x20 0.--3. 1. "CMD,Command for submodule."
|
|
line.long 0x24 "DCXCTRL,Enables transmission of DCX signal with SPI transactions and selects which CE signals will be used to transmit the DCX signal."
|
|
bitfld.long 0x24 4. "DCXEN,Global enable of the DCX function. Setting to 1 will enable the generation of the DCX signal which will assert when sending the offset bytes of the SPI transaction." "0,1"
|
|
hexmask.long.byte 0x24 0.--3. 1. "DCXSEL,Selects the CE channel used to convey the DCX function. The select is bitwise encoded with bit 0 = 1 enabling CE0 for DCX transmission bit 1 = 1 enableing CE1 for DCX transmission etc. If the CE used for the SPI transaction is set it will be.."
|
|
line.long 0x28 "OFFSETHI,High order bytes of offset for IO transaction"
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hexmask.long 0x28 0.--31. 1. "OFFSETHI,Holds the high order bytes of the byte addressing/offset field to use with IO commands. The number of offset bytes to use is specified in the command register"
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line.long 0x2C "CMDSTAT,Provides staus on the execution of the command currently in progress. The fields in this register will reflect the real time status of the internal state machines and data transfers within the IOM."
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hexmask.long.word 0x2C 8.--19. 1. "CTSIZE,The current number of bytes still to be transferred with this command. This field will count down to zero."
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bitfld.long 0x2C 5.--7. "CMDSTAT,The current status of the command execution." "?,1: Error encountered with command,2: Actively processing command,?,4: Idle state no active command no error,?,6: Command in progress but waiting on data from host,?"
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hexmask.long.byte 0x2C 0.--4. 1. "CCMD,Current command that is being executed; This will update based on the phase of the I2C and will indicate a write operation during transmission of the offset "
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group.long 0x200++0x4B
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line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
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bitfld.long 0x0 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x0 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x0 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x0 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x0 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x0 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. Also asserted during I2C write operations when value of 1 expected on bus but 0 is observed. When asserted the I2C state machine will.." "0,1"
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bitfld.long 0x0 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x0 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x0 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x0 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x0 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x0 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0x0 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0x0 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x0 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
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bitfld.long 0x4 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x4 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x4 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x4 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x4 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x4 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. Also asserted during I2C write operations when value of 1 expected on bus but 0 is observed. When asserted the I2C state machine will.." "0,1"
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bitfld.long 0x4 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x4 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x4 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x4 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x4 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x4 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0x4 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0x4 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x4 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
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bitfld.long 0x8 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x8 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x8 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x8 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x8 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x8 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. Also asserted during I2C write operations when value of 1 expected on bus but 0 is observed. When asserted the I2C state machine will.." "0,1"
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bitfld.long 0x8 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x8 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x8 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x8 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x8 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x8 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0x8 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0x8 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x8 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
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bitfld.long 0xC 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0xC 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0xC 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0xC 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0xC 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0xC 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. Also asserted during I2C write operations when value of 1 expected on bus but 0 is observed. When asserted the I2C state machine will.." "0,1"
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bitfld.long 0xC 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0xC 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0xC 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0xC 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0xC 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0xC 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0xC 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0xC 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0xC 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x10 "DMATRIGEN,Provides control on which event will trigger the DMA transfer after the DMA operation is setup and enabled. The trigger event will cause a number of bytes (depending on trigger event) to be"
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bitfld.long 0x10 1. "DTHREN,Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes) the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO and will transfer (WTHR/4) number of words" "0,1"
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bitfld.long 0x10 0. "DCMDCMPEN,Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered the number of words transferred will be the lesser of the remaining TOTCOUNT bytes or" "0,1"
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line.long 0x14 "DMATRIGSTAT,Provides the status of trigger events that have occurred for the transaction. Some of the bits are read only and some can be reset via a write of 0."
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bitfld.long 0x14 2. "DTOTCMP,DMA triggered when DCMDCMP = 0 and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is" "0,1"
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bitfld.long 0x14 1. "DTHR,Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA." "0,1"
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bitfld.long 0x14 0. "DCMDCMP,Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA." "0,1"
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line.long 0x18 "DMACFG,Configuration control of the DMA process. including the direction of DMA. and enablement of DMA"
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bitfld.long 0x18 9. "DPWROFF,Power off module after DMA is complete. If this bit is active the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain power down will not be performed." "0: Power off disabled,1: Power off enabled"
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bitfld.long 0x18 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x18 1. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction. To be..,1: Memory to Peripheral transaction. To be set when.."
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bitfld.long 0x18 0. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable DMA Function,1: Enable DMA Function"
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line.long 0x1C "DMATOTCOUNT,Contains the number of bytes to be transferred for this DMA transaction. This register is decremented as the data is transferred. and will be 0 at the completion of the DMA operation."
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hexmask.long.word 0x1C 0.--11. 1. "TOTCOUNT,Triggered DMA from Command complete event occured. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."
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line.long 0x20 "DMATARGADDR,The source or destination address internal the SRAM for the DMA data. For write operations. this can only be SRAM data (ADDR bit 28 = 1); For read operations. this can ve either SRAM or FLASH (ADDR bit 28 = 0)"
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hexmask.long 0x20 0.--28. 1. "TARGADDR,Bits [28:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment and does not have to be word aligned. In cases of non-word aligned addresses the DMA logic will take care for ensuring only.."
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line.long 0x24 "DMASTAT,Status of the DMA operation currently in progress."
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bitfld.long 0x24 2. "DMAERR,DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set this bit will remain set until cleared by software." "0,1"
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bitfld.long 0x24 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0 and will also be cleared when a new DMA is started." "0,1"
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bitfld.long 0x24 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
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line.long 0x28 "CQCFG,Controls parameters and options for execution of the command queue operation. To enable command queue. create this in memory. set the address. and enable it with a write to CQEN"
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bitfld.long 0x28 2.--3. "MSPIFLGSEL,Selects the MPSI modules used for sourcing the CQFLAG [11:8]." "0: Selects MPSI0 as source of signals used in..,1: Selects MPSI1 as source of signals used in..,2: Selects MPSI2 as source of signals used in..,?"
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bitfld.long 0x28 1. "CQPRI,Sets the Priority of the command queue dma request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x28 0. "CQEN,Command queue enable. When set will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled" "0: Disable CQ Function,1: Enable CQ Function"
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line.long 0x2C "CQADDR,The SRAM address which will be fetched next execution of the CQ operation. This register is updated as the CQ operation progresses. and is the live version of the register. The register can also be"
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hexmask.long 0x2C 2.--28. 1. "CQADDR,Bits 28:2 of target byte address for source of CQ . The buffer must be aligned on a word boundary"
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line.long 0x30 "CQSTAT,Provides the status of the command queue operation. If the command queue is disabled. these bits will be cleared. The bits are read only"
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bitfld.long 0x30 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
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bitfld.long 0x30 1. "CQPAUSED,Command queue operation is currently paused." "0,1"
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bitfld.long 0x30 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
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line.long 0x34 "CQFLAGS,Command Queue Flag"
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hexmask.long.word 0x34 16.--31. 1. "CQIRQMASK,Mask the bits used to generate the command queue interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE"
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hexmask.long.word 0x34 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
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line.long 0x38 "CQSETCLEAR,Set/Clear the command queue software pause flags on a per-bit basis. Contains 3 fields. allowing for setting. clearing or toggling the value in the software flags. Priority when the same bit"
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hexmask.long.byte 0x38 16.--23. 1. "CQFCLR,Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x38 8.--15. 1. "CQFTGL,Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x38 0.--7. 1. "CQFSET,Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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line.long 0x3C "CQPAUSEEN,Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the CQFLAG register is '1'. CQ processing will halt until either value is changed to '0'."
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hexmask.long.word 0x3C 0.--15. 1. "CQPEN,Enables the specified event to pause command processing when active"
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line.long 0x40 "CQCURIDX,Current index value. targeted to be written by register write operations within the command queue. This is compared to the CQENDIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and"
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hexmask.long.byte 0x40 0.--7. 1. "CQCURIDX,Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x44 "CQENDIDX,End index value. targeted to be written by software to indicate the last valid register pair contained within the command queue. rgister write operations within the command queue."
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hexmask.long.byte 0x44 0.--7. 1. "CQENDIDX,Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x48 "STATUS,IOM Module Status"
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bitfld.long 0x48 2. "IDLEST,indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to holdoffs from data availability or as the command gets propagated into the logic from the registers." "?,1: The I/O state machine is in the idle state."
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bitfld.long 0x48 1. "CMDACT,Indicates if the active I/O Command is currently processing a transaction or command is complete but the FIFO pointers are still syncronizing internally. This bit will go high at" "?,1: An I/O command is active. Indicates the active.."
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bitfld.long 0x48 0. "ERR,Bit has been deprecated. Please refer to the other error indicators. This will always return 0." "?,1: Bit has been deprecated and will always return 0."
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group.long 0x280++0x3
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line.long 0x0 "MSPICFG,Controls the configuration of the SPI master module. including POL/PHA. LSB. flow control. and delays for MISO and MOSI"
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bitfld.long 0x0 30. "MSPIRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 27.--29. "DOUTDLY,Delay tap to use for the output signal (MOSI). This give more hold time on the output data" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 24.--26. "DINDLY,Delay tap to use for the input signal (MISO). This gives more hold time on the input data." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "SPILSB,Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first." "0: Send and receive MSB bit first,1: Send and receive LSB bit first"
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bitfld.long 0x0 22. "RDFCPOL,Selects the read flow control signal polarity." "0: Flow control signal high creates flow control.,1: Flow control signal low creates flow control."
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bitfld.long 0x0 21. "WTFCPOL,selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 will allow a IRQ=1 to pause transfers)." "0: Flow control signal high(1) creates flow control..,1: Flow control signal low(0) creates flow control.."
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bitfld.long 0x0 20. "WTFCIRQ,Selects the write mode flow control signal." "0: MISO is used as the write mode flow control..,1: IRQ is used as the write mode flow control signal."
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bitfld.long 0x0 18. "MOSIINV,Inverts MOSI when flow control is enabled." "0: MOSI is set to 0 in read mode and 1 in write mode.,1: MOSI is set to 1 in read mode and 0 in write mode."
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bitfld.long 0x0 17. "RDFC,Enables read mode flow control." "0: Read mode flow control disabled.,1: Read mode flow control enabled."
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bitfld.long 0x0 16. "WTFC,enables write mode flow control." "0: Write mode flow control disabled.,1: Write mode flow control enabled."
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bitfld.long 0x0 2. "FULLDUP,Enables full duplex mode for Master SPI write operations. Data will be captured simultaneously into the read fifo" "0,1"
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bitfld.long 0x0 1. "SPHA,Selects SPI phase.IMPORTANT NOTICE: Due to the susceptibility of creating a clock glitch which could cause register corruption changing SPHA and SPOL bits should be done in separate writes to this register." "0: Sample on the leading (first) clock edge.,1: Sample on the trailing (second) clock edge."
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bitfld.long 0x0 0. "SPOL,Selects SPI polarity.IMPORTANT NOTICE: Due to the susceptibility of creating a clock glitch which could cause register corruption changing SPHA and SPOL bits should be done in separate writes to this register." "0: The base value of the clock is 0.,1: The base value of the clock is 1."
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group.long 0x2C0++0x7
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line.long 0x0 "MI2CCFG,Controls the configuration of the I2C bus master."
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bitfld.long 0x0 24. "STRDIS,Disable detection of clock stretch events smaller than 1 cycle" "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "SMPCNT,Number of Base clk cycles to wait before sampling the SCL clock to determine if a clock stretch event has occured"
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hexmask.long.byte 0x0 12.--15. 1. "SDAENDLY,Number of IOCLK cycles to delay the SDA output en (all transitions affected). Used to delay data relative to clock"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SCLENDLY,Number of IOCLK cycles to delay the rising edge of the SCL output en (clock will go low on this edge). Used to allow clock shaping."
|
|
newline
|
|
bitfld.long 0x0 6. "MI2CRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
|
|
bitfld.long 0x0 4.--5. "SDADLY,Delay to enable on the SDA output. Values are 0x0-0x3." "0,1,2,3"
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|
newline
|
|
bitfld.long 0x0 2. "ARBEN,Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master this function can be disabled to save clock cycles on I2C transactions" "0: Disable multi-master bus arbitration support for..,1: Enable multi-master bus arbitration support for.."
|
|
bitfld.long 0x0 1. "I2CLSB,Direction of data transmit and receive MSB(0) or LSB(1) first. Default per I2C specification is MSB first. This applies to both read and write data and read data will be bit" "0: Byte data is transmitted MSB first onto the..,1: Byte data is transmitted LSB first onto the.."
|
|
newline
|
|
bitfld.long 0x0 0. "ADDRSZ,Sets the I2C master device address size to either 7b (0) or 10b (1)." "0: Use 7b addressing for I2C master transactions,1: Use 10b addressing for I2C master transactions"
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|
line.long 0x4 "DEVCFG,Contains the I2C device address."
|
|
hexmask.long.word 0x4 0.--9. 1. "DEVADDR,I2C address of the device that the Master will use to target for read/write operations. This can be either a 7b or 10b address."
|
|
group.long 0x388++0x3
|
|
line.long 0x0 "IOMDBG,Debug control"
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|
hexmask.long 0x0 3.--31. 1. "DBGDATA,Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers."
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|
bitfld.long 0x0 2. "APBCLKON,APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "IOCLKON,IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
|
|
bitfld.long 0x0 0. "DBGEN,Debug Enable. Setting bit will enable the update of data within this register otherwise it is clock gated for power savings" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
tree "IOM7"
|
|
base ad:0x40057000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FIFO,Provides direct random access to both input and output fifos. The state of the FIFO is not distured by reading these locations (ie no POP will be done). FIFO0 is accessible from addresses 0x0 - 0x1C. and is used for data outuput from the IOM to.."
|
|
hexmask.long 0x0 0.--31. 1. "FIFO,FIFO direct access. Only locations 0 - 3F will return valid information."
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|
group.long 0x100++0x2F
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|
line.long 0x0 "FIFOPTR,Provides the current valid byte count of data within the FIFO as seen from the internal state machines. FIFO0 is dedicated to outgoing transactions and FIFO1 is dedicated to incoming transactions. All counts are specified in units of bytes."
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|
hexmask.long.byte 0x0 24.--31. 1. "FIFO1REM,The number of remaining data bytes slots currently in FIFO 1 (written by interface read by MCU)"
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|
hexmask.long.byte 0x0 16.--23. 1. "FIFO1SIZ,The number of valid data bytes currently in FIFO 1 (written by interface read by MCU)"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "FIFO0REM,The number of remaining data bytes slots currently in FIFO 0 (written by MCU read by interface)"
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|
hexmask.long.byte 0x0 0.--7. 1. "FIFO0SIZ,The number of valid data bytes currently in the FIFO 0 (written by MCU read by interface)"
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|
line.long 0x4 "FIFOTHR,Sets the threshold values for incoming and outgoing transactions. The threshold values are used to assert the interrupt if enabled. and also used during DMA to set the transfer size as a result of DMATHR trigger."
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|
hexmask.long.byte 0x4 8.--13. 1. "FIFOWTHR,FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the write fifo contains FIFOWTHR free bytes as.."
|
|
hexmask.long.byte 0x4 0.--5. 1. "FIFORTHR,FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the read fifo contains FIFORTHR valid bytes of data as.."
|
|
line.long 0x8 "FIFOPOP,Will advance the internal read pointer of the incoming FIFO (FIFO1) when read. if POPWR is not active. If POPWR is active. a write to this register is needed to advance the internal FIFO pointer."
|
|
hexmask.long 0x8 0.--31. 1. "FIFODOUT,This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0) the fifo read pointer will be advanced by one word as a result of the read."
|
|
line.long 0xC "FIFOPUSH,Will write new data into the outgoing FIFO and advance the internal write pointer."
|
|
hexmask.long 0xC 0.--31. 1. "FIFODIN,This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes)."
|
|
line.long 0x10 "FIFOCTRL,Provides controls for the operation of the internal FIFOs. Contains fields used to control the operation of the POP register. and also controls to reset the internal pointers of the FIFOs."
|
|
bitfld.long 0x10 1. "FIFORSTN,Active low manual reset of the fifo. Write to 0 to reset fifo and then write to 1 to remove the reset." "0,1"
|
|
bitfld.long 0x10 0. "POPWR,Selects the mode in which 'pop' events are done for the fifo read operations. A value of '1' will prevent a pop event on a read operation and will require a write to the FIFOPOP register to create a pop event." "0,1"
|
|
line.long 0x14 "FIFOLOC,Provides a read only value of the current read and write pointers. This register is read only and can be used alogn with the FIFO direct access method to determine the next data to be used for input and output functions."
|
|
hexmask.long.byte 0x14 8.--11. 1. "FIFORPTR,Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1) which is used to store read data returned from external devices during a read operation."
|
|
hexmask.long.byte 0x14 0.--3. 1. "FIFOWPTR,Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0) which is used during write operations to external devices."
|
|
line.long 0x18 "CLKCFG,Provides clock related controls used internal to the BLEIF module. and enablement of 32KHz clock to the BLE Core module. The internal clock sourced is selected via the FSEL and can be further divided by 3 using the DIV3 control."
|
|
hexmask.long.byte 0x18 24.--31. 1. "TOTPER,Clock total clock count minus 1. This provides the total period of the divided clock -1 when the DIVEN is active. The"
|
|
hexmask.long.byte 0x18 16.--23. 1. "LOWPER,Clock low clock count minus 1. This provides the number of clocks the divided clock will be low when the DIVEN = 1."
|
|
newline
|
|
bitfld.long 0x18 12. "DIVEN,Enable clock division by TOTPER and LOWPER" "0: Disable TOTPER division.,1: Enable TOTPER division."
|
|
bitfld.long 0x18 11. "DIV3,Enable divide by 3 of the source IOCLK. Division by 3 is done before the DIVEN programmable divider and if enabled" "0: Select divide by 1.,1: Select divide by 3."
|
|
newline
|
|
bitfld.long 0x18 8.--10. "FSEL,Select the input clock frequency." "0: Selects the minimum power clock. This setting..,1: Selects static 0 as the input clock. Previously..,2: Selects the HFRC 48MHz as the input clock.,3: Selects the HFRC 24MHz as the input clock.,4: Selects the HFRC 12MHz as the input clock.,5: Selects the HFRC 6MHz as the input clock.,6: Selects the HFRC 3MHz as the input clock.,7: Selects the HFRC 1.5MHz as the input clock."
|
|
bitfld.long 0x18 0. "IOCLKEN,Enable for the interface clock. Must be enabled prior to executing any IO operations." "0,1"
|
|
line.long 0x1C "SUBMODCTRL,Provides enable for each submodule. Only a sigle submodule can be enabled at one time."
|
|
bitfld.long 0x1C 9.--11. "SMOD2TYPE,Submodule 2 module type. This is the I2S Master/Slave interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,4: Master/Slave submodule,?,?,7: NOT INSTALLED"
|
|
bitfld.long 0x1C 8. "SMOD2EN,Submodule 2 enable (1) or disable (0)" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 5.--7. "SMOD1TYPE,Submodule 1 module type. This is the I2C Master interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,4: Master/Slave submodule,?,?,7: NOT INSTALLED"
|
|
bitfld.long 0x1C 4. "SMOD1EN,Submodule 1 enable (1) or disable (0)" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 1.--3. "SMOD0TYPE,Submodule 0 module type. This is the SPI Master interface." "0: MSPI submodule,1: I2C Master submodule,2: I2S Master/Slave Module,?,?,?,?,7: NOT INSTALLED"
|
|
bitfld.long 0x1C 0. "SMOD0EN,Submodule 0 enable (1) or disable (0)" "0,1"
|
|
line.long 0x20 "CMD,Writes to this register will start an IO transaction. as well as set various parameters for the command itself. Reads will return the command value written to the CMD register."
|
|
hexmask.long.byte 0x20 24.--31. 1. "OFFSETLO,This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command."
|
|
bitfld.long 0x20 20.--21. "CMDSEL,Command Specific selection information. Not used in Master I2C. Used as CEn select for Master SPI transactions" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x20 8.--19. 1. "TSIZE,Defines the transaction size in bytes. The offset transfer is not included in this size."
|
|
bitfld.long 0x20 7. "CONT,Contine to hold the bus after the current transaction if set to a 1 with a new command issued." "0,1"
|
|
newline
|
|
bitfld.long 0x20 4.--6. "OFFSETCNT,Number of offset bytes to use for the command - 0 1 2 3 4 5 are valid selections. The second (byte 1) third (byte 2) and forth (byte 3) are read from the OFFSETHI register and the low order byte is pulled from this register in the.." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x20 0.--3. 1. "CMD,Command for submodule."
|
|
line.long 0x24 "DCXCTRL,Enables transmission of DCX signal with SPI transactions and selects which CE signals will be used to transmit the DCX signal."
|
|
bitfld.long 0x24 4. "DCXEN,Global enable of the DCX function. Setting to 1 will enable the generation of the DCX signal which will assert when sending the offset bytes of the SPI transaction." "0,1"
|
|
hexmask.long.byte 0x24 0.--3. 1. "DCXSEL,Selects the CE channel used to convey the DCX function. The select is bitwise encoded with bit 0 = 1 enabling CE0 for DCX transmission bit 1 = 1 enableing CE1 for DCX transmission etc. If the CE used for the SPI transaction is set it will be.."
|
|
line.long 0x28 "OFFSETHI,High order bytes of offset for IO transaction"
|
|
hexmask.long 0x28 0.--31. 1. "OFFSETHI,Holds the high order bytes of the byte addressing/offset field to use with IO commands. The number of offset bytes to use is specified in the command register"
|
|
line.long 0x2C "CMDSTAT,Provides staus on the execution of the command currently in progress. The fields in this register will reflect the real time status of the internal state machines and data transfers within the IOM."
|
|
hexmask.long.word 0x2C 8.--19. 1. "CTSIZE,The current number of bytes still to be transferred with this command. This field will count down to zero."
|
|
bitfld.long 0x2C 5.--7. "CMDSTAT,The current status of the command execution." "?,1: Error encountered with command,2: Actively processing command,?,4: Idle state no active command no error,?,6: Command in progress but waiting on data from host,?"
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|
newline
|
|
hexmask.long.byte 0x2C 0.--4. 1. "CCMD,Current command that is being executed; This will update based on the phase of the I2C and will indicate a write operation during transmission of the offset "
|
|
group.long 0x200++0x4B
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 14. "CQERR,Error during command queue operations" "0,1"
|
|
bitfld.long 0x0 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
|
|
bitfld.long 0x0 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0x0 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. Also asserted during I2C write operations when value of 1 expected on bus but 0 is observed. When asserted the I2C state machine will.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x0 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x0 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0x0 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
|
|
bitfld.long 0x0 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 14. "CQERR,Error during command queue operations" "0,1"
|
|
bitfld.long 0x4 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
|
|
bitfld.long 0x4 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0x4 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. Also asserted during I2C write operations when value of 1 expected on bus but 0 is observed. When asserted the I2C state machine will.." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x4 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x4 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0x4 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
|
|
bitfld.long 0x4 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 14. "CQERR,Error during command queue operations" "0,1"
|
|
bitfld.long 0x8 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
|
|
bitfld.long 0x8 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0x8 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. Also asserted during I2C write operations when value of 1 expected on bus but 0 is observed. When asserted the I2C state machine will.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x8 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x8 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0x8 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
|
|
bitfld.long 0x8 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 14. "CQERR,Error during command queue operations" "0,1"
|
|
bitfld.long 0xC 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
|
|
bitfld.long 0xC 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0xC 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. Also asserted during I2C write operations when value of 1 expected on bus but 0 is observed. When asserted the I2C state machine will.." "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0xC 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0xC 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0xC 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
|
|
bitfld.long 0xC 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
|
|
line.long 0x10 "DMATRIGEN,Provides control on which event will trigger the DMA transfer after the DMA operation is setup and enabled. The trigger event will cause a number of bytes (depending on trigger event) to be"
|
|
bitfld.long 0x10 1. "DTHREN,Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes) the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO and will transfer (WTHR/4) number of words" "0,1"
|
|
bitfld.long 0x10 0. "DCMDCMPEN,Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered the number of words transferred will be the lesser of the remaining TOTCOUNT bytes or" "0,1"
|
|
line.long 0x14 "DMATRIGSTAT,Provides the status of trigger events that have occurred for the transaction. Some of the bits are read only and some can be reset via a write of 0."
|
|
bitfld.long 0x14 2. "DTOTCMP,DMA triggered when DCMDCMP = 0 and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is" "0,1"
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bitfld.long 0x14 1. "DTHR,Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA." "0,1"
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bitfld.long 0x14 0. "DCMDCMP,Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA." "0,1"
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|
line.long 0x18 "DMACFG,Configuration control of the DMA process. including the direction of DMA. and enablement of DMA"
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|
bitfld.long 0x18 9. "DPWROFF,Power off module after DMA is complete. If this bit is active the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain power down will not be performed." "0: Power off disabled,1: Power off enabled"
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bitfld.long 0x18 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x18 1. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction. To be..,1: Memory to Peripheral transaction. To be set when.."
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bitfld.long 0x18 0. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable DMA Function,1: Enable DMA Function"
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line.long 0x1C "DMATOTCOUNT,Contains the number of bytes to be transferred for this DMA transaction. This register is decremented as the data is transferred. and will be 0 at the completion of the DMA operation."
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hexmask.long.word 0x1C 0.--11. 1. "TOTCOUNT,Triggered DMA from Command complete event occured. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."
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line.long 0x20 "DMATARGADDR,The source or destination address internal the SRAM for the DMA data. For write operations. this can only be SRAM data (ADDR bit 28 = 1); For read operations. this can ve either SRAM or FLASH (ADDR bit 28 = 0)"
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hexmask.long 0x20 0.--28. 1. "TARGADDR,Bits [28:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment and does not have to be word aligned. In cases of non-word aligned addresses the DMA logic will take care for ensuring only.."
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|
line.long 0x24 "DMASTAT,Status of the DMA operation currently in progress."
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bitfld.long 0x24 2. "DMAERR,DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set this bit will remain set until cleared by software." "0,1"
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bitfld.long 0x24 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0 and will also be cleared when a new DMA is started." "0,1"
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bitfld.long 0x24 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
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line.long 0x28 "CQCFG,Controls parameters and options for execution of the command queue operation. To enable command queue. create this in memory. set the address. and enable it with a write to CQEN"
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bitfld.long 0x28 2.--3. "MSPIFLGSEL,Selects the MPSI modules used for sourcing the CQFLAG [11:8]." "0: Selects MPSI0 as source of signals used in..,1: Selects MPSI1 as source of signals used in..,2: Selects MPSI2 as source of signals used in..,?"
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bitfld.long 0x28 1. "CQPRI,Sets the Priority of the command queue dma request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x28 0. "CQEN,Command queue enable. When set will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled" "0: Disable CQ Function,1: Enable CQ Function"
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line.long 0x2C "CQADDR,The SRAM address which will be fetched next execution of the CQ operation. This register is updated as the CQ operation progresses. and is the live version of the register. The register can also be"
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hexmask.long 0x2C 2.--28. 1. "CQADDR,Bits 28:2 of target byte address for source of CQ . The buffer must be aligned on a word boundary"
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line.long 0x30 "CQSTAT,Provides the status of the command queue operation. If the command queue is disabled. these bits will be cleared. The bits are read only"
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bitfld.long 0x30 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
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bitfld.long 0x30 1. "CQPAUSED,Command queue operation is currently paused." "0,1"
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bitfld.long 0x30 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
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line.long 0x34 "CQFLAGS,Command Queue Flag"
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hexmask.long.word 0x34 16.--31. 1. "CQIRQMASK,Mask the bits used to generate the command queue interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE"
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hexmask.long.word 0x34 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
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line.long 0x38 "CQSETCLEAR,Set/Clear the command queue software pause flags on a per-bit basis. Contains 3 fields. allowing for setting. clearing or toggling the value in the software flags. Priority when the same bit"
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hexmask.long.byte 0x38 16.--23. 1. "CQFCLR,Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x38 8.--15. 1. "CQFTGL,Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x38 0.--7. 1. "CQFSET,Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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line.long 0x3C "CQPAUSEEN,Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the CQFLAG register is '1'. CQ processing will halt until either value is changed to '0'."
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hexmask.long.word 0x3C 0.--15. 1. "CQPEN,Enables the specified event to pause command processing when active"
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line.long 0x40 "CQCURIDX,Current index value. targeted to be written by register write operations within the command queue. This is compared to the CQENDIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and"
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hexmask.long.byte 0x40 0.--7. 1. "CQCURIDX,Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x44 "CQENDIDX,End index value. targeted to be written by software to indicate the last valid register pair contained within the command queue. rgister write operations within the command queue."
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hexmask.long.byte 0x44 0.--7. 1. "CQENDIDX,Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x48 "STATUS,IOM Module Status"
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bitfld.long 0x48 2. "IDLEST,indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to holdoffs from data availability or as the command gets propagated into the logic from the registers." "?,1: The I/O state machine is in the idle state."
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bitfld.long 0x48 1. "CMDACT,Indicates if the active I/O Command is currently processing a transaction or command is complete but the FIFO pointers are still syncronizing internally. This bit will go high at" "?,1: An I/O command is active. Indicates the active.."
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bitfld.long 0x48 0. "ERR,Bit has been deprecated. Please refer to the other error indicators. This will always return 0." "?,1: Bit has been deprecated and will always return 0."
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group.long 0x280++0x3
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line.long 0x0 "MSPICFG,Controls the configuration of the SPI master module. including POL/PHA. LSB. flow control. and delays for MISO and MOSI"
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bitfld.long 0x0 30. "MSPIRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 27.--29. "DOUTDLY,Delay tap to use for the output signal (MOSI). This give more hold time on the output data" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 24.--26. "DINDLY,Delay tap to use for the input signal (MISO). This gives more hold time on the input data." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "SPILSB,Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first." "0: Send and receive MSB bit first,1: Send and receive LSB bit first"
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bitfld.long 0x0 22. "RDFCPOL,Selects the read flow control signal polarity." "0: Flow control signal high creates flow control.,1: Flow control signal low creates flow control."
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bitfld.long 0x0 21. "WTFCPOL,selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 will allow a IRQ=1 to pause transfers)." "0: Flow control signal high(1) creates flow control..,1: Flow control signal low(0) creates flow control.."
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bitfld.long 0x0 20. "WTFCIRQ,Selects the write mode flow control signal." "0: MISO is used as the write mode flow control..,1: IRQ is used as the write mode flow control signal."
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bitfld.long 0x0 18. "MOSIINV,Inverts MOSI when flow control is enabled." "0: MOSI is set to 0 in read mode and 1 in write mode.,1: MOSI is set to 1 in read mode and 0 in write mode."
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bitfld.long 0x0 17. "RDFC,Enables read mode flow control." "0: Read mode flow control disabled.,1: Read mode flow control enabled."
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bitfld.long 0x0 16. "WTFC,enables write mode flow control." "0: Write mode flow control disabled.,1: Write mode flow control enabled."
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bitfld.long 0x0 2. "FULLDUP,Enables full duplex mode for Master SPI write operations. Data will be captured simultaneously into the read fifo" "0,1"
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bitfld.long 0x0 1. "SPHA,Selects SPI phase.IMPORTANT NOTICE: Due to the susceptibility of creating a clock glitch which could cause register corruption changing SPHA and SPOL bits should be done in separate writes to this register." "0: Sample on the leading (first) clock edge.,1: Sample on the trailing (second) clock edge."
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bitfld.long 0x0 0. "SPOL,Selects SPI polarity.IMPORTANT NOTICE: Due to the susceptibility of creating a clock glitch which could cause register corruption changing SPHA and SPOL bits should be done in separate writes to this register." "0: The base value of the clock is 0.,1: The base value of the clock is 1."
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group.long 0x2C0++0x7
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line.long 0x0 "MI2CCFG,Controls the configuration of the I2C bus master."
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bitfld.long 0x0 24. "STRDIS,Disable detection of clock stretch events smaller than 1 cycle" "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "SMPCNT,Number of Base clk cycles to wait before sampling the SCL clock to determine if a clock stretch event has occured"
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hexmask.long.byte 0x0 12.--15. 1. "SDAENDLY,Number of IOCLK cycles to delay the SDA output en (all transitions affected). Used to delay data relative to clock"
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hexmask.long.byte 0x0 8.--11. 1. "SCLENDLY,Number of IOCLK cycles to delay the rising edge of the SCL output en (clock will go low on this edge). Used to allow clock shaping."
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bitfld.long 0x0 6. "MI2CRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 4.--5. "SDADLY,Delay to enable on the SDA output. Values are 0x0-0x3." "0,1,2,3"
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bitfld.long 0x0 2. "ARBEN,Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master this function can be disabled to save clock cycles on I2C transactions" "0: Disable multi-master bus arbitration support for..,1: Enable multi-master bus arbitration support for.."
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bitfld.long 0x0 1. "I2CLSB,Direction of data transmit and receive MSB(0) or LSB(1) first. Default per I2C specification is MSB first. This applies to both read and write data and read data will be bit" "0: Byte data is transmitted MSB first onto the..,1: Byte data is transmitted LSB first onto the.."
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newline
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bitfld.long 0x0 0. "ADDRSZ,Sets the I2C master device address size to either 7b (0) or 10b (1)." "0: Use 7b addressing for I2C master transactions,1: Use 10b addressing for I2C master transactions"
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line.long 0x4 "DEVCFG,Contains the I2C device address."
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hexmask.long.word 0x4 0.--9. 1. "DEVADDR,I2C address of the device that the Master will use to target for read/write operations. This can be either a 7b or 10b address."
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group.long 0x388++0x3
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line.long 0x0 "IOMDBG,Debug control"
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hexmask.long 0x0 3.--31. 1. "DBGDATA,Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers."
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bitfld.long 0x0 2. "APBCLKON,APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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newline
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bitfld.long 0x0 1. "IOCLKON,IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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bitfld.long 0x0 0. "DBGEN,Debug Enable. Setting bit will enable the update of data within this register otherwise it is clock gated for power savings" "0,1"
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tree.end
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endif
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sif (cpuis("AMA4B2KL")||cpuis("AMA4B2KP")||cpuis("AMAP42KL")||cpuis("AMAP42KP"))
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tree "IOM0"
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base ad:0x40050000
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group.long 0x0++0x3
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line.long 0x0 "FIFO,Provides direct random access to both input and output fifos. The state of the FIFO is not distured by reading these locations (ie no POP will be done). FIFO0 is accessible from addresses 0x0 - 0x1C. and is used for data outuput from the IOM to.."
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hexmask.long 0x0 0.--31. 1. "FIFO,FIFO direct access. Only locations 0 - 3F will return valid information."
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group.long 0x100++0x2F
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line.long 0x0 "FIFOPTR,Provides the current valid byte count of data within the FIFO as seen from the internal state machines. FIFO0 is dedicated to outgoing transactions and FIFO1 is dedicated to incoming transactions. All counts are specified in units of bytes."
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hexmask.long.byte 0x0 24.--31. 1. "FIFO1REM,The number of remaining data bytes slots currently in FIFO 1 (written by interface read by MCU)"
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hexmask.long.byte 0x0 16.--23. 1. "FIFO1SIZ,The number of valid data bytes currently in FIFO 1 (written by interface read by MCU)"
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|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "FIFO0REM,The number of remaining data bytes slots currently in FIFO 0 (written by MCU read by interface)"
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hexmask.long.byte 0x0 0.--7. 1. "FIFO0SIZ,The number of valid data bytes currently in the FIFO 0 (written by MCU read by interface)"
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line.long 0x4 "FIFOTHR,Sets the threshold values for incoming and outgoing transactions. The threshold values are used to assert the interrupt if enabled. and also used during DMA to set the transfer size as a result of DMATHR trigger."
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hexmask.long.byte 0x4 8.--13. 1. "FIFOWTHR,FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the write fifo contains FIFOWTHR free bytes as.."
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|
hexmask.long.byte 0x4 0.--5. 1. "FIFORTHR,FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the read fifo contains FIFORTHR valid bytes of data as.."
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|
line.long 0x8 "FIFOPOP,Will advance the internal read pointer of the incoming FIFO (FIFO1) when read. if POPWR is not active. If POPWR is active. a write to this register is needed to advance the internal FIFO pointer."
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hexmask.long 0x8 0.--31. 1. "FIFODOUT,This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0) the fifo read pointer will be advanced by one word as a result of the read."
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line.long 0xC "FIFOPUSH,Will write new data into the outgoing FIFO and advance the internal write pointer."
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hexmask.long 0xC 0.--31. 1. "FIFODIN,This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes)."
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line.long 0x10 "FIFOCTRL,Provides controls for the operation of the internal FIFOs. Contains fields used to control the operation of the POP register. and also controls to reset the internal pointers of the FIFOs."
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bitfld.long 0x10 1. "FIFORSTN,Active low manual reset of the fifo. Write to 0 to reset fifo and then write to 1 to remove the reset." "0,1"
|
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bitfld.long 0x10 0. "POPWR,Selects the mode in which 'pop' events are done for the fifo read operations. A value of '1' will prevent a pop event on a read operation and will require a write to the FIFOPOP register to create a pop event." "0,1"
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line.long 0x14 "FIFOLOC,Provides a read only value of the current read and write pointers. This register is read only and can be used alogn with the FIFO direct access method to determine the next data to be used for input and output functions."
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hexmask.long.byte 0x14 8.--11. 1. "FIFORPTR,Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1) which is used to store read data returned from external devices during a read operation."
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hexmask.long.byte 0x14 0.--3. 1. "FIFOWPTR,Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0) which is used during write operations to external devices."
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line.long 0x18 "CLKCFG,Provides clock related controls used internal to the BLEIF module. and enablement of 32KHz clock to the BLE Core module. The internal clock sourced is selected via the FSEL and can be further divided by 3 using the DIV3 control."
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hexmask.long.byte 0x18 24.--31. 1. "TOTPER,Clock total clock count minus 1. This provides the total period of the divided clock -1 when the DIVEN is active. The"
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hexmask.long.byte 0x18 16.--23. 1. "LOWPER,Clock low clock count minus 1. This provides the number of clocks the divided clock will be low when the DIVEN = 1."
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newline
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bitfld.long 0x18 12. "DIVEN,Enable clock division by TOTPER and LOWPER" "0: Disable TOTPER division.,1: Enable TOTPER division."
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bitfld.long 0x18 11. "DIV3,Enable divide by 3 of the source IOCLK. Division by 3 is done before the DIVEN programmable divider and if enabled" "0: Select divide by 1.,1: Select divide by 3."
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newline
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bitfld.long 0x18 8.--10. "FSEL,Select the input clock frequency." "0: Selects the minimum power clock. This setting..,1: Selects static 0 as the input clock. Previously..,2: Selects the HFRC 48MHz as the input clock.,3: Selects the HFRC 24MHz as the input clock.,4: Selects the HFRC 12MHz as the input clock.,5: Selects the HFRC 6MHz as the input clock.,6: Selects the HFRC 3MHz as the input clock.,7: Selects the HFRC 1.5MHz as the input clock."
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bitfld.long 0x18 0. "IOCLKEN,Enable for the interface clock. Must be enabled prior to executing any IO operations." "0,1"
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|
line.long 0x1C "SUBMODCTRL,Provides enable for each submodule. Only a sigle submodule can be enabled at one time."
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bitfld.long 0x1C 9.--11. "SMOD2TYPE,Submodule 2 module type. This is the I2S Master/Slave interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,4: Master/Slave submodule,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 8. "SMOD2EN,Submodule 2 enable (1) or disable (0)" "0,1"
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newline
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bitfld.long 0x1C 5.--7. "SMOD1TYPE,Submodule 1 module type. This is the I2C Master interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,4: Master/Slave submodule,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 4. "SMOD1EN,Submodule 1 enable (1) or disable (0)" "0,1"
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|
newline
|
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bitfld.long 0x1C 1.--3. "SMOD0TYPE,Submodule 0 module type. This is the SPI Master interface." "0: MSPI submodule,1: I2C Master submodule,2: I2S Master/Slave Module,?,?,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 0. "SMOD0EN,Submodule 0 enable (1) or disable (0)" "0,1"
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|
line.long 0x20 "CMD,Writes to this register will start an IO transaction. as well as set various parameters for the command itself. Reads will return the command value written to the CMD register."
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hexmask.long.byte 0x20 24.--31. 1. "OFFSETLO,This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command."
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bitfld.long 0x20 20.--21. "CMDSEL,Command Specific selection information. Not used in Master I2C. Used as CEn select for Master SPI transactions" "0,1,2,3"
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hexmask.long.word 0x20 8.--19. 1. "TSIZE,Defines the transaction size in bytes. The offset transfer is not included in this size."
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|
bitfld.long 0x20 7. "CONT,Contine to hold the bus after the current transaction if set to a 1 with a new command issued." "0,1"
|
|
newline
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bitfld.long 0x20 4.--6. "OFFSETCNT,Number of offset bytes to use for the command - 0 1 2 3 4 5 are valid selections. The second (byte 1) third (byte 2) and forth (byte 3) are read from the OFFSETHI register and the low order byte is pulled from this register in the.." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x20 0.--3. 1. "CMD,Command for submodule."
|
|
line.long 0x24 "DCXCTRL,Enables transmission of DCX signal with SPI transactions and selects which CE signals will be used to transmit the DCX signal."
|
|
bitfld.long 0x24 4. "DCXEN,Global enable of the DCX function. Setting to 1 will enable the generation of the DCX signal which will assert when sending the offset bytes of the SPI transaction." "0,1"
|
|
hexmask.long.byte 0x24 0.--3. 1. "DCXSEL,Selects the CE channel used to convey the DCX function. The select is bitwise encoded with bit 0 = 1 enabling CE0 for DCX transmission bit 1 = 1 enableing CE1 for DCX transmission etc. If the CE used for the SPI transaction is set it will be.."
|
|
line.long 0x28 "OFFSETHI,High order bytes of offset for IO transaction"
|
|
hexmask.long 0x28 0.--31. 1. "OFFSETHI,Holds the high order bytes of the byte addressing/offset field to use with IO commands. The number of offset bytes to use is specified in the command register"
|
|
line.long 0x2C "CMDSTAT,Provides staus on the execution of the command currently in progress. The fields in this register will reflect the real time status of the internal state machines and data transfers within the IOM."
|
|
hexmask.long.word 0x2C 8.--19. 1. "CTSIZE,The current number of bytes still to be transferred with this command. This field will count down to zero."
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|
bitfld.long 0x2C 5.--7. "CMDSTAT,The current status of the command execution." "?,1: Error encountered with command,2: Actively processing command,?,4: Idle state no active command no error,?,6: Command in progress but waiting on data from host,?"
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hexmask.long.byte 0x2C 0.--4. 1. "CCMD,current command that is being executed"
|
|
group.long 0x200++0x4B
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 14. "CQERR,Error during command queue operations" "0,1"
|
|
bitfld.long 0x0 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x0 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x0 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x0 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x0 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0x0 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x0 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x0 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x0 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x0 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x0 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0x0 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0x0 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x0 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
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bitfld.long 0x4 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x4 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x4 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x4 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x4 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x4 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0x4 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x4 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x4 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x4 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x4 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x4 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0x4 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0x4 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x4 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
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bitfld.long 0x8 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x8 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x8 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x8 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x8 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x8 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0x8 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x8 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x8 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x8 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x8 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x8 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0x8 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0x8 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x8 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
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bitfld.long 0xC 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0xC 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0xC 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0xC 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0xC 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0xC 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0xC 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0xC 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0xC 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0xC 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0xC 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0xC 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0xC 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0xC 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0xC 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x10 "DMATRIGEN,Provides control on which event will trigger the DMA transfer after the DMA operation is setup and enabled. The trigger event will cause a number of bytes (depending on trigger event) to be"
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bitfld.long 0x10 1. "DTHREN,Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes) the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO and will transfer (WTHR/4) number of words" "0,1"
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bitfld.long 0x10 0. "DCMDCMPEN,Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered the number of words transferred will be the lesser of the remaining TOTCOUNT bytes or" "0,1"
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line.long 0x14 "DMATRIGSTAT,Provides the status of trigger events that have occurred for the transaction. Some of the bits are read only and some can be reset via a write of 0."
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bitfld.long 0x14 2. "DTOTCMP,DMA triggered when DCMDCMP = 0 and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is" "0,1"
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bitfld.long 0x14 1. "DTHR,Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA." "0,1"
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bitfld.long 0x14 0. "DCMDCMP,Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA." "0,1"
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line.long 0x18 "DMACFG,Configuration control of the DMA process. including the direction of DMA. and enablement of DMA"
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bitfld.long 0x18 9. "DPWROFF,Power off module after DMA is complete. If this bit is active the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain power down will not be performed." "0: Power off disabled,1: Power off enabled"
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bitfld.long 0x18 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x18 1. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction. To be..,1: Memory to Peripheral transaction. To be set when.."
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bitfld.long 0x18 0. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable DMA Function,1: Enable DMA Function"
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line.long 0x1C "DMATOTCOUNT,Contains the number of bytes to be transferred for this DMA transaction. This register is decremented as the data is transferred. and will be 0 at the completion of the DMA operation."
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hexmask.long.word 0x1C 0.--11. 1. "TOTCOUNT,Triggered DMA from Command complete event occured. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."
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line.long 0x20 "DMATARGADDR,The source or destination address internal the SRAM for the DMA data. For write operations. this can only be SRAM data (ADDR bit 28 = 1); For read operations. this can ve either SRAM or FLASH (ADDR bit 28 = 0)"
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hexmask.long 0x20 0.--28. 1. "TARGADDR,Bits [28:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment and does not have to be word aligned. In cases of non-word aligned addresses the DMA logic will take care for ensuring only.."
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line.long 0x24 "DMASTAT,Status of the DMA operation currently in progress."
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bitfld.long 0x24 2. "DMAERR,DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set this bit will remain set until cleared by software." "0,1"
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bitfld.long 0x24 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0 and will also be cleared when a new DMA is started." "0,1"
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bitfld.long 0x24 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
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line.long 0x28 "CQCFG,Controls parameters and options for execution of the command queue operation. To enable command queue. create this in memory. set the address. and enable it with a write to CQEN"
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bitfld.long 0x28 2.--3. "MSPIFLGSEL,Selects the MPSI modules used for sourcing the CQFLAG [11:8]." "0: Selects MPSI0 as source of signals used in..,1: Selects MPSI1 as source of signals used in..,2: Selects MPSI2 as source of signals used in..,?"
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bitfld.long 0x28 1. "CQPRI,Sets the Priority of the command queue dma request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x28 0. "CQEN,Command queue enable. When set will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled" "0: Disable CQ Function,1: Enable CQ Function"
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line.long 0x2C "CQADDR,The SRAM address which will be fetched next execution of the CQ operation. This register is updated as the CQ operation progresses. and is the live version of the register. The register can also be"
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hexmask.long 0x2C 2.--28. 1. "CQADDR,Bits 28:2 of target byte address for source of CQ . The buffer must be aligned on a word boundary"
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line.long 0x30 "CQSTAT,Provides the status of the command queue operation. If the command queue is disabled. these bits will be cleared. The bits are read only"
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bitfld.long 0x30 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
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bitfld.long 0x30 1. "CQPAUSED,Command queue operation is currently paused." "0,1"
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bitfld.long 0x30 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
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line.long 0x34 "CQFLAGS,Command Queue Flag"
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hexmask.long.word 0x34 16.--31. 1. "CQIRQMASK,Mask the bits used to generate the command queue interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE"
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hexmask.long.word 0x34 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
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line.long 0x38 "CQSETCLEAR,Set/Clear the command queue software pause flags on a per-bit basis. Contains 3 fields. allowing for setting. clearing or toggling the value in the software flags. Priority when the same bit"
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hexmask.long.byte 0x38 16.--23. 1. "CQFCLR,Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x38 8.--15. 1. "CQFTGL,Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x38 0.--7. 1. "CQFSET,Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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line.long 0x3C "CQPAUSEEN,Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the CQFLAG register is '1'. CQ processing will halt until either value is changed to '0'."
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hexmask.long.word 0x3C 0.--15. 1. "CQPEN,Enables the specified event to pause command processing when active"
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line.long 0x40 "CQCURIDX,Current index value. targeted to be written by register write operations within the command queue. This is compared to the CQENDIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and"
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hexmask.long.byte 0x40 0.--7. 1. "CQCURIDX,Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x44 "CQENDIDX,End index value. targeted to be written by software to indicate the last valid register pair contained within the command queue. rgister write operations within the command queue."
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hexmask.long.byte 0x44 0.--7. 1. "CQENDIDX,Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x48 "STATUS,IOM Module Status"
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bitfld.long 0x48 2. "IDLEST,indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to holdoffs from data availability or as the command gets propagated into the logic from the registers." "0: The I/O state machine is in the non-idle/run..,1: The I/O state machine is in the idle state."
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bitfld.long 0x48 1. "CMDACT,Indicates if the active I/O Command is currently processing a transaction or command is complete but the FIFO pointers are still syncronizing internally. This bit will go high at" "0: An I/O command is inactive. Indicating that the..,1: An I/O command is active. Indicates the active.."
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bitfld.long 0x48 0. "ERR,Bit has been deprecated. Please refer to the other error indicators. This will always return 0." "0: Default value.,1: Bit has been deprecated and will always return 0."
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group.long 0x280++0x3
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line.long 0x0 "MSPICFG,Controls the configuration of the SPI master module. including POL/PHA. LSB. flow control. and delays for MISO and MOSI"
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bitfld.long 0x0 30. "MSPIRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 27.--29. "DOUTDLY,Delay tap to use for the output signal (MOSI). This give more hold time on the output data" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 24.--26. "DINDLY,Delay tap to use for the input signal (MISO). This gives more hold time on the input data." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "SPILSB,Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first." "0: Send and receive MSB bit first,1: Send and receive LSB bit first"
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bitfld.long 0x0 22. "RDFCPOL,Selects the read flow control signal polarity." "0: Flow control signal high creates flow control.,1: Flow control signal low creates flow control."
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bitfld.long 0x0 21. "WTFCPOL,selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 will allow a IRQ=1 to pause transfers)." "0: Flow control signal high(1) creates flow control..,1: Flow control signal low(0) creates flow control.."
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bitfld.long 0x0 20. "WTFCIRQ,Selects the write mode flow control signal." "0: MISO is used as the write mode flow control..,1: IRQ is used as the write mode flow control signal."
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bitfld.long 0x0 18. "MOSIINV,Inverts MOSI when flow control is enabled." "0: MOSI is set to 0 in read mode and 1 in write mode.,1: MOSI is set to 1 in read mode and 0 in write mode."
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bitfld.long 0x0 17. "RDFC,Enables read mode flow control." "0: Read mode flow control disabled.,1: Read mode flow control enabled."
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bitfld.long 0x0 16. "WTFC,enables write mode flow control." "0: Write mode flow control disabled.,1: Write mode flow control enabled."
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bitfld.long 0x0 2. "FULLDUP,Enables full duplex mode for Master SPI write operations. Data will be captured simultaneously into the read fifo" "0,1"
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bitfld.long 0x0 1. "SPHA,Selects SPI phase.IMPORTANT NOTICE: Due to the susceptibility of creating a clock glitch which could cause register corruption changing SPHA and SPOL bits should be done in separate writes to this register." "0: Sample on the leading (first) clock edge.,1: Sample on the trailing (second) clock edge."
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bitfld.long 0x0 0. "SPOL,Selects SPI polarity.IMPORTANT NOTICE: Due to the susceptibility of creating a clock glitch which could cause register corruption changing SPHA and SPOL bits should be done in separate writes to this register." "0: The base value of the clock is 0.,1: The base value of the clock is 1."
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group.long 0x2C0++0x7
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line.long 0x0 "MI2CCFG,Controls the configuration of the I2C bus master."
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bitfld.long 0x0 24. "STRDIS,Disable detection of clock stretch events smaller than 1 cycle" "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "SMPCNT,Number of Base clk cycles to wait before sampling the SCL clock to determine if a clock stretch event has occured"
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hexmask.long.byte 0x0 12.--15. 1. "SDAENDLY,Number of IOCLK cycles to delay the SDA output en (all transitions affected). Used to delay data relative to clock"
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hexmask.long.byte 0x0 8.--11. 1. "SCLENDLY,Number of IOCLK cycles to delay the rising edge of the SCL output en (clock will go low on this edge). Used to allow clock shaping."
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bitfld.long 0x0 6. "MI2CRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 4.--5. "SDADLY,Delay to enable on the SDA output. Values are 0x0-0x3." "0,1,2,3"
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bitfld.long 0x0 2. "ARBEN,Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master this function can be disabled to save clock cycles on I2C transactions" "0: Disable multi-master bus arbitration support for..,1: Enable multi-master bus arbitration support for.."
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bitfld.long 0x0 1. "I2CLSB,Direction of data transmit and receive MSB(0) or LSB(1) first. Default per I2C specification is MSB first. This applies to both read and write data and read data will be bit" "0: Byte data is transmitted MSB first onto the..,1: Byte data is transmitted LSB first onto the.."
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bitfld.long 0x0 0. "ADDRSZ,Sets the I2C master device address size to either 7b (0) or 10b (1)." "0: Use 7b addressing for I2C master transactions,1: Use 10b addressing for I2C master transactions"
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line.long 0x4 "DEVCFG,Contains the I2C device address."
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hexmask.long.word 0x4 0.--9. 1. "DEVADDR,I2C address of the device that the Master will use to target for read/write operations. This can be either a 7b or 10b address."
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group.long 0x388++0x3
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line.long 0x0 "IOMDBG,Debug control"
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|
hexmask.long 0x0 3.--31. 1. "DBGDATA,Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers."
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|
bitfld.long 0x0 2. "APBCLKON,APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "IOCLKON,IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
|
|
bitfld.long 0x0 0. "DBGEN,Debug Enable. Setting bit will enable the update of data within this register otherwise it is clock gated for power savings" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMA4B2KP")||cpuis("AMAP42KL")||cpuis("AMAP42KP"))
|
|
tree "IOM1"
|
|
base ad:0x40051000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FIFO,Provides direct random access to both input and output fifos. The state of the FIFO is not distured by reading these locations (ie no POP will be done). FIFO0 is accessible from addresses 0x0 - 0x1C. and is used for data outuput from the IOM to.."
|
|
hexmask.long 0x0 0.--31. 1. "FIFO,FIFO direct access. Only locations 0 - 3F will return valid information."
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|
group.long 0x100++0x2F
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|
line.long 0x0 "FIFOPTR,Provides the current valid byte count of data within the FIFO as seen from the internal state machines. FIFO0 is dedicated to outgoing transactions and FIFO1 is dedicated to incoming transactions. All counts are specified in units of bytes."
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|
hexmask.long.byte 0x0 24.--31. 1. "FIFO1REM,The number of remaining data bytes slots currently in FIFO 1 (written by interface read by MCU)"
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|
hexmask.long.byte 0x0 16.--23. 1. "FIFO1SIZ,The number of valid data bytes currently in FIFO 1 (written by interface read by MCU)"
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|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "FIFO0REM,The number of remaining data bytes slots currently in FIFO 0 (written by MCU read by interface)"
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|
hexmask.long.byte 0x0 0.--7. 1. "FIFO0SIZ,The number of valid data bytes currently in the FIFO 0 (written by MCU read by interface)"
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|
line.long 0x4 "FIFOTHR,Sets the threshold values for incoming and outgoing transactions. The threshold values are used to assert the interrupt if enabled. and also used during DMA to set the transfer size as a result of DMATHR trigger."
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|
hexmask.long.byte 0x4 8.--13. 1. "FIFOWTHR,FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the write fifo contains FIFOWTHR free bytes as.."
|
|
hexmask.long.byte 0x4 0.--5. 1. "FIFORTHR,FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the read fifo contains FIFORTHR valid bytes of data as.."
|
|
line.long 0x8 "FIFOPOP,Will advance the internal read pointer of the incoming FIFO (FIFO1) when read. if POPWR is not active. If POPWR is active. a write to this register is needed to advance the internal FIFO pointer."
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|
hexmask.long 0x8 0.--31. 1. "FIFODOUT,This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0) the fifo read pointer will be advanced by one word as a result of the read."
|
|
line.long 0xC "FIFOPUSH,Will write new data into the outgoing FIFO and advance the internal write pointer."
|
|
hexmask.long 0xC 0.--31. 1. "FIFODIN,This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes)."
|
|
line.long 0x10 "FIFOCTRL,Provides controls for the operation of the internal FIFOs. Contains fields used to control the operation of the POP register. and also controls to reset the internal pointers of the FIFOs."
|
|
bitfld.long 0x10 1. "FIFORSTN,Active low manual reset of the fifo. Write to 0 to reset fifo and then write to 1 to remove the reset." "0,1"
|
|
bitfld.long 0x10 0. "POPWR,Selects the mode in which 'pop' events are done for the fifo read operations. A value of '1' will prevent a pop event on a read operation and will require a write to the FIFOPOP register to create a pop event." "0,1"
|
|
line.long 0x14 "FIFOLOC,Provides a read only value of the current read and write pointers. This register is read only and can be used alogn with the FIFO direct access method to determine the next data to be used for input and output functions."
|
|
hexmask.long.byte 0x14 8.--11. 1. "FIFORPTR,Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1) which is used to store read data returned from external devices during a read operation."
|
|
hexmask.long.byte 0x14 0.--3. 1. "FIFOWPTR,Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0) which is used during write operations to external devices."
|
|
line.long 0x18 "CLKCFG,Provides clock related controls used internal to the BLEIF module. and enablement of 32KHz clock to the BLE Core module. The internal clock sourced is selected via the FSEL and can be further divided by 3 using the DIV3 control."
|
|
hexmask.long.byte 0x18 24.--31. 1. "TOTPER,Clock total clock count minus 1. This provides the total period of the divided clock -1 when the DIVEN is active. The"
|
|
hexmask.long.byte 0x18 16.--23. 1. "LOWPER,Clock low clock count minus 1. This provides the number of clocks the divided clock will be low when the DIVEN = 1."
|
|
newline
|
|
bitfld.long 0x18 12. "DIVEN,Enable clock division by TOTPER and LOWPER" "0: Disable TOTPER division.,1: Enable TOTPER division."
|
|
bitfld.long 0x18 11. "DIV3,Enable divide by 3 of the source IOCLK. Division by 3 is done before the DIVEN programmable divider and if enabled" "0: Select divide by 1.,1: Select divide by 3."
|
|
newline
|
|
bitfld.long 0x18 8.--10. "FSEL,Select the input clock frequency." "0: Selects the minimum power clock. This setting..,1: Selects static 0 as the input clock. Previously..,2: Selects the HFRC 48MHz as the input clock.,3: Selects the HFRC 24MHz as the input clock.,4: Selects the HFRC 12MHz as the input clock.,5: Selects the HFRC 6MHz as the input clock.,6: Selects the HFRC 3MHz as the input clock.,7: Selects the HFRC 1.5MHz as the input clock."
|
|
bitfld.long 0x18 0. "IOCLKEN,Enable for the interface clock. Must be enabled prior to executing any IO operations." "0,1"
|
|
line.long 0x1C "SUBMODCTRL,Provides enable for each submodule. Only a sigle submodule can be enabled at one time."
|
|
bitfld.long 0x1C 9.--11. "SMOD2TYPE,Submodule 2 module type. This is the I2S Master/Slave interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,4: Master/Slave submodule,?,?,7: NOT INSTALLED"
|
|
bitfld.long 0x1C 8. "SMOD2EN,Submodule 2 enable (1) or disable (0)" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 5.--7. "SMOD1TYPE,Submodule 1 module type. This is the I2C Master interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,4: Master/Slave submodule,?,?,7: NOT INSTALLED"
|
|
bitfld.long 0x1C 4. "SMOD1EN,Submodule 1 enable (1) or disable (0)" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 1.--3. "SMOD0TYPE,Submodule 0 module type. This is the SPI Master interface." "0: MSPI submodule,1: I2C Master submodule,2: I2S Master/Slave Module,?,?,?,?,7: NOT INSTALLED"
|
|
bitfld.long 0x1C 0. "SMOD0EN,Submodule 0 enable (1) or disable (0)" "0,1"
|
|
line.long 0x20 "CMD,Writes to this register will start an IO transaction. as well as set various parameters for the command itself. Reads will return the command value written to the CMD register."
|
|
hexmask.long.byte 0x20 24.--31. 1. "OFFSETLO,This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command."
|
|
bitfld.long 0x20 20.--21. "CMDSEL,Command Specific selection information. Not used in Master I2C. Used as CEn select for Master SPI transactions" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x20 8.--19. 1. "TSIZE,Defines the transaction size in bytes. The offset transfer is not included in this size."
|
|
bitfld.long 0x20 7. "CONT,Contine to hold the bus after the current transaction if set to a 1 with a new command issued." "0,1"
|
|
newline
|
|
bitfld.long 0x20 4.--6. "OFFSETCNT,Number of offset bytes to use for the command - 0 1 2 3 4 5 are valid selections. The second (byte 1) third (byte 2) and forth (byte 3) are read from the OFFSETHI register and the low order byte is pulled from this register in the.." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x20 0.--3. 1. "CMD,Command for submodule."
|
|
line.long 0x24 "DCXCTRL,Enables transmission of DCX signal with SPI transactions and selects which CE signals will be used to transmit the DCX signal."
|
|
bitfld.long 0x24 4. "DCXEN,Global enable of the DCX function. Setting to 1 will enable the generation of the DCX signal which will assert when sending the offset bytes of the SPI transaction." "0,1"
|
|
hexmask.long.byte 0x24 0.--3. 1. "DCXSEL,Selects the CE channel used to convey the DCX function. The select is bitwise encoded with bit 0 = 1 enabling CE0 for DCX transmission bit 1 = 1 enableing CE1 for DCX transmission etc. If the CE used for the SPI transaction is set it will be.."
|
|
line.long 0x28 "OFFSETHI,High order bytes of offset for IO transaction"
|
|
hexmask.long 0x28 0.--31. 1. "OFFSETHI,Holds the high order bytes of the byte addressing/offset field to use with IO commands. The number of offset bytes to use is specified in the command register"
|
|
line.long 0x2C "CMDSTAT,Provides staus on the execution of the command currently in progress. The fields in this register will reflect the real time status of the internal state machines and data transfers within the IOM."
|
|
hexmask.long.word 0x2C 8.--19. 1. "CTSIZE,The current number of bytes still to be transferred with this command. This field will count down to zero."
|
|
bitfld.long 0x2C 5.--7. "CMDSTAT,The current status of the command execution." "?,1: Error encountered with command,2: Actively processing command,?,4: Idle state no active command no error,?,6: Command in progress but waiting on data from host,?"
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|
newline
|
|
hexmask.long.byte 0x2C 0.--4. 1. "CCMD,current command that is being executed"
|
|
group.long 0x200++0x4B
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 14. "CQERR,Error during command queue operations" "0,1"
|
|
bitfld.long 0x0 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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|
newline
|
|
bitfld.long 0x0 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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|
bitfld.long 0x0 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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|
newline
|
|
bitfld.long 0x0 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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|
bitfld.long 0x0 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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|
newline
|
|
bitfld.long 0x0 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x0 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x0 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0x0 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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|
newline
|
|
bitfld.long 0x0 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
|
|
bitfld.long 0x0 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 14. "CQERR,Error during command queue operations" "0,1"
|
|
bitfld.long 0x4 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
|
|
bitfld.long 0x4 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0x4 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x4 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x4 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0x4 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
|
|
bitfld.long 0x4 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 14. "CQERR,Error during command queue operations" "0,1"
|
|
bitfld.long 0x8 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
|
|
bitfld.long 0x8 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0x8 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x8 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x8 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0x8 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
|
|
bitfld.long 0x8 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 14. "CQERR,Error during command queue operations" "0,1"
|
|
bitfld.long 0xC 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
|
|
bitfld.long 0xC 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0xC 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0xC 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0xC 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0xC 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
|
|
bitfld.long 0xC 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
|
|
line.long 0x10 "DMATRIGEN,Provides control on which event will trigger the DMA transfer after the DMA operation is setup and enabled. The trigger event will cause a number of bytes (depending on trigger event) to be"
|
|
bitfld.long 0x10 1. "DTHREN,Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes) the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO and will transfer (WTHR/4) number of words" "0,1"
|
|
bitfld.long 0x10 0. "DCMDCMPEN,Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered the number of words transferred will be the lesser of the remaining TOTCOUNT bytes or" "0,1"
|
|
line.long 0x14 "DMATRIGSTAT,Provides the status of trigger events that have occurred for the transaction. Some of the bits are read only and some can be reset via a write of 0."
|
|
bitfld.long 0x14 2. "DTOTCMP,DMA triggered when DCMDCMP = 0 and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is" "0,1"
|
|
bitfld.long 0x14 1. "DTHR,Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA." "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "DCMDCMP,Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA." "0,1"
|
|
line.long 0x18 "DMACFG,Configuration control of the DMA process. including the direction of DMA. and enablement of DMA"
|
|
bitfld.long 0x18 9. "DPWROFF,Power off module after DMA is complete. If this bit is active the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain power down will not be performed." "0: Power off disabled,1: Power off enabled"
|
|
bitfld.long 0x18 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
|
|
newline
|
|
bitfld.long 0x18 1. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction. To be..,1: Memory to Peripheral transaction. To be set when.."
|
|
bitfld.long 0x18 0. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable DMA Function,1: Enable DMA Function"
|
|
line.long 0x1C "DMATOTCOUNT,Contains the number of bytes to be transferred for this DMA transaction. This register is decremented as the data is transferred. and will be 0 at the completion of the DMA operation."
|
|
hexmask.long.word 0x1C 0.--11. 1. "TOTCOUNT,Triggered DMA from Command complete event occured. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."
|
|
line.long 0x20 "DMATARGADDR,The source or destination address internal the SRAM for the DMA data. For write operations. this can only be SRAM data (ADDR bit 28 = 1); For read operations. this can ve either SRAM or FLASH (ADDR bit 28 = 0)"
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|
hexmask.long 0x20 0.--28. 1. "TARGADDR,Bits [28:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment and does not have to be word aligned. In cases of non-word aligned addresses the DMA logic will take care for ensuring only.."
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|
line.long 0x24 "DMASTAT,Status of the DMA operation currently in progress."
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|
bitfld.long 0x24 2. "DMAERR,DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set this bit will remain set until cleared by software." "0,1"
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|
bitfld.long 0x24 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0 and will also be cleared when a new DMA is started." "0,1"
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|
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bitfld.long 0x24 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
|
|
line.long 0x28 "CQCFG,Controls parameters and options for execution of the command queue operation. To enable command queue. create this in memory. set the address. and enable it with a write to CQEN"
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bitfld.long 0x28 2.--3. "MSPIFLGSEL,Selects the MPSI modules used for sourcing the CQFLAG [11:8]." "0: Selects MPSI0 as source of signals used in..,1: Selects MPSI1 as source of signals used in..,2: Selects MPSI2 as source of signals used in..,?"
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|
bitfld.long 0x28 1. "CQPRI,Sets the Priority of the command queue dma request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x28 0. "CQEN,Command queue enable. When set will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled" "0: Disable CQ Function,1: Enable CQ Function"
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|
line.long 0x2C "CQADDR,The SRAM address which will be fetched next execution of the CQ operation. This register is updated as the CQ operation progresses. and is the live version of the register. The register can also be"
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|
hexmask.long 0x2C 2.--28. 1. "CQADDR,Bits 28:2 of target byte address for source of CQ . The buffer must be aligned on a word boundary"
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|
line.long 0x30 "CQSTAT,Provides the status of the command queue operation. If the command queue is disabled. these bits will be cleared. The bits are read only"
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|
bitfld.long 0x30 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
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bitfld.long 0x30 1. "CQPAUSED,Command queue operation is currently paused." "0,1"
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bitfld.long 0x30 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
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line.long 0x34 "CQFLAGS,Command Queue Flag"
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hexmask.long.word 0x34 16.--31. 1. "CQIRQMASK,Mask the bits used to generate the command queue interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE"
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hexmask.long.word 0x34 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
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|
line.long 0x38 "CQSETCLEAR,Set/Clear the command queue software pause flags on a per-bit basis. Contains 3 fields. allowing for setting. clearing or toggling the value in the software flags. Priority when the same bit"
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hexmask.long.byte 0x38 16.--23. 1. "CQFCLR,Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x38 8.--15. 1. "CQFTGL,Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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|
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hexmask.long.byte 0x38 0.--7. 1. "CQFSET,Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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|
line.long 0x3C "CQPAUSEEN,Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the CQFLAG register is '1'. CQ processing will halt until either value is changed to '0'."
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hexmask.long.word 0x3C 0.--15. 1. "CQPEN,Enables the specified event to pause command processing when active"
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line.long 0x40 "CQCURIDX,Current index value. targeted to be written by register write operations within the command queue. This is compared to the CQENDIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and"
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hexmask.long.byte 0x40 0.--7. 1. "CQCURIDX,Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x44 "CQENDIDX,End index value. targeted to be written by software to indicate the last valid register pair contained within the command queue. rgister write operations within the command queue."
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hexmask.long.byte 0x44 0.--7. 1. "CQENDIDX,Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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|
line.long 0x48 "STATUS,IOM Module Status"
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bitfld.long 0x48 2. "IDLEST,indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to holdoffs from data availability or as the command gets propagated into the logic from the registers." "0: The I/O state machine is in the non-idle/run..,1: The I/O state machine is in the idle state."
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bitfld.long 0x48 1. "CMDACT,Indicates if the active I/O Command is currently processing a transaction or command is complete but the FIFO pointers are still syncronizing internally. This bit will go high at" "0: An I/O command is inactive. Indicating that the..,1: An I/O command is active. Indicates the active.."
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bitfld.long 0x48 0. "ERR,Bit has been deprecated. Please refer to the other error indicators. This will always return 0." "0: Default value.,1: Bit has been deprecated and will always return 0."
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|
group.long 0x280++0x3
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|
line.long 0x0 "MSPICFG,Controls the configuration of the SPI master module. including POL/PHA. LSB. flow control. and delays for MISO and MOSI"
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bitfld.long 0x0 30. "MSPIRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 27.--29. "DOUTDLY,Delay tap to use for the output signal (MOSI). This give more hold time on the output data" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 24.--26. "DINDLY,Delay tap to use for the input signal (MISO). This gives more hold time on the input data." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "SPILSB,Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first." "0: Send and receive MSB bit first,1: Send and receive LSB bit first"
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bitfld.long 0x0 22. "RDFCPOL,Selects the read flow control signal polarity." "0: Flow control signal high creates flow control.,1: Flow control signal low creates flow control."
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bitfld.long 0x0 21. "WTFCPOL,selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 will allow a IRQ=1 to pause transfers)." "0: Flow control signal high(1) creates flow control..,1: Flow control signal low(0) creates flow control.."
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bitfld.long 0x0 20. "WTFCIRQ,Selects the write mode flow control signal." "0: MISO is used as the write mode flow control..,1: IRQ is used as the write mode flow control signal."
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bitfld.long 0x0 18. "MOSIINV,Inverts MOSI when flow control is enabled." "0: MOSI is set to 0 in read mode and 1 in write mode.,1: MOSI is set to 1 in read mode and 0 in write mode."
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bitfld.long 0x0 17. "RDFC,Enables read mode flow control." "0: Read mode flow control disabled.,1: Read mode flow control enabled."
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bitfld.long 0x0 16. "WTFC,enables write mode flow control." "0: Write mode flow control disabled.,1: Write mode flow control enabled."
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bitfld.long 0x0 2. "FULLDUP,Enables full duplex mode for Master SPI write operations. Data will be captured simultaneously into the read fifo" "0,1"
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bitfld.long 0x0 1. "SPHA,Selects SPI phase.IMPORTANT NOTICE: Due to the susceptibility of creating a clock glitch which could cause register corruption changing SPHA and SPOL bits should be done in separate writes to this register." "0: Sample on the leading (first) clock edge.,1: Sample on the trailing (second) clock edge."
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bitfld.long 0x0 0. "SPOL,Selects SPI polarity.IMPORTANT NOTICE: Due to the susceptibility of creating a clock glitch which could cause register corruption changing SPHA and SPOL bits should be done in separate writes to this register." "0: The base value of the clock is 0.,1: The base value of the clock is 1."
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|
group.long 0x2C0++0x7
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line.long 0x0 "MI2CCFG,Controls the configuration of the I2C bus master."
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bitfld.long 0x0 24. "STRDIS,Disable detection of clock stretch events smaller than 1 cycle" "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "SMPCNT,Number of Base clk cycles to wait before sampling the SCL clock to determine if a clock stretch event has occured"
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hexmask.long.byte 0x0 12.--15. 1. "SDAENDLY,Number of IOCLK cycles to delay the SDA output en (all transitions affected). Used to delay data relative to clock"
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|
hexmask.long.byte 0x0 8.--11. 1. "SCLENDLY,Number of IOCLK cycles to delay the rising edge of the SCL output en (clock will go low on this edge). Used to allow clock shaping."
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bitfld.long 0x0 6. "MI2CRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 4.--5. "SDADLY,Delay to enable on the SDA output. Values are 0x0-0x3." "0,1,2,3"
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bitfld.long 0x0 2. "ARBEN,Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master this function can be disabled to save clock cycles on I2C transactions" "0: Disable multi-master bus arbitration support for..,1: Enable multi-master bus arbitration support for.."
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bitfld.long 0x0 1. "I2CLSB,Direction of data transmit and receive MSB(0) or LSB(1) first. Default per I2C specification is MSB first. This applies to both read and write data and read data will be bit" "0: Byte data is transmitted MSB first onto the..,1: Byte data is transmitted LSB first onto the.."
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bitfld.long 0x0 0. "ADDRSZ,Sets the I2C master device address size to either 7b (0) or 10b (1)." "0: Use 7b addressing for I2C master transactions,1: Use 10b addressing for I2C master transactions"
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line.long 0x4 "DEVCFG,Contains the I2C device address."
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hexmask.long.word 0x4 0.--9. 1. "DEVADDR,I2C address of the device that the Master will use to target for read/write operations. This can be either a 7b or 10b address."
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group.long 0x388++0x3
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line.long 0x0 "IOMDBG,Debug control"
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hexmask.long 0x0 3.--31. 1. "DBGDATA,Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers."
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bitfld.long 0x0 2. "APBCLKON,APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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newline
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bitfld.long 0x0 1. "IOCLKON,IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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bitfld.long 0x0 0. "DBGEN,Debug Enable. Setting bit will enable the update of data within this register otherwise it is clock gated for power savings" "0,1"
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tree.end
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endif
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sif (cpuis("AMA4B2KL")||cpuis("AMA4B2KP")||cpuis("AMAP42KL")||cpuis("AMAP42KP"))
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tree "IOM2"
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base ad:0x40052000
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group.long 0x0++0x3
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line.long 0x0 "FIFO,Provides direct random access to both input and output fifos. The state of the FIFO is not distured by reading these locations (ie no POP will be done). FIFO0 is accessible from addresses 0x0 - 0x1C. and is used for data outuput from the IOM to.."
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hexmask.long 0x0 0.--31. 1. "FIFO,FIFO direct access. Only locations 0 - 3F will return valid information."
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group.long 0x100++0x2F
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line.long 0x0 "FIFOPTR,Provides the current valid byte count of data within the FIFO as seen from the internal state machines. FIFO0 is dedicated to outgoing transactions and FIFO1 is dedicated to incoming transactions. All counts are specified in units of bytes."
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hexmask.long.byte 0x0 24.--31. 1. "FIFO1REM,The number of remaining data bytes slots currently in FIFO 1 (written by interface read by MCU)"
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hexmask.long.byte 0x0 16.--23. 1. "FIFO1SIZ,The number of valid data bytes currently in FIFO 1 (written by interface read by MCU)"
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hexmask.long.byte 0x0 8.--15. 1. "FIFO0REM,The number of remaining data bytes slots currently in FIFO 0 (written by MCU read by interface)"
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hexmask.long.byte 0x0 0.--7. 1. "FIFO0SIZ,The number of valid data bytes currently in the FIFO 0 (written by MCU read by interface)"
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line.long 0x4 "FIFOTHR,Sets the threshold values for incoming and outgoing transactions. The threshold values are used to assert the interrupt if enabled. and also used during DMA to set the transfer size as a result of DMATHR trigger."
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hexmask.long.byte 0x4 8.--13. 1. "FIFOWTHR,FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the write fifo contains FIFOWTHR free bytes as.."
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|
hexmask.long.byte 0x4 0.--5. 1. "FIFORTHR,FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the read fifo contains FIFORTHR valid bytes of data as.."
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|
line.long 0x8 "FIFOPOP,Will advance the internal read pointer of the incoming FIFO (FIFO1) when read. if POPWR is not active. If POPWR is active. a write to this register is needed to advance the internal FIFO pointer."
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hexmask.long 0x8 0.--31. 1. "FIFODOUT,This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0) the fifo read pointer will be advanced by one word as a result of the read."
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|
line.long 0xC "FIFOPUSH,Will write new data into the outgoing FIFO and advance the internal write pointer."
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hexmask.long 0xC 0.--31. 1. "FIFODIN,This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes)."
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line.long 0x10 "FIFOCTRL,Provides controls for the operation of the internal FIFOs. Contains fields used to control the operation of the POP register. and also controls to reset the internal pointers of the FIFOs."
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bitfld.long 0x10 1. "FIFORSTN,Active low manual reset of the fifo. Write to 0 to reset fifo and then write to 1 to remove the reset." "0,1"
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|
bitfld.long 0x10 0. "POPWR,Selects the mode in which 'pop' events are done for the fifo read operations. A value of '1' will prevent a pop event on a read operation and will require a write to the FIFOPOP register to create a pop event." "0,1"
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line.long 0x14 "FIFOLOC,Provides a read only value of the current read and write pointers. This register is read only and can be used alogn with the FIFO direct access method to determine the next data to be used for input and output functions."
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hexmask.long.byte 0x14 8.--11. 1. "FIFORPTR,Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1) which is used to store read data returned from external devices during a read operation."
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hexmask.long.byte 0x14 0.--3. 1. "FIFOWPTR,Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0) which is used during write operations to external devices."
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line.long 0x18 "CLKCFG,Provides clock related controls used internal to the BLEIF module. and enablement of 32KHz clock to the BLE Core module. The internal clock sourced is selected via the FSEL and can be further divided by 3 using the DIV3 control."
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hexmask.long.byte 0x18 24.--31. 1. "TOTPER,Clock total clock count minus 1. This provides the total period of the divided clock -1 when the DIVEN is active. The"
|
|
hexmask.long.byte 0x18 16.--23. 1. "LOWPER,Clock low clock count minus 1. This provides the number of clocks the divided clock will be low when the DIVEN = 1."
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newline
|
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bitfld.long 0x18 12. "DIVEN,Enable clock division by TOTPER and LOWPER" "0: Disable TOTPER division.,1: Enable TOTPER division."
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bitfld.long 0x18 11. "DIV3,Enable divide by 3 of the source IOCLK. Division by 3 is done before the DIVEN programmable divider and if enabled" "0: Select divide by 1.,1: Select divide by 3."
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newline
|
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bitfld.long 0x18 8.--10. "FSEL,Select the input clock frequency." "0: Selects the minimum power clock. This setting..,1: Selects static 0 as the input clock. Previously..,2: Selects the HFRC 48MHz as the input clock.,3: Selects the HFRC 24MHz as the input clock.,4: Selects the HFRC 12MHz as the input clock.,5: Selects the HFRC 6MHz as the input clock.,6: Selects the HFRC 3MHz as the input clock.,7: Selects the HFRC 1.5MHz as the input clock."
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bitfld.long 0x18 0. "IOCLKEN,Enable for the interface clock. Must be enabled prior to executing any IO operations." "0,1"
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|
line.long 0x1C "SUBMODCTRL,Provides enable for each submodule. Only a sigle submodule can be enabled at one time."
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bitfld.long 0x1C 9.--11. "SMOD2TYPE,Submodule 2 module type. This is the I2S Master/Slave interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,4: Master/Slave submodule,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 8. "SMOD2EN,Submodule 2 enable (1) or disable (0)" "0,1"
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newline
|
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bitfld.long 0x1C 5.--7. "SMOD1TYPE,Submodule 1 module type. This is the I2C Master interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,4: Master/Slave submodule,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 4. "SMOD1EN,Submodule 1 enable (1) or disable (0)" "0,1"
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|
newline
|
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bitfld.long 0x1C 1.--3. "SMOD0TYPE,Submodule 0 module type. This is the SPI Master interface." "0: MSPI submodule,1: I2C Master submodule,2: I2S Master/Slave Module,?,?,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 0. "SMOD0EN,Submodule 0 enable (1) or disable (0)" "0,1"
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|
line.long 0x20 "CMD,Writes to this register will start an IO transaction. as well as set various parameters for the command itself. Reads will return the command value written to the CMD register."
|
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hexmask.long.byte 0x20 24.--31. 1. "OFFSETLO,This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command."
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bitfld.long 0x20 20.--21. "CMDSEL,Command Specific selection information. Not used in Master I2C. Used as CEn select for Master SPI transactions" "0,1,2,3"
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newline
|
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hexmask.long.word 0x20 8.--19. 1. "TSIZE,Defines the transaction size in bytes. The offset transfer is not included in this size."
|
|
bitfld.long 0x20 7. "CONT,Contine to hold the bus after the current transaction if set to a 1 with a new command issued." "0,1"
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|
newline
|
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bitfld.long 0x20 4.--6. "OFFSETCNT,Number of offset bytes to use for the command - 0 1 2 3 4 5 are valid selections. The second (byte 1) third (byte 2) and forth (byte 3) are read from the OFFSETHI register and the low order byte is pulled from this register in the.." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x20 0.--3. 1. "CMD,Command for submodule."
|
|
line.long 0x24 "DCXCTRL,Enables transmission of DCX signal with SPI transactions and selects which CE signals will be used to transmit the DCX signal."
|
|
bitfld.long 0x24 4. "DCXEN,Global enable of the DCX function. Setting to 1 will enable the generation of the DCX signal which will assert when sending the offset bytes of the SPI transaction." "0,1"
|
|
hexmask.long.byte 0x24 0.--3. 1. "DCXSEL,Selects the CE channel used to convey the DCX function. The select is bitwise encoded with bit 0 = 1 enabling CE0 for DCX transmission bit 1 = 1 enableing CE1 for DCX transmission etc. If the CE used for the SPI transaction is set it will be.."
|
|
line.long 0x28 "OFFSETHI,High order bytes of offset for IO transaction"
|
|
hexmask.long 0x28 0.--31. 1. "OFFSETHI,Holds the high order bytes of the byte addressing/offset field to use with IO commands. The number of offset bytes to use is specified in the command register"
|
|
line.long 0x2C "CMDSTAT,Provides staus on the execution of the command currently in progress. The fields in this register will reflect the real time status of the internal state machines and data transfers within the IOM."
|
|
hexmask.long.word 0x2C 8.--19. 1. "CTSIZE,The current number of bytes still to be transferred with this command. This field will count down to zero."
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|
bitfld.long 0x2C 5.--7. "CMDSTAT,The current status of the command execution." "?,1: Error encountered with command,2: Actively processing command,?,4: Idle state no active command no error,?,6: Command in progress but waiting on data from host,?"
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|
newline
|
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hexmask.long.byte 0x2C 0.--4. 1. "CCMD,current command that is being executed"
|
|
group.long 0x200++0x4B
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 14. "CQERR,Error during command queue operations" "0,1"
|
|
bitfld.long 0x0 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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|
newline
|
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bitfld.long 0x0 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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|
bitfld.long 0x0 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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newline
|
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bitfld.long 0x0 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0x0 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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|
newline
|
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bitfld.long 0x0 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x0 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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|
newline
|
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bitfld.long 0x0 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x0 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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newline
|
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bitfld.long 0x0 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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|
bitfld.long 0x0 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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newline
|
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bitfld.long 0x0 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0x0 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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newline
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bitfld.long 0x0 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
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bitfld.long 0x4 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x4 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x4 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x4 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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newline
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bitfld.long 0x4 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x4 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0x4 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x4 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x4 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x4 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x4 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x4 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0x4 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0x4 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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newline
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bitfld.long 0x4 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
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bitfld.long 0x8 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x8 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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newline
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bitfld.long 0x8 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x8 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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newline
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bitfld.long 0x8 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x8 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0x8 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x8 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x8 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x8 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x8 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x8 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0x8 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0x8 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x8 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
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bitfld.long 0xC 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0xC 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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newline
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bitfld.long 0xC 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0xC 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0xC 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0xC 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0xC 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0xC 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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newline
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bitfld.long 0xC 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0xC 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0xC 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0xC 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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newline
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bitfld.long 0xC 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0xC 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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newline
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bitfld.long 0xC 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x10 "DMATRIGEN,Provides control on which event will trigger the DMA transfer after the DMA operation is setup and enabled. The trigger event will cause a number of bytes (depending on trigger event) to be"
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bitfld.long 0x10 1. "DTHREN,Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes) the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO and will transfer (WTHR/4) number of words" "0,1"
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bitfld.long 0x10 0. "DCMDCMPEN,Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered the number of words transferred will be the lesser of the remaining TOTCOUNT bytes or" "0,1"
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line.long 0x14 "DMATRIGSTAT,Provides the status of trigger events that have occurred for the transaction. Some of the bits are read only and some can be reset via a write of 0."
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bitfld.long 0x14 2. "DTOTCMP,DMA triggered when DCMDCMP = 0 and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is" "0,1"
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bitfld.long 0x14 1. "DTHR,Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA." "0,1"
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bitfld.long 0x14 0. "DCMDCMP,Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA." "0,1"
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line.long 0x18 "DMACFG,Configuration control of the DMA process. including the direction of DMA. and enablement of DMA"
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bitfld.long 0x18 9. "DPWROFF,Power off module after DMA is complete. If this bit is active the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain power down will not be performed." "0: Power off disabled,1: Power off enabled"
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bitfld.long 0x18 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x18 1. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction. To be..,1: Memory to Peripheral transaction. To be set when.."
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bitfld.long 0x18 0. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable DMA Function,1: Enable DMA Function"
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line.long 0x1C "DMATOTCOUNT,Contains the number of bytes to be transferred for this DMA transaction. This register is decremented as the data is transferred. and will be 0 at the completion of the DMA operation."
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hexmask.long.word 0x1C 0.--11. 1. "TOTCOUNT,Triggered DMA from Command complete event occured. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."
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line.long 0x20 "DMATARGADDR,The source or destination address internal the SRAM for the DMA data. For write operations. this can only be SRAM data (ADDR bit 28 = 1); For read operations. this can ve either SRAM or FLASH (ADDR bit 28 = 0)"
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hexmask.long 0x20 0.--28. 1. "TARGADDR,Bits [28:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment and does not have to be word aligned. In cases of non-word aligned addresses the DMA logic will take care for ensuring only.."
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line.long 0x24 "DMASTAT,Status of the DMA operation currently in progress."
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bitfld.long 0x24 2. "DMAERR,DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set this bit will remain set until cleared by software." "0,1"
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bitfld.long 0x24 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0 and will also be cleared when a new DMA is started." "0,1"
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newline
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bitfld.long 0x24 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
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line.long 0x28 "CQCFG,Controls parameters and options for execution of the command queue operation. To enable command queue. create this in memory. set the address. and enable it with a write to CQEN"
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bitfld.long 0x28 2.--3. "MSPIFLGSEL,Selects the MPSI modules used for sourcing the CQFLAG [11:8]." "0: Selects MPSI0 as source of signals used in..,1: Selects MPSI1 as source of signals used in..,2: Selects MPSI2 as source of signals used in..,?"
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bitfld.long 0x28 1. "CQPRI,Sets the Priority of the command queue dma request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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newline
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bitfld.long 0x28 0. "CQEN,Command queue enable. When set will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled" "0: Disable CQ Function,1: Enable CQ Function"
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line.long 0x2C "CQADDR,The SRAM address which will be fetched next execution of the CQ operation. This register is updated as the CQ operation progresses. and is the live version of the register. The register can also be"
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hexmask.long 0x2C 2.--28. 1. "CQADDR,Bits 28:2 of target byte address for source of CQ . The buffer must be aligned on a word boundary"
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line.long 0x30 "CQSTAT,Provides the status of the command queue operation. If the command queue is disabled. these bits will be cleared. The bits are read only"
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bitfld.long 0x30 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
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bitfld.long 0x30 1. "CQPAUSED,Command queue operation is currently paused." "0,1"
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bitfld.long 0x30 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
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line.long 0x34 "CQFLAGS,Command Queue Flag"
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hexmask.long.word 0x34 16.--31. 1. "CQIRQMASK,Mask the bits used to generate the command queue interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE"
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hexmask.long.word 0x34 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
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line.long 0x38 "CQSETCLEAR,Set/Clear the command queue software pause flags on a per-bit basis. Contains 3 fields. allowing for setting. clearing or toggling the value in the software flags. Priority when the same bit"
|
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hexmask.long.byte 0x38 16.--23. 1. "CQFCLR,Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x38 8.--15. 1. "CQFTGL,Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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newline
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hexmask.long.byte 0x38 0.--7. 1. "CQFSET,Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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line.long 0x3C "CQPAUSEEN,Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the CQFLAG register is '1'. CQ processing will halt until either value is changed to '0'."
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hexmask.long.word 0x3C 0.--15. 1. "CQPEN,Enables the specified event to pause command processing when active"
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line.long 0x40 "CQCURIDX,Current index value. targeted to be written by register write operations within the command queue. This is compared to the CQENDIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and"
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hexmask.long.byte 0x40 0.--7. 1. "CQCURIDX,Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x44 "CQENDIDX,End index value. targeted to be written by software to indicate the last valid register pair contained within the command queue. rgister write operations within the command queue."
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hexmask.long.byte 0x44 0.--7. 1. "CQENDIDX,Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x48 "STATUS,IOM Module Status"
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bitfld.long 0x48 2. "IDLEST,indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to holdoffs from data availability or as the command gets propagated into the logic from the registers." "0: The I/O state machine is in the non-idle/run..,1: The I/O state machine is in the idle state."
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bitfld.long 0x48 1. "CMDACT,Indicates if the active I/O Command is currently processing a transaction or command is complete but the FIFO pointers are still syncronizing internally. This bit will go high at" "0: An I/O command is inactive. Indicating that the..,1: An I/O command is active. Indicates the active.."
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newline
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bitfld.long 0x48 0. "ERR,Bit has been deprecated. Please refer to the other error indicators. This will always return 0." "0: Default value.,1: Bit has been deprecated and will always return 0."
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group.long 0x280++0x3
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line.long 0x0 "MSPICFG,Controls the configuration of the SPI master module. including POL/PHA. LSB. flow control. and delays for MISO and MOSI"
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bitfld.long 0x0 30. "MSPIRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 27.--29. "DOUTDLY,Delay tap to use for the output signal (MOSI). This give more hold time on the output data" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x0 24.--26. "DINDLY,Delay tap to use for the input signal (MISO). This gives more hold time on the input data." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "SPILSB,Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first." "0: Send and receive MSB bit first,1: Send and receive LSB bit first"
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bitfld.long 0x0 22. "RDFCPOL,Selects the read flow control signal polarity." "0: Flow control signal high creates flow control.,1: Flow control signal low creates flow control."
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bitfld.long 0x0 21. "WTFCPOL,selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 will allow a IRQ=1 to pause transfers)." "0: Flow control signal high(1) creates flow control..,1: Flow control signal low(0) creates flow control.."
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bitfld.long 0x0 20. "WTFCIRQ,Selects the write mode flow control signal." "0: MISO is used as the write mode flow control..,1: IRQ is used as the write mode flow control signal."
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bitfld.long 0x0 18. "MOSIINV,Inverts MOSI when flow control is enabled." "0: MOSI is set to 0 in read mode and 1 in write mode.,1: MOSI is set to 1 in read mode and 0 in write mode."
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newline
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bitfld.long 0x0 17. "RDFC,Enables read mode flow control." "0: Read mode flow control disabled.,1: Read mode flow control enabled."
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bitfld.long 0x0 16. "WTFC,enables write mode flow control." "0: Write mode flow control disabled.,1: Write mode flow control enabled."
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newline
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bitfld.long 0x0 2. "FULLDUP,Enables full duplex mode for Master SPI write operations. Data will be captured simultaneously into the read fifo" "0,1"
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bitfld.long 0x0 1. "SPHA,Selects SPI phase.IMPORTANT NOTICE: Due to the susceptibility of creating a clock glitch which could cause register corruption changing SPHA and SPOL bits should be done in separate writes to this register." "0: Sample on the leading (first) clock edge.,1: Sample on the trailing (second) clock edge."
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newline
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bitfld.long 0x0 0. "SPOL,Selects SPI polarity.IMPORTANT NOTICE: Due to the susceptibility of creating a clock glitch which could cause register corruption changing SPHA and SPOL bits should be done in separate writes to this register." "0: The base value of the clock is 0.,1: The base value of the clock is 1."
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|
group.long 0x2C0++0x7
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line.long 0x0 "MI2CCFG,Controls the configuration of the I2C bus master."
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bitfld.long 0x0 24. "STRDIS,Disable detection of clock stretch events smaller than 1 cycle" "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "SMPCNT,Number of Base clk cycles to wait before sampling the SCL clock to determine if a clock stretch event has occured"
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newline
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hexmask.long.byte 0x0 12.--15. 1. "SDAENDLY,Number of IOCLK cycles to delay the SDA output en (all transitions affected). Used to delay data relative to clock"
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|
hexmask.long.byte 0x0 8.--11. 1. "SCLENDLY,Number of IOCLK cycles to delay the rising edge of the SCL output en (clock will go low on this edge). Used to allow clock shaping."
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newline
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bitfld.long 0x0 6. "MI2CRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
|
|
bitfld.long 0x0 4.--5. "SDADLY,Delay to enable on the SDA output. Values are 0x0-0x3." "0,1,2,3"
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newline
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bitfld.long 0x0 2. "ARBEN,Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master this function can be disabled to save clock cycles on I2C transactions" "0: Disable multi-master bus arbitration support for..,1: Enable multi-master bus arbitration support for.."
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|
bitfld.long 0x0 1. "I2CLSB,Direction of data transmit and receive MSB(0) or LSB(1) first. Default per I2C specification is MSB first. This applies to both read and write data and read data will be bit" "0: Byte data is transmitted MSB first onto the..,1: Byte data is transmitted LSB first onto the.."
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newline
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bitfld.long 0x0 0. "ADDRSZ,Sets the I2C master device address size to either 7b (0) or 10b (1)." "0: Use 7b addressing for I2C master transactions,1: Use 10b addressing for I2C master transactions"
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line.long 0x4 "DEVCFG,Contains the I2C device address."
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hexmask.long.word 0x4 0.--9. 1. "DEVADDR,I2C address of the device that the Master will use to target for read/write operations. This can be either a 7b or 10b address."
|
|
group.long 0x388++0x3
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line.long 0x0 "IOMDBG,Debug control"
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hexmask.long 0x0 3.--31. 1. "DBGDATA,Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers."
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bitfld.long 0x0 2. "APBCLKON,APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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newline
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bitfld.long 0x0 1. "IOCLKON,IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
|
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bitfld.long 0x0 0. "DBGEN,Debug Enable. Setting bit will enable the update of data within this register otherwise it is clock gated for power savings" "0,1"
|
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tree.end
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMA4B2KP")||cpuis("AMAP42KL")||cpuis("AMAP42KP"))
|
|
tree "IOM3"
|
|
base ad:0x40053000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FIFO,Provides direct random access to both input and output fifos. The state of the FIFO is not distured by reading these locations (ie no POP will be done). FIFO0 is accessible from addresses 0x0 - 0x1C. and is used for data outuput from the IOM to.."
|
|
hexmask.long 0x0 0.--31. 1. "FIFO,FIFO direct access. Only locations 0 - 3F will return valid information."
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|
group.long 0x100++0x2F
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|
line.long 0x0 "FIFOPTR,Provides the current valid byte count of data within the FIFO as seen from the internal state machines. FIFO0 is dedicated to outgoing transactions and FIFO1 is dedicated to incoming transactions. All counts are specified in units of bytes."
|
|
hexmask.long.byte 0x0 24.--31. 1. "FIFO1REM,The number of remaining data bytes slots currently in FIFO 1 (written by interface read by MCU)"
|
|
hexmask.long.byte 0x0 16.--23. 1. "FIFO1SIZ,The number of valid data bytes currently in FIFO 1 (written by interface read by MCU)"
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hexmask.long.byte 0x0 8.--15. 1. "FIFO0REM,The number of remaining data bytes slots currently in FIFO 0 (written by MCU read by interface)"
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hexmask.long.byte 0x0 0.--7. 1. "FIFO0SIZ,The number of valid data bytes currently in the FIFO 0 (written by MCU read by interface)"
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line.long 0x4 "FIFOTHR,Sets the threshold values for incoming and outgoing transactions. The threshold values are used to assert the interrupt if enabled. and also used during DMA to set the transfer size as a result of DMATHR trigger."
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hexmask.long.byte 0x4 8.--13. 1. "FIFOWTHR,FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the write fifo contains FIFOWTHR free bytes as.."
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hexmask.long.byte 0x4 0.--5. 1. "FIFORTHR,FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the read fifo contains FIFORTHR valid bytes of data as.."
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line.long 0x8 "FIFOPOP,Will advance the internal read pointer of the incoming FIFO (FIFO1) when read. if POPWR is not active. If POPWR is active. a write to this register is needed to advance the internal FIFO pointer."
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hexmask.long 0x8 0.--31. 1. "FIFODOUT,This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0) the fifo read pointer will be advanced by one word as a result of the read."
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line.long 0xC "FIFOPUSH,Will write new data into the outgoing FIFO and advance the internal write pointer."
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hexmask.long 0xC 0.--31. 1. "FIFODIN,This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes)."
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line.long 0x10 "FIFOCTRL,Provides controls for the operation of the internal FIFOs. Contains fields used to control the operation of the POP register. and also controls to reset the internal pointers of the FIFOs."
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bitfld.long 0x10 1. "FIFORSTN,Active low manual reset of the fifo. Write to 0 to reset fifo and then write to 1 to remove the reset." "0,1"
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bitfld.long 0x10 0. "POPWR,Selects the mode in which 'pop' events are done for the fifo read operations. A value of '1' will prevent a pop event on a read operation and will require a write to the FIFOPOP register to create a pop event." "0,1"
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line.long 0x14 "FIFOLOC,Provides a read only value of the current read and write pointers. This register is read only and can be used alogn with the FIFO direct access method to determine the next data to be used for input and output functions."
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hexmask.long.byte 0x14 8.--11. 1. "FIFORPTR,Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1) which is used to store read data returned from external devices during a read operation."
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hexmask.long.byte 0x14 0.--3. 1. "FIFOWPTR,Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0) which is used during write operations to external devices."
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line.long 0x18 "CLKCFG,Provides clock related controls used internal to the BLEIF module. and enablement of 32KHz clock to the BLE Core module. The internal clock sourced is selected via the FSEL and can be further divided by 3 using the DIV3 control."
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hexmask.long.byte 0x18 24.--31. 1. "TOTPER,Clock total clock count minus 1. This provides the total period of the divided clock -1 when the DIVEN is active. The"
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hexmask.long.byte 0x18 16.--23. 1. "LOWPER,Clock low clock count minus 1. This provides the number of clocks the divided clock will be low when the DIVEN = 1."
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bitfld.long 0x18 12. "DIVEN,Enable clock division by TOTPER and LOWPER" "0: Disable TOTPER division.,1: Enable TOTPER division."
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bitfld.long 0x18 11. "DIV3,Enable divide by 3 of the source IOCLK. Division by 3 is done before the DIVEN programmable divider and if enabled" "0: Select divide by 1.,1: Select divide by 3."
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bitfld.long 0x18 8.--10. "FSEL,Select the input clock frequency." "0: Selects the minimum power clock. This setting..,1: Selects static 0 as the input clock. Previously..,2: Selects the HFRC 48MHz as the input clock.,3: Selects the HFRC 24MHz as the input clock.,4: Selects the HFRC 12MHz as the input clock.,5: Selects the HFRC 6MHz as the input clock.,6: Selects the HFRC 3MHz as the input clock.,7: Selects the HFRC 1.5MHz as the input clock."
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bitfld.long 0x18 0. "IOCLKEN,Enable for the interface clock. Must be enabled prior to executing any IO operations." "0,1"
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line.long 0x1C "SUBMODCTRL,Provides enable for each submodule. Only a sigle submodule can be enabled at one time."
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bitfld.long 0x1C 9.--11. "SMOD2TYPE,Submodule 2 module type. This is the I2S Master/Slave interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,4: Master/Slave submodule,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 8. "SMOD2EN,Submodule 2 enable (1) or disable (0)" "0,1"
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bitfld.long 0x1C 5.--7. "SMOD1TYPE,Submodule 1 module type. This is the I2C Master interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,4: Master/Slave submodule,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 4. "SMOD1EN,Submodule 1 enable (1) or disable (0)" "0,1"
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bitfld.long 0x1C 1.--3. "SMOD0TYPE,Submodule 0 module type. This is the SPI Master interface." "0: MSPI submodule,1: I2C Master submodule,2: I2S Master/Slave Module,?,?,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 0. "SMOD0EN,Submodule 0 enable (1) or disable (0)" "0,1"
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line.long 0x20 "CMD,Writes to this register will start an IO transaction. as well as set various parameters for the command itself. Reads will return the command value written to the CMD register."
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hexmask.long.byte 0x20 24.--31. 1. "OFFSETLO,This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command."
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bitfld.long 0x20 20.--21. "CMDSEL,Command Specific selection information. Not used in Master I2C. Used as CEn select for Master SPI transactions" "0,1,2,3"
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hexmask.long.word 0x20 8.--19. 1. "TSIZE,Defines the transaction size in bytes. The offset transfer is not included in this size."
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bitfld.long 0x20 7. "CONT,Contine to hold the bus after the current transaction if set to a 1 with a new command issued." "0,1"
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bitfld.long 0x20 4.--6. "OFFSETCNT,Number of offset bytes to use for the command - 0 1 2 3 4 5 are valid selections. The second (byte 1) third (byte 2) and forth (byte 3) are read from the OFFSETHI register and the low order byte is pulled from this register in the.." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x20 0.--3. 1. "CMD,Command for submodule."
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line.long 0x24 "DCXCTRL,Enables transmission of DCX signal with SPI transactions and selects which CE signals will be used to transmit the DCX signal."
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bitfld.long 0x24 4. "DCXEN,Global enable of the DCX function. Setting to 1 will enable the generation of the DCX signal which will assert when sending the offset bytes of the SPI transaction." "0,1"
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hexmask.long.byte 0x24 0.--3. 1. "DCXSEL,Selects the CE channel used to convey the DCX function. The select is bitwise encoded with bit 0 = 1 enabling CE0 for DCX transmission bit 1 = 1 enableing CE1 for DCX transmission etc. If the CE used for the SPI transaction is set it will be.."
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line.long 0x28 "OFFSETHI,High order bytes of offset for IO transaction"
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hexmask.long 0x28 0.--31. 1. "OFFSETHI,Holds the high order bytes of the byte addressing/offset field to use with IO commands. The number of offset bytes to use is specified in the command register"
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line.long 0x2C "CMDSTAT,Provides staus on the execution of the command currently in progress. The fields in this register will reflect the real time status of the internal state machines and data transfers within the IOM."
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hexmask.long.word 0x2C 8.--19. 1. "CTSIZE,The current number of bytes still to be transferred with this command. This field will count down to zero."
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bitfld.long 0x2C 5.--7. "CMDSTAT,The current status of the command execution." "?,1: Error encountered with command,2: Actively processing command,?,4: Idle state no active command no error,?,6: Command in progress but waiting on data from host,?"
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hexmask.long.byte 0x2C 0.--4. 1. "CCMD,current command that is being executed"
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group.long 0x200++0x4B
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line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
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bitfld.long 0x0 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x0 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x0 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x0 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x0 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x0 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0x0 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x0 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x0 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x0 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x0 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x0 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0x0 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0x0 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x0 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
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bitfld.long 0x4 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x4 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x4 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x4 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x4 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x4 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0x4 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x4 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x4 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x4 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x4 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x4 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0x4 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0x4 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x4 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
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bitfld.long 0x8 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x8 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x8 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x8 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x8 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x8 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0x8 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x8 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x8 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x8 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x8 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x8 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0x8 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0x8 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x8 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
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bitfld.long 0xC 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0xC 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0xC 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0xC 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0xC 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0xC 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0xC 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0xC 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0xC 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0xC 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0xC 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0xC 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0xC 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0xC 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0xC 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x10 "DMATRIGEN,Provides control on which event will trigger the DMA transfer after the DMA operation is setup and enabled. The trigger event will cause a number of bytes (depending on trigger event) to be"
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bitfld.long 0x10 1. "DTHREN,Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes) the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO and will transfer (WTHR/4) number of words" "0,1"
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bitfld.long 0x10 0. "DCMDCMPEN,Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered the number of words transferred will be the lesser of the remaining TOTCOUNT bytes or" "0,1"
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line.long 0x14 "DMATRIGSTAT,Provides the status of trigger events that have occurred for the transaction. Some of the bits are read only and some can be reset via a write of 0."
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bitfld.long 0x14 2. "DTOTCMP,DMA triggered when DCMDCMP = 0 and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is" "0,1"
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bitfld.long 0x14 1. "DTHR,Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA." "0,1"
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bitfld.long 0x14 0. "DCMDCMP,Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA." "0,1"
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line.long 0x18 "DMACFG,Configuration control of the DMA process. including the direction of DMA. and enablement of DMA"
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bitfld.long 0x18 9. "DPWROFF,Power off module after DMA is complete. If this bit is active the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain power down will not be performed." "0: Power off disabled,1: Power off enabled"
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bitfld.long 0x18 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x18 1. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction. To be..,1: Memory to Peripheral transaction. To be set when.."
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bitfld.long 0x18 0. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable DMA Function,1: Enable DMA Function"
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line.long 0x1C "DMATOTCOUNT,Contains the number of bytes to be transferred for this DMA transaction. This register is decremented as the data is transferred. and will be 0 at the completion of the DMA operation."
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hexmask.long.word 0x1C 0.--11. 1. "TOTCOUNT,Triggered DMA from Command complete event occured. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."
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line.long 0x20 "DMATARGADDR,The source or destination address internal the SRAM for the DMA data. For write operations. this can only be SRAM data (ADDR bit 28 = 1); For read operations. this can ve either SRAM or FLASH (ADDR bit 28 = 0)"
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hexmask.long 0x20 0.--28. 1. "TARGADDR,Bits [28:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment and does not have to be word aligned. In cases of non-word aligned addresses the DMA logic will take care for ensuring only.."
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line.long 0x24 "DMASTAT,Status of the DMA operation currently in progress."
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bitfld.long 0x24 2. "DMAERR,DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set this bit will remain set until cleared by software." "0,1"
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bitfld.long 0x24 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0 and will also be cleared when a new DMA is started." "0,1"
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bitfld.long 0x24 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
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line.long 0x28 "CQCFG,Controls parameters and options for execution of the command queue operation. To enable command queue. create this in memory. set the address. and enable it with a write to CQEN"
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bitfld.long 0x28 2.--3. "MSPIFLGSEL,Selects the MPSI modules used for sourcing the CQFLAG [11:8]." "0: Selects MPSI0 as source of signals used in..,1: Selects MPSI1 as source of signals used in..,2: Selects MPSI2 as source of signals used in..,?"
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bitfld.long 0x28 1. "CQPRI,Sets the Priority of the command queue dma request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x28 0. "CQEN,Command queue enable. When set will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled" "0: Disable CQ Function,1: Enable CQ Function"
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line.long 0x2C "CQADDR,The SRAM address which will be fetched next execution of the CQ operation. This register is updated as the CQ operation progresses. and is the live version of the register. The register can also be"
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hexmask.long 0x2C 2.--28. 1. "CQADDR,Bits 28:2 of target byte address for source of CQ . The buffer must be aligned on a word boundary"
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|
line.long 0x30 "CQSTAT,Provides the status of the command queue operation. If the command queue is disabled. these bits will be cleared. The bits are read only"
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|
bitfld.long 0x30 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
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|
bitfld.long 0x30 1. "CQPAUSED,Command queue operation is currently paused." "0,1"
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|
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bitfld.long 0x30 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
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|
line.long 0x34 "CQFLAGS,Command Queue Flag"
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|
hexmask.long.word 0x34 16.--31. 1. "CQIRQMASK,Mask the bits used to generate the command queue interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE"
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hexmask.long.word 0x34 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
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|
line.long 0x38 "CQSETCLEAR,Set/Clear the command queue software pause flags on a per-bit basis. Contains 3 fields. allowing for setting. clearing or toggling the value in the software flags. Priority when the same bit"
|
|
hexmask.long.byte 0x38 16.--23. 1. "CQFCLR,Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field"
|
|
hexmask.long.byte 0x38 8.--15. 1. "CQFTGL,Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field"
|
|
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hexmask.long.byte 0x38 0.--7. 1. "CQFSET,Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field"
|
|
line.long 0x3C "CQPAUSEEN,Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the CQFLAG register is '1'. CQ processing will halt until either value is changed to '0'."
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hexmask.long.word 0x3C 0.--15. 1. "CQPEN,Enables the specified event to pause command processing when active"
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|
line.long 0x40 "CQCURIDX,Current index value. targeted to be written by register write operations within the command queue. This is compared to the CQENDIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and"
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|
hexmask.long.byte 0x40 0.--7. 1. "CQCURIDX,Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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|
line.long 0x44 "CQENDIDX,End index value. targeted to be written by software to indicate the last valid register pair contained within the command queue. rgister write operations within the command queue."
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|
hexmask.long.byte 0x44 0.--7. 1. "CQENDIDX,Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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|
line.long 0x48 "STATUS,IOM Module Status"
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|
bitfld.long 0x48 2. "IDLEST,indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to holdoffs from data availability or as the command gets propagated into the logic from the registers." "0: The I/O state machine is in the non-idle/run..,1: The I/O state machine is in the idle state."
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bitfld.long 0x48 1. "CMDACT,Indicates if the active I/O Command is currently processing a transaction or command is complete but the FIFO pointers are still syncronizing internally. This bit will go high at" "0: An I/O command is inactive. Indicating that the..,1: An I/O command is active. Indicates the active.."
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|
newline
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bitfld.long 0x48 0. "ERR,Bit has been deprecated. Please refer to the other error indicators. This will always return 0." "0: Default value.,1: Bit has been deprecated and will always return 0."
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|
group.long 0x280++0x3
|
|
line.long 0x0 "MSPICFG,Controls the configuration of the SPI master module. including POL/PHA. LSB. flow control. and delays for MISO and MOSI"
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|
bitfld.long 0x0 30. "MSPIRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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|
bitfld.long 0x0 27.--29. "DOUTDLY,Delay tap to use for the output signal (MOSI). This give more hold time on the output data" "0,1,2,3,4,5,6,7"
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|
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bitfld.long 0x0 24.--26. "DINDLY,Delay tap to use for the input signal (MISO). This gives more hold time on the input data." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "SPILSB,Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first." "0: Send and receive MSB bit first,1: Send and receive LSB bit first"
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bitfld.long 0x0 22. "RDFCPOL,Selects the read flow control signal polarity." "0: Flow control signal high creates flow control.,1: Flow control signal low creates flow control."
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bitfld.long 0x0 21. "WTFCPOL,selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 will allow a IRQ=1 to pause transfers)." "0: Flow control signal high(1) creates flow control..,1: Flow control signal low(0) creates flow control.."
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bitfld.long 0x0 20. "WTFCIRQ,Selects the write mode flow control signal." "0: MISO is used as the write mode flow control..,1: IRQ is used as the write mode flow control signal."
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bitfld.long 0x0 18. "MOSIINV,Inverts MOSI when flow control is enabled." "0: MOSI is set to 0 in read mode and 1 in write mode.,1: MOSI is set to 1 in read mode and 0 in write mode."
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bitfld.long 0x0 17. "RDFC,Enables read mode flow control." "0: Read mode flow control disabled.,1: Read mode flow control enabled."
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|
bitfld.long 0x0 16. "WTFC,enables write mode flow control." "0: Write mode flow control disabled.,1: Write mode flow control enabled."
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|
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bitfld.long 0x0 2. "FULLDUP,Enables full duplex mode for Master SPI write operations. Data will be captured simultaneously into the read fifo" "0,1"
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bitfld.long 0x0 1. "SPHA,Selects SPI phase.IMPORTANT NOTICE: Due to the susceptibility of creating a clock glitch which could cause register corruption changing SPHA and SPOL bits should be done in separate writes to this register." "0: Sample on the leading (first) clock edge.,1: Sample on the trailing (second) clock edge."
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bitfld.long 0x0 0. "SPOL,Selects SPI polarity.IMPORTANT NOTICE: Due to the susceptibility of creating a clock glitch which could cause register corruption changing SPHA and SPOL bits should be done in separate writes to this register." "0: The base value of the clock is 0.,1: The base value of the clock is 1."
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|
group.long 0x2C0++0x7
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|
line.long 0x0 "MI2CCFG,Controls the configuration of the I2C bus master."
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|
bitfld.long 0x0 24. "STRDIS,Disable detection of clock stretch events smaller than 1 cycle" "0,1"
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|
hexmask.long.byte 0x0 16.--23. 1. "SMPCNT,Number of Base clk cycles to wait before sampling the SCL clock to determine if a clock stretch event has occured"
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|
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hexmask.long.byte 0x0 12.--15. 1. "SDAENDLY,Number of IOCLK cycles to delay the SDA output en (all transitions affected). Used to delay data relative to clock"
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|
hexmask.long.byte 0x0 8.--11. 1. "SCLENDLY,Number of IOCLK cycles to delay the rising edge of the SCL output en (clock will go low on this edge). Used to allow clock shaping."
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|
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bitfld.long 0x0 6. "MI2CRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 4.--5. "SDADLY,Delay to enable on the SDA output. Values are 0x0-0x3." "0,1,2,3"
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bitfld.long 0x0 2. "ARBEN,Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master this function can be disabled to save clock cycles on I2C transactions" "0: Disable multi-master bus arbitration support for..,1: Enable multi-master bus arbitration support for.."
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|
bitfld.long 0x0 1. "I2CLSB,Direction of data transmit and receive MSB(0) or LSB(1) first. Default per I2C specification is MSB first. This applies to both read and write data and read data will be bit" "0: Byte data is transmitted MSB first onto the..,1: Byte data is transmitted LSB first onto the.."
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|
newline
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|
bitfld.long 0x0 0. "ADDRSZ,Sets the I2C master device address size to either 7b (0) or 10b (1)." "0: Use 7b addressing for I2C master transactions,1: Use 10b addressing for I2C master transactions"
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|
line.long 0x4 "DEVCFG,Contains the I2C device address."
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|
hexmask.long.word 0x4 0.--9. 1. "DEVADDR,I2C address of the device that the Master will use to target for read/write operations. This can be either a 7b or 10b address."
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|
group.long 0x388++0x3
|
|
line.long 0x0 "IOMDBG,Debug control"
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|
hexmask.long 0x0 3.--31. 1. "DBGDATA,Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers."
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bitfld.long 0x0 2. "APBCLKON,APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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newline
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bitfld.long 0x0 1. "IOCLKON,IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
|
|
bitfld.long 0x0 0. "DBGEN,Debug Enable. Setting bit will enable the update of data within this register otherwise it is clock gated for power savings" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMA4B2KP")||cpuis("AMAP42KL")||cpuis("AMAP42KP"))
|
|
tree "IOM4"
|
|
base ad:0x40054000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FIFO,Provides direct random access to both input and output fifos. The state of the FIFO is not distured by reading these locations (ie no POP will be done). FIFO0 is accessible from addresses 0x0 - 0x1C. and is used for data outuput from the IOM to.."
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hexmask.long 0x0 0.--31. 1. "FIFO,FIFO direct access. Only locations 0 - 3F will return valid information."
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|
group.long 0x100++0x2F
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line.long 0x0 "FIFOPTR,Provides the current valid byte count of data within the FIFO as seen from the internal state machines. FIFO0 is dedicated to outgoing transactions and FIFO1 is dedicated to incoming transactions. All counts are specified in units of bytes."
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hexmask.long.byte 0x0 24.--31. 1. "FIFO1REM,The number of remaining data bytes slots currently in FIFO 1 (written by interface read by MCU)"
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hexmask.long.byte 0x0 16.--23. 1. "FIFO1SIZ,The number of valid data bytes currently in FIFO 1 (written by interface read by MCU)"
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|
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hexmask.long.byte 0x0 8.--15. 1. "FIFO0REM,The number of remaining data bytes slots currently in FIFO 0 (written by MCU read by interface)"
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hexmask.long.byte 0x0 0.--7. 1. "FIFO0SIZ,The number of valid data bytes currently in the FIFO 0 (written by MCU read by interface)"
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line.long 0x4 "FIFOTHR,Sets the threshold values for incoming and outgoing transactions. The threshold values are used to assert the interrupt if enabled. and also used during DMA to set the transfer size as a result of DMATHR trigger."
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hexmask.long.byte 0x4 8.--13. 1. "FIFOWTHR,FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the write fifo contains FIFOWTHR free bytes as.."
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|
hexmask.long.byte 0x4 0.--5. 1. "FIFORTHR,FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the read fifo contains FIFORTHR valid bytes of data as.."
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line.long 0x8 "FIFOPOP,Will advance the internal read pointer of the incoming FIFO (FIFO1) when read. if POPWR is not active. If POPWR is active. a write to this register is needed to advance the internal FIFO pointer."
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hexmask.long 0x8 0.--31. 1. "FIFODOUT,This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0) the fifo read pointer will be advanced by one word as a result of the read."
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|
line.long 0xC "FIFOPUSH,Will write new data into the outgoing FIFO and advance the internal write pointer."
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hexmask.long 0xC 0.--31. 1. "FIFODIN,This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes)."
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line.long 0x10 "FIFOCTRL,Provides controls for the operation of the internal FIFOs. Contains fields used to control the operation of the POP register. and also controls to reset the internal pointers of the FIFOs."
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bitfld.long 0x10 1. "FIFORSTN,Active low manual reset of the fifo. Write to 0 to reset fifo and then write to 1 to remove the reset." "0,1"
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|
bitfld.long 0x10 0. "POPWR,Selects the mode in which 'pop' events are done for the fifo read operations. A value of '1' will prevent a pop event on a read operation and will require a write to the FIFOPOP register to create a pop event." "0,1"
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line.long 0x14 "FIFOLOC,Provides a read only value of the current read and write pointers. This register is read only and can be used alogn with the FIFO direct access method to determine the next data to be used for input and output functions."
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hexmask.long.byte 0x14 8.--11. 1. "FIFORPTR,Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1) which is used to store read data returned from external devices during a read operation."
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hexmask.long.byte 0x14 0.--3. 1. "FIFOWPTR,Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0) which is used during write operations to external devices."
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line.long 0x18 "CLKCFG,Provides clock related controls used internal to the BLEIF module. and enablement of 32KHz clock to the BLE Core module. The internal clock sourced is selected via the FSEL and can be further divided by 3 using the DIV3 control."
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hexmask.long.byte 0x18 24.--31. 1. "TOTPER,Clock total clock count minus 1. This provides the total period of the divided clock -1 when the DIVEN is active. The"
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|
hexmask.long.byte 0x18 16.--23. 1. "LOWPER,Clock low clock count minus 1. This provides the number of clocks the divided clock will be low when the DIVEN = 1."
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newline
|
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bitfld.long 0x18 12. "DIVEN,Enable clock division by TOTPER and LOWPER" "0: Disable TOTPER division.,1: Enable TOTPER division."
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bitfld.long 0x18 11. "DIV3,Enable divide by 3 of the source IOCLK. Division by 3 is done before the DIVEN programmable divider and if enabled" "0: Select divide by 1.,1: Select divide by 3."
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newline
|
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bitfld.long 0x18 8.--10. "FSEL,Select the input clock frequency." "0: Selects the minimum power clock. This setting..,1: Selects static 0 as the input clock. Previously..,2: Selects the HFRC 48MHz as the input clock.,3: Selects the HFRC 24MHz as the input clock.,4: Selects the HFRC 12MHz as the input clock.,5: Selects the HFRC 6MHz as the input clock.,6: Selects the HFRC 3MHz as the input clock.,7: Selects the HFRC 1.5MHz as the input clock."
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bitfld.long 0x18 0. "IOCLKEN,Enable for the interface clock. Must be enabled prior to executing any IO operations." "0,1"
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|
line.long 0x1C "SUBMODCTRL,Provides enable for each submodule. Only a sigle submodule can be enabled at one time."
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|
bitfld.long 0x1C 9.--11. "SMOD2TYPE,Submodule 2 module type. This is the I2S Master/Slave interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,4: Master/Slave submodule,?,?,7: NOT INSTALLED"
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|
bitfld.long 0x1C 8. "SMOD2EN,Submodule 2 enable (1) or disable (0)" "0,1"
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|
newline
|
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bitfld.long 0x1C 5.--7. "SMOD1TYPE,Submodule 1 module type. This is the I2C Master interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,4: Master/Slave submodule,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 4. "SMOD1EN,Submodule 1 enable (1) or disable (0)" "0,1"
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|
newline
|
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bitfld.long 0x1C 1.--3. "SMOD0TYPE,Submodule 0 module type. This is the SPI Master interface." "0: MSPI submodule,1: I2C Master submodule,2: I2S Master/Slave Module,?,?,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 0. "SMOD0EN,Submodule 0 enable (1) or disable (0)" "0,1"
|
|
line.long 0x20 "CMD,Writes to this register will start an IO transaction. as well as set various parameters for the command itself. Reads will return the command value written to the CMD register."
|
|
hexmask.long.byte 0x20 24.--31. 1. "OFFSETLO,This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command."
|
|
bitfld.long 0x20 20.--21. "CMDSEL,Command Specific selection information. Not used in Master I2C. Used as CEn select for Master SPI transactions" "0,1,2,3"
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|
newline
|
|
hexmask.long.word 0x20 8.--19. 1. "TSIZE,Defines the transaction size in bytes. The offset transfer is not included in this size."
|
|
bitfld.long 0x20 7. "CONT,Contine to hold the bus after the current transaction if set to a 1 with a new command issued." "0,1"
|
|
newline
|
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bitfld.long 0x20 4.--6. "OFFSETCNT,Number of offset bytes to use for the command - 0 1 2 3 4 5 are valid selections. The second (byte 1) third (byte 2) and forth (byte 3) are read from the OFFSETHI register and the low order byte is pulled from this register in the.." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x20 0.--3. 1. "CMD,Command for submodule."
|
|
line.long 0x24 "DCXCTRL,Enables transmission of DCX signal with SPI transactions and selects which CE signals will be used to transmit the DCX signal."
|
|
bitfld.long 0x24 4. "DCXEN,Global enable of the DCX function. Setting to 1 will enable the generation of the DCX signal which will assert when sending the offset bytes of the SPI transaction." "0,1"
|
|
hexmask.long.byte 0x24 0.--3. 1. "DCXSEL,Selects the CE channel used to convey the DCX function. The select is bitwise encoded with bit 0 = 1 enabling CE0 for DCX transmission bit 1 = 1 enableing CE1 for DCX transmission etc. If the CE used for the SPI transaction is set it will be.."
|
|
line.long 0x28 "OFFSETHI,High order bytes of offset for IO transaction"
|
|
hexmask.long 0x28 0.--31. 1. "OFFSETHI,Holds the high order bytes of the byte addressing/offset field to use with IO commands. The number of offset bytes to use is specified in the command register"
|
|
line.long 0x2C "CMDSTAT,Provides staus on the execution of the command currently in progress. The fields in this register will reflect the real time status of the internal state machines and data transfers within the IOM."
|
|
hexmask.long.word 0x2C 8.--19. 1. "CTSIZE,The current number of bytes still to be transferred with this command. This field will count down to zero."
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|
bitfld.long 0x2C 5.--7. "CMDSTAT,The current status of the command execution." "?,1: Error encountered with command,2: Actively processing command,?,4: Idle state no active command no error,?,6: Command in progress but waiting on data from host,?"
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|
newline
|
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hexmask.long.byte 0x2C 0.--4. 1. "CCMD,current command that is being executed"
|
|
group.long 0x200++0x4B
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 14. "CQERR,Error during command queue operations" "0,1"
|
|
bitfld.long 0x0 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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|
newline
|
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bitfld.long 0x0 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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|
bitfld.long 0x0 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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|
newline
|
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bitfld.long 0x0 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0x0 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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|
newline
|
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bitfld.long 0x0 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x0 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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|
newline
|
|
bitfld.long 0x0 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x0 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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|
newline
|
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bitfld.long 0x0 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0x0 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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newline
|
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bitfld.long 0x0 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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|
bitfld.long 0x0 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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|
newline
|
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bitfld.long 0x0 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 14. "CQERR,Error during command queue operations" "0,1"
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|
bitfld.long 0x4 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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|
newline
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bitfld.long 0x4 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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|
bitfld.long 0x4 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
newline
|
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bitfld.long 0x4 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0x4 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x4 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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|
newline
|
|
bitfld.long 0x4 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x4 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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newline
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bitfld.long 0x4 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x4 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0x4 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0x4 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x4 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
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bitfld.long 0x8 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x8 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x8 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x8 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x8 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x8 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0x8 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x8 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x8 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x8 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x8 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x8 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0x8 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0x8 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x8 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
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bitfld.long 0xC 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0xC 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0xC 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0xC 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0xC 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0xC 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0xC 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0xC 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0xC 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0xC 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0xC 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0xC 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0xC 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0xC 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0xC 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x10 "DMATRIGEN,Provides control on which event will trigger the DMA transfer after the DMA operation is setup and enabled. The trigger event will cause a number of bytes (depending on trigger event) to be"
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|
bitfld.long 0x10 1. "DTHREN,Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes) the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO and will transfer (WTHR/4) number of words" "0,1"
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bitfld.long 0x10 0. "DCMDCMPEN,Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered the number of words transferred will be the lesser of the remaining TOTCOUNT bytes or" "0,1"
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line.long 0x14 "DMATRIGSTAT,Provides the status of trigger events that have occurred for the transaction. Some of the bits are read only and some can be reset via a write of 0."
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bitfld.long 0x14 2. "DTOTCMP,DMA triggered when DCMDCMP = 0 and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is" "0,1"
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bitfld.long 0x14 1. "DTHR,Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA." "0,1"
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bitfld.long 0x14 0. "DCMDCMP,Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA." "0,1"
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line.long 0x18 "DMACFG,Configuration control of the DMA process. including the direction of DMA. and enablement of DMA"
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bitfld.long 0x18 9. "DPWROFF,Power off module after DMA is complete. If this bit is active the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain power down will not be performed." "0: Power off disabled,1: Power off enabled"
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bitfld.long 0x18 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x18 1. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction. To be..,1: Memory to Peripheral transaction. To be set when.."
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bitfld.long 0x18 0. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable DMA Function,1: Enable DMA Function"
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line.long 0x1C "DMATOTCOUNT,Contains the number of bytes to be transferred for this DMA transaction. This register is decremented as the data is transferred. and will be 0 at the completion of the DMA operation."
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hexmask.long.word 0x1C 0.--11. 1. "TOTCOUNT,Triggered DMA from Command complete event occured. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."
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line.long 0x20 "DMATARGADDR,The source or destination address internal the SRAM for the DMA data. For write operations. this can only be SRAM data (ADDR bit 28 = 1); For read operations. this can ve either SRAM or FLASH (ADDR bit 28 = 0)"
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hexmask.long 0x20 0.--28. 1. "TARGADDR,Bits [28:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment and does not have to be word aligned. In cases of non-word aligned addresses the DMA logic will take care for ensuring only.."
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line.long 0x24 "DMASTAT,Status of the DMA operation currently in progress."
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bitfld.long 0x24 2. "DMAERR,DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set this bit will remain set until cleared by software." "0,1"
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bitfld.long 0x24 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0 and will also be cleared when a new DMA is started." "0,1"
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bitfld.long 0x24 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
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line.long 0x28 "CQCFG,Controls parameters and options for execution of the command queue operation. To enable command queue. create this in memory. set the address. and enable it with a write to CQEN"
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bitfld.long 0x28 2.--3. "MSPIFLGSEL,Selects the MPSI modules used for sourcing the CQFLAG [11:8]." "0: Selects MPSI0 as source of signals used in..,1: Selects MPSI1 as source of signals used in..,2: Selects MPSI2 as source of signals used in..,?"
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bitfld.long 0x28 1. "CQPRI,Sets the Priority of the command queue dma request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x28 0. "CQEN,Command queue enable. When set will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled" "0: Disable CQ Function,1: Enable CQ Function"
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line.long 0x2C "CQADDR,The SRAM address which will be fetched next execution of the CQ operation. This register is updated as the CQ operation progresses. and is the live version of the register. The register can also be"
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hexmask.long 0x2C 2.--28. 1. "CQADDR,Bits 28:2 of target byte address for source of CQ . The buffer must be aligned on a word boundary"
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line.long 0x30 "CQSTAT,Provides the status of the command queue operation. If the command queue is disabled. these bits will be cleared. The bits are read only"
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bitfld.long 0x30 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
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bitfld.long 0x30 1. "CQPAUSED,Command queue operation is currently paused." "0,1"
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bitfld.long 0x30 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
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line.long 0x34 "CQFLAGS,Command Queue Flag"
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hexmask.long.word 0x34 16.--31. 1. "CQIRQMASK,Mask the bits used to generate the command queue interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE"
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hexmask.long.word 0x34 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
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line.long 0x38 "CQSETCLEAR,Set/Clear the command queue software pause flags on a per-bit basis. Contains 3 fields. allowing for setting. clearing or toggling the value in the software flags. Priority when the same bit"
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hexmask.long.byte 0x38 16.--23. 1. "CQFCLR,Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x38 8.--15. 1. "CQFTGL,Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x38 0.--7. 1. "CQFSET,Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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line.long 0x3C "CQPAUSEEN,Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the CQFLAG register is '1'. CQ processing will halt until either value is changed to '0'."
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hexmask.long.word 0x3C 0.--15. 1. "CQPEN,Enables the specified event to pause command processing when active"
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line.long 0x40 "CQCURIDX,Current index value. targeted to be written by register write operations within the command queue. This is compared to the CQENDIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and"
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hexmask.long.byte 0x40 0.--7. 1. "CQCURIDX,Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x44 "CQENDIDX,End index value. targeted to be written by software to indicate the last valid register pair contained within the command queue. rgister write operations within the command queue."
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hexmask.long.byte 0x44 0.--7. 1. "CQENDIDX,Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x48 "STATUS,IOM Module Status"
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bitfld.long 0x48 2. "IDLEST,indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to holdoffs from data availability or as the command gets propagated into the logic from the registers." "0: The I/O state machine is in the non-idle/run..,1: The I/O state machine is in the idle state."
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bitfld.long 0x48 1. "CMDACT,Indicates if the active I/O Command is currently processing a transaction or command is complete but the FIFO pointers are still syncronizing internally. This bit will go high at" "0: An I/O command is inactive. Indicating that the..,1: An I/O command is active. Indicates the active.."
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bitfld.long 0x48 0. "ERR,Bit has been deprecated. Please refer to the other error indicators. This will always return 0." "0: Default value.,1: Bit has been deprecated and will always return 0."
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group.long 0x280++0x3
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line.long 0x0 "MSPICFG,Controls the configuration of the SPI master module. including POL/PHA. LSB. flow control. and delays for MISO and MOSI"
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bitfld.long 0x0 30. "MSPIRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 27.--29. "DOUTDLY,Delay tap to use for the output signal (MOSI). This give more hold time on the output data" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 24.--26. "DINDLY,Delay tap to use for the input signal (MISO). This gives more hold time on the input data." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "SPILSB,Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first." "0: Send and receive MSB bit first,1: Send and receive LSB bit first"
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bitfld.long 0x0 22. "RDFCPOL,Selects the read flow control signal polarity." "0: Flow control signal high creates flow control.,1: Flow control signal low creates flow control."
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bitfld.long 0x0 21. "WTFCPOL,selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 will allow a IRQ=1 to pause transfers)." "0: Flow control signal high(1) creates flow control..,1: Flow control signal low(0) creates flow control.."
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bitfld.long 0x0 20. "WTFCIRQ,Selects the write mode flow control signal." "0: MISO is used as the write mode flow control..,1: IRQ is used as the write mode flow control signal."
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bitfld.long 0x0 18. "MOSIINV,Inverts MOSI when flow control is enabled." "0: MOSI is set to 0 in read mode and 1 in write mode.,1: MOSI is set to 1 in read mode and 0 in write mode."
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bitfld.long 0x0 17. "RDFC,Enables read mode flow control." "0: Read mode flow control disabled.,1: Read mode flow control enabled."
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bitfld.long 0x0 16. "WTFC,enables write mode flow control." "0: Write mode flow control disabled.,1: Write mode flow control enabled."
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bitfld.long 0x0 2. "FULLDUP,Enables full duplex mode for Master SPI write operations. Data will be captured simultaneously into the read fifo" "0,1"
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bitfld.long 0x0 1. "SPHA,Selects SPI phase.IMPORTANT NOTICE: Due to the susceptibility of creating a clock glitch which could cause register corruption changing SPHA and SPOL bits should be done in separate writes to this register." "0: Sample on the leading (first) clock edge.,1: Sample on the trailing (second) clock edge."
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newline
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bitfld.long 0x0 0. "SPOL,Selects SPI polarity.IMPORTANT NOTICE: Due to the susceptibility of creating a clock glitch which could cause register corruption changing SPHA and SPOL bits should be done in separate writes to this register." "0: The base value of the clock is 0.,1: The base value of the clock is 1."
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group.long 0x2C0++0x7
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line.long 0x0 "MI2CCFG,Controls the configuration of the I2C bus master."
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bitfld.long 0x0 24. "STRDIS,Disable detection of clock stretch events smaller than 1 cycle" "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "SMPCNT,Number of Base clk cycles to wait before sampling the SCL clock to determine if a clock stretch event has occured"
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hexmask.long.byte 0x0 12.--15. 1. "SDAENDLY,Number of IOCLK cycles to delay the SDA output en (all transitions affected). Used to delay data relative to clock"
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hexmask.long.byte 0x0 8.--11. 1. "SCLENDLY,Number of IOCLK cycles to delay the rising edge of the SCL output en (clock will go low on this edge). Used to allow clock shaping."
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bitfld.long 0x0 6. "MI2CRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 4.--5. "SDADLY,Delay to enable on the SDA output. Values are 0x0-0x3." "0,1,2,3"
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bitfld.long 0x0 2. "ARBEN,Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master this function can be disabled to save clock cycles on I2C transactions" "0: Disable multi-master bus arbitration support for..,1: Enable multi-master bus arbitration support for.."
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bitfld.long 0x0 1. "I2CLSB,Direction of data transmit and receive MSB(0) or LSB(1) first. Default per I2C specification is MSB first. This applies to both read and write data and read data will be bit" "0: Byte data is transmitted MSB first onto the..,1: Byte data is transmitted LSB first onto the.."
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bitfld.long 0x0 0. "ADDRSZ,Sets the I2C master device address size to either 7b (0) or 10b (1)." "0: Use 7b addressing for I2C master transactions,1: Use 10b addressing for I2C master transactions"
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line.long 0x4 "DEVCFG,Contains the I2C device address."
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hexmask.long.word 0x4 0.--9. 1. "DEVADDR,I2C address of the device that the Master will use to target for read/write operations. This can be either a 7b or 10b address."
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group.long 0x388++0x3
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line.long 0x0 "IOMDBG,Debug control"
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hexmask.long 0x0 3.--31. 1. "DBGDATA,Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers."
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bitfld.long 0x0 2. "APBCLKON,APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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newline
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bitfld.long 0x0 1. "IOCLKON,IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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bitfld.long 0x0 0. "DBGEN,Debug Enable. Setting bit will enable the update of data within this register otherwise it is clock gated for power savings" "0,1"
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tree.end
|
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endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMA4B2KP")||cpuis("AMAP42KL")||cpuis("AMAP42KP"))
|
|
tree "IOM5"
|
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base ad:0x40055000
|
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group.long 0x0++0x3
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|
line.long 0x0 "FIFO,Provides direct random access to both input and output fifos. The state of the FIFO is not distured by reading these locations (ie no POP will be done). FIFO0 is accessible from addresses 0x0 - 0x1C. and is used for data outuput from the IOM to.."
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hexmask.long 0x0 0.--31. 1. "FIFO,FIFO direct access. Only locations 0 - 3F will return valid information."
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group.long 0x100++0x2F
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line.long 0x0 "FIFOPTR,Provides the current valid byte count of data within the FIFO as seen from the internal state machines. FIFO0 is dedicated to outgoing transactions and FIFO1 is dedicated to incoming transactions. All counts are specified in units of bytes."
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hexmask.long.byte 0x0 24.--31. 1. "FIFO1REM,The number of remaining data bytes slots currently in FIFO 1 (written by interface read by MCU)"
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hexmask.long.byte 0x0 16.--23. 1. "FIFO1SIZ,The number of valid data bytes currently in FIFO 1 (written by interface read by MCU)"
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|
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hexmask.long.byte 0x0 8.--15. 1. "FIFO0REM,The number of remaining data bytes slots currently in FIFO 0 (written by MCU read by interface)"
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hexmask.long.byte 0x0 0.--7. 1. "FIFO0SIZ,The number of valid data bytes currently in the FIFO 0 (written by MCU read by interface)"
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line.long 0x4 "FIFOTHR,Sets the threshold values for incoming and outgoing transactions. The threshold values are used to assert the interrupt if enabled. and also used during DMA to set the transfer size as a result of DMATHR trigger."
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hexmask.long.byte 0x4 8.--13. 1. "FIFOWTHR,FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the write fifo contains FIFOWTHR free bytes as.."
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|
hexmask.long.byte 0x4 0.--5. 1. "FIFORTHR,FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the read fifo contains FIFORTHR valid bytes of data as.."
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|
line.long 0x8 "FIFOPOP,Will advance the internal read pointer of the incoming FIFO (FIFO1) when read. if POPWR is not active. If POPWR is active. a write to this register is needed to advance the internal FIFO pointer."
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hexmask.long 0x8 0.--31. 1. "FIFODOUT,This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0) the fifo read pointer will be advanced by one word as a result of the read."
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line.long 0xC "FIFOPUSH,Will write new data into the outgoing FIFO and advance the internal write pointer."
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hexmask.long 0xC 0.--31. 1. "FIFODIN,This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes)."
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|
line.long 0x10 "FIFOCTRL,Provides controls for the operation of the internal FIFOs. Contains fields used to control the operation of the POP register. and also controls to reset the internal pointers of the FIFOs."
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bitfld.long 0x10 1. "FIFORSTN,Active low manual reset of the fifo. Write to 0 to reset fifo and then write to 1 to remove the reset." "0,1"
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bitfld.long 0x10 0. "POPWR,Selects the mode in which 'pop' events are done for the fifo read operations. A value of '1' will prevent a pop event on a read operation and will require a write to the FIFOPOP register to create a pop event." "0,1"
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line.long 0x14 "FIFOLOC,Provides a read only value of the current read and write pointers. This register is read only and can be used alogn with the FIFO direct access method to determine the next data to be used for input and output functions."
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hexmask.long.byte 0x14 8.--11. 1. "FIFORPTR,Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1) which is used to store read data returned from external devices during a read operation."
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hexmask.long.byte 0x14 0.--3. 1. "FIFOWPTR,Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0) which is used during write operations to external devices."
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line.long 0x18 "CLKCFG,Provides clock related controls used internal to the BLEIF module. and enablement of 32KHz clock to the BLE Core module. The internal clock sourced is selected via the FSEL and can be further divided by 3 using the DIV3 control."
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hexmask.long.byte 0x18 24.--31. 1. "TOTPER,Clock total clock count minus 1. This provides the total period of the divided clock -1 when the DIVEN is active. The"
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hexmask.long.byte 0x18 16.--23. 1. "LOWPER,Clock low clock count minus 1. This provides the number of clocks the divided clock will be low when the DIVEN = 1."
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bitfld.long 0x18 12. "DIVEN,Enable clock division by TOTPER and LOWPER" "0: Disable TOTPER division.,1: Enable TOTPER division."
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bitfld.long 0x18 11. "DIV3,Enable divide by 3 of the source IOCLK. Division by 3 is done before the DIVEN programmable divider and if enabled" "0: Select divide by 1.,1: Select divide by 3."
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bitfld.long 0x18 8.--10. "FSEL,Select the input clock frequency." "0: Selects the minimum power clock. This setting..,1: Selects static 0 as the input clock. Previously..,2: Selects the HFRC 48MHz as the input clock.,3: Selects the HFRC 24MHz as the input clock.,4: Selects the HFRC 12MHz as the input clock.,5: Selects the HFRC 6MHz as the input clock.,6: Selects the HFRC 3MHz as the input clock.,7: Selects the HFRC 1.5MHz as the input clock."
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bitfld.long 0x18 0. "IOCLKEN,Enable for the interface clock. Must be enabled prior to executing any IO operations." "0,1"
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line.long 0x1C "SUBMODCTRL,Provides enable for each submodule. Only a sigle submodule can be enabled at one time."
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bitfld.long 0x1C 9.--11. "SMOD2TYPE,Submodule 2 module type. This is the I2S Master/Slave interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,4: Master/Slave submodule,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 8. "SMOD2EN,Submodule 2 enable (1) or disable (0)" "0,1"
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bitfld.long 0x1C 5.--7. "SMOD1TYPE,Submodule 1 module type. This is the I2C Master interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,4: Master/Slave submodule,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 4. "SMOD1EN,Submodule 1 enable (1) or disable (0)" "0,1"
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bitfld.long 0x1C 1.--3. "SMOD0TYPE,Submodule 0 module type. This is the SPI Master interface." "0: MSPI submodule,1: I2C Master submodule,2: I2S Master/Slave Module,?,?,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 0. "SMOD0EN,Submodule 0 enable (1) or disable (0)" "0,1"
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line.long 0x20 "CMD,Writes to this register will start an IO transaction. as well as set various parameters for the command itself. Reads will return the command value written to the CMD register."
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hexmask.long.byte 0x20 24.--31. 1. "OFFSETLO,This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command."
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bitfld.long 0x20 20.--21. "CMDSEL,Command Specific selection information. Not used in Master I2C. Used as CEn select for Master SPI transactions" "0,1,2,3"
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hexmask.long.word 0x20 8.--19. 1. "TSIZE,Defines the transaction size in bytes. The offset transfer is not included in this size."
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bitfld.long 0x20 7. "CONT,Contine to hold the bus after the current transaction if set to a 1 with a new command issued." "0,1"
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bitfld.long 0x20 4.--6. "OFFSETCNT,Number of offset bytes to use for the command - 0 1 2 3 4 5 are valid selections. The second (byte 1) third (byte 2) and forth (byte 3) are read from the OFFSETHI register and the low order byte is pulled from this register in the.." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x20 0.--3. 1. "CMD,Command for submodule."
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line.long 0x24 "DCXCTRL,Enables transmission of DCX signal with SPI transactions and selects which CE signals will be used to transmit the DCX signal."
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bitfld.long 0x24 4. "DCXEN,Global enable of the DCX function. Setting to 1 will enable the generation of the DCX signal which will assert when sending the offset bytes of the SPI transaction." "0,1"
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hexmask.long.byte 0x24 0.--3. 1. "DCXSEL,Selects the CE channel used to convey the DCX function. The select is bitwise encoded with bit 0 = 1 enabling CE0 for DCX transmission bit 1 = 1 enableing CE1 for DCX transmission etc. If the CE used for the SPI transaction is set it will be.."
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line.long 0x28 "OFFSETHI,High order bytes of offset for IO transaction"
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hexmask.long 0x28 0.--31. 1. "OFFSETHI,Holds the high order bytes of the byte addressing/offset field to use with IO commands. The number of offset bytes to use is specified in the command register"
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line.long 0x2C "CMDSTAT,Provides staus on the execution of the command currently in progress. The fields in this register will reflect the real time status of the internal state machines and data transfers within the IOM."
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hexmask.long.word 0x2C 8.--19. 1. "CTSIZE,The current number of bytes still to be transferred with this command. This field will count down to zero."
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bitfld.long 0x2C 5.--7. "CMDSTAT,The current status of the command execution." "?,1: Error encountered with command,2: Actively processing command,?,4: Idle state no active command no error,?,6: Command in progress but waiting on data from host,?"
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hexmask.long.byte 0x2C 0.--4. 1. "CCMD,current command that is being executed"
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group.long 0x200++0x4B
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line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
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bitfld.long 0x0 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x0 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x0 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x0 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x0 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x0 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0x0 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x0 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x0 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x0 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x0 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x0 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0x0 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0x0 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x0 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
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bitfld.long 0x4 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x4 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x4 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x4 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x4 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x4 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0x4 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x4 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x4 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x4 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x4 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x4 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0x4 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0x4 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x4 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
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bitfld.long 0x8 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x8 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x8 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x8 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x8 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x8 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0x8 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x8 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x8 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x8 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x8 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x8 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0x8 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0x8 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x8 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
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bitfld.long 0xC 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0xC 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0xC 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0xC 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0xC 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0xC 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0xC 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0xC 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0xC 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0xC 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0xC 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0xC 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0xC 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0xC 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0xC 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x10 "DMATRIGEN,Provides control on which event will trigger the DMA transfer after the DMA operation is setup and enabled. The trigger event will cause a number of bytes (depending on trigger event) to be"
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bitfld.long 0x10 1. "DTHREN,Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes) the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO and will transfer (WTHR/4) number of words" "0,1"
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bitfld.long 0x10 0. "DCMDCMPEN,Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered the number of words transferred will be the lesser of the remaining TOTCOUNT bytes or" "0,1"
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line.long 0x14 "DMATRIGSTAT,Provides the status of trigger events that have occurred for the transaction. Some of the bits are read only and some can be reset via a write of 0."
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bitfld.long 0x14 2. "DTOTCMP,DMA triggered when DCMDCMP = 0 and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is" "0,1"
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bitfld.long 0x14 1. "DTHR,Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA." "0,1"
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bitfld.long 0x14 0. "DCMDCMP,Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA." "0,1"
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line.long 0x18 "DMACFG,Configuration control of the DMA process. including the direction of DMA. and enablement of DMA"
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bitfld.long 0x18 9. "DPWROFF,Power off module after DMA is complete. If this bit is active the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain power down will not be performed." "0: Power off disabled,1: Power off enabled"
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bitfld.long 0x18 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x18 1. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction. To be..,1: Memory to Peripheral transaction. To be set when.."
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bitfld.long 0x18 0. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable DMA Function,1: Enable DMA Function"
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line.long 0x1C "DMATOTCOUNT,Contains the number of bytes to be transferred for this DMA transaction. This register is decremented as the data is transferred. and will be 0 at the completion of the DMA operation."
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hexmask.long.word 0x1C 0.--11. 1. "TOTCOUNT,Triggered DMA from Command complete event occured. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."
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line.long 0x20 "DMATARGADDR,The source or destination address internal the SRAM for the DMA data. For write operations. this can only be SRAM data (ADDR bit 28 = 1); For read operations. this can ve either SRAM or FLASH (ADDR bit 28 = 0)"
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hexmask.long 0x20 0.--28. 1. "TARGADDR,Bits [28:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment and does not have to be word aligned. In cases of non-word aligned addresses the DMA logic will take care for ensuring only.."
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line.long 0x24 "DMASTAT,Status of the DMA operation currently in progress."
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bitfld.long 0x24 2. "DMAERR,DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set this bit will remain set until cleared by software." "0,1"
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bitfld.long 0x24 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0 and will also be cleared when a new DMA is started." "0,1"
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bitfld.long 0x24 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
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line.long 0x28 "CQCFG,Controls parameters and options for execution of the command queue operation. To enable command queue. create this in memory. set the address. and enable it with a write to CQEN"
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bitfld.long 0x28 2.--3. "MSPIFLGSEL,Selects the MPSI modules used for sourcing the CQFLAG [11:8]." "0: Selects MPSI0 as source of signals used in..,1: Selects MPSI1 as source of signals used in..,2: Selects MPSI2 as source of signals used in..,?"
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bitfld.long 0x28 1. "CQPRI,Sets the Priority of the command queue dma request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x28 0. "CQEN,Command queue enable. When set will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled" "0: Disable CQ Function,1: Enable CQ Function"
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line.long 0x2C "CQADDR,The SRAM address which will be fetched next execution of the CQ operation. This register is updated as the CQ operation progresses. and is the live version of the register. The register can also be"
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hexmask.long 0x2C 2.--28. 1. "CQADDR,Bits 28:2 of target byte address for source of CQ . The buffer must be aligned on a word boundary"
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line.long 0x30 "CQSTAT,Provides the status of the command queue operation. If the command queue is disabled. these bits will be cleared. The bits are read only"
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bitfld.long 0x30 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
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bitfld.long 0x30 1. "CQPAUSED,Command queue operation is currently paused." "0,1"
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bitfld.long 0x30 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
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line.long 0x34 "CQFLAGS,Command Queue Flag"
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hexmask.long.word 0x34 16.--31. 1. "CQIRQMASK,Mask the bits used to generate the command queue interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE"
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hexmask.long.word 0x34 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
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line.long 0x38 "CQSETCLEAR,Set/Clear the command queue software pause flags on a per-bit basis. Contains 3 fields. allowing for setting. clearing or toggling the value in the software flags. Priority when the same bit"
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hexmask.long.byte 0x38 16.--23. 1. "CQFCLR,Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x38 8.--15. 1. "CQFTGL,Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x38 0.--7. 1. "CQFSET,Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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line.long 0x3C "CQPAUSEEN,Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the CQFLAG register is '1'. CQ processing will halt until either value is changed to '0'."
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|
hexmask.long.word 0x3C 0.--15. 1. "CQPEN,Enables the specified event to pause command processing when active"
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|
line.long 0x40 "CQCURIDX,Current index value. targeted to be written by register write operations within the command queue. This is compared to the CQENDIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and"
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|
hexmask.long.byte 0x40 0.--7. 1. "CQCURIDX,Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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|
line.long 0x44 "CQENDIDX,End index value. targeted to be written by software to indicate the last valid register pair contained within the command queue. rgister write operations within the command queue."
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|
hexmask.long.byte 0x44 0.--7. 1. "CQENDIDX,Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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|
line.long 0x48 "STATUS,IOM Module Status"
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|
bitfld.long 0x48 2. "IDLEST,indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to holdoffs from data availability or as the command gets propagated into the logic from the registers." "0: The I/O state machine is in the non-idle/run..,1: The I/O state machine is in the idle state."
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bitfld.long 0x48 1. "CMDACT,Indicates if the active I/O Command is currently processing a transaction or command is complete but the FIFO pointers are still syncronizing internally. This bit will go high at" "0: An I/O command is inactive. Indicating that the..,1: An I/O command is active. Indicates the active.."
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|
newline
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bitfld.long 0x48 0. "ERR,Bit has been deprecated. Please refer to the other error indicators. This will always return 0." "0: Default value.,1: Bit has been deprecated and will always return 0."
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|
group.long 0x280++0x3
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|
line.long 0x0 "MSPICFG,Controls the configuration of the SPI master module. including POL/PHA. LSB. flow control. and delays for MISO and MOSI"
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|
bitfld.long 0x0 30. "MSPIRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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|
bitfld.long 0x0 27.--29. "DOUTDLY,Delay tap to use for the output signal (MOSI). This give more hold time on the output data" "0,1,2,3,4,5,6,7"
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|
newline
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bitfld.long 0x0 24.--26. "DINDLY,Delay tap to use for the input signal (MISO). This gives more hold time on the input data." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "SPILSB,Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first." "0: Send and receive MSB bit first,1: Send and receive LSB bit first"
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|
newline
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bitfld.long 0x0 22. "RDFCPOL,Selects the read flow control signal polarity." "0: Flow control signal high creates flow control.,1: Flow control signal low creates flow control."
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bitfld.long 0x0 21. "WTFCPOL,selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 will allow a IRQ=1 to pause transfers)." "0: Flow control signal high(1) creates flow control..,1: Flow control signal low(0) creates flow control.."
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newline
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bitfld.long 0x0 20. "WTFCIRQ,Selects the write mode flow control signal." "0: MISO is used as the write mode flow control..,1: IRQ is used as the write mode flow control signal."
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bitfld.long 0x0 18. "MOSIINV,Inverts MOSI when flow control is enabled." "0: MOSI is set to 0 in read mode and 1 in write mode.,1: MOSI is set to 1 in read mode and 0 in write mode."
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newline
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bitfld.long 0x0 17. "RDFC,Enables read mode flow control." "0: Read mode flow control disabled.,1: Read mode flow control enabled."
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|
bitfld.long 0x0 16. "WTFC,enables write mode flow control." "0: Write mode flow control disabled.,1: Write mode flow control enabled."
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|
newline
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bitfld.long 0x0 2. "FULLDUP,Enables full duplex mode for Master SPI write operations. Data will be captured simultaneously into the read fifo" "0,1"
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bitfld.long 0x0 1. "SPHA,Selects SPI phase.IMPORTANT NOTICE: Due to the susceptibility of creating a clock glitch which could cause register corruption changing SPHA and SPOL bits should be done in separate writes to this register." "0: Sample on the leading (first) clock edge.,1: Sample on the trailing (second) clock edge."
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newline
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bitfld.long 0x0 0. "SPOL,Selects SPI polarity.IMPORTANT NOTICE: Due to the susceptibility of creating a clock glitch which could cause register corruption changing SPHA and SPOL bits should be done in separate writes to this register." "0: The base value of the clock is 0.,1: The base value of the clock is 1."
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|
group.long 0x2C0++0x7
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|
line.long 0x0 "MI2CCFG,Controls the configuration of the I2C bus master."
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|
bitfld.long 0x0 24. "STRDIS,Disable detection of clock stretch events smaller than 1 cycle" "0,1"
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|
hexmask.long.byte 0x0 16.--23. 1. "SMPCNT,Number of Base clk cycles to wait before sampling the SCL clock to determine if a clock stretch event has occured"
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|
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hexmask.long.byte 0x0 12.--15. 1. "SDAENDLY,Number of IOCLK cycles to delay the SDA output en (all transitions affected). Used to delay data relative to clock"
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|
hexmask.long.byte 0x0 8.--11. 1. "SCLENDLY,Number of IOCLK cycles to delay the rising edge of the SCL output en (clock will go low on this edge). Used to allow clock shaping."
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|
newline
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bitfld.long 0x0 6. "MI2CRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 4.--5. "SDADLY,Delay to enable on the SDA output. Values are 0x0-0x3." "0,1,2,3"
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|
newline
|
|
bitfld.long 0x0 2. "ARBEN,Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master this function can be disabled to save clock cycles on I2C transactions" "0: Disable multi-master bus arbitration support for..,1: Enable multi-master bus arbitration support for.."
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|
bitfld.long 0x0 1. "I2CLSB,Direction of data transmit and receive MSB(0) or LSB(1) first. Default per I2C specification is MSB first. This applies to both read and write data and read data will be bit" "0: Byte data is transmitted MSB first onto the..,1: Byte data is transmitted LSB first onto the.."
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|
newline
|
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bitfld.long 0x0 0. "ADDRSZ,Sets the I2C master device address size to either 7b (0) or 10b (1)." "0: Use 7b addressing for I2C master transactions,1: Use 10b addressing for I2C master transactions"
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|
line.long 0x4 "DEVCFG,Contains the I2C device address."
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hexmask.long.word 0x4 0.--9. 1. "DEVADDR,I2C address of the device that the Master will use to target for read/write operations. This can be either a 7b or 10b address."
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|
group.long 0x388++0x3
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|
line.long 0x0 "IOMDBG,Debug control"
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|
hexmask.long 0x0 3.--31. 1. "DBGDATA,Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers."
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bitfld.long 0x0 2. "APBCLKON,APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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|
newline
|
|
bitfld.long 0x0 1. "IOCLKON,IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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|
bitfld.long 0x0 0. "DBGEN,Debug Enable. Setting bit will enable the update of data within this register otherwise it is clock gated for power savings" "0,1"
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|
tree.end
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMA4B2KP")||cpuis("AMAP42KL")||cpuis("AMAP42KP"))
|
|
tree "IOM6"
|
|
base ad:0x40056000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FIFO,Provides direct random access to both input and output fifos. The state of the FIFO is not distured by reading these locations (ie no POP will be done). FIFO0 is accessible from addresses 0x0 - 0x1C. and is used for data outuput from the IOM to.."
|
|
hexmask.long 0x0 0.--31. 1. "FIFO,FIFO direct access. Only locations 0 - 3F will return valid information."
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|
group.long 0x100++0x2F
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|
line.long 0x0 "FIFOPTR,Provides the current valid byte count of data within the FIFO as seen from the internal state machines. FIFO0 is dedicated to outgoing transactions and FIFO1 is dedicated to incoming transactions. All counts are specified in units of bytes."
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hexmask.long.byte 0x0 24.--31. 1. "FIFO1REM,The number of remaining data bytes slots currently in FIFO 1 (written by interface read by MCU)"
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|
hexmask.long.byte 0x0 16.--23. 1. "FIFO1SIZ,The number of valid data bytes currently in FIFO 1 (written by interface read by MCU)"
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|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "FIFO0REM,The number of remaining data bytes slots currently in FIFO 0 (written by MCU read by interface)"
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|
hexmask.long.byte 0x0 0.--7. 1. "FIFO0SIZ,The number of valid data bytes currently in the FIFO 0 (written by MCU read by interface)"
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|
line.long 0x4 "FIFOTHR,Sets the threshold values for incoming and outgoing transactions. The threshold values are used to assert the interrupt if enabled. and also used during DMA to set the transfer size as a result of DMATHR trigger."
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|
hexmask.long.byte 0x4 8.--13. 1. "FIFOWTHR,FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the write fifo contains FIFOWTHR free bytes as.."
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|
hexmask.long.byte 0x4 0.--5. 1. "FIFORTHR,FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the read fifo contains FIFORTHR valid bytes of data as.."
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|
line.long 0x8 "FIFOPOP,Will advance the internal read pointer of the incoming FIFO (FIFO1) when read. if POPWR is not active. If POPWR is active. a write to this register is needed to advance the internal FIFO pointer."
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hexmask.long 0x8 0.--31. 1. "FIFODOUT,This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0) the fifo read pointer will be advanced by one word as a result of the read."
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|
line.long 0xC "FIFOPUSH,Will write new data into the outgoing FIFO and advance the internal write pointer."
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|
hexmask.long 0xC 0.--31. 1. "FIFODIN,This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes)."
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line.long 0x10 "FIFOCTRL,Provides controls for the operation of the internal FIFOs. Contains fields used to control the operation of the POP register. and also controls to reset the internal pointers of the FIFOs."
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bitfld.long 0x10 1. "FIFORSTN,Active low manual reset of the fifo. Write to 0 to reset fifo and then write to 1 to remove the reset." "0,1"
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bitfld.long 0x10 0. "POPWR,Selects the mode in which 'pop' events are done for the fifo read operations. A value of '1' will prevent a pop event on a read operation and will require a write to the FIFOPOP register to create a pop event." "0,1"
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line.long 0x14 "FIFOLOC,Provides a read only value of the current read and write pointers. This register is read only and can be used alogn with the FIFO direct access method to determine the next data to be used for input and output functions."
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hexmask.long.byte 0x14 8.--11. 1. "FIFORPTR,Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1) which is used to store read data returned from external devices during a read operation."
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hexmask.long.byte 0x14 0.--3. 1. "FIFOWPTR,Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0) which is used during write operations to external devices."
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line.long 0x18 "CLKCFG,Provides clock related controls used internal to the BLEIF module. and enablement of 32KHz clock to the BLE Core module. The internal clock sourced is selected via the FSEL and can be further divided by 3 using the DIV3 control."
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hexmask.long.byte 0x18 24.--31. 1. "TOTPER,Clock total clock count minus 1. This provides the total period of the divided clock -1 when the DIVEN is active. The"
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hexmask.long.byte 0x18 16.--23. 1. "LOWPER,Clock low clock count minus 1. This provides the number of clocks the divided clock will be low when the DIVEN = 1."
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newline
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bitfld.long 0x18 12. "DIVEN,Enable clock division by TOTPER and LOWPER" "0: Disable TOTPER division.,1: Enable TOTPER division."
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bitfld.long 0x18 11. "DIV3,Enable divide by 3 of the source IOCLK. Division by 3 is done before the DIVEN programmable divider and if enabled" "0: Select divide by 1.,1: Select divide by 3."
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newline
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bitfld.long 0x18 8.--10. "FSEL,Select the input clock frequency." "0: Selects the minimum power clock. This setting..,1: Selects static 0 as the input clock. Previously..,2: Selects the HFRC 48MHz as the input clock.,3: Selects the HFRC 24MHz as the input clock.,4: Selects the HFRC 12MHz as the input clock.,5: Selects the HFRC 6MHz as the input clock.,6: Selects the HFRC 3MHz as the input clock.,7: Selects the HFRC 1.5MHz as the input clock."
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bitfld.long 0x18 0. "IOCLKEN,Enable for the interface clock. Must be enabled prior to executing any IO operations." "0,1"
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line.long 0x1C "SUBMODCTRL,Provides enable for each submodule. Only a sigle submodule can be enabled at one time."
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bitfld.long 0x1C 9.--11. "SMOD2TYPE,Submodule 2 module type. This is the I2S Master/Slave interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,4: Master/Slave submodule,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 8. "SMOD2EN,Submodule 2 enable (1) or disable (0)" "0,1"
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newline
|
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bitfld.long 0x1C 5.--7. "SMOD1TYPE,Submodule 1 module type. This is the I2C Master interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,4: Master/Slave submodule,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 4. "SMOD1EN,Submodule 1 enable (1) or disable (0)" "0,1"
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newline
|
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bitfld.long 0x1C 1.--3. "SMOD0TYPE,Submodule 0 module type. This is the SPI Master interface." "0: MSPI submodule,1: I2C Master submodule,2: I2S Master/Slave Module,?,?,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 0. "SMOD0EN,Submodule 0 enable (1) or disable (0)" "0,1"
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line.long 0x20 "CMD,Writes to this register will start an IO transaction. as well as set various parameters for the command itself. Reads will return the command value written to the CMD register."
|
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hexmask.long.byte 0x20 24.--31. 1. "OFFSETLO,This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command."
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bitfld.long 0x20 20.--21. "CMDSEL,Command Specific selection information. Not used in Master I2C. Used as CEn select for Master SPI transactions" "0,1,2,3"
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newline
|
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hexmask.long.word 0x20 8.--19. 1. "TSIZE,Defines the transaction size in bytes. The offset transfer is not included in this size."
|
|
bitfld.long 0x20 7. "CONT,Contine to hold the bus after the current transaction if set to a 1 with a new command issued." "0,1"
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|
newline
|
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bitfld.long 0x20 4.--6. "OFFSETCNT,Number of offset bytes to use for the command - 0 1 2 3 4 5 are valid selections. The second (byte 1) third (byte 2) and forth (byte 3) are read from the OFFSETHI register and the low order byte is pulled from this register in the.." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x20 0.--3. 1. "CMD,Command for submodule."
|
|
line.long 0x24 "DCXCTRL,Enables transmission of DCX signal with SPI transactions and selects which CE signals will be used to transmit the DCX signal."
|
|
bitfld.long 0x24 4. "DCXEN,Global enable of the DCX function. Setting to 1 will enable the generation of the DCX signal which will assert when sending the offset bytes of the SPI transaction." "0,1"
|
|
hexmask.long.byte 0x24 0.--3. 1. "DCXSEL,Selects the CE channel used to convey the DCX function. The select is bitwise encoded with bit 0 = 1 enabling CE0 for DCX transmission bit 1 = 1 enableing CE1 for DCX transmission etc. If the CE used for the SPI transaction is set it will be.."
|
|
line.long 0x28 "OFFSETHI,High order bytes of offset for IO transaction"
|
|
hexmask.long 0x28 0.--31. 1. "OFFSETHI,Holds the high order bytes of the byte addressing/offset field to use with IO commands. The number of offset bytes to use is specified in the command register"
|
|
line.long 0x2C "CMDSTAT,Provides staus on the execution of the command currently in progress. The fields in this register will reflect the real time status of the internal state machines and data transfers within the IOM."
|
|
hexmask.long.word 0x2C 8.--19. 1. "CTSIZE,The current number of bytes still to be transferred with this command. This field will count down to zero."
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|
bitfld.long 0x2C 5.--7. "CMDSTAT,The current status of the command execution." "?,1: Error encountered with command,2: Actively processing command,?,4: Idle state no active command no error,?,6: Command in progress but waiting on data from host,?"
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|
newline
|
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hexmask.long.byte 0x2C 0.--4. 1. "CCMD,current command that is being executed"
|
|
group.long 0x200++0x4B
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 14. "CQERR,Error during command queue operations" "0,1"
|
|
bitfld.long 0x0 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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|
newline
|
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bitfld.long 0x0 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x0 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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newline
|
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bitfld.long 0x0 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0x0 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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|
newline
|
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bitfld.long 0x0 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x0 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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|
newline
|
|
bitfld.long 0x0 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x0 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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newline
|
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bitfld.long 0x0 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x0 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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newline
|
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bitfld.long 0x0 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0x0 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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|
newline
|
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bitfld.long 0x0 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x4 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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newline
|
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bitfld.long 0x4 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
|
|
bitfld.long 0x4 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
newline
|
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bitfld.long 0x4 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0x4 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x4 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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|
newline
|
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bitfld.long 0x4 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x4 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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|
newline
|
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bitfld.long 0x4 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0x4 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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|
newline
|
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bitfld.long 0x4 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
|
|
bitfld.long 0x4 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 14. "CQERR,Error during command queue operations" "0,1"
|
|
bitfld.long 0x8 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
|
|
newline
|
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bitfld.long 0x8 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
|
|
bitfld.long 0x8 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x8 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0x8 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x8 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x8 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x8 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x8 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x8 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0x8 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0x8 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x8 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
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bitfld.long 0xC 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0xC 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0xC 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0xC 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0xC 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0xC 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0xC 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0xC 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0xC 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0xC 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0xC 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0xC 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0xC 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0xC 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0xC 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x10 "DMATRIGEN,Provides control on which event will trigger the DMA transfer after the DMA operation is setup and enabled. The trigger event will cause a number of bytes (depending on trigger event) to be"
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bitfld.long 0x10 1. "DTHREN,Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes) the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO and will transfer (WTHR/4) number of words" "0,1"
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bitfld.long 0x10 0. "DCMDCMPEN,Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered the number of words transferred will be the lesser of the remaining TOTCOUNT bytes or" "0,1"
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line.long 0x14 "DMATRIGSTAT,Provides the status of trigger events that have occurred for the transaction. Some of the bits are read only and some can be reset via a write of 0."
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bitfld.long 0x14 2. "DTOTCMP,DMA triggered when DCMDCMP = 0 and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is" "0,1"
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bitfld.long 0x14 1. "DTHR,Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA." "0,1"
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bitfld.long 0x14 0. "DCMDCMP,Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA." "0,1"
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line.long 0x18 "DMACFG,Configuration control of the DMA process. including the direction of DMA. and enablement of DMA"
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bitfld.long 0x18 9. "DPWROFF,Power off module after DMA is complete. If this bit is active the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain power down will not be performed." "0: Power off disabled,1: Power off enabled"
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bitfld.long 0x18 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x18 1. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction. To be..,1: Memory to Peripheral transaction. To be set when.."
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bitfld.long 0x18 0. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable DMA Function,1: Enable DMA Function"
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line.long 0x1C "DMATOTCOUNT,Contains the number of bytes to be transferred for this DMA transaction. This register is decremented as the data is transferred. and will be 0 at the completion of the DMA operation."
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hexmask.long.word 0x1C 0.--11. 1. "TOTCOUNT,Triggered DMA from Command complete event occured. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."
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line.long 0x20 "DMATARGADDR,The source or destination address internal the SRAM for the DMA data. For write operations. this can only be SRAM data (ADDR bit 28 = 1); For read operations. this can ve either SRAM or FLASH (ADDR bit 28 = 0)"
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hexmask.long 0x20 0.--28. 1. "TARGADDR,Bits [28:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment and does not have to be word aligned. In cases of non-word aligned addresses the DMA logic will take care for ensuring only.."
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line.long 0x24 "DMASTAT,Status of the DMA operation currently in progress."
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bitfld.long 0x24 2. "DMAERR,DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set this bit will remain set until cleared by software." "0,1"
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bitfld.long 0x24 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0 and will also be cleared when a new DMA is started." "0,1"
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bitfld.long 0x24 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
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line.long 0x28 "CQCFG,Controls parameters and options for execution of the command queue operation. To enable command queue. create this in memory. set the address. and enable it with a write to CQEN"
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bitfld.long 0x28 2.--3. "MSPIFLGSEL,Selects the MPSI modules used for sourcing the CQFLAG [11:8]." "0: Selects MPSI0 as source of signals used in..,1: Selects MPSI1 as source of signals used in..,2: Selects MPSI2 as source of signals used in..,?"
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bitfld.long 0x28 1. "CQPRI,Sets the Priority of the command queue dma request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x28 0. "CQEN,Command queue enable. When set will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled" "0: Disable CQ Function,1: Enable CQ Function"
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line.long 0x2C "CQADDR,The SRAM address which will be fetched next execution of the CQ operation. This register is updated as the CQ operation progresses. and is the live version of the register. The register can also be"
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hexmask.long 0x2C 2.--28. 1. "CQADDR,Bits 28:2 of target byte address for source of CQ . The buffer must be aligned on a word boundary"
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line.long 0x30 "CQSTAT,Provides the status of the command queue operation. If the command queue is disabled. these bits will be cleared. The bits are read only"
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bitfld.long 0x30 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
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bitfld.long 0x30 1. "CQPAUSED,Command queue operation is currently paused." "0,1"
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bitfld.long 0x30 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
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line.long 0x34 "CQFLAGS,Command Queue Flag"
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hexmask.long.word 0x34 16.--31. 1. "CQIRQMASK,Mask the bits used to generate the command queue interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE"
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hexmask.long.word 0x34 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
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line.long 0x38 "CQSETCLEAR,Set/Clear the command queue software pause flags on a per-bit basis. Contains 3 fields. allowing for setting. clearing or toggling the value in the software flags. Priority when the same bit"
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hexmask.long.byte 0x38 16.--23. 1. "CQFCLR,Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x38 8.--15. 1. "CQFTGL,Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x38 0.--7. 1. "CQFSET,Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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line.long 0x3C "CQPAUSEEN,Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the CQFLAG register is '1'. CQ processing will halt until either value is changed to '0'."
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hexmask.long.word 0x3C 0.--15. 1. "CQPEN,Enables the specified event to pause command processing when active"
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line.long 0x40 "CQCURIDX,Current index value. targeted to be written by register write operations within the command queue. This is compared to the CQENDIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and"
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hexmask.long.byte 0x40 0.--7. 1. "CQCURIDX,Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x44 "CQENDIDX,End index value. targeted to be written by software to indicate the last valid register pair contained within the command queue. rgister write operations within the command queue."
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hexmask.long.byte 0x44 0.--7. 1. "CQENDIDX,Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x48 "STATUS,IOM Module Status"
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bitfld.long 0x48 2. "IDLEST,indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to holdoffs from data availability or as the command gets propagated into the logic from the registers." "0: The I/O state machine is in the non-idle/run..,1: The I/O state machine is in the idle state."
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bitfld.long 0x48 1. "CMDACT,Indicates if the active I/O Command is currently processing a transaction or command is complete but the FIFO pointers are still syncronizing internally. This bit will go high at" "0: An I/O command is inactive. Indicating that the..,1: An I/O command is active. Indicates the active.."
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bitfld.long 0x48 0. "ERR,Bit has been deprecated. Please refer to the other error indicators. This will always return 0." "0: Default value.,1: Bit has been deprecated and will always return 0."
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group.long 0x280++0x3
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line.long 0x0 "MSPICFG,Controls the configuration of the SPI master module. including POL/PHA. LSB. flow control. and delays for MISO and MOSI"
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bitfld.long 0x0 30. "MSPIRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 27.--29. "DOUTDLY,Delay tap to use for the output signal (MOSI). This give more hold time on the output data" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 24.--26. "DINDLY,Delay tap to use for the input signal (MISO). This gives more hold time on the input data." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "SPILSB,Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first." "0: Send and receive MSB bit first,1: Send and receive LSB bit first"
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bitfld.long 0x0 22. "RDFCPOL,Selects the read flow control signal polarity." "0: Flow control signal high creates flow control.,1: Flow control signal low creates flow control."
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bitfld.long 0x0 21. "WTFCPOL,selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 will allow a IRQ=1 to pause transfers)." "0: Flow control signal high(1) creates flow control..,1: Flow control signal low(0) creates flow control.."
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bitfld.long 0x0 20. "WTFCIRQ,Selects the write mode flow control signal." "0: MISO is used as the write mode flow control..,1: IRQ is used as the write mode flow control signal."
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bitfld.long 0x0 18. "MOSIINV,Inverts MOSI when flow control is enabled." "0: MOSI is set to 0 in read mode and 1 in write mode.,1: MOSI is set to 1 in read mode and 0 in write mode."
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bitfld.long 0x0 17. "RDFC,Enables read mode flow control." "0: Read mode flow control disabled.,1: Read mode flow control enabled."
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bitfld.long 0x0 16. "WTFC,enables write mode flow control." "0: Write mode flow control disabled.,1: Write mode flow control enabled."
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bitfld.long 0x0 2. "FULLDUP,Enables full duplex mode for Master SPI write operations. Data will be captured simultaneously into the read fifo" "0,1"
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bitfld.long 0x0 1. "SPHA,Selects SPI phase.IMPORTANT NOTICE: Due to the susceptibility of creating a clock glitch which could cause register corruption changing SPHA and SPOL bits should be done in separate writes to this register." "0: Sample on the leading (first) clock edge.,1: Sample on the trailing (second) clock edge."
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newline
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bitfld.long 0x0 0. "SPOL,Selects SPI polarity.IMPORTANT NOTICE: Due to the susceptibility of creating a clock glitch which could cause register corruption changing SPHA and SPOL bits should be done in separate writes to this register." "0: The base value of the clock is 0.,1: The base value of the clock is 1."
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group.long 0x2C0++0x7
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line.long 0x0 "MI2CCFG,Controls the configuration of the I2C bus master."
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bitfld.long 0x0 24. "STRDIS,Disable detection of clock stretch events smaller than 1 cycle" "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "SMPCNT,Number of Base clk cycles to wait before sampling the SCL clock to determine if a clock stretch event has occured"
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hexmask.long.byte 0x0 12.--15. 1. "SDAENDLY,Number of IOCLK cycles to delay the SDA output en (all transitions affected). Used to delay data relative to clock"
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hexmask.long.byte 0x0 8.--11. 1. "SCLENDLY,Number of IOCLK cycles to delay the rising edge of the SCL output en (clock will go low on this edge). Used to allow clock shaping."
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bitfld.long 0x0 6. "MI2CRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 4.--5. "SDADLY,Delay to enable on the SDA output. Values are 0x0-0x3." "0,1,2,3"
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bitfld.long 0x0 2. "ARBEN,Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master this function can be disabled to save clock cycles on I2C transactions" "0: Disable multi-master bus arbitration support for..,1: Enable multi-master bus arbitration support for.."
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bitfld.long 0x0 1. "I2CLSB,Direction of data transmit and receive MSB(0) or LSB(1) first. Default per I2C specification is MSB first. This applies to both read and write data and read data will be bit" "0: Byte data is transmitted MSB first onto the..,1: Byte data is transmitted LSB first onto the.."
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bitfld.long 0x0 0. "ADDRSZ,Sets the I2C master device address size to either 7b (0) or 10b (1)." "0: Use 7b addressing for I2C master transactions,1: Use 10b addressing for I2C master transactions"
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line.long 0x4 "DEVCFG,Contains the I2C device address."
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hexmask.long.word 0x4 0.--9. 1. "DEVADDR,I2C address of the device that the Master will use to target for read/write operations. This can be either a 7b or 10b address."
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group.long 0x388++0x3
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line.long 0x0 "IOMDBG,Debug control"
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hexmask.long 0x0 3.--31. 1. "DBGDATA,Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers."
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bitfld.long 0x0 2. "APBCLKON,APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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bitfld.long 0x0 1. "IOCLKON,IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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bitfld.long 0x0 0. "DBGEN,Debug Enable. Setting bit will enable the update of data within this register otherwise it is clock gated for power savings" "0,1"
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tree.end
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endif
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|
sif (cpuis("AMA4B2KL")||cpuis("AMA4B2KP")||cpuis("AMAP42KL")||cpuis("AMAP42KP"))
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tree "IOM7"
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base ad:0x40057000
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group.long 0x0++0x3
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line.long 0x0 "FIFO,Provides direct random access to both input and output fifos. The state of the FIFO is not distured by reading these locations (ie no POP will be done). FIFO0 is accessible from addresses 0x0 - 0x1C. and is used for data outuput from the IOM to.."
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hexmask.long 0x0 0.--31. 1. "FIFO,FIFO direct access. Only locations 0 - 3F will return valid information."
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group.long 0x100++0x2F
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line.long 0x0 "FIFOPTR,Provides the current valid byte count of data within the FIFO as seen from the internal state machines. FIFO0 is dedicated to outgoing transactions and FIFO1 is dedicated to incoming transactions. All counts are specified in units of bytes."
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hexmask.long.byte 0x0 24.--31. 1. "FIFO1REM,The number of remaining data bytes slots currently in FIFO 1 (written by interface read by MCU)"
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hexmask.long.byte 0x0 16.--23. 1. "FIFO1SIZ,The number of valid data bytes currently in FIFO 1 (written by interface read by MCU)"
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hexmask.long.byte 0x0 8.--15. 1. "FIFO0REM,The number of remaining data bytes slots currently in FIFO 0 (written by MCU read by interface)"
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hexmask.long.byte 0x0 0.--7. 1. "FIFO0SIZ,The number of valid data bytes currently in the FIFO 0 (written by MCU read by interface)"
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line.long 0x4 "FIFOTHR,Sets the threshold values for incoming and outgoing transactions. The threshold values are used to assert the interrupt if enabled. and also used during DMA to set the transfer size as a result of DMATHR trigger."
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hexmask.long.byte 0x4 8.--13. 1. "FIFOWTHR,FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the write fifo contains FIFOWTHR free bytes as.."
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|
hexmask.long.byte 0x4 0.--5. 1. "FIFORTHR,FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the read fifo contains FIFORTHR valid bytes of data as.."
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line.long 0x8 "FIFOPOP,Will advance the internal read pointer of the incoming FIFO (FIFO1) when read. if POPWR is not active. If POPWR is active. a write to this register is needed to advance the internal FIFO pointer."
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hexmask.long 0x8 0.--31. 1. "FIFODOUT,This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0) the fifo read pointer will be advanced by one word as a result of the read."
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line.long 0xC "FIFOPUSH,Will write new data into the outgoing FIFO and advance the internal write pointer."
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hexmask.long 0xC 0.--31. 1. "FIFODIN,This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes)."
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line.long 0x10 "FIFOCTRL,Provides controls for the operation of the internal FIFOs. Contains fields used to control the operation of the POP register. and also controls to reset the internal pointers of the FIFOs."
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bitfld.long 0x10 1. "FIFORSTN,Active low manual reset of the fifo. Write to 0 to reset fifo and then write to 1 to remove the reset." "0,1"
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bitfld.long 0x10 0. "POPWR,Selects the mode in which 'pop' events are done for the fifo read operations. A value of '1' will prevent a pop event on a read operation and will require a write to the FIFOPOP register to create a pop event." "0,1"
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line.long 0x14 "FIFOLOC,Provides a read only value of the current read and write pointers. This register is read only and can be used alogn with the FIFO direct access method to determine the next data to be used for input and output functions."
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hexmask.long.byte 0x14 8.--11. 1. "FIFORPTR,Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1) which is used to store read data returned from external devices during a read operation."
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hexmask.long.byte 0x14 0.--3. 1. "FIFOWPTR,Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0) which is used during write operations to external devices."
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line.long 0x18 "CLKCFG,Provides clock related controls used internal to the BLEIF module. and enablement of 32KHz clock to the BLE Core module. The internal clock sourced is selected via the FSEL and can be further divided by 3 using the DIV3 control."
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hexmask.long.byte 0x18 24.--31. 1. "TOTPER,Clock total clock count minus 1. This provides the total period of the divided clock -1 when the DIVEN is active. The"
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hexmask.long.byte 0x18 16.--23. 1. "LOWPER,Clock low clock count minus 1. This provides the number of clocks the divided clock will be low when the DIVEN = 1."
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newline
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bitfld.long 0x18 12. "DIVEN,Enable clock division by TOTPER and LOWPER" "0: Disable TOTPER division.,1: Enable TOTPER division."
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bitfld.long 0x18 11. "DIV3,Enable divide by 3 of the source IOCLK. Division by 3 is done before the DIVEN programmable divider and if enabled" "0: Select divide by 1.,1: Select divide by 3."
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bitfld.long 0x18 8.--10. "FSEL,Select the input clock frequency." "0: Selects the minimum power clock. This setting..,1: Selects static 0 as the input clock. Previously..,2: Selects the HFRC 48MHz as the input clock.,3: Selects the HFRC 24MHz as the input clock.,4: Selects the HFRC 12MHz as the input clock.,5: Selects the HFRC 6MHz as the input clock.,6: Selects the HFRC 3MHz as the input clock.,7: Selects the HFRC 1.5MHz as the input clock."
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bitfld.long 0x18 0. "IOCLKEN,Enable for the interface clock. Must be enabled prior to executing any IO operations." "0,1"
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line.long 0x1C "SUBMODCTRL,Provides enable for each submodule. Only a sigle submodule can be enabled at one time."
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bitfld.long 0x1C 9.--11. "SMOD2TYPE,Submodule 2 module type. This is the I2S Master/Slave interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,4: Master/Slave submodule,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 8. "SMOD2EN,Submodule 2 enable (1) or disable (0)" "0,1"
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bitfld.long 0x1C 5.--7. "SMOD1TYPE,Submodule 1 module type. This is the I2C Master interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,4: Master/Slave submodule,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 4. "SMOD1EN,Submodule 1 enable (1) or disable (0)" "0,1"
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bitfld.long 0x1C 1.--3. "SMOD0TYPE,Submodule 0 module type. This is the SPI Master interface." "0: MSPI submodule,1: I2C Master submodule,2: I2S Master/Slave Module,?,?,?,?,7: NOT INSTALLED"
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bitfld.long 0x1C 0. "SMOD0EN,Submodule 0 enable (1) or disable (0)" "0,1"
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line.long 0x20 "CMD,Writes to this register will start an IO transaction. as well as set various parameters for the command itself. Reads will return the command value written to the CMD register."
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hexmask.long.byte 0x20 24.--31. 1. "OFFSETLO,This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command."
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bitfld.long 0x20 20.--21. "CMDSEL,Command Specific selection information. Not used in Master I2C. Used as CEn select for Master SPI transactions" "0,1,2,3"
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hexmask.long.word 0x20 8.--19. 1. "TSIZE,Defines the transaction size in bytes. The offset transfer is not included in this size."
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bitfld.long 0x20 7. "CONT,Contine to hold the bus after the current transaction if set to a 1 with a new command issued." "0,1"
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bitfld.long 0x20 4.--6. "OFFSETCNT,Number of offset bytes to use for the command - 0 1 2 3 4 5 are valid selections. The second (byte 1) third (byte 2) and forth (byte 3) are read from the OFFSETHI register and the low order byte is pulled from this register in the.." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x20 0.--3. 1. "CMD,Command for submodule."
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line.long 0x24 "DCXCTRL,Enables transmission of DCX signal with SPI transactions and selects which CE signals will be used to transmit the DCX signal."
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bitfld.long 0x24 4. "DCXEN,Global enable of the DCX function. Setting to 1 will enable the generation of the DCX signal which will assert when sending the offset bytes of the SPI transaction." "0,1"
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hexmask.long.byte 0x24 0.--3. 1. "DCXSEL,Selects the CE channel used to convey the DCX function. The select is bitwise encoded with bit 0 = 1 enabling CE0 for DCX transmission bit 1 = 1 enableing CE1 for DCX transmission etc. If the CE used for the SPI transaction is set it will be.."
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line.long 0x28 "OFFSETHI,High order bytes of offset for IO transaction"
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hexmask.long 0x28 0.--31. 1. "OFFSETHI,Holds the high order bytes of the byte addressing/offset field to use with IO commands. The number of offset bytes to use is specified in the command register"
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line.long 0x2C "CMDSTAT,Provides staus on the execution of the command currently in progress. The fields in this register will reflect the real time status of the internal state machines and data transfers within the IOM."
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hexmask.long.word 0x2C 8.--19. 1. "CTSIZE,The current number of bytes still to be transferred with this command. This field will count down to zero."
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bitfld.long 0x2C 5.--7. "CMDSTAT,The current status of the command execution." "?,1: Error encountered with command,2: Actively processing command,?,4: Idle state no active command no error,?,6: Command in progress but waiting on data from host,?"
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hexmask.long.byte 0x2C 0.--4. 1. "CCMD,current command that is being executed"
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group.long 0x200++0x4B
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line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
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bitfld.long 0x0 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x0 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x0 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x0 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x0 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x0 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0x0 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x0 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x0 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x0 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x0 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x0 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0x0 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0x0 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x0 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
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bitfld.long 0x4 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x4 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x4 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x4 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x4 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x4 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0x4 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x4 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x4 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x4 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x4 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x4 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0x4 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0x4 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x4 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
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bitfld.long 0x8 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x8 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x8 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x8 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x8 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x8 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0x8 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x8 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x8 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x8 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x8 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x8 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0x8 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0x8 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x8 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
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bitfld.long 0xC 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0xC 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0xC 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0xC 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0xC 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0xC 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0xC 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0xC 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0xC 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0xC 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0xC 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0xC 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop." "0,1"
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bitfld.long 0xC 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo." "0,1"
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bitfld.long 0xC 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0xC 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x10 "DMATRIGEN,Provides control on which event will trigger the DMA transfer after the DMA operation is setup and enabled. The trigger event will cause a number of bytes (depending on trigger event) to be"
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bitfld.long 0x10 1. "DTHREN,Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes) the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO and will transfer (WTHR/4) number of words" "0,1"
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bitfld.long 0x10 0. "DCMDCMPEN,Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered the number of words transferred will be the lesser of the remaining TOTCOUNT bytes or" "0,1"
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line.long 0x14 "DMATRIGSTAT,Provides the status of trigger events that have occurred for the transaction. Some of the bits are read only and some can be reset via a write of 0."
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bitfld.long 0x14 2. "DTOTCMP,DMA triggered when DCMDCMP = 0 and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is" "0,1"
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bitfld.long 0x14 1. "DTHR,Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA." "0,1"
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bitfld.long 0x14 0. "DCMDCMP,Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA." "0,1"
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line.long 0x18 "DMACFG,Configuration control of the DMA process. including the direction of DMA. and enablement of DMA"
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bitfld.long 0x18 9. "DPWROFF,Power off module after DMA is complete. If this bit is active the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain power down will not be performed." "0: Power off disabled,1: Power off enabled"
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bitfld.long 0x18 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x18 1. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction. To be..,1: Memory to Peripheral transaction. To be set when.."
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bitfld.long 0x18 0. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable DMA Function,1: Enable DMA Function"
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line.long 0x1C "DMATOTCOUNT,Contains the number of bytes to be transferred for this DMA transaction. This register is decremented as the data is transferred. and will be 0 at the completion of the DMA operation."
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hexmask.long.word 0x1C 0.--11. 1. "TOTCOUNT,Triggered DMA from Command complete event occured. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."
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line.long 0x20 "DMATARGADDR,The source or destination address internal the SRAM for the DMA data. For write operations. this can only be SRAM data (ADDR bit 28 = 1); For read operations. this can ve either SRAM or FLASH (ADDR bit 28 = 0)"
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hexmask.long 0x20 0.--28. 1. "TARGADDR,Bits [28:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment and does not have to be word aligned. In cases of non-word aligned addresses the DMA logic will take care for ensuring only.."
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line.long 0x24 "DMASTAT,Status of the DMA operation currently in progress."
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bitfld.long 0x24 2. "DMAERR,DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set this bit will remain set until cleared by software." "0,1"
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bitfld.long 0x24 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0 and will also be cleared when a new DMA is started." "0,1"
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bitfld.long 0x24 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
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line.long 0x28 "CQCFG,Controls parameters and options for execution of the command queue operation. To enable command queue. create this in memory. set the address. and enable it with a write to CQEN"
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bitfld.long 0x28 2.--3. "MSPIFLGSEL,Selects the MPSI modules used for sourcing the CQFLAG [11:8]." "0: Selects MPSI0 as source of signals used in..,1: Selects MPSI1 as source of signals used in..,2: Selects MPSI2 as source of signals used in..,?"
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bitfld.long 0x28 1. "CQPRI,Sets the Priority of the command queue dma request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x28 0. "CQEN,Command queue enable. When set will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled" "0: Disable CQ Function,1: Enable CQ Function"
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line.long 0x2C "CQADDR,The SRAM address which will be fetched next execution of the CQ operation. This register is updated as the CQ operation progresses. and is the live version of the register. The register can also be"
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hexmask.long 0x2C 2.--28. 1. "CQADDR,Bits 28:2 of target byte address for source of CQ . The buffer must be aligned on a word boundary"
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line.long 0x30 "CQSTAT,Provides the status of the command queue operation. If the command queue is disabled. these bits will be cleared. The bits are read only"
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bitfld.long 0x30 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
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bitfld.long 0x30 1. "CQPAUSED,Command queue operation is currently paused." "0,1"
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bitfld.long 0x30 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
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line.long 0x34 "CQFLAGS,Command Queue Flag"
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hexmask.long.word 0x34 16.--31. 1. "CQIRQMASK,Mask the bits used to generate the command queue interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE"
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hexmask.long.word 0x34 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
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line.long 0x38 "CQSETCLEAR,Set/Clear the command queue software pause flags on a per-bit basis. Contains 3 fields. allowing for setting. clearing or toggling the value in the software flags. Priority when the same bit"
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hexmask.long.byte 0x38 16.--23. 1. "CQFCLR,Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x38 8.--15. 1. "CQFTGL,Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x38 0.--7. 1. "CQFSET,Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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line.long 0x3C "CQPAUSEEN,Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the CQFLAG register is '1'. CQ processing will halt until either value is changed to '0'."
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hexmask.long.word 0x3C 0.--15. 1. "CQPEN,Enables the specified event to pause command processing when active"
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line.long 0x40 "CQCURIDX,Current index value. targeted to be written by register write operations within the command queue. This is compared to the CQENDIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and"
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hexmask.long.byte 0x40 0.--7. 1. "CQCURIDX,Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x44 "CQENDIDX,End index value. targeted to be written by software to indicate the last valid register pair contained within the command queue. rgister write operations within the command queue."
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hexmask.long.byte 0x44 0.--7. 1. "CQENDIDX,Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x48 "STATUS,IOM Module Status"
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bitfld.long 0x48 2. "IDLEST,indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to holdoffs from data availability or as the command gets propagated into the logic from the registers." "0: The I/O state machine is in the non-idle/run..,1: The I/O state machine is in the idle state."
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bitfld.long 0x48 1. "CMDACT,Indicates if the active I/O Command is currently processing a transaction or command is complete but the FIFO pointers are still syncronizing internally. This bit will go high at" "0: An I/O command is inactive. Indicating that the..,1: An I/O command is active. Indicates the active.."
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bitfld.long 0x48 0. "ERR,Bit has been deprecated. Please refer to the other error indicators. This will always return 0." "0: Default value.,1: Bit has been deprecated and will always return 0."
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group.long 0x280++0x3
|
|
line.long 0x0 "MSPICFG,Controls the configuration of the SPI master module. including POL/PHA. LSB. flow control. and delays for MISO and MOSI"
|
|
bitfld.long 0x0 30. "MSPIRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
|
|
bitfld.long 0x0 27.--29. "DOUTDLY,Delay tap to use for the output signal (MOSI). This give more hold time on the output data" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "DINDLY,Delay tap to use for the input signal (MISO). This gives more hold time on the input data." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 23. "SPILSB,Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first." "0: Send and receive MSB bit first,1: Send and receive LSB bit first"
|
|
newline
|
|
bitfld.long 0x0 22. "RDFCPOL,Selects the read flow control signal polarity." "0: Flow control signal high creates flow control.,1: Flow control signal low creates flow control."
|
|
bitfld.long 0x0 21. "WTFCPOL,selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 will allow a IRQ=1 to pause transfers)." "0: Flow control signal high(1) creates flow control..,1: Flow control signal low(0) creates flow control.."
|
|
newline
|
|
bitfld.long 0x0 20. "WTFCIRQ,Selects the write mode flow control signal." "0: MISO is used as the write mode flow control..,1: IRQ is used as the write mode flow control signal."
|
|
bitfld.long 0x0 18. "MOSIINV,Inverts MOSI when flow control is enabled." "0: MOSI is set to 0 in read mode and 1 in write mode.,1: MOSI is set to 1 in read mode and 0 in write mode."
|
|
newline
|
|
bitfld.long 0x0 17. "RDFC,Enables read mode flow control." "0: Read mode flow control disabled.,1: Read mode flow control enabled."
|
|
bitfld.long 0x0 16. "WTFC,enables write mode flow control." "0: Write mode flow control disabled.,1: Write mode flow control enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "FULLDUP,Enables full duplex mode for Master SPI write operations. Data will be captured simultaneously into the read fifo" "0,1"
|
|
bitfld.long 0x0 1. "SPHA,Selects SPI phase.IMPORTANT NOTICE: Due to the susceptibility of creating a clock glitch which could cause register corruption changing SPHA and SPOL bits should be done in separate writes to this register." "0: Sample on the leading (first) clock edge.,1: Sample on the trailing (second) clock edge."
|
|
newline
|
|
bitfld.long 0x0 0. "SPOL,Selects SPI polarity.IMPORTANT NOTICE: Due to the susceptibility of creating a clock glitch which could cause register corruption changing SPHA and SPOL bits should be done in separate writes to this register." "0: The base value of the clock is 0.,1: The base value of the clock is 1."
|
|
group.long 0x2C0++0x7
|
|
line.long 0x0 "MI2CCFG,Controls the configuration of the I2C bus master."
|
|
bitfld.long 0x0 24. "STRDIS,Disable detection of clock stretch events smaller than 1 cycle" "0,1"
|
|
hexmask.long.byte 0x0 16.--23. 1. "SMPCNT,Number of Base clk cycles to wait before sampling the SCL clock to determine if a clock stretch event has occured"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "SDAENDLY,Number of IOCLK cycles to delay the SDA output en (all transitions affected). Used to delay data relative to clock"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SCLENDLY,Number of IOCLK cycles to delay the rising edge of the SCL output en (clock will go low on this edge). Used to allow clock shaping."
|
|
newline
|
|
bitfld.long 0x0 6. "MI2CRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
|
|
bitfld.long 0x0 4.--5. "SDADLY,Delay to enable on the SDA output. Values are 0x0-0x3." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 2. "ARBEN,Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master this function can be disabled to save clock cycles on I2C transactions" "0: Disable multi-master bus arbitration support for..,1: Enable multi-master bus arbitration support for.."
|
|
bitfld.long 0x0 1. "I2CLSB,Direction of data transmit and receive MSB(0) or LSB(1) first. Default per I2C specification is MSB first. This applies to both read and write data and read data will be bit" "0: Byte data is transmitted MSB first onto the..,1: Byte data is transmitted LSB first onto the.."
|
|
newline
|
|
bitfld.long 0x0 0. "ADDRSZ,Sets the I2C master device address size to either 7b (0) or 10b (1)." "0: Use 7b addressing for I2C master transactions,1: Use 10b addressing for I2C master transactions"
|
|
line.long 0x4 "DEVCFG,Contains the I2C device address."
|
|
hexmask.long.word 0x4 0.--9. 1. "DEVADDR,I2C address of the device that the Master will use to target for read/write operations. This can be either a 7b or 10b address."
|
|
group.long 0x388++0x3
|
|
line.long 0x0 "IOMDBG,Debug control"
|
|
hexmask.long 0x0 3.--31. 1. "DBGDATA,Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers."
|
|
bitfld.long 0x0 2. "APBCLKON,APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "IOCLKON,IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
|
|
bitfld.long 0x0 0. "DBGEN,Debug Enable. Setting bit will enable the update of data within this register otherwise it is clock gated for power savings" "0,1"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "IOSLAVE (I2C/SPI Slave)"
|
|
base ad:0x40034000
|
|
group.long 0x100++0x2B
|
|
line.long 0x0 "FIFOPTR,Current FIFO Pointer"
|
|
hexmask.long.byte 0x0 8.--15. 1. "FIFOSIZ,The number of bytes currently in the hardware FIFO."
|
|
hexmask.long.byte 0x0 0.--7. 1. "FIFOPTR,Current FIFO pointer."
|
|
line.long 0x4 "FIFOCFG,FIFO Configuration"
|
|
hexmask.long.byte 0x4 24.--29. 1. "ROBASE,Defines the read-only area. The IO Slave read-only area is situated in LRAM at (ROBASE*8) to (FIFOBASE*8-1)"
|
|
hexmask.long.byte 0x4 8.--13. 1. "FIFOMAX,These bits hold the maximum FIFO address in 8 byte segments. It is also the beginning of the RAM area of the LRAM. Note that no RAM area is configured if FIFOMAX is set to 0x1F."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "FIFOBASE,These bits hold the base address of the I/O FIFO in 8 byte segments. The IO Slave FIFO is situated in LRAM at (FIFOBASE*8) to (FIFOMAX*8-1)."
|
|
line.long 0x8 "FIFOTHR,FIFO Threshold Configuration"
|
|
hexmask.long.byte 0x8 0.--7. 1. "FIFOTHR,FIFO size interrupt threshold."
|
|
line.long 0xC "FUPD,FIFO Update Status"
|
|
bitfld.long 0xC 1. "IOREAD,This bitfield indicates an IO read is active." "0,1"
|
|
bitfld.long 0xC 0. "FIFOUPD,This bit indicates that a FIFO update is underway." "0,1"
|
|
line.long 0x10 "FIFOCTR,Overall FIFO Counter"
|
|
hexmask.long.word 0x10 0.--9. 1. "FIFOCTR,Virtual FIFO byte count"
|
|
line.long 0x14 "FIFOINC,Overall FIFO Counter Increment"
|
|
hexmask.long.word 0x14 0.--9. 1. "FIFOINC,Increment the Overall FIFO Counter by this value on a write"
|
|
line.long 0x18 "CFG,I/O Slave Configuration"
|
|
bitfld.long 0x18 31. "IFCEN,IOSLAVE interface enable." "0: Disable the IOSLAVE,1: Enable the IOSLAVE"
|
|
bitfld.long 0x18 20. "WRAPPTR,Address pointer wrap mode enable." "0: Address pointer does not wrap around to..,1: Address pointer wraps around to FIFOBASE*8 after.."
|
|
newline
|
|
hexmask.long.word 0x18 8.--19. 1. "I2CADDR,7-bit or 10-bit I2C device address."
|
|
bitfld.long 0x18 4. "STARTRD,This bit holds the cycle to initiate an I/O RAM read." "0: Initiate I/O RAM read late in each transferred..,1: Initiate I/O RAM read early in each transferred.."
|
|
newline
|
|
bitfld.long 0x18 2. "LSB,This bit selects the transfer bit ordering." "0: Data is assumed to be sent and received with MSB..,1: Data is assumed to be sent and received with LSB.."
|
|
bitfld.long 0x18 1. "SPOL,This bit selects SPI polarity." "0: Polarity 0 handles SPI modes 0 and 3.,1: Polarity 1 handles SPI modes 1 and 2."
|
|
newline
|
|
bitfld.long 0x18 0. "IFCSEL,This bit selects the I/O interface." "0: Selects I2C interface for the IO Slave.,1: Selects SPI interface for the IO Slave."
|
|
line.long 0x1C "PRENC,I/O Slave Interrupt Priority Encode"
|
|
hexmask.long.byte 0x1C 0.--4. 1. "PRENC,These bits hold the priority encode of the REGACC interrupts."
|
|
line.long 0x20 "IOINTCTL,I/O Interrupt Control"
|
|
hexmask.long.byte 0x20 24.--31. 1. "IOINTSET,These bits set the IOINT interrupts when written with a 1."
|
|
bitfld.long 0x20 16. "IOINTCLR,This bit clears all of the IOINT interrupts when written with a 1." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x20 8.--15. 1. "IOINT,These bits read the IOINT interrupts."
|
|
hexmask.long.byte 0x20 0.--7. 1. "IOINTEN,These read-only bits indicate whether the IOINT interrupts are enabled."
|
|
line.long 0x24 "GENADD,General Address Data"
|
|
hexmask.long.byte 0x24 0.--7. 1. "GADATA,The data supplied on the last General Address reference."
|
|
line.long 0x28 "ADDPTR,Address pointer"
|
|
hexmask.long.byte 0x28 0.--7. 1. "ADDPTR,The current value in the Address pointer."
|
|
group.long 0x200++0x1F
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 9. "XCMPWR,Transfer complete interrupt write to register space." "0,1"
|
|
bitfld.long 0x0 8. "XCMPWF,Transfer complete interrupt write to FIFO space." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "XCMPRR,Transfer complete interrupt read from register space." "0,1"
|
|
bitfld.long 0x0 6. "XCMPRF,Transfer complete interrupt read from FIFO space." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IOINTW,IO Write interrupt." "0,1"
|
|
bitfld.long 0x0 4. "GENAD,I2C General Address interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FRDERR,FIFO Read Error interrupt." "0,1"
|
|
bitfld.long 0x0 2. "FUNDFL,FIFO Underflow interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "FOVFL,FIFO Overflow interrupt." "0,1"
|
|
bitfld.long 0x0 0. "FSIZE,FIFO Size interrupt." "0,1"
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 9. "XCMPWR,Transfer complete interrupt write to register space." "0,1"
|
|
bitfld.long 0x4 8. "XCMPWF,Transfer complete interrupt write to FIFO space." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "XCMPRR,Transfer complete interrupt read from register space." "0,1"
|
|
bitfld.long 0x4 6. "XCMPRF,Transfer complete interrupt read from FIFO space." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "IOINTW,IO Write interrupt." "0,1"
|
|
bitfld.long 0x4 4. "GENAD,I2C General Address interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FRDERR,FIFO Read Error interrupt." "0,1"
|
|
bitfld.long 0x4 2. "FUNDFL,FIFO Underflow interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "FOVFL,FIFO Overflow interrupt." "0,1"
|
|
bitfld.long 0x4 0. "FSIZE,FIFO Size interrupt." "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 9. "XCMPWR,Transfer complete interrupt write to register space." "0,1"
|
|
bitfld.long 0x8 8. "XCMPWF,Transfer complete interrupt write to FIFO space." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "XCMPRR,Transfer complete interrupt read from register space." "0,1"
|
|
bitfld.long 0x8 6. "XCMPRF,Transfer complete interrupt read from FIFO space." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "IOINTW,IO Write interrupt." "0,1"
|
|
bitfld.long 0x8 4. "GENAD,I2C General Address interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FRDERR,FIFO Read Error interrupt." "0,1"
|
|
bitfld.long 0x8 2. "FUNDFL,FIFO Underflow interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "FOVFL,FIFO Overflow interrupt." "0,1"
|
|
bitfld.long 0x8 0. "FSIZE,FIFO Size interrupt." "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 9. "XCMPWR,Transfer complete interrupt write to register space." "0,1"
|
|
bitfld.long 0xC 8. "XCMPWF,Transfer complete interrupt write to FIFO space." "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "XCMPRR,Transfer complete interrupt read from register space." "0,1"
|
|
bitfld.long 0xC 6. "XCMPRF,Transfer complete interrupt read from FIFO space." "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "IOINTW,IO Write interrupt." "0,1"
|
|
bitfld.long 0xC 4. "GENAD,I2C General Address interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "FRDERR,FIFO Read Error interrupt." "0,1"
|
|
bitfld.long 0xC 2. "FUNDFL,FIFO Underflow interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "FOVFL,FIFO Overflow interrupt." "0,1"
|
|
bitfld.long 0xC 0. "FSIZE,FIFO Size interrupt." "0,1"
|
|
line.long 0x10 "REGACCINTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
hexmask.long 0x10 0.--31. 1. "REGACC,Register access interrupts."
|
|
line.long 0x14 "REGACCINTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
hexmask.long 0x14 0.--31. 1. "REGACC,Register access interrupts."
|
|
line.long 0x18 "REGACCINTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
hexmask.long 0x18 0.--31. 1. "REGACC,Register access interrupts."
|
|
line.long 0x1C "REGACCINTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
hexmask.long 0x1C 0.--31. 1. "REGACC,Register access interrupts."
|
|
tree.end
|
|
tree "MCUCTRL (MCU Miscellaneous Control Logic)"
|
|
base ad:0x40020000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CHIPPN,Chip Information"
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 24.--31. 1. "PN,Apollo family device type."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 24.--31. 1. "PN,Apollo family device type."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 20.--23. 1. "MRAMSIZE,MRAM size."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 20.--23. 1. "MRAMSIZE,MRAM size."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 16.--19. 1. "SRAMSIZE,SRAM size."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 16.--19. 1. "SRAMSIZE,SRAM size."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 12.--15. 1. "REVMAJ,Major revision."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 12.--15. 1. "REVMAJ,Major revision."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 8.--11. 1. "REVMIN,Minor revision."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 8.--11. 1. "REVMIN,Minor revision."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 6.--7. "PKG,Package type." "0: SIP package.,1: SIP2 package.,2: BGA package.,3: CSP package."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 6.--7. "PKG,Package type." "0: SIP package.,1: QFN package.,2: BGA package.,3: CSP package."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 3.--5. "PINS,Number of pins for this package." "0: 25 pins,1: 49 pins,2: 64 pins,3: 81 pins,?,?,?,?"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 3.--5. "PINS,Number of pins for this package." "0: 25 pins,1: 49 pins,2: 64 pins,3: 81 pins,?,?,?,?"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 1.--2. "TEMP,Temperature." "0: Commercial temperature,1: Military temperature,2: Automotive temperature,3: Industrial temperature"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 1.--2. "TEMP,Temperature." "0: Commercial temperature,1: Military temperature,2: Automotive temperature,3: Industrial temperature"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long 0x0 0.--31. 1. "PARTNUM,BCD part number."
|
|
endif
|
|
line.long 0x4 "CHIPID0,Unique Chip ID 0"
|
|
hexmask.long 0x4 0.--31. 1. "CHIPID0,Unique chip ID 0."
|
|
line.long 0x8 "CHIPID1,Unique Chip ID 1"
|
|
hexmask.long 0x8 0.--31. 1. "CHIPID1,Unique chip ID 1."
|
|
line.long 0xC "CHIPREV,Chip Revision"
|
|
hexmask.long.word 0xC 8.--19. 1. "SIPART,Silicon Part ID"
|
|
newline
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0xC 4.--7. 1. "REVMAJ,Major Revision ID."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0xC 4.--7. 1. "REVMAJ,Major Revision ID."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0xC 4.--7. 1. "REVMAJ,Major Revision ID."
|
|
newline
|
|
endif
|
|
hexmask.long.byte 0xC 0.--3. 1. "REVMIN,Minor Revision ID."
|
|
line.long 0x10 "VENDORID,Unique Vendor ID"
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long 0x10 0.--31. 1. "VENDORID,Unique Vendor ID"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long 0x10 0.--31. 1. "VENDORID,Unique Vendor ID"
|
|
endif
|
|
line.long 0x14 "SKU,Unique Chip SKU"
|
|
bitfld.long 0x14 10. "SKUSECURESPOT,Secure boot feature" "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. "SKUUSB,USB available" "0,1"
|
|
newline
|
|
bitfld.long 0x14 8. "SKUGFX,GFX available" "0,1"
|
|
newline
|
|
bitfld.long 0x14 7. "SKUMIPIDSI,MIPI DSI available" "0,1"
|
|
newline
|
|
bitfld.long 0x14 6. "SKUTURBOSPOT,High performance mode for MCU and DSPs." "0,1"
|
|
newline
|
|
bitfld.long 0x14 4.--5. "SKUDSP,DSP availability SKU setting. 0:No DSPs available 1: DSP0 only available 2 (or 3): Both DSP0 and DSP1 are available" "0: No DSPs available,1: DSP0 only available,?,?"
|
|
newline
|
|
bitfld.long 0x14 2.--3. "SKUMRAMSIZE,MRAM size SKU. 0:0.5MB 1=1MB 2=1.5MB 3:2MB" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 0.--1. "SKUSRAMSIZE,SRAM SKU dictates the available memory for MCU. All of the MCU TCM is always available in addition to these. 0: 512K SSRAM 1: 1MB SSRAM 2: 1MB SSRAM + DSP Memories" "0,1,2,3"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "DEBUGGER,Debugger Control"
|
|
hexmask.long 0x0 0.--31. 1. "LOCKOUT,Lockout of debugger (SWD)."
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "ACRG,Active Current Reference Generator Control"
|
|
hexmask.long.byte 0x0 3.--7. 1. "ACRGTRIM,ACRG Trim value"
|
|
newline
|
|
bitfld.long 0x0 2. "ACRGIBIASSEL,Set the ACRG ibias. Note: the SWE mux select in PWRSEQ2SWE must be set for this to take effect. The inversion of this register is driven to analog." "0: Selects the bandgap,1: Selects the CCRG"
|
|
newline
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 1. "ACRGPWD,Power down the ACRG." "0: Power up the ACRG trim.,1: Powers down the ACRG trim."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 1. "ACRGPWD,Power down the ACRG." "0: Power up the ACRG trim.,1: Powers down the ACRG trim."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
bitfld.long 0x0 1. "ACRGPWD,Power down the ACRG." "?,1: Powers down the ACRG trim."
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 0. "ACRGSWE,Software enablement for ACRG register. A value of 1 will allow writes to the register" "0,1"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "VREFGEN2,Voltage Reference Generator 2 Control"
|
|
bitfld.long 0x0 29. "TVRG2SELVREF,TVRG2 SEL VREF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "TVRGSELVREF,TVRG SEL VREF" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 21.--27. 1. "TVRG2VREFTRIM,Calibrated voltage reference 580m trim"
|
|
newline
|
|
bitfld.long 0x0 20. "TVRG2CURRENTTRIM,Calibrated voltage reference current trim." "0,1"
|
|
newline
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 19. "TVRG2PWD,Power Down Calibrated Voltage Reference Generator." "0: Power up the CVRG.,1: Powers down the CVRG."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 19. "TVRG2PWD,Power Down Calibrated Voltage Reference Generator." "0: Power up the CVRG.,1: Powers down the CVRG."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
bitfld.long 0x0 19. "TVRG2PWD,Power Down Calibrated Voltage Reference Generator." "?,1: Powers down the CVRG."
|
|
newline
|
|
bitfld.long 0x0 5. "TVRGPWD,Power Down Calibrated Voltage Reference Generator." "?,1: Powers down the CVRG."
|
|
newline
|
|
endif
|
|
hexmask.long.byte 0x0 14.--18. 1. "TVRG2TEMPCOTRIM,Calibrated Voltage Reference Generator tc trim (bottom transistor)"
|
|
newline
|
|
hexmask.long.byte 0x0 7.--13. 1. "TVRGVREFTRIM,Calibrated voltage reference 580m trim"
|
|
newline
|
|
bitfld.long 0x0 6. "TVRGCURRENTTRIM,Calibrated voltage reference current trim." "0,1"
|
|
newline
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 5. "TVRGPWD,Power Down Calibrated Voltage Reference Generator." "0: Power up the CVRG.,1: Powers down the CVRG."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 5. "TVRGPWD,Power Down Calibrated Voltage Reference Generator." "0: Power up the CVRG.,1: Powers down the CVRG."
|
|
newline
|
|
endif
|
|
hexmask.long.byte 0x0 0.--4. 1. "TVRGTEMPCOTRIM,Calibrated Voltage Reference Generator tc trim (bottom transistor)"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "VRCTRL,Overrides for Voltage Regulators Controls"
|
|
bitfld.long 0x0 19. "SIMOBUCKACTIVE,SIMO BUCK ACTIVE control. Override for PWRCTRL going to analog when SIMOBUCKOVER = 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "SIMOBUCKRSTB,SIMO BUCK RSTB control. Override for PWRCTRL going to analog when SIMOBUCKOVER = 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "SIMOBUCKPDNB,SIMO BUCK PDNB control. Override for PWRCTRL going to analog when SIMOBUCKOVER = 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SIMOBUCKOVER,Override control for SIMO BUCK signals" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "ANALDOACTIVE,ANALDO LDO ACTIVE control. Override for PWRCTRL going to analog when ANALDOOVER = 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "ANALDOPDNB,ANALDO PDNB control. Override for PWRCTRL going to analog when ANALDOOVER = 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ANALDOOVER,Override control for ANALDO signals" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "MEMLPLDOACTIVE,MEM LP LDO ACTVIVE control. Override for PWRCTRL going to analog when MEMLPLDOOVER = 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "MEMLPLDOPDNB,MEM LP LDO PDNB control. Override for PWRCTRL going to analog when MEMLPLDOOVER = 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "MEMLPLDOOVER,Override control for MEM LP LDO signals" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MEMLDOCOLDSTARTEN,MEM LDO COLDSTART EN control. This is a shadow backed register and no need to set MEMLDOOVER." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "MEMLDOACTIVE,MEM LDO ACTIVE control. Override for PWRCTRL going to analog when MEMLDOOVER = 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MEMLDOACTIVEEARLY,MEM LDO EARLY ACTIVE control. Override for PWRCTRL going to analog when MEMLDOOVER = 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "MEMLDOPDNB,MEM LDO PDNB control. Override signal for PWRCTRL going to analog when MEMLDOOVER = 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MEMLDOOVER,Override control for MEM LDO signals" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CORELDOCOLDSTARTEN,CORE LDO COLDSTART EN control. This is a shadow backed register and no need to set CORELDOOVER." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CORELDOACTIVE,CORE LDO ACTIVE control. Override for PWRCTRL going to analog when CORELDOOVER = 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CORELDOACTIVEEARLY,CORE LDO EARLY ACTIVE control. Override for PWRCTRL going to analog when CORELDOOVER = 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CORELDOPDNB,CORE LDO PDNB control. Override for PWRCTRL going to analog when CORELDOOVER = 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CORELDOOVER,Override control for CORE LDO signals" "0,1"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "LDOREG1,CORELDO trims Reg"
|
|
bitfld.long 0x0 21. "CORELDOIBIASSEL,Core LDO IBIAS sel. Note: the SWE mux select in PWRSEQ2SWE must be set for this to take effect." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "CORELDOIBIASTRIM,CORE LDO IBIAS Trim" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 14.--19. 1. "CORELDOLPTRIM,CORE LDO Low Power Trim"
|
|
newline
|
|
hexmask.long.byte 0x0 10.--13. 1. "CORELDOTEMPCOTRIM,CORE LDO TEMPCO trim"
|
|
newline
|
|
hexmask.long.word 0x0 0.--9. 1. "CORELDOACTIVETRIM,CORE LDO active trim"
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "LDOREG2,MEMLDO and MEMLPLDO Trims"
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 26.--29. 1. "TRIMANALDO,Analog LDO Trim."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 26.--29. 1. "TRIMANALDO,Analog LDO Trim."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 25. "MEMLDOIBIASSEL,Mem LDO IBIAS sel. Note: the SWE mux select in PWRSEQ2SWE must be set for this to take effect." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 25. "MEMLDOIBIASSEL,Mem LDO IBIAS sel. Note: the SWE mux select in PWRSEQ2SWE must be set for this to take effect." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 24. "MEMLPLDOIBIASTRIM,Mem LPLDO IBIAS trim" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 24. "MEMLPLDOIBIASTRIM,Mem LPLDO IBIAS trim" "0,1"
|
|
newline
|
|
endif
|
|
hexmask.long.byte 0x0 18.--23. 1. "MEMLPLDOTRIM,MEM LPLDO TRIM"
|
|
newline
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 12.--17. 1. "MEMLDOLPALTTRIM,MEM LDO TRIM LP ALT SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 12.--17. 1. "MEMLDOLPALTTRIM,MEM LDO TRIM LP ALT SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 6.--11. 1. "MEMLDOLPTRIM,MEM LDO LP trim"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 6.--11. 1. "MEMLDOLPTRIM,MEM LDO LP trim"
|
|
newline
|
|
endif
|
|
hexmask.long.byte 0x0 0.--5. 1. "MEMLDOACTIVETRIM,MEM LDO active trim"
|
|
group.long 0xE0++0x3
|
|
line.long 0x0 "LFRC,LFRC Control"
|
|
bitfld.long 0x0 10.--12. "LFRCSIMOCLKDIV,SIMOBUCK LP mode clock divider" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,?,?"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "LFRCITAILTRIM,LFRC ITAIL trim" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 7. "RESETLFRC,LFRC Reset." "0: Enable LFRC.,1: Reset LFRC."
|
|
newline
|
|
bitfld.long 0x0 6. "PWDLFRC,Power Down LFRC." "0: Power up LFRC.,1: Power down LFRC."
|
|
newline
|
|
hexmask.long.byte 0x0 1.--5. 1. "TRIMTUNELFRC,LFRC Frequency Tune trim bits"
|
|
newline
|
|
bitfld.long 0x0 0. "LFRCSWE,LFRC Software Override Enable." "0: LFRC Software Override Disable.,1: LFRC Software Override Enable."
|
|
group.long 0x100++0x13
|
|
line.long 0x0 "BODCTRL,BOD control"
|
|
bitfld.long 0x0 7. "BODHVREFSEL,BODH External Reference Select. Note: the SWE mux select in PWRSEQ2SWE must be set for this to take effect." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "BODLVREFSEL,BODL External Reference Select. Note: the SWE mux select in PWRSEQ2SWE must be set for this to take effect." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "BODCLVPWD,BODC_LV Power Down." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "BODSPWD,BODS Power Down." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "BODFPWD,BODF Power Down." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "BODCPWD,BODC Power Down." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "BODHPWD,BODH Power Down." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BODLPWD,BODL Power Down." "0,1"
|
|
line.long 0x4 "ADCPWRDLY,ADC Power Up Delay Control"
|
|
hexmask.long.byte 0x4 8.--15. 1. "ADCPWR1,ADC Reference Keeper enable delay in 16 ADC CLK increments for ADC_CLKSEL = 0x1 8 ADC CLOCK increments for ADC_CLKSEL = 0x2."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "ADCPWR0,ADC Reference Buffer Power Enable delay in 64 ADC CLK increments for ADC_CLKSEL = 0x1 32 ADC CLOCK increments for ADC_CLKSEL = 0x2."
|
|
line.long 0x8 "ADCPWRCTRL,ADC Power Control"
|
|
bitfld.long 0x8 16. "ADCKEEPOUTEN,ADC reference keeper out en" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "ADCRFBUFSLWEN,ADC reference buffer slew enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 14. "ADCINBUFEN,ADC Input Buffer Power Enable ( if the ADCPWRCTRLSWE bit is set )" "0,1"
|
|
newline
|
|
bitfld.long 0x8 12.--13. "ADCINBUFSEL,ADC input buffer mux select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 11. "ADCVBATDIVEN,ADC VBAT DIV Power Enable ( if the ADCPWRCTRLSWE bit is set )" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "VDDADCRESETN,RESETN signal for Power Switched SAR and Digital Controller (when global power switch is off and if the ADCPWRCTRLSWE bit is set)" "0: Resetn is asserted,1: Resetn is de-asserted"
|
|
newline
|
|
bitfld.long 0x8 8. "VDDADCDIGISOLATE,ISOLATE signal for ADC Digital Contoller ( when ADCAPSEN is switched off and if the ADCPWRCTRLSWE bit is set)" "0: No Isolation,1: Isolate"
|
|
newline
|
|
bitfld.long 0x8 7. "VDDADCSARISOLATE,ISOLATE signal for Power Switched SAR ( when ADCBPSEN is switched off )" "0: No Isolation,1: Isolate"
|
|
newline
|
|
bitfld.long 0x8 6. "REFKEEPPEN,Reference Buffer Keeper Power Switch Enable" "0: Reference Buffer Keeper Power Switch disable.,1: Reference Buffer Keeper Power Switch enable."
|
|
newline
|
|
bitfld.long 0x8 5. "REFBUFPEN,Reference Buffer Power Switch Enable" "0: Reference Buffer Power Switch disable.,1: Reference Buffer Power Switch enable."
|
|
newline
|
|
bitfld.long 0x8 4. "BGTLPPEN,Bandgap and Temperature Sensor Power Switch Enable" "0: Bandgap and temperature sensor disable.,1: Bandgap and temperature sensor enable."
|
|
newline
|
|
bitfld.long 0x8 3. "BGTPEN,Bandgap and Temperature Sensor Power Switch Enable" "0: Bandgap and temperature sensor disable.,1: Bandgap and temperature sensor enable."
|
|
newline
|
|
bitfld.long 0x8 2. "ADCBPSEN,Enable the Analog IO and SAR Digital logic Power Switch on when set to 1 if the ADCPWRCTRLSWE bit is set." "0: ADC power switch software power disable.,1: ADC power switch software power enable."
|
|
newline
|
|
bitfld.long 0x8 1. "ADCAPSEN,Enable the Global ADC Power Switch on when set to 1 if the ADCPWRCTRLSWE bit is set." "0: ADC power switch software power disable.,1: ADC power switch software power enable."
|
|
newline
|
|
bitfld.long 0x8 0. "ADCPWRCTRLSWE,ADC Power Control Software Override Enable" "0: ADC temperature sensor and bandgap Software..,1: ADC temperature sensor and bandgap Software.."
|
|
line.long 0xC "ADCCAL,ADC Calibration Control"
|
|
bitfld.long 0xC 1. "ADCCALIBRATED,Status for ADC Calibration" "0: ADC is not calibrated,1: ADC is calibrated"
|
|
newline
|
|
bitfld.long 0xC 0. "CALONPWRUP,Run ADC Calibration on initial power up sequence" "0: Disable automatic calibration on initial power up,1: Enable automatic calibration on initial power up"
|
|
line.long 0x10 "ADCBATTLOAD,ADC Battery Load Enable"
|
|
bitfld.long 0x10 0. "BATTLOAD,Enable the ADC battery load resistor" "0: Battery load is disconnected,1: Battery load is enabled"
|
|
group.long 0x120++0xF
|
|
line.long 0x0 "XTALCTRL,XTAL Oscillator Control"
|
|
bitfld.long 0x0 7.--8. "XTALICOMPTRIM,XTAL ICOMP trim" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 5.--6. "XTALIBUFTRIM,XTAL IBUFF trim" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 4. "XTALCOMPPDNB,XTAL Oscillator Power Down Comparator." "0: Power down XTAL oscillator comparator.,1: Power up XTAL oscillator comparator."
|
|
newline
|
|
bitfld.long 0x0 3. "XTALPDNB,XTAL Oscillator Power Down Core." "0: Power down XTAL oscillator core.,1: Power up XTAL oscillator core."
|
|
newline
|
|
bitfld.long 0x0 2. "XTALCOMPBYPASS,XTAL Oscillator Bypass Comparator." "0: Use the XTAL oscillator comparator.,1: Bypass the XTAL oscillator comparator."
|
|
newline
|
|
bitfld.long 0x0 1. "XTALCOREDISFB,XTAL Oscillator Disable Feedback." "0: Enable XTAL oscillator comparator.,1: Disable XTAL oscillator comparator."
|
|
newline
|
|
bitfld.long 0x0 0. "XTALSWE,XTAL Software Override Enable." "0: XTAL Software Override Disable.,1: XTAL Software Override Enable."
|
|
line.long 0x4 "XTALGENCTRL,XTAL Oscillator General Control"
|
|
hexmask.long.byte 0x4 8.--13. 1. "XTALKSBIASTRIM,XTAL IBIAS Kick start trim. This trim value is used during the startup process to enable a faster lock."
|
|
newline
|
|
hexmask.long.byte 0x4 2.--7. 1. "XTALBIASTRIM,XTAL BIAS trim"
|
|
newline
|
|
bitfld.long 0x4 0.--1. "ACWARMUP,Auto-calibration delay control" "0: Warmup period of 1-2 seconds,1: Warmup period of 2-4 seconds,2: Warmup period of 4-8 seconds,3: Warmup period of 8-16 seconds"
|
|
line.long 0x8 "XTALHSTRIMS,XTALHS Trims"
|
|
bitfld.long 0x8 29. "XTALHSSPARE,xtalhs_spare" "0,1"
|
|
newline
|
|
bitfld.long 0x8 28. "XTALHSRSTRIM,xtalhs_rs_trim" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 21.--27. 1. "XTALHSIBIASTRIM,xtalhs_ibias_trim"
|
|
newline
|
|
hexmask.long.byte 0x8 17.--20. 1. "XTALHSIBIASCOMPTRIM,xtalhs_ibias_comp_trim"
|
|
newline
|
|
bitfld.long 0x8 15.--16. "XTALHSIBIASCOMP2TRIM,xtalhs_ibias_comp2_trim" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 12.--14. "XTALHSDRIVERSTRENGTH,xtalhs_driver_strength" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "XTALHSDRIVETRIM,xtalhs_drive_trim" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x8 6.--9. 1. "XTALHSCAPTRIM,xtalhs_cap_trim"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--5. 1. "XTALHSCAP2TRIM,xtalhs_cap2_trim"
|
|
line.long 0xC "XTALHSCTRL,XTALHS Control"
|
|
bitfld.long 0xC 8. "XTALHSEXTERNALCLOCK,xtalhs_external_clock" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "XTALHSPADOUTEN,xtalhs_padout_en" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "XTALHSSELRCOM,xtalhs_sel_rcom" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "XTALHSPDNPNIMPROVE,xtalhs_pdn_pn_improve" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "XTALHSINJECTIONENABLE,xtalhs_injection_enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "XTALHSIBSTENABLE,xtalhs_ibst_enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "XTALHSCOMPSEL,xtalhs_comp_sel" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "XTALHSCOMPPDNB,xtalhs_comp_pdnb" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "XTALHSPDNB,xtalhs_pdnb" "0,1"
|
|
group.long 0x180++0x3
|
|
line.long 0x0 "MRAMPWRCTRL,MRAM Power Control"
|
|
bitfld.long 0x0 2. "MRAMPWRCTRL,MRAM low power mode control. '0' tmc_lpr and tmc_slp are driven into mcu_ctrl '1' tmc_lpr and tmc_slp are driven into MRAM wrapper." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MRAMSLPEN,MRAM sleep mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MRAMLPREN,MRAM low power mode enable" "0,1"
|
|
group.long 0x1AC++0x3
|
|
line.long 0x0 "BODISABLE,Brownout Disable"
|
|
bitfld.long 0x0 4. "BODCLVREN,Disable VDDC_LV Brown Out reset." "0: Disable VDDC_LV Brown Out reset.,1: Enable VDDC_LV Brown Out reset."
|
|
newline
|
|
bitfld.long 0x0 3. "BODSREN,Disable VDDS Brown Out reset." "0: Disable VDDS Brown Out reset.,1: Enable VDDS Brown Out reset."
|
|
newline
|
|
bitfld.long 0x0 2. "BODFREN,Disable VDDF Brown Out reset." "0: Disable VDDF Brown Out reset.,1: Enable VDDF Brown Out reset."
|
|
newline
|
|
bitfld.long 0x0 1. "BODCREN,Disable VDDC Brown Out reset." "0: Disable VDDC Brown Out reset.,1: Enable VDDC Brown Out reset."
|
|
newline
|
|
bitfld.long 0x0 0. "BODLRDE,Disable Unregulated 1.8V Brown-out reset." "0: Enable Unregulated 1.8v brown out reset.,1: Disable Unregulated 1.8v brown out reset."
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
group.long 0x1B0++0x3
|
|
line.long 0x0 "D2ASPARE,Spare registers to analog module"
|
|
bitfld.long 0x0 4. "VDDCAOROVERRIDE,VDDCAOR Override. Set to 1 to connect to the VDDC rail set to 0 to connect to the VDDC_LV rail. Before setting this bit to 0 the VDDC_LV rail must first be enabled by setting SIMOBUCK0_b.VDDCLVRXCOMPEN. Do not modify this field unless.." "0,1"
|
|
bitfld.long 0x0 3. "VDDCPUOVERRIDE,VDDCPU Override. Set to 1 to connect to the VDDC rail set to 0 to connect to the VDDC_LV rail. Before setting this bit to 0 the VDDC_LV rail must first be enabled by setting SIMOBUCK0_b.VDDCLVRXCOMPEN. Do not modify this field unless.." "0,1"
|
|
group.long 0x1C4++0x3
|
|
line.long 0x0 "SCRATCH1,Scratch register that is not reset by any reset"
|
|
hexmask.long 0x0 0.--31. 1. "SCRATCH1,Scratch register 1."
|
|
group.long 0x388++0x3
|
|
line.long 0x0 "USBRSTCTRL,USB Reset Startup Control"
|
|
bitfld.long 0x0 2. "USBUTMIRSTRELEASE,Set this bit to '1' after USB power domain is up. This will release the reset override condition" "0,1"
|
|
bitfld.long 0x0 1. "USBPORRSTRELEASE,Set this bit to '1' after USB power domain is up. This will release the reset override condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "USBRSTENABLE,This bit enables this register control. If set to '1' the reset release bits will be active. If set to '0' this register is not controlling the USB override bits." "0,1"
|
|
endif
|
|
group.long 0x1B8++0xB
|
|
line.long 0x0 "BOOTLOADER,Bootloader and secure boot functions"
|
|
bitfld.long 0x0 30.--31. "SECBOOTONRST,Indicates whether the secure boot on warm reset is enabled" "0: Secure boot disabled,1: Secure boot enabled,2: Error in secure boot configuration,?"
|
|
newline
|
|
bitfld.long 0x0 28.--29. "SECBOOT,Indicates whether the secure boot on cold reset is enabled" "0: Secure boot disabled,1: Secure boot enabled,2: Error in secure boot configuration,?"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "SECBOOTFEATURE,Indicates whether the secure boot feature is enabled." "0: Secure boot disabled,1: Secure boot enabled,2: Error in secure boot configuration,?"
|
|
newline
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 3. "SBLLOCK,Secure boot loader lock. Always resets to 1 write 1 to clear. Enables system visibility to bootloader until set." "0: Disable the secure boot lock,1: Enable the secure boot lock"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 3. "SBLLOCK,Secure boot loader lock. Always resets to 1 write 1 to clear. Enables system visibility to bootloader until set." "0: Disable the secure boot lock,1: Enable the secure boot lock"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
bitfld.long 0x0 3. "SBLLOCK,Secure boot loader lock. Always resets to 1 write 1 to clear. Enables system visibility to bootloader until set." "?,1: Enable the secure boot lock"
|
|
newline
|
|
bitfld.long 0x0 1. "SBRLOCK,Secure boot ROM lock. Always resets to 1 write 1 to clear. Enables system visibility to bootloader until set." "?,1: Enable the secure boot lock"
|
|
newline
|
|
bitfld.long 0x0 0. "BOOTLOADERLOW,Determines whether the bootloader code is visible at address 0x00000000 or not. Resets to 1 write 1 to clear." "?,1: Bootloader code at 0x00000000."
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 2. "PROTLOCK,This field controls access to OEM keybank and restricts further application of NVM protections via the FLASHWPROTn and FLASHRPROTn registers. On read 0 indicates locked 1 indicates unlocked. Write 1 to clear (lock) the register. Default value.." "0: On write this value (writing 0) has no effect.,1: On write this value asserts the lock. On read.."
|
|
newline
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 1. "SBRLOCK,Secure boot ROM lock. Always resets to 1 write 1 to clear. Enables system visibility to bootloader until set." "0: Default value.,1: Enable the secure boot lock"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 1. "SBRLOCK,Secure boot ROM lock. Always resets to 1 write 1 to clear. Enables system visibility to bootloader until set." "0: Default value.,1: Enable the secure boot lock"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 0. "BOOTLOADERLOW,Determines whether the bootloader code is visible at address 0x00000000 or not. Resets to 1 write 1 to clear." "0: Bootloader code is not visible at address,1: Bootloader code at 0x00000000."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 0. "BOOTLOADERLOW,Determines whether the bootloader code is visible at address 0x00000000 or not. Resets to 1 write 1 to clear." "0: Bootloader code is not visible at address,1: Bootloader code at 0x00000000."
|
|
endif
|
|
line.long 0x4 "SHADOWVALID,Register to indicate whether the shadow registers have been successfully loaded from the Flash Information Space."
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
bitfld.long 0x4 2. "INFO0VALID,Indicates whether info0 contains valid data" "?,1: Flash info0 (customer) space contains valid data."
|
|
newline
|
|
bitfld.long 0x4 1. "BLDSLEEP,Indicates whether the bootloader should sleep or deep sleep if no image loaded." "?,1: Bootloader will go to deep sleep if no flash.."
|
|
newline
|
|
bitfld.long 0x4 0. "VALID,Indicates whether the shadow registers contain valid data from the Flash Information Space." "?,1: Flash information space contains valid data."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 2. "INFO0VALID,Indicates whether info0 contains valid data" "0: Default value.,1: Flash info0 (customer) space contains valid data."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 1. "BLDSLEEP,Indicates whether the bootloader should sleep or deep sleep if no image loaded." "0: Bootloader will go to normalsleep if no flash..,1: Bootloader will go to deep sleep if no flash.."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 1. "BLDSLEEP,Indicates whether the bootloader should sleep or deep sleep if no image loaded." "0: Bootloader will go to normalsleep if no flash..,1: Bootloader will go to deep sleep if no flash.."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 0. "VALID,Indicates whether the shadow registers contain valid data from the Flash Information Space." "0: Default value.,1: Flash information space contains valid data."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 0. "VALID,Indicates whether the shadow registers contain valid data from the Flash Information Space." "0: Default value.,1: Flash information space contains valid data."
|
|
endif
|
|
line.long 0x8 "SCRATCH0,Scratch register that is not reset by any reset"
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
bitfld.long 0x8 0. "HALTREQ,Reset-Halt requested from debugger." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long 0x8 0.--31. 1. "SCRATCH0,Scratch register 0."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long 0x8 0.--31. 1. "SCRATCH0,Scratch register 0."
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
group.long 0x1C4++0x3
|
|
line.long 0x0 "SCRATCH1,Scratch register that is not reset by any reset"
|
|
hexmask.long 0x0 0.--31. 1. "SCRATCH1,Scratch register 1."
|
|
group.long 0x388++0x3
|
|
line.long 0x0 "USBRSTCTRL,USB Reset Startup Control"
|
|
bitfld.long 0x0 2. "USBUTMIRSTRELEASE,Set this bit to '1' after USB power domain is up. This will release the reset override condition" "0,1"
|
|
bitfld.long 0x0 1. "USBPORRSTRELEASE,Set this bit to '1' after USB power domain is up. This will release the reset override condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "USBRSTENABLE,This bit enables this register control. If set to '1' the reset release bits will be active. If set to '0' this register is not controlling the USB override bits." "0,1"
|
|
endif
|
|
group.long 0x200++0x7
|
|
line.long 0x0 "DBGR1,Read-only debug 1"
|
|
hexmask.long 0x0 0.--31. 1. "ONETO8,Read-only register for communication validation"
|
|
line.long 0x4 "DBGR2,Read-only debug 2"
|
|
hexmask.long 0x4 0.--31. 1. "COOLCODE,Read-only register for communication validation"
|
|
group.long 0x220++0x3
|
|
line.long 0x0 "PMUENABLE,Control bit to enable/disable the PMU"
|
|
bitfld.long 0x0 0. "ENABLE,PMU Enable Control bit. When set the MCU's PMU will place the MCU into the lowest power consuming Deep Sleep mode upon execution of a WFI instruction (dependent on the setting of the SLEEPDEEP bit in the ARM SCR register). When cleared .." "0: Disable MCU power management.,1: Enable MCU power management."
|
|
group.long 0x250++0x3
|
|
line.long 0x0 "DBGCTRL,Debug subsystem Control. Determines the debug components enable and clk frequency."
|
|
bitfld.long 0x0 17. "DBGDSP1OCDHALTONRST,Debug subsystem DSP1 OCD Halt on Reset" "0: Disable DSP1 OCD Halt on Reset.,1: Enable DSP1 OCD Halt on Reset."
|
|
newline
|
|
bitfld.long 0x0 16. "DBGDSP0OCDHALTONRST,Debug subsystem DSP0 OCD Halt on Reset" "0: Disable DSP0 OCD Halt on Reset.,1: Enable DSP0 OCD Halt on Reset."
|
|
newline
|
|
bitfld.long 0x0 12.--14. "DBGTSCLKSEL,This field selects the frequency of the ARM M4 dbg ts port." "0: Low power state.,1: Selects HFRC divided by 2 as the source dbg ts clk,2: Selects HFRC divided by 8 as the source dbg ts clk,3: Selects HFRC divided by 16 as the source dbg ts..,4: Selects HFRC divided by 32 as the source dbg ts..,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 11. "DBGDSP1TRACEEN,Debug subsystem DSP1 trace enable" "0: Disable DSP1 trace.,1: Enable DSP1 trace."
|
|
newline
|
|
bitfld.long 0x0 10. "DBGDSP0TRACEEN,Debug subsystem DSP0 trace enable" "0: Disable DSP0 trace.,1: Enable DSP0 trace."
|
|
newline
|
|
bitfld.long 0x0 9. "DBGETMTRACEEN,Debug subsystem ETM trace enable" "0: Disable ETM trace.,1: Enable ETM trace."
|
|
newline
|
|
bitfld.long 0x0 8. "DBGETBENABLE,Debug subsystem ETB enable to store the trace data." "0: Disable ETB.,1: Enable ETB."
|
|
newline
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
bitfld.long 0x0 5.--7. "DBGCLKSEL,This field selects the frequency of the Debug Trace TPIU port." "0: Low power state.,1: Selects HFRC 96Mhz as the source TPIU clk,2: Selects HFRC 48Mhz as the source TPIU clk,3: Selects HFRC 24Mhz as the source TPIU clk,4: Selects HFRC 6Mhz as the source TPIU clk,5: Selects HFRC 3Mhz as the source TPIU clk,6: Selects HFRC 1.5Mhz as the source TPIU clk,?"
|
|
newline
|
|
bitfld.long 0x0 4. "DBGTPIUENABLE,TPIU Enable field. When set the Debug Trace TPIU is enabled and data can be streamed out of the MCU ETM or DSP TRAXs." "0: Disable the TPIU.,1: Enable the TPIU."
|
|
newline
|
|
bitfld.long 0x0 1.--3. "CM4CLKSEL,This field selects the frequency of the ARM M4 TPIU port." "0: Low power state.,1: Selects HFRC divided by 4 as the source TPIU clk..,2: Selects HFRC divided by 16 as the source TPIU..,3: Selects HFRC divided by 32 as the source TPIU..,4: Selects HFRC divided by 64 as the source TPIU..,?,?,?"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 1.--3. "CM4CLKSEL,This field selects the frequency of the ARM M4 TPIU port." "0: Low power state.,1: Selects HFRC 96Mhz as the source TPIU clk,2: Selects HFRC 48Mhz as the source TPIU clk,3: Selects HFRC 24Mhz as the source TPIU clk,4: Selects HFRC 6Mhz as the source TPIU clk,5: Selects HFRC 3Mhz as the source TPIU clk,6: Selects HFRC 1.5Mhz as the source TPIU clk,7: Selects HFRC2 192Mhz as the source TPIU clk."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 1.--3. "CM4CLKSEL,This field selects the frequency of the ARM M4 TPIU port." "0: Low power state.,1: Selects HFRC 96Mhz as the source TPIU clk,2: Selects HFRC 48Mhz as the source TPIU clk,3: Selects HFRC 24Mhz as the source TPIU clk,4: Selects HFRC 6Mhz as the source TPIU clk,5: Selects HFRC 3Mhz as the source TPIU clk,6: Selects HFRC 1.5Mhz as the source TPIU clk,7: Selects HFRC2 192Mhz as the source TPIU clk."
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 0. "CM4TPIUENABLE,TPIU Enable field. When set the ARM M4 TPIU is enabled and data can be streamed out of the MCU's SWO port using the ARM ITM and TPIU modules." "0: Disable the TPIU.,1: Enable the TPIU."
|
|
group.long 0x264++0x3
|
|
line.long 0x0 "OTAPOINTER,OTA (Over the Air) Update Pointer/Status. Reset only by POA"
|
|
hexmask.long 0x0 2.--31. 1. "OTAPOINTER,Flash page pointer with updated OTA image"
|
|
newline
|
|
bitfld.long 0x0 1. "OTASBLUPDATE,Indicates that the sbl_init has been updated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "OTAVALID,Indicates that an OTA update is valid" "0,1"
|
|
group.long 0x280++0x3
|
|
line.long 0x0 "APBDMACTRL,DMA Control Register. Determines misc settings for DMA operation"
|
|
hexmask.long.byte 0x0 8.--15. 1. "HYSTERESIS,This field determines how long the DMA engine of apb/disp/gfx will remain active during deep sleep before shutting down and returning the system to full deep sleep. Values are based on a 94KHz clock and are roughly 10us increments for a range.."
|
|
newline
|
|
bitfld.long 0x0 1. "DECODEABORT,APB Decode Abort. When set the APB bridge will issue a data abort (bus fault) on transactions to peripherals that are powered down. When set to 0 writes are quietly discarded and reads return 0." "0: Bus operations to powered down peripherals are..,1: Bus operations to powered down peripherals.."
|
|
newline
|
|
bitfld.long 0x0 0. "DMAENABLE,Enable the DMA controller. When disabled DMA requests will be ignored by the controller" "0: DMA operations disabled,1: DMA operations enabled"
|
|
group.long 0x338++0x13
|
|
line.long 0x0 "KEXTCLKSEL,Locks the state of the EXTCLKSEL register from writes. This is done to prevent errant writes to the register. as this could cause the chip to halt. Write a value of 0x53 to unlock write access to the EXTCLKSEL register. Once unlocked. the.."
|
|
hexmask.long 0x0 0.--31. 1. "KEXTCLKSEL,Key register value."
|
|
line.long 0x4 "SIMOBUCK0,This WRITE_ONLY register controls various buck parameters. It will read back as 0x00000000."
|
|
bitfld.long 0x4 4. "TONTOFFNODEGLITCH,Enable the ton and toff signals no deglitch output." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "VDDCLVRXCOMPEN,Enable the VDDC LV rail." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "VDDSRXCOMPEN,Enable the VDDS rail." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "VDDFRXCOMPEN,Enable the VDDS rail." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "VDDCRXCOMPEN,Enable the VDDC rail." "0,1"
|
|
line.long 0x8 "SIMOBUCK1,1. Control the even division of 3 clocks: refresh. low power and TONCLK. 2. Control gap bewteen secondary switches. 3. Debug features: control the amount of time TONCLK is on. and the time before snubber asserts for each buck sequence. 4."
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x8 22.--25. 1. "SIMOBUCKTONCLKTRIM,This divides the 100 MHz ton clock. Even divides are supported only. This value represents the division amount minus 1."
|
|
newline
|
|
hexmask.long.byte 0x8 6.--10. 1. "SIMOBUCKRXCLKACTTRIM,This divides the 5 MHz refresh clock. Even divides are supported only. This value represents the division amount minus 1."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x8 22.--25. 1. "TONCLKTRIM,This divides the 100 MHz ton clock. Even divides are supported only. This value represents the division amount minus 1."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x8 22.--25. 1. "TONCLKTRIM,This divides the 100 MHz ton clock. Even divides are supported only. This value represents the division amount minus 1."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x8 6.--10. 1. "RXCLKACTTRIM,This divides the 5 MHz refresh clock. Even divides are supported only. This value represents the division amount minus 1."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x8 6.--10. 1. "RXCLKACTTRIM,This divides the 5 MHz refresh clock. Even divides are supported only. This value represents the division amount minus 1."
|
|
endif
|
|
line.long 0xC "SIMOBUCK2,SIMO Buck Muxed VDDC Active Sequence Trim Control"
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0xC 24.--27. 1. "SIMOBUCKVDDCACTLOWTONTRIM,VDDC active high ton trim control for Buck sequence."
|
|
newline
|
|
hexmask.long.byte 0xC 11.--14. 1. "SIMOBUCKVDDCACTHIGHTONTRIM,VDDC active high ton trim control for Buck sequence."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0xC 24.--28. 1. "VDDCACTLOWTONTRIM,VDDC active high ton trim control for Buck sequence."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0xC 24.--28. 1. "VDDCACTLOWTONTRIM,VDDC active high ton trim control for Buck sequence."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0xC 11.--14. 1. "VDDCACTHIGHTONTRIM,VDDC active high ton trim control for Buck sequence."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0xC 11.--14. 1. "VDDCACTHIGHTONTRIM,VDDC active high ton trim control for Buck sequence."
|
|
endif
|
|
line.long 0x10 "SIMOBUCK3,SIMO Buck Muxed VDDC low power Sequence Trim Control"
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x10 26.--29. 1. "SIMOBUCKVDDCLPLOWTONTRIM,VDDC LP low ton trim control for Buck sequence."
|
|
newline
|
|
hexmask.long.byte 0x10 21.--25. 1. "SIMOBUCKVDDCLPLOWTOFFTRIM,VDDC LP low toff trim control for Buck sequence."
|
|
newline
|
|
hexmask.long.byte 0x10 13.--16. 1. "SIMOBUCKVDDCLPHIGHTONTRIM,VDDC LP high ton trim control for Buck sequence."
|
|
newline
|
|
hexmask.long.byte 0x10 8.--12. 1. "SIMOBUCKVDDCLPHIGHTOFFTRIM,VDDC LP high toff trim control for Buck sequence."
|
|
newline
|
|
bitfld.long 0x10 2.--3. "SIMOBUCKVDDCLPDRVSTRTRIM,VDDC LP trim control for drive strength." "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x10 26.--29. 1. "VDDCLPLOWTONTRIM,VDDC LP low ton trim control for Buck sequence."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x10 26.--29. 1. "VDDCLPLOWTONTRIM,VDDC LP low ton trim control for Buck sequence."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x10 13.--16. 1. "VDDCLPHIGHTONTRIM,VDDC LP high ton trim control for Buck sequence."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x10 13.--16. 1. "VDDCLPHIGHTONTRIM,VDDC LP high ton trim control for Buck sequence."
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
group.long 0x34C++0x3
|
|
line.long 0x0 "SIMOBUCK4,SIMO Buck Muxed VDDC LV Active Sequence Trim Control"
|
|
hexmask.long.byte 0x0 24.--27. 1. "VDDCLVACTLOWTONTRIM,VDDC LV active low ton trim control for Buck sequence."
|
|
hexmask.long.byte 0x0 19.--23. 1. "VDDCLVACTLOWTOFFTRIM,VDDC LV active low trim control for a 500 MHz clock inside the simobuck analog design."
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "VDDCLVACTHIGHTONTRIM,VDDC LV active high ton trim control for Buck sequence."
|
|
hexmask.long.byte 0x0 6.--10. 1. "VDDCLVACTHIGHTOFFTRIM,VDDC LV active high toff trim control for Buck sequence."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "VDDCLVACTDRVSTRTRIM,VDDC LV active trim control for drive strength." "0,1,2,3"
|
|
endif
|
|
group.long 0x354++0xF
|
|
line.long 0x0 "SIMOBUCK6,SIMO Buck Muxed VDDF Active Sequence Trim Control"
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x0 17.--20. 1. "SIMOBUCKVDDFACTHIGHTONTRIM,VDDF active high ton trim control for Buck sequence."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 17.--20. 1. "VDDFACTHIGHTONTRIM,VDDF active high ton trim control for Buck sequence."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 17.--20. 1. "VDDFACTHIGHTONTRIM,VDDF active high ton trim control for Buck sequence."
|
|
endif
|
|
line.long 0x4 "SIMOBUCK7,SIMO Buck Muxed VDDF active Sequence Trim Control"
|
|
hexmask.long.byte 0x4 18.--22. 1. "ZXCOMPZXTRIM,Zxcomp trim. Feedthrough to analog."
|
|
newline
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
bitfld.long 0x4 13.--14. "VDDFLPDRVSTRTRIM,VDDF active trim control for drive strength." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 9.--12. 1. "VDDFACTLOWTONTRIM,VDDF active low ton trim control for Buck sequence."
|
|
newline
|
|
hexmask.long.byte 0x4 4.--8. 1. "VDDFACTLOWTOFFTRIM,VDDF active low toff trim control for Buck sequence."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x4 8.--12. 1. "VDDFACTLOWTONTRIM,VDDF active low ton trim control for Buck sequence."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x4 8.--12. 1. "VDDFACTLOWTONTRIM,VDDF active low ton trim control for Buck sequence."
|
|
endif
|
|
line.long 0x8 "SIMOBUCK8,SIMO Buck Muxed VDDF Low Power Sequence Trim Control"
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x8 22.--25. 1. "SIMOBUCKVDDFLPLOWTONTRIM,VDDF low power low ton trim control for Buck sequence."
|
|
newline
|
|
hexmask.long.byte 0x8 17.--21. 1. "SIMOBUCKVDDFLPLOWTOFFTRIM,VDDF low power low toff trim control for Buck sequence."
|
|
newline
|
|
hexmask.long.byte 0x8 9.--12. 1. "SIMOBUCKVDDFLPHIGHTONTRIM,VDDF low power high ton trim control for Buck sequence."
|
|
newline
|
|
hexmask.long.byte 0x8 4.--8. 1. "SIMOBUCKVDDFLPHIGHTOFFTRIM,VDDF low power high toff trim control for Buck sequence."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x8 22.--25. 1. "VDDFLPLOWTONTRIM,VDDF low power low ton trim control for Buck sequence."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x8 22.--25. 1. "VDDFLPLOWTONTRIM,VDDF low power low ton trim control for Buck sequence."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x8 9.--12. 1. "VDDFLPHIGHTONTRIM,VDDF low power high ton trim control for Buck sequence."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x8 9.--12. 1. "VDDFLPHIGHTONTRIM,VDDF low power high ton trim control for Buck sequence."
|
|
endif
|
|
line.long 0xC "SIMOBUCK9,SIMO Buck Muxed VDDS Active Sequence Trim Control"
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0xC 22.--25. 1. "SIMOBUCKVDDSACTLOWTONTRIM,VDDS active low ton trim control for Buck sequence."
|
|
newline
|
|
hexmask.long.byte 0xC 17.--20. 1. "SIMOBUCKVDDSACTHIGHTONTRIM,VDDS active high ton trim control for Buck sequence."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0xC 22.--26. 1. "VDDSACTLOWTONTRIM,VDDS active low ton trim control for Buck sequence."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0xC 22.--26. 1. "VDDSACTLOWTONTRIM,VDDS active low ton trim control for Buck sequence."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0xC 17.--20. 1. "VDDSACTHIGHTONTRIM,VDDS active high ton trim control for Buck sequence."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0xC 17.--20. 1. "VDDSACTHIGHTONTRIM,VDDS active high ton trim control for Buck sequence."
|
|
endif
|
|
group.long 0x36C++0x7
|
|
line.long 0x0 "SIMOBUCK12,SIMO Buck Compare. Brown out. Active. Low power Trim Control"
|
|
hexmask.long.byte 0x0 26.--31. 1. "LPTRIMVDDF,Low power VDDF trim."
|
|
newline
|
|
hexmask.long.byte 0x0 20.--25. 1. "ACTTRIMVDDF,Active VDDF trim."
|
|
newline
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.word 0x0 10.--19. 1. "VDDCLVBRNOUTTRIM,Digital brown out max counter value for VDDC LV rail."
|
|
newline
|
|
hexmask.long.byte 0x0 5.--9. 1. "VDDCLVCOMPTRIMPLUS,Static trim to allow separation when low power GT active rail."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "VDDCLVCOMPTRIMMINUS,Static trim to allow separation between low power and active rail."
|
|
endif
|
|
line.long 0x4 "SIMOBUCK13,SIMO Buck Compare. Brown out. Active. Low power Trim Control"
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x4 26.--31. 1. "SIMOBUCKLPTRIMVDDS,Low power VDDS trim."
|
|
newline
|
|
hexmask.long.byte 0x4 20.--25. 1. "SIMOBUCKACTTRIMVDDS,Active VDDS trim."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x4 26.--31. 1. "LPTRIMVDDS,Low power VDDS trim."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x4 26.--31. 1. "LPTRIMVDDS,Low power VDDS trim."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x4 20.--25. 1. "ACTTRIMVDDS,Active VDDS trim."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x4 20.--25. 1. "ACTTRIMVDDS,Active VDDS trim."
|
|
endif
|
|
group.long 0x378++0xB
|
|
line.long 0x0 "SIMOBUCK15,SIMO Buck Compare. Brown out. Active and Low power Trim Control"
|
|
bitfld.long 0x0 31. "TRIMLATCHOVER,Override / Bypass the simobuck trim latch to enable on-the-fly trimming for VDDF and VDDS active and LP trims" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--28. 1. "ZXCOMPOFFSETTRIM,Zxcomp offset trim. Feedthrough to analog."
|
|
newline
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
bitfld.long 0x0 23. "VDDCRXCOMPTRIMEN,Enable the VDDC rail. If not enabled the rail will not be regulated. This must be done before simobuck comes up." "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "VDDFRXCOMPTRIMEN,Enable the VDDF rail. If not enabled the rail will not be regulated. This must be done before simobuck comes up." "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "VDDSRXCOMPTRIMEN,Enable the VDDS rail. If not enabled the rail will not be regulated. This must be done before simobuck comes up." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "VDDCLVRXCOMPTRIMEN,Enable the VDDC LV rail. If not enabled the rail will not be regulated. This must be done before simobuck comes up." "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 10.--19. 1. "VDDCBRNOUTTRIM,Digital brown out max counter value for VDDC rail."
|
|
newline
|
|
hexmask.long.byte 0x0 5.--9. 1. "VDDCCOMPTRIMPLUS,Static trim to allow separation when low power GT active rail."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "VDDCCOMPTRIMMINUS,Static trim to allow separation between low power and active rail."
|
|
endif
|
|
line.long 0x4 "PWRSW0,PWRSW Control 0"
|
|
bitfld.long 0x4 31. "PWRSWVDDRCPUOVERRIDE,override enable for pwrsw_vddrcpu_dynsel and pgn" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "PWRSWVDDRCPUSTATSEL,VDDRCPU power switch static select" "0: Select VDDFLP rail,1: Select VDDC rail"
|
|
newline
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 29. "PWRSWVDDRCPUPGN,override value for pwrsw_vddrcpu_pgn" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 29. "PWRSWVDDRCPUPGN,override value for pwrsw_vddrcpu_pgn" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x4 27.--28. "PWRSWVDDRCPUDYNSEL,override value for pwrsw_vddrcpu_dynsel" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 26. "PWRSWVDDMLOVERRIDE,override enable for pwrsw_vddml_dynsel" "0,1"
|
|
newline
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 25. "PWRSWVDDMLSTATSEL,VDDML power switch static select" "0: Select VDDC rail,1: Select VDDF rail"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 25. "PWRSWVDDMLSTATSEL,VDDML power switch static select" "0: Select VDDC rail,1: Select VDDF rail"
|
|
newline
|
|
endif
|
|
bitfld.long 0x4 24. "PWRSWVDDMLDYNSEL,override value for pwrsw_vddml_dynsel" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "PWRSWVDDMDSP1OVERRIDE,override enable for pwrsw_vddmdsp1_dynsel" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "PWRSWVDDMDSP1STATSEL,VDDMDSP1 power switch static select" "0: Select VDDC rail,1: Select VDDF rail"
|
|
newline
|
|
bitfld.long 0x4 21. "PWRSWVDDMDSP1DYNSEL,override value for pwrsw_vddmdsp1_dynsel" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PWRSWVDDMDSP0OVERRIDE,override enable for pwrsw_vddmdsp0_dynsel" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "PWRSWVDDMDSP0STATSEL,VDDMDSP0 power switch static select" "0: Select VDDC rail,1: Select VDDF rail"
|
|
newline
|
|
bitfld.long 0x4 18. "PWRSWVDDMDSP0DYNSEL,override value for pwrsw_vddmdsp0_dynsel" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PWRSWVDDMCPUOVERRIDE,override enable for pwrsw_vddmcpu_dynsel" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "PWRSWVDDMCPUSTATSEL,VDDMCPU power switch static select" "0: Select VDDC rail,1: Select VDDF rail"
|
|
newline
|
|
bitfld.long 0x4 15. "PWRSWVDDMCPUDYNSEL,override value for pwrsw_vddmcpu_dynsel" "0,1"
|
|
newline
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 14. "PWRSWVDDDSP1OVERRIDE,override enable for pwrsw_vdddsp1_dynsel and pgn" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 14. "PWRSWVDDDSP1OVERRIDE,override enable for pwrsw_vdddsp1_dynsel and pgn" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 13. "PWRSWVDDDSP1PGN,override value for pwrsw_vdddsp1_pgn" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 13. "PWRSWVDDDSP1PGN,override value for pwrsw_vdddsp1_pgn" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 11.--12. "PWRSWVDDDSP1DYNSEL,override value for pwrsw_vdddsp1_dynsel" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 11.--12. "PWRSWVDDDSP1DYNSEL,override value for pwrsw_vdddsp1_dynsel" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 10. "PWRSWVDDDSP0OVERRIDE,override enable for pwrsw_vdddsp0_dynsel and pgn" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 10. "PWRSWVDDDSP0OVERRIDE,override enable for pwrsw_vdddsp0_dynsel and pgn" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 9. "PWRSWVDDDSP0PGN,override value for pwrsw_vdddsp0_pgn" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 9. "PWRSWVDDDSP0PGN,override value for pwrsw_vdddsp0_pgn" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 7.--8. "PWRSWVDDDSP0DYNSEL,override value for pwrsw_vdddsp0_dynsel" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 7.--8. "PWRSWVDDDSP0DYNSEL,override value for pwrsw_vdddsp0_dynsel" "0,1,2,3"
|
|
newline
|
|
endif
|
|
bitfld.long 0x4 6. "PWRSWVDDCAOROVERRIDE,override enable for pwrsw_vddcaor_dynsel" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--5. "PWRSWVDDCAORDYNSEL,override value for pwrsw_vddcaor_dynsel" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 3. "PWRSWVDDCPUOVERRIDE,override enable for pwrsw_vddcpu_dynsel and pgn" "0,1"
|
|
newline
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 2. "PWRSWVDDCPUPGN,override value for pwrsw_vddcpu_pgn" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 2. "PWRSWVDDCPUPGN,override value for pwrsw_vddcpu_pgn" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x4 0.--1. "PWRSWVDDCPUDYNSEL,override value for pwrsw_vddcpu_dynsel" "0,1,2,3"
|
|
line.long 0x8 "PWRSW1,PWRSW Control 1"
|
|
bitfld.long 0x8 31. "SHORTVDDFVDDSORVAL,pwrsw short override value for vddf/vdds" "0,1"
|
|
newline
|
|
bitfld.long 0x8 30. "SHORTVDDFVDDSOREN,pwrsw short override select for vddf/vdds" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "SHORTVDDCVDDCLVORVAL,pwrsw short override value for vddc/vddclv" "0,1"
|
|
newline
|
|
bitfld.long 0x8 28. "SHORTVDDCVDDCLVOREN,pwrsw short override select for vddc/vddclv" "0,1"
|
|
newline
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 27. "FORCEVDDRMOFF,Setting this bit forces VDDRM to be open when Flash is off. This is valid for only normal operational mode (i.e. without overrides)." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 27. "FORCEVDDRMOFF,Setting this bit forces VDDRM to be open when Flash is off. This is valid for only normal operational mode (i.e. without overrides)." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 26. "FORCEVDDRMVDDS,Setting this bit selects VDDS for VDDRM when Flash is off. This is valid for only normal operational mode (i.e. without overrides)." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 26. "FORCEVDDRMVDDS,Setting this bit selects VDDS for VDDRM when Flash is off. This is valid for only normal operational mode (i.e. without overrides)." "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x8 25. "USEVDDF4VDDRCPUINHP,Setting this bit selects VDDF for VDDRCPU in when MCU is in HP mode. This is valid for only normal operational mode (i.e without overrides)." "0,1"
|
|
newline
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 23.--24. "DIGPWRSWOVRDRVSEL,digpwrsw_ovrdrv_sel" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 23.--24. "DIGPWRSWOVRDRVSEL,digpwrsw_ovrdrv_sel" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 22. "DIGPWRSWOVRDRVEN,digpwrsw_ovrdrv_en" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 22. "DIGPWRSWOVRDRVEN,digpwrsw_ovrdrv_en" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 21. "PWRSWOVRDRVEN,pwrsw_ovrdrv_en" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 21. "PWRSWOVRDRVEN,pwrsw_ovrdrv_en" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 20. "PWRSWCOMPPDNB,pwrsw_comp_pdnb" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 20. "PWRSWCOMPPDNB,pwrsw_comp_pdnb" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 19. "PWRSWVDDLOVERRIDE,override enable for pwrsw_vddl_pgn" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 19. "PWRSWVDDLOVERRIDE,override enable for pwrsw_vddl_pgn" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 18. "PWRSWVDDLPGN,override value for pwrsw_vddl_pgn" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 18. "PWRSWVDDLPGN,override value for pwrsw_vddl_pgn" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 17. "PWRSWVDDRMOVERRIDE,override enable for pwrsw_vddrm_dynsel and pgn" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 17. "PWRSWVDDRMOVERRIDE,override enable for pwrsw_vddrm_dynsel and pgn" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 16. "PWRSWVDDRMSTATSEL,VDDRM power switch static select" "0: Select VDDFLP rail,1: Select VDDC rail"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 16. "PWRSWVDDRMSTATSEL,VDDRM power switch static select" "0: Select VDDFLP rail,1: Select VDDC rail"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 15. "PWRSWVDDRMPGN,override value for pwrsw_vddrm_pgn" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 15. "PWRSWVDDRMPGN,override value for pwrsw_vddrm_pgn" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 14. "PWRSWVDDRMDYNSEL,override value for pwrsw_vddrm_dynsel" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 14. "PWRSWVDDRMDYNSEL,override value for pwrsw_vddrm_dynsel" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 13. "PWRSWVDDRLOVERRIDE,override enable for pwrsw_vddrl_dynsel and pgn" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 13. "PWRSWVDDRLOVERRIDE,override enable for pwrsw_vddrl_dynsel and pgn" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 12. "PWRSWVDDRLSTATSEL,VDDRL power switch static select" "0: Select VDDFLP rail,1: Select VDDC rail"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 12. "PWRSWVDDRLSTATSEL,VDDRL power switch static select" "0: Select VDDFLP rail,1: Select VDDC rail"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 11. "PWRSWVDDRLPGN,override value for pwrsw_vddrl_pgn" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 11. "PWRSWVDDRLPGN,override value for pwrsw_vddrl_pgn" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 10. "PWRSWVDDRLDYNSEL,override value for pwrsw_vddrl_dynsel" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 10. "PWRSWVDDRLDYNSEL,override value for pwrsw_vddrl_dynsel" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 9. "PWRSWVDDRDSP1OVERRIDE,override enable for pwrsw_vddrdsp1_dynsel and pgn" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 9. "PWRSWVDDRDSP1OVERRIDE,override enable for pwrsw_vddrdsp1_dynsel and pgn" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 8. "PWRSWVDDRDSP1STATSEL,VDDRDSP1 power switch static select" "0: Select VDDFLP rail,1: Select VDDC rail"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 8. "PWRSWVDDRDSP1STATSEL,VDDRDSP1 power switch static select" "0: Select VDDFLP rail,1: Select VDDC rail"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 7. "PWRSWVDDRDSP1PGN,override value for pwrsw_vddrdsp1_pgn" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 7. "PWRSWVDDRDSP1PGN,override value for pwrsw_vddrdsp1_pgn" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 5.--6. "PWRSWVDDRDSP1DYNSEL,override value for pwrsw_vddrdsp1_dynsel" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 5.--6. "PWRSWVDDRDSP1DYNSEL,override value for pwrsw_vddrdsp1_dynsel" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 4. "PWRSWVDDRDSP0OVERRIDE,override enable for pwrsw_vddrdsp0_dynsel and pgn" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 4. "PWRSWVDDRDSP0OVERRIDE,override enable for pwrsw_vddrdsp0_dynsel and pgn" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 3. "PWRSWVDDRDSP0STATSEL,VDDRDSP0 power switch static select" "0: Select VDDFLP rail,1: Select VDDC rail"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 3. "PWRSWVDDRDSP0STATSEL,VDDRDSP0 power switch static select" "0: Select VDDFLP rail,1: Select VDDC rail"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 2. "PWRSWVDDRDSP0PGN,override value for pwrsw_vddrdsp0_pgn" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 2. "PWRSWVDDRDSP0PGN,override value for pwrsw_vddrdsp0_pgn" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 0.--1. "PWRSWVDDRDSP0DYNSEL,override value for pwrsw_vddrdsp0_dynsel" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 0.--1. "PWRSWVDDRDSP0DYNSEL,override value for pwrsw_vddrdsp0_dynsel" "0,1,2,3"
|
|
endif
|
|
group.long 0x3A8++0x2F
|
|
line.long 0x0 "FLASHWPROT0,These bits write-protect flash in 16KB chunks."
|
|
hexmask.long 0x0 0.--31. 1. "FW0BITS,Write protect flash 0x00000000 - 0x0007FFFF. Each bit provides write protection for 16KB chunks of flash data space. Bits are cleared by writing a 1 to the bit. When read 0 indicates the region is protected. Bits are sticky (can be set when.."
|
|
line.long 0x4 "FLASHWPROT1,These bits write-protect flash in 16KB chunks."
|
|
hexmask.long 0x4 0.--31. 1. "FW1BITS,Write protect flash 0x00080000 - 0x000FFFFF. Each bit provides write protection for 16KB chunks of flash data space. Bits are cleared by writing a 1 to the bit. When read 0 indicates the region is protected. Bits are sticky (can be set when.."
|
|
line.long 0x8 "FLASHWPROT2,These bits write-protect flash in 16KB chunks."
|
|
hexmask.long 0x8 0.--31. 1. "FW2BITS,Write protect flash 0x00100000 - 0x0017FFFF. Each bit provides write protection for 16KB chunks of flash data space. Bits are cleared by writing a 1 to the bit. When read 0 indicates the region is protected. Bits are sticky (can be set when.."
|
|
line.long 0xC "FLASHWPROT3,These bits write-protect flash in 16KB chunks."
|
|
hexmask.long 0xC 0.--31. 1. "FW3BITS,Write protect flash 0x00180000 - 0x001FFFFF. Each bit provides write protection for 16KB chunks of flash data space. Bits are cleared by writing a 1 to the bit. When read 0 indicates the region is protected. Bits are sticky (can be set when.."
|
|
line.long 0x10 "FLASHRPROT0,These bits read-protect flash in 16KB chunks."
|
|
hexmask.long 0x10 0.--31. 1. "FR0BITS,Copy (read) protect flash 0x00000000 - 0x0007FFFF. Each bit provides read protection for 16KB chunks of flash. Bits are cleared by writing a 1 to the bit. When read 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK.."
|
|
line.long 0x14 "FLASHRPROT1,These bits read-protect flash in 16KB chunks."
|
|
hexmask.long 0x14 0.--31. 1. "FR1BITS,Copy (read) protect flash 0x00080000 - 0x000FFFFF. Each bit provides read protection for 16KB chunks of flash. Bits are cleared by writing a 1 to the bit. When read 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK.."
|
|
line.long 0x18 "FLASHRPROT2,These bits read-protect flash in 16KB chunks."
|
|
hexmask.long 0x18 0.--31. 1. "FR2BITS,Copy (read) protect flash 0x00100000 - 0x0017FFFF. Each bit provides read protection for 16KB chunks of flash. Bits are cleared by writing a 1 to the bit. When read 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK.."
|
|
line.long 0x1C "FLASHRPROT3,These bits read-protect flash in 16KB chunks."
|
|
hexmask.long 0x1C 0.--31. 1. "FR3BITS,Copy (read) protect flash 0x00180000 - 0x001FFFFF. Each bit provides read protection for 16KB chunks of flash. Bits are cleared by writing a 1 to the bit. When read 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK.."
|
|
line.long 0x20 "DMASRAMWPROT0,These bits write-protect system SRAM from DMA operations in 8KB chunks."
|
|
hexmask.long 0x20 0.--31. 1. "DMAWPROT0,Write protect SRAM from DMA. Each bit provides write protection for an 8KB region of memory. When set to 1 the region will be protected from DMA writes when set to 0 DMA may write the region."
|
|
line.long 0x24 "DMASRAMWPROT1,These bits write-protect system SRAM from DMA operations in 8KB chunks."
|
|
hexmask.long.word 0x24 0.--15. 1. "DMAWPROT1,Write protect SRAM from DMA. Each bit provides write protection for an 8KB region of memory. When set to 1 the region will be protected from DMA writes when set to 0 DMA may write the region."
|
|
line.long 0x28 "DMASRAMRPROT0,These bits read-protect system SRAM from DMA operations in 8KB chunks."
|
|
hexmask.long 0x28 0.--31. 1. "DMARPROT0,Read protect SRAM from DMA. Each bit provides write protection for an 8KB region of memory. When set to 1 the region will be protected from DMA reads when set to 0 DMA may read the region."
|
|
line.long 0x2C "DMASRAMRPROT1,These bits read-protect system SRAM from DMA operations in 8KB chunks."
|
|
hexmask.long.word 0x2C 0.--15. 1. "DMARPROT1,Read protect SRAM from DMA. Each bit provides write protection for an 8KB region of memory. When set to 1 the region will be protected from DMA reads when set to 0 DMA may read the region."
|
|
group.long 0x418++0x3
|
|
line.long 0x0 "USBPHYRESET,DSP0 CACHE RAM TRIM"
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 31. "RESERVED18,Self-timed override (test mode only)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 31. "RESERVED18,Self-timed override (test mode only)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 28.--30. "RESERVED17,DSP0 ICACHE DATA WABLM - 00=No adjust 11=increased delay enabled by WABL" "0: No adjust 11=increased delay,?,?,?,?,?,?,?"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 28.--30. "RESERVED17,DSP0 ICACHE DATA WABLM - 00=No adjust 11=increased delay enabled by WABL" "0: No adjust 11=increased delay,?,?,?,?,?,?,?"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 27. "RESERVED16,DSP0 ICACHE DATA RAM WABL - Write Assist Enable (active high)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 27. "RESERVED16,DSP0 ICACHE DATA RAM WABL - Write Assist Enable (active high)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 25.--26. "RESERVED15,DSP0 ICACHE DATA RAWLM" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 25.--26. "RESERVED15,DSP0 ICACHE DATA RAWLM" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 24. "RESERVED14,DSP0 ICACHE DATA RAWL" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 24. "RESERVED14,DSP0 ICACHE DATA RAWL" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 22.--23. "RESERVED13,DSP0 ICACHE DATA EMAW" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 22.--23. "RESERVED13,DSP0 ICACHE DATA EMAW" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 21. "RESERVED12,DSP0 ICACHE DATA EMAS" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 21. "RESERVED12,DSP0 ICACHE DATA EMAS" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 18.--20. "RESERVED11,DSP0 ICACHE DATA EMA" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 18.--20. "RESERVED11,DSP0 ICACHE DATA EMA" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 17. "RESERVED10,Override for DSP0 ICACHE DATA RET1N override enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 17. "RESERVED10,Override for DSP0 ICACHE DATA RET1N override enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 16. "RESERVED09,DSP0 ICACHE DATA RET1N value" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 16. "RESERVED09,DSP0 ICACHE DATA RET1N value" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 12.--14. "RESERVED07,DSP0 ICACHE TAG WABLM - 00=No adjust 11=increased delay enabled by WABL" "0: No adjust 11=increased delay,?,?,?,?,?,?,?"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 12.--14. "RESERVED07,DSP0 ICACHE TAG WABLM - 00=No adjust 11=increased delay enabled by WABL" "0: No adjust 11=increased delay,?,?,?,?,?,?,?"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 11. "RESERVED06,DSP0 ICACHE TAG RAM WABL - Write Assist Enable (active high)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 11. "RESERVED06,DSP0 ICACHE TAG RAM WABL - Write Assist Enable (active high)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 9.--10. "RESERVED05,DSP0 ICACHE TAG RAWLM" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 9.--10. "RESERVED05,DSP0 ICACHE TAG RAWLM" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 8. "RESERVED04,DSP0 ICACHE TAG RAWL" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 8. "RESERVED04,DSP0 ICACHE TAG RAWL" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 6.--7. "RESERVED03,DSP0 ICACHE TAG EMAW" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 6.--7. "RESERVED03,DSP0 ICACHE TAG EMAW" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 5. "RESERVED02,DSP0 ICACHE TAG EMAS" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 5. "RESERVED02,DSP0 ICACHE TAG EMAS" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 2.--4. "RESERVED01,DSP0 ICACHE TAG EMA" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 2.--4. "RESERVED01,DSP0 ICACHE TAG EMA" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 1. "USBPHYUTMIRSTDIS,De-assert USB PHY UTMI reset override" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "USBPHYPORRSTDIS,De-assert USB PHY POR reset override" "0,1"
|
|
group.long 0x42C++0x7
|
|
line.long 0x0 "AUDADCPWRCTRL,Audio ADC Power Control"
|
|
bitfld.long 0x0 18. "AUDADCKEEPOUTEN,Audio ADC reference keeper out en" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "AUDADCRFBUFSLWEN,Audio ADC reference buffer slew enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "AUDADCINBUFEN,Audio ADC Input Buffer Power Enable ( if the AUDADCPWRCTRLSWE bit is set )" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "AUDADCINBUFSEL,Audio ADC input buffer mux select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 12. "AUDADCVBATDIVEN,Audio ADC VBAT DIV Power Enable ( if the AUDADCPWRCTRLSWE bit is set )" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "VDDAUDADCRESETN,RESETN signal for Power Switched SAR and Digital Controller (when global power switch is off and if the AUDADCPWRCTRLSWE bit is set)" "0: Resetn is asserted,1: Resetn is de-asserted"
|
|
newline
|
|
bitfld.long 0x0 9. "VDDAUDADCDIGISOLATE,ISOLATE signal for audio ADC Digital Contoller ( when AUDADCAPSEN is switched off and if the AUDADCPWRCTRLSWE bit is set)" "0: No Isolation,1: Isolate"
|
|
newline
|
|
bitfld.long 0x0 8. "VDDAUDADCSARISOLATE,ISOLATE signal for Power Switched SAR ( when AUDADCBPSEN is switched off )" "0: No Isolation,1: Isolate"
|
|
newline
|
|
bitfld.long 0x0 5. "AUDREFKEEPPEN,Reference Buffer Keeper Power Switch Enable" "0: Reference Buffer Keeper Power Switch disable.,1: Reference Buffer Keeper Power Switch enable."
|
|
newline
|
|
bitfld.long 0x0 4. "AUDREFBUFPEN,Reference Buffer Power Switch Enable" "0: Reference Buffer Power Switch disable.,1: Reference Buffer Power Switch enable."
|
|
newline
|
|
bitfld.long 0x0 3. "AUDBGTPEN,Bandgap and Temperature Sensor Power Switch Enable" "0: Bandgap and temperature sensor disable.,1: Bandgap and temperature sensor enable."
|
|
newline
|
|
bitfld.long 0x0 2. "AUDADCBPSEN,Enable the Analog IO and SAR Digital logic Power Switch on when set to 1 if the AUDADCPWRCTRLSWE bit is set." "0: AUDADC power switch software power disable.,1: AUDADC power switch software power enable."
|
|
newline
|
|
bitfld.long 0x0 1. "AUDADCAPSEN,Enable the Global audio ADC Power Switch on when set to 1 if the AUDADCPWRCTRLSWE bit is set." "0: AUDADC power switch software power disable.,1: AUDADC power switch software power enable."
|
|
newline
|
|
bitfld.long 0x0 0. "AUDADCPWRCTRLSWE,Audio ADC Power Control Software Override Enable" "0: Audio ADC temperature sensor and bandgap..,1: Audio ADC temperature sensor and bandgap.."
|
|
line.long 0x4 "AUDIO1,Audio trims 1"
|
|
bitfld.long 0x4 12. "MICBIASPDNB,Power down control for the block" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 6.--11. 1. "MICBIASVOLTAGETRIM,Output voltage trim"
|
|
group.long 0x438++0xF
|
|
line.long 0x0 "PGAADCIFCTRL,PGA ADCIF control"
|
|
bitfld.long 0x0 13.--14. "PGAADCIFVCOMPSEL,Select for VCOMP output (0: A0 1: A1 2: B0 3: B1)" "0: A0,1: A1,2: B0,3: B1)"
|
|
newline
|
|
bitfld.long 0x0 12. "PGAADCIFVCOMPEN,Enable for VCOMP output" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "PGAADCIFCHBPDNB,Power down for channels B0 and B1 (0 = powered down; 1 = standby)" "0: powered down;,1: standby),?,?"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "PGAADCIFCHBACTIVE,PGAADCIF active signal for channels B0 and B1. Starts and stops 2 clocks after demultiplexed SOC signal." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "PGAADCIFCHAPDNB,Power down for channels A0 and A1 (0 = powered down; 1 = standby)" "0: powered down;,1: standby),?,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "PGAADCIFCHAACTIVE,PGAADCIF active signal for channels A0 and A1. Starts and stops 2 clocks after demultiplexed SOC signal." "0,1,2,3"
|
|
line.long 0x4 "PGACTRL1,PGA control 1"
|
|
bitfld.long 0x4 31. "PGAGAINAOVRD,Apply BYPASS and GAIN bits from this register (for channel A) instead of automatically via audio ADC. Note that audio ADC FIFO meta data will not reflect dB gain as used when configuring audio ADC." "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "VCOMPSELPGA,Select for VCOMP output (0: A0 1: A1 2: B0 3: B1)" "0: A0,1: A1"
|
|
newline
|
|
bitfld.long 0x4 28. "PGAVREFGENQUICKSTARTEN,VREFGEN quick start enable (pulsed during startup)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "PGAVREFGENPDNB,VREFGEN power down (0: powered down 1: powered up)" "0: powered down,1: powered up)"
|
|
newline
|
|
bitfld.long 0x4 26. "PGAIREFGENPDNB,IREFGEN power down (0: powered down 1: powered up)" "0: powered down,1: powered up)"
|
|
newline
|
|
bitfld.long 0x4 25. "PGACHAVCMGENQCHARGEEN,Channel A VCMGEN quick charge enable (pulsed during channel powerup)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "PGACHAVCMGENPDNB,Channel A VCMGEN power down (0: powered down 1: powered up)" "0: powered down,1: powered up)"
|
|
newline
|
|
bitfld.long 0x4 22.--23. "PGACHAOPAMPOUTPDNB,Channels A0 and A1 output stage opamp power down (0: powered down 1: powered up)" "0: powered down,1: powered up),?,?"
|
|
newline
|
|
bitfld.long 0x4 20.--21. "PGACHAOPAMPINPDNB,Channels A0 and A1 input stage opamp power down (0: powered down 1: powered up). Must be 1 when respective PGACHABYPASSEN = 0." "0: powered down,1: powered up),?,?"
|
|
newline
|
|
bitfld.long 0x4 18.--19. "PGACHABYPASSEN,Bypass enable for Channels A0 and A1 (1: bypass when gain LT 12 dB; 0: otherwise)" "0: otherwise),1: bypass,?,?"
|
|
newline
|
|
hexmask.long.byte 0x4 13.--17. 1. "PGACHA1GAIN2SEL,Channel A1 PGA gain (0: 0dB ... 23: 11.5dB in 0.5 dB steps)"
|
|
newline
|
|
bitfld.long 0x4 12. "PGACHA1GAIN2DIV2SEL,Channel A1 PGA divide by two select (0: 0 dB 1: -6dB) needed for fully differential inputs" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9.--11. "PGACHA1GAIN1SEL,Channel A1 preamp gain (0: 12dB ... 7: 33dB in 3 dB steps)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--8. 1. "PGACHA0GAIN2SEL,Channel A0 PGA gain (0: 0dB ... 23: 11.5dB in 0.5 dB steps)"
|
|
newline
|
|
bitfld.long 0x4 3. "PGACHA0GAIN2DIV2SEL,Channel A0 PGA divide by two select (0: 0 dB 1: -6dB) needed for fully differential inputs" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "PGACHA0GAIN1SEL,Channel A0 preamp gain (0: 12dB ... 7: 33dB in 3 dB steps)" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "PGACTRL2,PGA control 2"
|
|
bitfld.long 0x8 31. "PGAGAINBOVRD,Apply BYPASS and GAIN bits from this register (for channel B) instead of automatically via audio ADC. Note that audio ADC FIFO meta data will not reflect dB gain as used when configuring audio ADC." "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "PGACHBVCMGENQCHARGEEN,Channel B VCMGEN quick charge enable (pulsed during channel powerup)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 24. "PGACHBVCMGENPDNB,Channel B VCMGEN power down (0: powered down 1: powered up)" "0: powered down,1: powered up)"
|
|
newline
|
|
bitfld.long 0x8 22.--23. "PGACHBOPAMPOUTPDNB,Channels B0 and B1 output stage opamp power down (0: powered down 1: powered up)" "0: powered down,1: powered up),?,?"
|
|
newline
|
|
bitfld.long 0x8 20.--21. "PGACHBOPAMPINPDNB,Channels B0 and B1 input stage opamp power down (0: powered down 1: powered up). Must be 1 when respective PGACHBBYPASSEN = 0." "0: powered down,1: powered up),?,?"
|
|
newline
|
|
bitfld.long 0x8 18.--19. "PGACHBBYPASSEN,Bypass enable for Channels B0 and B1 (1: bypass when gain LT 12 dB; 0: otherwise)" "0: otherwise),1: bypass,?,?"
|
|
newline
|
|
hexmask.long.byte 0x8 13.--17. 1. "PGACHB1GAIN2SEL,Channel B1 PGA gain (0: 0dB ... 23: 11.5dB in 0.5 dB steps)"
|
|
newline
|
|
bitfld.long 0x8 12. "PGACHB1GAIN2DIV2SEL,Channel B1 PGA divide by two select (0: 0 dB 1: -6dB) needed for fully differential inputs" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9.--11. "PGACHB1GAIN1SEL,Channel B1 preamp gain (0: 12dB ... 7: 33dB in 3 dB steps)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--8. 1. "PGACHB0GAIN2SEL,Channel B0 PGA gain (0: 0dB ... 23: 11.5dB in 0.5 dB steps)"
|
|
newline
|
|
bitfld.long 0x8 3. "PGACHB0GAIN2DIV2SEL,Channel B0 PGA divide by two select (0: 0 dB 1: -6dB) needed for fully differential inputs" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "PGACHB0GAIN1SEL,Channel B0 preamp gain (0: 12dB ... 7: 33dB in 3 dB steps)" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "AUDADCPWRDLY,Audio ADC Power Up Delay Control"
|
|
hexmask.long.byte 0xC 8.--15. 1. "AUDADCPWR1,ADC Reference Keeper enable delay in 16 ADC CLK increments for ADC_CLKSEL = 0x1 8 ADC CLOCK increments for ADC_CLKSEL = 0x2."
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "AUDADCPWR0,ADC Reference Buffer Power Enable delay in 64 ADC CLK increments for ADC_CLKSEL = 0x1 32 ADC CLOCK increments for ADC_CLKSEL = 0x2."
|
|
group.long 0x450++0x7
|
|
line.long 0x0 "SDIOCTRL,SDIO/eMMC Control"
|
|
bitfld.long 0x0 18. "SDIODATOPENDRAINEN,SDIO DAT line configured as open-drian. 0: Push-pull mode 1: Open-drain mode" "0: Push-pull mode,1: Open-drain mode"
|
|
newline
|
|
bitfld.long 0x0 17. "SDIOCMDOPENDRAINEN,SDIO CMD line configured as open-drian. 0: Push-pull mode 1: Open-drain mode" "0: Push-pull mode,1: Open-drain mode"
|
|
newline
|
|
bitfld.long 0x0 15.--16. "SDIOXINCLKSEL,Select clock source for SDIO xin_clk." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 14. "SDIOASYNCWKUPENA,SDIO asynchronous wakeup mode. 0: Synchronous wakeup mode 1: Asynchronous wakeup mode" "0: Synchronous wakeup mode,1: Asynchronous wakeup mode"
|
|
newline
|
|
hexmask.long.byte 0x0 10.--13. 1. "SDIOOTAPDLYSEL,Selects one of the 16 Taps on the sdcard_clk. This is effective only when otapdlyena is asserted."
|
|
newline
|
|
bitfld.long 0x0 9. "SDIOOTAPDLYENA,Used to enable the selective Tap delay on the sdcard_clk so as to generate the delayed sdcard_clk. This is used to latch the CMD/DAT outputs to generate delay on them w.r.t CLK going out. This signal along with otapdlysel[3:0] selects the.." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--8. 1. "SDIOITAPDLYSEL,Selects one of the 32 Taps on the rxclk_in line. This is effective only when itapdlyena is asserted and Tuning is not enabled."
|
|
newline
|
|
bitfld.long 0x0 3. "SDIOITAPDLYENA,Used to enable selective Tap delay line on the Looped back SD Clock (rxclk_in). This signal along with the itapdlysel[4:0] selects the the amount of delay to be inserted on the line. When Tuning is enabled (for SDR104 and optionally for.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "SDIOITAPCHGWIN,This is used to gate the output of the Tap Delay lines so as to avoid glithches being propagated into the Core. This signal should be asserted few clocks before the itapdlysel changes and should be asserted for few clocks after." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SDIOXINCLKEN,SDIO serial clock source enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SDIOSYSCLKEN,SDIO system clock enable." "0,1"
|
|
line.long 0x4 "PDMCTRL,PDM Control"
|
|
bitfld.long 0x4 0. "PDMGLOBALEN,PDM global enable to allow all PDMs to have synchronized interface clocks and FIFO sampling." "0,1"
|
|
tree.end
|
|
tree "MSPI (Multi-bit SPI Master)"
|
|
base ad:0x0
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
tree "MSPI0"
|
|
base ad:0x40060000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,This register is used to enable individual PIO based transactions to a device on the bus. The CFG register must be programmed properly for the transfer. and the ADDR and INSTR registers should be programmed if the SENDI and SENDA fields are enabled."
|
|
hexmask.long.word 0x0 16.--31. 1. "XFERBYTES,Number of bytes to transmit or receive (based on TXRX bit)"
|
|
newline
|
|
bitfld.long 0x0 13.--15. "PIOMIXED,Provides override controls for data operations where instruction address and data may transfer in different rates." "0: Transfers all proceed using the settings in..,1: Data operations proceed in dual data rate,?,3: Address and Data operations proceed in dual data..,?,5: Data operations proceed in quad data rate,?,7: Address and Data operations proceed in quad data.."
|
|
newline
|
|
bitfld.long 0x0 12. "ENWLAT,Enable Write Latency Counter (time between address and first data byte). Counter value is WRITELATENCY." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "ENDCX,Enable DCX signal on data [1]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ENTURN,Indicates whether TX->RX turnaround cycles should be enabled for this operation (see TURNAROUND field in CFG register)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PIOSCRAMBLE,Enables data scrambling for PIO opertions. This should only be used for data operations and never for commands to a device." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "BIGENDIAN,1 indicates data in FIFO is in big endian format (MSB first); 0 indicates little endian data (default LSB first)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXRX,1 Indicates a TX operation 0 indicates an RX operation of XFERBYTES" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "SENDI,Indicates whether an instruction phase should be sent (see INSTR field and ISIZE field in CFG register)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SENDA,Indicates whether an address phase should be sent (see ADDR register and ASIZE field in CFG register)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PIODEV,Selects the Device configutation to use for PIO requests" "0: Use DEVICE0 Configuration,1: Use DEVICE1 CONFIGURATION"
|
|
newline
|
|
bitfld.long 0x0 2. "BUSY,Command status: 1 indicates controller is busy (command in progress)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STATUS,Command status: 1 indicates command has completed. Cleared by writing 1 to this bit or starting a new transfer." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Write to 1 to initiate a PIO transaction on the bus (typically the entire register should be written at once with this bit set)." "0,1"
|
|
group.long 0x8++0x1B
|
|
line.long 0x0 "ADDR,Optional Address field to send for PIO transfers"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Optional Address field to send (after optional instruction field) - qualified by ASIZE in CMD register. NOTE: This register is aliased to DMADEVADDR."
|
|
line.long 0x4 "INSTR,Optional Instruction field to send for PIO transfers"
|
|
hexmask.long.word 0x4 0.--15. 1. "INSTR,Optional Instruction field to send (1st byte) - qualified by ISEND/ISIZE"
|
|
line.long 0x8 "TXFIFO,TX Data FIFO"
|
|
hexmask.long 0x8 0.--31. 1. "TXFIFO,Data to be transmitted. Data should normally be aligned to the LSB (pad the upper bits with zeros) unless BIGENDIAN is set."
|
|
line.long 0xC "RXFIFO,RX Data FIFO"
|
|
hexmask.long 0xC 0.--31. 1. "RXFIFO,Receive data. Data is aligned to the LSB (padded zeros on upper bits) unless BIGENDIAN is set."
|
|
line.long 0x10 "TXENTRIES,Number of words in TX FIFO"
|
|
hexmask.long.byte 0x10 0.--5. 1. "TXENTRIES,Number of 32-bit words/entries in TX FIFO"
|
|
line.long 0x14 "RXENTRIES,Number of words in RX FIFO"
|
|
hexmask.long.byte 0x14 0.--5. 1. "RXENTRIES,Number of 32-bit words/entries in RX FIFO"
|
|
line.long 0x18 "THRESHOLD,Threshold levels that trigger RXFull and TXEmpty interrupts"
|
|
hexmask.long.byte 0x18 8.--13. 1. "RXTHRESH,Number of entries in TX FIFO that cause RXE interrupt"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--5. 1. "TXTHRESH,Number of entries in TX FIFO that cause TXF interrupt"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "MSPICFG,Timing configuration bits for the MSPI module. PRSTN. IPRSTN. and FIFORESET can be used to reset portions of the MSPI interface in order to clear error conditions. The remaining bits control clock frequency and TX/RX capture timings."
|
|
bitfld.long 0x0 31. "PRSTN,Peripheral reset. Master reset to the entire MSPI module (DMA XIP and transfer state machines). 1=normal operation 0=in reset." "0: in reset,1: normal operation"
|
|
newline
|
|
bitfld.long 0x0 30. "IPRSTN,IP block reset. Write to 0 to put the transfer module in reset or 1 for normal operation. This may be required after error conditions to clear the transfer on the bus." "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "FIFORESET,Reset MSPI FIFO (active high). 1=reset FIFO 0=normal operation. May be used to manually flush the FIFO in error handling." "0: normal operation,1: reset FIFO"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "IOMSEL,Selects which IOM is selected for CQ handshake status."
|
|
newline
|
|
bitfld.long 0x0 0. "APBCLK,Enable continuous APB clock. For power-efficient operation APBCLK should be set to 0." "0: Disable continuous clock.,1: Enable continuous clock."
|
|
group.long 0x44++0xB
|
|
line.long 0x0 "PADOUTEN,Enable bits for the MSPI output pads. Each active MSPI line should be set to 1 in the OUTEN field below."
|
|
bitfld.long 0x0 12. "CLKOND4,Output clock on MSPI data[4]" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--9. 1. "OUTEN,Output pad enable configuration. Indicates which pads should be driven. Bits [3:0] are Quad0 data [7:4] are Quad1 data and [8] is clock."
|
|
line.long 0x4 "PADOVEREN,Enables PIO-like pad override control"
|
|
hexmask.long.word 0x4 0.--9. 1. "OVERRIDEEN,Output pad override enable. Bit mask for pad outputs. When set to 1 the values in the OVERRIDE field are driven on the pad (output enable is implicitly set in this mode). [7:0]=data [8]=clock [9]=DM"
|
|
line.long 0x8 "PADOVER,Override data value"
|
|
hexmask.long.word 0x8 0.--9. 1. "OVERRIDE,Output pad override value. [7:0]=data [8]=clock [9]=DM"
|
|
group.long 0x80++0xB
|
|
line.long 0x0 "DEV0AXI,Specifies the base address and aperture range of the device as mapped onto the AXI bus"
|
|
hexmask.long.word 0x0 16.--25. 1. "BASE0,XIPEN has to be enabled to enable aperture"
|
|
newline
|
|
bitfld.long 0x0 4. "READONLY0,Indicates the AXI aperture is read-only" "0: Indicates AXI aperture supports read and write..,1: Indicates AXI aperture only supports read.."
|
|
newline
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hexmask.long.byte 0x0 0.--3. 1. "SIZE0,Indicates the AXI aperture size"
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line.long 0x4 "DEV0CFG,Command formatting for PIO based transactions (initiated by writes to CTRL register)"
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hexmask.long.byte 0x4 26.--31. 1. "WRITELATENCY0,Number of write Latency cycles. Qualified by ENTURN bit field."
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bitfld.long 0x4 24. "TXNEG0,Launches TX data a half clock cycle (~10ns) early. This should normally be programmed to zero (NORMAL)." "0: TX launched from posedge internal clock,1: TX data launched from negedge of internal clock"
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bitfld.long 0x4 23. "RXNEG0,Adjusts the RX capture phase to the negedge of the 48MHz internal clock (~10ns early). For normal operation it is expected that RXNEG will be set to 0." "0: RX data sampled on posedge of internal clock,1: RX data sampled on negedge of internal clock"
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bitfld.long 0x4 22. "RXCAP0,Controls RX data capture phase. A setting of 0 (NORMAL) captures read data at the normal capture point relative to the internal clock launch point. However to accomodate chip/pad/board delays a setting of RXCAP of 1 is expected to be used to.." "0: RX Capture phase aligns with CPHA setting,1: RX Capture phase is delayed from CPHA setting by.."
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hexmask.long.byte 0x4 16.--21. 1. "CLKDIV0,Clock Divider. Allows dividing 96 MHz base clock by integer multiples. Enumerations are provided for common frequency but any integer divide from 96 MHz is allowed. Odd divide ratios will result in a 33/66 percent duty cycle with a long low.."
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bitfld.long 0x4 15. "CPOL0,Serial clock polarity." "0: Clock inactive state is low.,1: Clock inactive state is high."
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bitfld.long 0x4 14. "CPHA0,Serial clock phase." "0: Clock toggles in middle of data bit.,1: Clock toggles at start of data bit."
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hexmask.long.byte 0x4 8.--13. 1. "TURNAROUND0,Number of turnaound cycles (for TX->RX transitions). Qualified by ENTURN bit field."
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bitfld.long 0x4 7. "SEPIO0,Separate IO configuration. This bit should be set when the target device has separate MOSI and MISO pins. Respective IN/OUT bits below should be set to map pins." "0,1"
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bitfld.long 0x4 6. "ISIZE0,Instruction Size" "0: Instruction is 1 byte,1: Instruction is 2 bytes"
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bitfld.long 0x4 4.--5. "ASIZE0,Address Size. Address bytes to send from ADDR register" "0: Send one address byte,1: Send two address bytes,2: Send three address bytes,3: Send four address bytes"
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hexmask.long.byte 0x4 0.--3. 1. "DEVCFG0,Flash configuration for XIP and AUTO DMA operations. Controls value for SER (Slave Enable) for XIP operations and address generation for DMA/XIP modes. Also used to configure SPIFRF (frame format)."
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line.long 0x8 "DEV0DDR,Timing configuration bits for DDR operation of the MSPI module."
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hexmask.long.byte 0x8 16.--20. 1. "TXDQSDELAY0,When OVERRIDEDQSDELAY is set this sets the DQS delay line value. In ENABLEDQS mode this acts as an offset to the computed value (should be set to 0 by default)"
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hexmask.long.byte 0x8 8.--12. 1. "RXDQSDELAY0,When OVERRIDEDQSDELAY is set this sets the DQS delay line value. In ENABLEDQS mode this acts as an offset to the computed value (should be set to 0 by default)"
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bitfld.long 0x8 6. "ENABLEFINEDELAY0,Enables use of delay line to provide fine control over traditional RX capture clock." "0,1"
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bitfld.long 0x8 5. "OVERRIDEDDRCLKOUTDELAY0,Override TX delay line with the value in DQSDELAY (for TX clock offset when in QUADDDR mode)" "0,1"
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bitfld.long 0x8 4. "OVERRIDERXDQSDELAY0,Override DQS delay line with the value in DQSDELAY (for RX capture in QUADDDR mode)" "0,1"
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bitfld.long 0x8 3. "DQSSYNCNEG0,Use negative edge of clock for DDR data sync" "0,1"
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bitfld.long 0x8 2. "ENABLEDQS0,In EMULATEDDR mode enable DQS for read capture" "0,1"
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bitfld.long 0x8 1. "QUADDDR0,Enables use of delay line to provide fine control over traditional RX capture clock." "0,1"
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bitfld.long 0x8 0. "EMULATEDDR0,Drive external clock at 1/2 rate to emulate DDR mode" "0,1"
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group.long 0x90++0x13
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line.long 0x0 "DEV0XIP,When any SPI flash is configured. this register must be properly programmed before XIP or AUTO DMA operations commence."
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hexmask.long.byte 0x0 19.--24. 1. "XIPWRITELATENCY0,Number of write Latency cycles. Qualified by XIPENWLAT bit field."
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hexmask.long.byte 0x0 13.--18. 1. "XIPTURNAROUND0,Number of turnaound cycles (for TX->RX transitions). Qualified by XIPENTURN bit field."
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bitfld.long 0x0 12. "XIPENWLAT0,Enable Write Latency counter for XIP write transactions" "0,1"
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bitfld.long 0x0 11. "XIPENDCX0,Enable DCX signal on data [1] for XIP/DMA operations" "0,1"
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bitfld.long 0x0 8.--10. "XIPMIXED0,Provides override controls for data operations where instruction address and data may transfer in different rates." "0: Transfers all proceed using the settings in..,1: Data operations proceed in dual data rate,?,3: Address and Data operations proceed in dual data..,?,5: Data operations proceed in quad data rate,?,7: Address and Data operations proceed in quad data.."
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bitfld.long 0x0 7. "XIPSENDI0,Indicates whether XIP/AUTO DMA operations should send an instruction (see READINSTR field and ISIZE field in CFG)" "0,1"
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bitfld.long 0x0 6. "XIPSENDA0,Indicates whether XIP/AUTO DMA operations should send an an address phase (see DMADEVADDR register and ASIZE field in CFG)" "0,1"
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bitfld.long 0x0 5. "XIPENTURN0,Indicates whether XIP/AUTO DMA operations should enable TX->RX turnaround cycles" "0,1"
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bitfld.long 0x0 4. "XIPBIGENDIAN0,Indicates whether XIP/AUTO DMA data transfers are in big or little endian format" "0,1"
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bitfld.long 0x0 2.--3. "XIPACK0,Controls transmission of Micron XIP acknowledge cycles (Micron Flash devices only)" "0: No acknowledege sent. Data IOs are tristated the..,?,2: Positive acknowledege sent. Data IOs are driven..,3: Negative acknowledege sent. Data IOs are driven.."
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bitfld.long 0x0 0. "XIPEN0,Enable the XIP (eXecute In Place) function which effectively enables the address decoding of the MSPI device in the flash/cache address space at address 0x04000000-0x07FFFFFF." "0,1"
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line.long 0x4 "DEV0INSTR,When any SPI flash is configured. this register must be properly programmed before XIP or AUTO DMA operations commence."
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hexmask.long.word 0x4 16.--31. 1. "READINSTR0,Read command sent to flash for DMA/XIP operations"
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hexmask.long.word 0x4 0.--15. 1. "WRITEINSTR0,Write command sent for DMA operations"
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line.long 0x8 "DEV0BOUNDARY,Allows large transfers to be broken up into smaller ones in hardware to accommodate needs of external devices and allow XIP/XIPMM. Only applicable for memory-mapped devices (PSRAM. Flash. etc) where address can be retransmitted without side.."
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hexmask.long.byte 0x8 12.--15. 1. "DMABOUND0,DMA Address boundary"
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hexmask.long.word 0x8 0.--11. 1. "DMATIMELIMIT0,DMA time limit. Can be used to limit the transaction time on the MSPI bus. The count is in 50 ns increments for the 96 MHz clock input on rev B silicon (100 ns increments for the 48 MHz clock on rev A). A value of 0 disables the counter."
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line.long 0xC "DEV0SCRAMBLING,Enables data scrambling for the specified range external flash addresses. Scrambling does not impact flash access performance."
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bitfld.long 0xC 31. "SCRENABLE0,Enables Data Scrambling Region. When 1 reads and writes to the range will be scrambled. When 0 data will be read/written unmodified. Address range is specified in 64K granularity and the START/END ranges are included within the range." "0,1"
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hexmask.long.word 0xC 16.--25. 1. "SCREND0,Scrambling region end address [25:16] (64K block granularity). The END block is the LAST block included in the scrambled address range."
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hexmask.long.word 0xC 0.--9. 1. "SCRSTART0,Scrambling region start address [25:16] (64K block granularity). The START block is the FIRST block included in the scrambled address range."
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line.long 0x10 "DEV0XIPMISC,Miscellaneous XIP control registers for AXI logic"
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bitfld.long 0x10 21. "APNDODD0,Append dummy byte to odd number of write" "0: No appending byte,1: Append one dummy byte"
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hexmask.long.byte 0x10 16.--20. 1. "AFIFOLVL0,AFIFOLVL0 register description needed."
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bitfld.long 0x10 15. "XIPBOUNDARY0,Control DMAxBOUNDARY to AXI" "0: ERROR: desc VALUE MISSING,1: ERROR: desc VALUE MISSING"
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bitfld.long 0x10 14. "BEON0,Byte enable always on for all lanes" "0: Byte enable is calculated on the fly,1: Byte enable of all bytes are always on"
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bitfld.long 0x10 13. "BEPOL0,byte mask polarity to MSPI xfer" "0,1"
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bitfld.long 0x10 12. "XIPODD0,Convert odd starting address to even starting address with bytemask" "0: No conversion,1: Enable the conversion"
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hexmask.long.word 0x10 0.--11. 1. "CEBREAK0,CEBREAK0 field description needed."
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group.long 0x100++0x1B
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line.long 0x0 "DMACFG,DMA Configuration"
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bitfld.long 0x0 18. "DMAPWROFF,Power off MSPI domain upon completion of DMA operation." "0,1"
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bitfld.long 0x0 4.--5. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately),2: Auto Priority (priority raised once TX FIFO..,?"
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bitfld.long 0x0 3. "DMADEV,DMA Device Select" "0: Select Device 0 for DMA,?"
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bitfld.long 0x0 2. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction,1: Memory to Peripheral transaction"
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bitfld.long 0x0 0.--1. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation" "0: Disable DMA Function,?,?,3: Enable HW controlled DMA Function to manage DMA.."
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line.long 0x4 "DMASTAT,DMA Status"
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bitfld.long 0x4 3. "SCRERR,Scrambling Access Alignment Error. This active high bit signals that a scrambling operation was specified for a non-word aligned DEVADDR." "0,1"
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bitfld.long 0x4 2. "DMAERR,DMA Error. This active high bit signals that an error was encountered during the DMA operation." "0,1"
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bitfld.long 0x4 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation." "0,1"
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bitfld.long 0x4 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority. All of these will be indicated with a 1. A 0 will indicate that the DMA is.." "0,1"
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line.long 0x8 "DMATARGADDR,DMA Target Address"
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hexmask.long 0x8 0.--31. 1. "TARGADDR,Target byte address for source of DMA (either read or write). In cases of non-word aligned addresses the DMA logic will take care for ensuring only the target bytes are read/written."
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line.long 0xC "DMADEVADDR,DMA Device Address"
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hexmask.long 0xC 0.--31. 1. "DEVADDR,SPI Device address for automated DMA transactions (both read and write)."
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line.long 0x10 "DMATOTCOUNT,DMA Total Transfer Count"
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hexmask.long.tbyte 0x10 0.--23. 1. "TOTCOUNT,Total Transfer Count in bytes."
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line.long 0x14 "DMABCOUNT,DMA BYTE Transfer Count"
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hexmask.long.byte 0x14 0.--7. 1. "BCOUNT,Burst transfer size in bytes. This is the number of bytes transferred when a FIFO trigger event occurs. Recommended value is 32."
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line.long 0x18 "DMATHRESH,Indicates FIFO level at which a DMA should be triggered. For most configurations. a setting of 8 is recommended for both read and write operations."
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hexmask.long.byte 0x18 8.--12. 1. "DMARXTHRESH,DMA transfer FIFO level trigger. For read operations DMA is triggered when the FIFO level is greater than this value. For write operations DMA is triggered when the FIFO level is less than this level. Each DMA operation will consist of.."
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hexmask.long.byte 0x18 0.--4. 1. "DMATXTHRESH,DMA transfer FIFO level trigger. For read operations DMA is triggered when the FIFO level is greater than this value. For write operations DMA is triggered when the FIFO level is less than this level. Each DMA operation will consist of.."
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group.long 0x200++0xF
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line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
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bitfld.long 0x0 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
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bitfld.long 0x0 11. "CQERR,Command Queue Error Interrupt" "0,1"
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bitfld.long 0x0 10. "CQPAUSED,Command Queue is Paused." "0,1"
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bitfld.long 0x0 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
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bitfld.long 0x0 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
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bitfld.long 0x0 7. "DERR,DMA Error Interrupt" "0,1"
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bitfld.long 0x0 6. "DCMP,DMA Complete Interrupt" "0,1"
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bitfld.long 0x0 5. "RXF,Receive FIFO full" "0,1"
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bitfld.long 0x0 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
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bitfld.long 0x0 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
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bitfld.long 0x0 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
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bitfld.long 0x0 1. "TXE,Transmit FIFO empty." "0,1"
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bitfld.long 0x0 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
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line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
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bitfld.long 0x4 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
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bitfld.long 0x4 11. "CQERR,Command Queue Error Interrupt" "0,1"
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bitfld.long 0x4 10. "CQPAUSED,Command Queue is Paused." "0,1"
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bitfld.long 0x4 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
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bitfld.long 0x4 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
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bitfld.long 0x4 7. "DERR,DMA Error Interrupt" "0,1"
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bitfld.long 0x4 6. "DCMP,DMA Complete Interrupt" "0,1"
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bitfld.long 0x4 5. "RXF,Receive FIFO full" "0,1"
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bitfld.long 0x4 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
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bitfld.long 0x4 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
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bitfld.long 0x4 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
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bitfld.long 0x4 1. "TXE,Transmit FIFO empty." "0,1"
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bitfld.long 0x4 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
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line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
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bitfld.long 0x8 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
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bitfld.long 0x8 11. "CQERR,Command Queue Error Interrupt" "0,1"
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bitfld.long 0x8 10. "CQPAUSED,Command Queue is Paused." "0,1"
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bitfld.long 0x8 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
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bitfld.long 0x8 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
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bitfld.long 0x8 7. "DERR,DMA Error Interrupt" "0,1"
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bitfld.long 0x8 6. "DCMP,DMA Complete Interrupt" "0,1"
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bitfld.long 0x8 5. "RXF,Receive FIFO full" "0,1"
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bitfld.long 0x8 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
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bitfld.long 0x8 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
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bitfld.long 0x8 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
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bitfld.long 0x8 1. "TXE,Transmit FIFO empty." "0,1"
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bitfld.long 0x8 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
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line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
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bitfld.long 0xC 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
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bitfld.long 0xC 11. "CQERR,Command Queue Error Interrupt" "0,1"
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bitfld.long 0xC 10. "CQPAUSED,Command Queue is Paused." "0,1"
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bitfld.long 0xC 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
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bitfld.long 0xC 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
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bitfld.long 0xC 7. "DERR,DMA Error Interrupt" "0,1"
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bitfld.long 0xC 6. "DCMP,DMA Complete Interrupt" "0,1"
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bitfld.long 0xC 5. "RXF,Receive FIFO full" "0,1"
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bitfld.long 0xC 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
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bitfld.long 0xC 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
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bitfld.long 0xC 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
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bitfld.long 0xC 1. "TXE,Transmit FIFO empty." "0,1"
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bitfld.long 0xC 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
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group.long 0x2A0++0x3
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line.long 0x0 "CQCFG,This register controls Command Queuing (CQ) operations in a manner similar to the DMACFG register."
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bitfld.long 0x0 3. "CQAUTOCLEARMASK,Enable clear of CQMASK after each pause operation. This may be useful when using software flags to pause CQ." "0,1"
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bitfld.long 0x0 2. "CQPWROFF,Power off MSPI domain upon completion of DMA operation." "0,1"
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bitfld.long 0x0 1. "CQPRI,Sets the Priority of the command queue DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x0 0. "CQEN,Command queue enable. When set will enable the processing of the command queue" "0: Disable CQ Function,1: Enable CQ Function"
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group.long 0x2A8++0x13
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line.long 0x0 "CQADDR,Location of the command queue in SRAM or flash memory. This register will increment as CQ operations commence. Software should only write CQADDR when CQEN is disabled. however the command queue script itself may update CQADDR in order to perform.."
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hexmask.long 0x0 0.--28. 1. "CQADDR,Address of command queue buffer in SRAM or flash. The buffer address must be aligned to a word boundary."
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line.long 0x4 "CQSTAT,Command Queue Status"
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bitfld.long 0x4 3. "CQPAUSED,Command queue is currently paused status." "0,1"
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bitfld.long 0x4 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
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bitfld.long 0x4 1. "CQCPL,Command queue operation Complete. This signals the end of the command queue operation." "0,1"
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bitfld.long 0x4 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
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line.long 0x8 "CQFLAGS,Command Queue Flags"
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hexmask.long.word 0x8 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
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line.long 0xC "CQSETCLEAR,Command Queue Flag Set/Clear"
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hexmask.long.byte 0xC 16.--23. 1. "CQFCLR,Clear CQFlag status bits."
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hexmask.long.byte 0xC 8.--15. 1. "CQFTOGGLE,Toggle CQFlag status bits"
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|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CQFSET,Set CQFlag status bits. Set has priority over clear if both are high."
|
|
line.long 0x10 "CQPAUSE,Command Queue Pause Mask"
|
|
hexmask.long.word 0x10 0.--15. 1. "CQMASK,CQ will pause processing when ALL specified events are satisfied -- i.e. when (CQMASK and CQPAUSE)==CQMASK."
|
|
group.long 0x2C0++0x7
|
|
line.long 0x0 "CQCURIDX,This register can be used in conjunction with the CQENDIDX register to manage the command queue. Typically software will initialize the CQCURIDX and CQENDIDX to the same value. which will cause the CQ to be paused when enabled. Software may then.."
|
|
hexmask.long.byte 0x0 0.--7. 1. "CQCURIDX,Can be used to indicate the current position of the command queue by having CQ operations write this field. A CQ hardware status flag indicates when CURIDX and ENDIDX are not equal allowing SW to pause the CQ processing until the end index is.."
|
|
line.long 0x4 "CQENDIDX,Command Queue End Index"
|
|
hexmask.long.byte 0x4 0.--7. 1. "CQENDIDX,Can be used to indicate the end position of the command queue. A CQ hardware status bit indices when CURIDX != ENDIDX so that the CQ can be paused when it reaches the end pointer."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
tree "MSPI1"
|
|
base ad:0x40061000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,This register is used to enable individual PIO based transactions to a device on the bus. The CFG register must be programmed properly for the transfer. and the ADDR and INSTR registers should be programmed if the SENDI and SENDA fields are enabled."
|
|
hexmask.long.word 0x0 16.--31. 1. "XFERBYTES,Number of bytes to transmit or receive (based on TXRX bit)"
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|
newline
|
|
bitfld.long 0x0 13.--15. "PIOMIXED,Provides override controls for data operations where instruction address and data may transfer in different rates." "0: Transfers all proceed using the settings in..,1: Data operations proceed in dual data rate,?,3: Address and Data operations proceed in dual data..,?,5: Data operations proceed in quad data rate,?,7: Address and Data operations proceed in quad data.."
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|
newline
|
|
bitfld.long 0x0 12. "ENWLAT,Enable Write Latency Counter (time between address and first data byte). Counter value is WRITELATENCY." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "ENDCX,Enable DCX signal on data [1]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ENTURN,Indicates whether TX->RX turnaround cycles should be enabled for this operation (see TURNAROUND field in CFG register)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PIOSCRAMBLE,Enables data scrambling for PIO opertions. This should only be used for data operations and never for commands to a device." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "BIGENDIAN,1 indicates data in FIFO is in big endian format (MSB first); 0 indicates little endian data (default LSB first)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXRX,1 Indicates a TX operation 0 indicates an RX operation of XFERBYTES" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "SENDI,Indicates whether an instruction phase should be sent (see INSTR field and ISIZE field in CFG register)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SENDA,Indicates whether an address phase should be sent (see ADDR register and ASIZE field in CFG register)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PIODEV,Selects the Device configutation to use for PIO requests" "0: Use DEVICE0 Configuration,1: Use DEVICE1 CONFIGURATION"
|
|
newline
|
|
bitfld.long 0x0 2. "BUSY,Command status: 1 indicates controller is busy (command in progress)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STATUS,Command status: 1 indicates command has completed. Cleared by writing 1 to this bit or starting a new transfer." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Write to 1 to initiate a PIO transaction on the bus (typically the entire register should be written at once with this bit set)." "0,1"
|
|
group.long 0x8++0x1B
|
|
line.long 0x0 "ADDR,Optional Address field to send for PIO transfers"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Optional Address field to send (after optional instruction field) - qualified by ASIZE in CMD register. NOTE: This register is aliased to DMADEVADDR."
|
|
line.long 0x4 "INSTR,Optional Instruction field to send for PIO transfers"
|
|
hexmask.long.word 0x4 0.--15. 1. "INSTR,Optional Instruction field to send (1st byte) - qualified by ISEND/ISIZE"
|
|
line.long 0x8 "TXFIFO,TX Data FIFO"
|
|
hexmask.long 0x8 0.--31. 1. "TXFIFO,Data to be transmitted. Data should normally be aligned to the LSB (pad the upper bits with zeros) unless BIGENDIAN is set."
|
|
line.long 0xC "RXFIFO,RX Data FIFO"
|
|
hexmask.long 0xC 0.--31. 1. "RXFIFO,Receive data. Data is aligned to the LSB (padded zeros on upper bits) unless BIGENDIAN is set."
|
|
line.long 0x10 "TXENTRIES,Number of words in TX FIFO"
|
|
hexmask.long.byte 0x10 0.--5. 1. "TXENTRIES,Number of 32-bit words/entries in TX FIFO"
|
|
line.long 0x14 "RXENTRIES,Number of words in RX FIFO"
|
|
hexmask.long.byte 0x14 0.--5. 1. "RXENTRIES,Number of 32-bit words/entries in RX FIFO"
|
|
line.long 0x18 "THRESHOLD,Threshold levels that trigger RXFull and TXEmpty interrupts"
|
|
hexmask.long.byte 0x18 8.--13. 1. "RXTHRESH,Number of entries in TX FIFO that cause RXE interrupt"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--5. 1. "TXTHRESH,Number of entries in TX FIFO that cause TXF interrupt"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "MSPICFG,Timing configuration bits for the MSPI module. PRSTN. IPRSTN. and FIFORESET can be used to reset portions of the MSPI interface in order to clear error conditions. The remaining bits control clock frequency and TX/RX capture timings."
|
|
bitfld.long 0x0 31. "PRSTN,Peripheral reset. Master reset to the entire MSPI module (DMA XIP and transfer state machines). 1=normal operation 0=in reset." "0: in reset,1: normal operation"
|
|
newline
|
|
bitfld.long 0x0 30. "IPRSTN,IP block reset. Write to 0 to put the transfer module in reset or 1 for normal operation. This may be required after error conditions to clear the transfer on the bus." "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "FIFORESET,Reset MSPI FIFO (active high). 1=reset FIFO 0=normal operation. May be used to manually flush the FIFO in error handling." "0: normal operation,1: reset FIFO"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "IOMSEL,Selects which IOM is selected for CQ handshake status."
|
|
newline
|
|
bitfld.long 0x0 0. "APBCLK,Enable continuous APB clock. For power-efficient operation APBCLK should be set to 0." "0: Disable continuous clock.,1: Enable continuous clock."
|
|
group.long 0x44++0xB
|
|
line.long 0x0 "PADOUTEN,Enable bits for the MSPI output pads. Each active MSPI line should be set to 1 in the OUTEN field below."
|
|
bitfld.long 0x0 12. "CLKOND4,Output clock on MSPI data[4]" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--9. 1. "OUTEN,Output pad enable configuration. Indicates which pads should be driven. Bits [3:0] are Quad0 data [7:4] are Quad1 data and [8] is clock."
|
|
line.long 0x4 "PADOVEREN,Enables PIO-like pad override control"
|
|
hexmask.long.word 0x4 0.--9. 1. "OVERRIDEEN,Output pad override enable. Bit mask for pad outputs. When set to 1 the values in the OVERRIDE field are driven on the pad (output enable is implicitly set in this mode). [7:0]=data [8]=clock [9]=DM"
|
|
line.long 0x8 "PADOVER,Override data value"
|
|
hexmask.long.word 0x8 0.--9. 1. "OVERRIDE,Output pad override value. [7:0]=data [8]=clock [9]=DM"
|
|
group.long 0x80++0xB
|
|
line.long 0x0 "DEV0AXI,Specifies the base address and aperture range of the device as mapped onto the AXI bus"
|
|
hexmask.long.word 0x0 16.--25. 1. "BASE0,XIPEN has to be enabled to enable aperture"
|
|
newline
|
|
bitfld.long 0x0 4. "READONLY0,Indicates the AXI aperture is read-only" "0: Indicates AXI aperture supports read and write..,1: Indicates AXI aperture only supports read.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SIZE0,Indicates the AXI aperture size"
|
|
line.long 0x4 "DEV0CFG,Command formatting for PIO based transactions (initiated by writes to CTRL register)"
|
|
hexmask.long.byte 0x4 26.--31. 1. "WRITELATENCY0,Number of write Latency cycles. Qualified by ENTURN bit field."
|
|
newline
|
|
bitfld.long 0x4 24. "TXNEG0,Launches TX data a half clock cycle (~10ns) early. This should normally be programmed to zero (NORMAL)." "0: TX launched from posedge internal clock,1: TX data launched from negedge of internal clock"
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|
newline
|
|
bitfld.long 0x4 23. "RXNEG0,Adjusts the RX capture phase to the negedge of the 48MHz internal clock (~10ns early). For normal operation it is expected that RXNEG will be set to 0." "0: RX data sampled on posedge of internal clock,1: RX data sampled on negedge of internal clock"
|
|
newline
|
|
bitfld.long 0x4 22. "RXCAP0,Controls RX data capture phase. A setting of 0 (NORMAL) captures read data at the normal capture point relative to the internal clock launch point. However to accomodate chip/pad/board delays a setting of RXCAP of 1 is expected to be used to.." "0: RX Capture phase aligns with CPHA setting,1: RX Capture phase is delayed from CPHA setting by.."
|
|
newline
|
|
hexmask.long.byte 0x4 16.--21. 1. "CLKDIV0,Clock Divider. Allows dividing 96 MHz base clock by integer multiples. Enumerations are provided for common frequency but any integer divide from 96 MHz is allowed. Odd divide ratios will result in a 33/66 percent duty cycle with a long low.."
|
|
newline
|
|
bitfld.long 0x4 15. "CPOL0,Serial clock polarity." "0: Clock inactive state is low.,1: Clock inactive state is high."
|
|
newline
|
|
bitfld.long 0x4 14. "CPHA0,Serial clock phase." "0: Clock toggles in middle of data bit.,1: Clock toggles at start of data bit."
|
|
newline
|
|
hexmask.long.byte 0x4 8.--13. 1. "TURNAROUND0,Number of turnaound cycles (for TX->RX transitions). Qualified by ENTURN bit field."
|
|
newline
|
|
bitfld.long 0x4 7. "SEPIO0,Separate IO configuration. This bit should be set when the target device has separate MOSI and MISO pins. Respective IN/OUT bits below should be set to map pins." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "ISIZE0,Instruction Size" "0: Instruction is 1 byte,1: Instruction is 2 bytes"
|
|
newline
|
|
bitfld.long 0x4 4.--5. "ASIZE0,Address Size. Address bytes to send from ADDR register" "0: Send one address byte,1: Send two address bytes,2: Send three address bytes,3: Send four address bytes"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DEVCFG0,Flash configuration for XIP and AUTO DMA operations. Controls value for SER (Slave Enable) for XIP operations and address generation for DMA/XIP modes. Also used to configure SPIFRF (frame format)."
|
|
line.long 0x8 "DEV0DDR,Timing configuration bits for DDR operation of the MSPI module."
|
|
hexmask.long.byte 0x8 16.--20. 1. "TXDQSDELAY0,When OVERRIDEDQSDELAY is set this sets the DQS delay line value. In ENABLEDQS mode this acts as an offset to the computed value (should be set to 0 by default)"
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|
newline
|
|
hexmask.long.byte 0x8 8.--12. 1. "RXDQSDELAY0,When OVERRIDEDQSDELAY is set this sets the DQS delay line value. In ENABLEDQS mode this acts as an offset to the computed value (should be set to 0 by default)"
|
|
newline
|
|
bitfld.long 0x8 6. "ENABLEFINEDELAY0,Enables use of delay line to provide fine control over traditional RX capture clock." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERRIDEDDRCLKOUTDELAY0,Override TX delay line with the value in DQSDELAY (for TX clock offset when in QUADDDR mode)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "OVERRIDERXDQSDELAY0,Override DQS delay line with the value in DQSDELAY (for RX capture in QUADDDR mode)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "DQSSYNCNEG0,Use negative edge of clock for DDR data sync" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ENABLEDQS0,In EMULATEDDR mode enable DQS for read capture" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "QUADDDR0,Enables use of delay line to provide fine control over traditional RX capture clock." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "EMULATEDDR0,Drive external clock at 1/2 rate to emulate DDR mode" "0,1"
|
|
group.long 0x90++0x13
|
|
line.long 0x0 "DEV0XIP,When any SPI flash is configured. this register must be properly programmed before XIP or AUTO DMA operations commence."
|
|
hexmask.long.byte 0x0 19.--24. 1. "XIPWRITELATENCY0,Number of write Latency cycles. Qualified by XIPENWLAT bit field."
|
|
newline
|
|
hexmask.long.byte 0x0 13.--18. 1. "XIPTURNAROUND0,Number of turnaound cycles (for TX->RX transitions). Qualified by XIPENTURN bit field."
|
|
newline
|
|
bitfld.long 0x0 12. "XIPENWLAT0,Enable Write Latency counter for XIP write transactions" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "XIPENDCX0,Enable DCX signal on data [1] for XIP/DMA operations" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "XIPMIXED0,Provides override controls for data operations where instruction address and data may transfer in different rates." "0: Transfers all proceed using the settings in..,1: Data operations proceed in dual data rate,?,3: Address and Data operations proceed in dual data..,?,5: Data operations proceed in quad data rate,?,7: Address and Data operations proceed in quad data.."
|
|
newline
|
|
bitfld.long 0x0 7. "XIPSENDI0,Indicates whether XIP/AUTO DMA operations should send an instruction (see READINSTR field and ISIZE field in CFG)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "XIPSENDA0,Indicates whether XIP/AUTO DMA operations should send an an address phase (see DMADEVADDR register and ASIZE field in CFG)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "XIPENTURN0,Indicates whether XIP/AUTO DMA operations should enable TX->RX turnaround cycles" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "XIPBIGENDIAN0,Indicates whether XIP/AUTO DMA data transfers are in big or little endian format" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "XIPACK0,Controls transmission of Micron XIP acknowledge cycles (Micron Flash devices only)" "0: No acknowledege sent. Data IOs are tristated the..,?,2: Positive acknowledege sent. Data IOs are driven..,3: Negative acknowledege sent. Data IOs are driven.."
|
|
newline
|
|
bitfld.long 0x0 0. "XIPEN0,Enable the XIP (eXecute In Place) function which effectively enables the address decoding of the MSPI device in the flash/cache address space at address 0x04000000-0x07FFFFFF." "0,1"
|
|
line.long 0x4 "DEV0INSTR,When any SPI flash is configured. this register must be properly programmed before XIP or AUTO DMA operations commence."
|
|
hexmask.long.word 0x4 16.--31. 1. "READINSTR0,Read command sent to flash for DMA/XIP operations"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "WRITEINSTR0,Write command sent for DMA operations"
|
|
line.long 0x8 "DEV0BOUNDARY,Allows large transfers to be broken up into smaller ones in hardware to accommodate needs of external devices and allow XIP/XIPMM. Only applicable for memory-mapped devices (PSRAM. Flash. etc) where address can be retransmitted without side.."
|
|
hexmask.long.byte 0x8 12.--15. 1. "DMABOUND0,DMA Address boundary"
|
|
newline
|
|
hexmask.long.word 0x8 0.--11. 1. "DMATIMELIMIT0,DMA time limit. Can be used to limit the transaction time on the MSPI bus. The count is in 50 ns increments for the 96 MHz clock input on rev B silicon (100 ns increments for the 48 MHz clock on rev A). A value of 0 disables the counter."
|
|
line.long 0xC "DEV0SCRAMBLING,Enables data scrambling for the specified range external flash addresses. Scrambling does not impact flash access performance."
|
|
bitfld.long 0xC 31. "SCRENABLE0,Enables Data Scrambling Region. When 1 reads and writes to the range will be scrambled. When 0 data will be read/written unmodified. Address range is specified in 64K granularity and the START/END ranges are included within the range." "0,1"
|
|
newline
|
|
hexmask.long.word 0xC 16.--25. 1. "SCREND0,Scrambling region end address [25:16] (64K block granularity). The END block is the LAST block included in the scrambled address range."
|
|
newline
|
|
hexmask.long.word 0xC 0.--9. 1. "SCRSTART0,Scrambling region start address [25:16] (64K block granularity). The START block is the FIRST block included in the scrambled address range."
|
|
line.long 0x10 "DEV0XIPMISC,Miscellaneous XIP control registers for AXI logic"
|
|
bitfld.long 0x10 21. "APNDODD0,Append dummy byte to odd number of write" "0: No appending byte,1: Append one dummy byte"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--20. 1. "AFIFOLVL0,AFIFOLVL0 register description needed."
|
|
newline
|
|
bitfld.long 0x10 15. "XIPBOUNDARY0,Control DMAxBOUNDARY to AXI" "0: ERROR: desc VALUE MISSING,1: ERROR: desc VALUE MISSING"
|
|
newline
|
|
bitfld.long 0x10 14. "BEON0,Byte enable always on for all lanes" "0: Byte enable is calculated on the fly,1: Byte enable of all bytes are always on"
|
|
newline
|
|
bitfld.long 0x10 13. "BEPOL0,byte mask polarity to MSPI xfer" "0,1"
|
|
newline
|
|
bitfld.long 0x10 12. "XIPODD0,Convert odd starting address to even starting address with bytemask" "0: No conversion,1: Enable the conversion"
|
|
newline
|
|
hexmask.long.word 0x10 0.--11. 1. "CEBREAK0,CEBREAK0 field description needed."
|
|
group.long 0x100++0x1B
|
|
line.long 0x0 "DMACFG,DMA Configuration"
|
|
bitfld.long 0x0 18. "DMAPWROFF,Power off MSPI domain upon completion of DMA operation." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately),2: Auto Priority (priority raised once TX FIFO..,?"
|
|
newline
|
|
bitfld.long 0x0 3. "DMADEV,DMA Device Select" "0: Select Device 0 for DMA,?"
|
|
newline
|
|
bitfld.long 0x0 2. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction,1: Memory to Peripheral transaction"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation" "0: Disable DMA Function,?,?,3: Enable HW controlled DMA Function to manage DMA.."
|
|
line.long 0x4 "DMASTAT,DMA Status"
|
|
bitfld.long 0x4 3. "SCRERR,Scrambling Access Alignment Error. This active high bit signals that a scrambling operation was specified for a non-word aligned DEVADDR." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DMAERR,DMA Error. This active high bit signals that an error was encountered during the DMA operation." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority. All of these will be indicated with a 1. A 0 will indicate that the DMA is.." "0,1"
|
|
line.long 0x8 "DMATARGADDR,DMA Target Address"
|
|
hexmask.long 0x8 0.--31. 1. "TARGADDR,Target byte address for source of DMA (either read or write). In cases of non-word aligned addresses the DMA logic will take care for ensuring only the target bytes are read/written."
|
|
line.long 0xC "DMADEVADDR,DMA Device Address"
|
|
hexmask.long 0xC 0.--31. 1. "DEVADDR,SPI Device address for automated DMA transactions (both read and write)."
|
|
line.long 0x10 "DMATOTCOUNT,DMA Total Transfer Count"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "TOTCOUNT,Total Transfer Count in bytes."
|
|
line.long 0x14 "DMABCOUNT,DMA BYTE Transfer Count"
|
|
hexmask.long.byte 0x14 0.--7. 1. "BCOUNT,Burst transfer size in bytes. This is the number of bytes transferred when a FIFO trigger event occurs. Recommended value is 32."
|
|
line.long 0x18 "DMATHRESH,Indicates FIFO level at which a DMA should be triggered. For most configurations. a setting of 8 is recommended for both read and write operations."
|
|
hexmask.long.byte 0x18 8.--12. 1. "DMARXTHRESH,DMA transfer FIFO level trigger. For read operations DMA is triggered when the FIFO level is greater than this value. For write operations DMA is triggered when the FIFO level is less than this level. Each DMA operation will consist of.."
|
|
newline
|
|
hexmask.long.byte 0x18 0.--4. 1. "DMATXTHRESH,DMA transfer FIFO level trigger. For read operations DMA is triggered when the FIFO level is greater than this value. For write operations DMA is triggered when the FIFO level is less than this level. Each DMA operation will consist of.."
|
|
group.long 0x200++0xF
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CQERR,Command Queue Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "CQPAUSED,Command Queue is Paused." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "DERR,DMA Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "DCMP,DMA Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXF,Receive FIFO full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXE,Transmit FIFO empty." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CQERR,Command Queue Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "CQPAUSED,Command Queue is Paused." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "DERR,DMA Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "DCMP,DMA Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXF,Receive FIFO full" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXE,Transmit FIFO empty." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "CQERR,Command Queue Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "CQPAUSED,Command Queue is Paused." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "DERR,DMA Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "DCMP,DMA Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "RXF,Receive FIFO full" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "TXE,Transmit FIFO empty." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "CQERR,Command Queue Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "CQPAUSED,Command Queue is Paused." "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "DERR,DMA Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "DCMP,DMA Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "RXF,Receive FIFO full" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
|
|
newline
|
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bitfld.long 0xC 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "TXE,Transmit FIFO empty." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
|
|
group.long 0x2A0++0x3
|
|
line.long 0x0 "CQCFG,This register controls Command Queuing (CQ) operations in a manner similar to the DMACFG register."
|
|
bitfld.long 0x0 3. "CQAUTOCLEARMASK,Enable clear of CQMASK after each pause operation. This may be useful when using software flags to pause CQ." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CQPWROFF,Power off MSPI domain upon completion of DMA operation." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CQPRI,Sets the Priority of the command queue DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
|
|
newline
|
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bitfld.long 0x0 0. "CQEN,Command queue enable. When set will enable the processing of the command queue" "0: Disable CQ Function,1: Enable CQ Function"
|
|
group.long 0x2A8++0x13
|
|
line.long 0x0 "CQADDR,Location of the command queue in SRAM or flash memory. This register will increment as CQ operations commence. Software should only write CQADDR when CQEN is disabled. however the command queue script itself may update CQADDR in order to perform.."
|
|
hexmask.long 0x0 0.--28. 1. "CQADDR,Address of command queue buffer in SRAM or flash. The buffer address must be aligned to a word boundary."
|
|
line.long 0x4 "CQSTAT,Command Queue Status"
|
|
bitfld.long 0x4 3. "CQPAUSED,Command queue is currently paused status." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CQCPL,Command queue operation Complete. This signals the end of the command queue operation." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
|
|
line.long 0x8 "CQFLAGS,Command Queue Flags"
|
|
hexmask.long.word 0x8 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
|
|
line.long 0xC "CQSETCLEAR,Command Queue Flag Set/Clear"
|
|
hexmask.long.byte 0xC 16.--23. 1. "CQFCLR,Clear CQFlag status bits."
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "CQFTOGGLE,Toggle CQFlag status bits"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CQFSET,Set CQFlag status bits. Set has priority over clear if both are high."
|
|
line.long 0x10 "CQPAUSE,Command Queue Pause Mask"
|
|
hexmask.long.word 0x10 0.--15. 1. "CQMASK,CQ will pause processing when ALL specified events are satisfied -- i.e. when (CQMASK and CQPAUSE)==CQMASK."
|
|
group.long 0x2C0++0x7
|
|
line.long 0x0 "CQCURIDX,This register can be used in conjunction with the CQENDIDX register to manage the command queue. Typically software will initialize the CQCURIDX and CQENDIDX to the same value. which will cause the CQ to be paused when enabled. Software may then.."
|
|
hexmask.long.byte 0x0 0.--7. 1. "CQCURIDX,Can be used to indicate the current position of the command queue by having CQ operations write this field. A CQ hardware status flag indicates when CURIDX and ENDIDX are not equal allowing SW to pause the CQ processing until the end index is.."
|
|
line.long 0x4 "CQENDIDX,Command Queue End Index"
|
|
hexmask.long.byte 0x4 0.--7. 1. "CQENDIDX,Can be used to indicate the end position of the command queue. A CQ hardware status bit indices when CURIDX != ENDIDX so that the CQ can be paused when it reaches the end pointer."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
tree "MSPI2"
|
|
base ad:0x40062000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,This register is used to enable individual PIO based transactions to a device on the bus. The CFG register must be programmed properly for the transfer. and the ADDR and INSTR registers should be programmed if the SENDI and SENDA fields are enabled."
|
|
hexmask.long.word 0x0 16.--31. 1. "XFERBYTES,Number of bytes to transmit or receive (based on TXRX bit)"
|
|
newline
|
|
bitfld.long 0x0 13.--15. "PIOMIXED,Provides override controls for data operations where instruction address and data may transfer in different rates." "0: Transfers all proceed using the settings in..,1: Data operations proceed in dual data rate,?,3: Address and Data operations proceed in dual data..,?,5: Data operations proceed in quad data rate,?,7: Address and Data operations proceed in quad data.."
|
|
newline
|
|
bitfld.long 0x0 12. "ENWLAT,Enable Write Latency Counter (time between address and first data byte). Counter value is WRITELATENCY." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "ENDCX,Enable DCX signal on data [1]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ENTURN,Indicates whether TX->RX turnaround cycles should be enabled for this operation (see TURNAROUND field in CFG register)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PIOSCRAMBLE,Enables data scrambling for PIO opertions. This should only be used for data operations and never for commands to a device." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "BIGENDIAN,1 indicates data in FIFO is in big endian format (MSB first); 0 indicates little endian data (default LSB first)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXRX,1 Indicates a TX operation 0 indicates an RX operation of XFERBYTES" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "SENDI,Indicates whether an instruction phase should be sent (see INSTR field and ISIZE field in CFG register)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SENDA,Indicates whether an address phase should be sent (see ADDR register and ASIZE field in CFG register)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PIODEV,Selects the Device configutation to use for PIO requests" "0: Use DEVICE0 Configuration,1: Use DEVICE1 CONFIGURATION"
|
|
newline
|
|
bitfld.long 0x0 2. "BUSY,Command status: 1 indicates controller is busy (command in progress)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STATUS,Command status: 1 indicates command has completed. Cleared by writing 1 to this bit or starting a new transfer." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Write to 1 to initiate a PIO transaction on the bus (typically the entire register should be written at once with this bit set)." "0,1"
|
|
group.long 0x8++0x1B
|
|
line.long 0x0 "ADDR,Optional Address field to send for PIO transfers"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Optional Address field to send (after optional instruction field) - qualified by ASIZE in CMD register. NOTE: This register is aliased to DMADEVADDR."
|
|
line.long 0x4 "INSTR,Optional Instruction field to send for PIO transfers"
|
|
hexmask.long.word 0x4 0.--15. 1. "INSTR,Optional Instruction field to send (1st byte) - qualified by ISEND/ISIZE"
|
|
line.long 0x8 "TXFIFO,TX Data FIFO"
|
|
hexmask.long 0x8 0.--31. 1. "TXFIFO,Data to be transmitted. Data should normally be aligned to the LSB (pad the upper bits with zeros) unless BIGENDIAN is set."
|
|
line.long 0xC "RXFIFO,RX Data FIFO"
|
|
hexmask.long 0xC 0.--31. 1. "RXFIFO,Receive data. Data is aligned to the LSB (padded zeros on upper bits) unless BIGENDIAN is set."
|
|
line.long 0x10 "TXENTRIES,Number of words in TX FIFO"
|
|
hexmask.long.byte 0x10 0.--5. 1. "TXENTRIES,Number of 32-bit words/entries in TX FIFO"
|
|
line.long 0x14 "RXENTRIES,Number of words in RX FIFO"
|
|
hexmask.long.byte 0x14 0.--5. 1. "RXENTRIES,Number of 32-bit words/entries in RX FIFO"
|
|
line.long 0x18 "THRESHOLD,Threshold levels that trigger RXFull and TXEmpty interrupts"
|
|
hexmask.long.byte 0x18 8.--13. 1. "RXTHRESH,Number of entries in TX FIFO that cause RXE interrupt"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--5. 1. "TXTHRESH,Number of entries in TX FIFO that cause TXF interrupt"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "MSPICFG,Timing configuration bits for the MSPI module. PRSTN. IPRSTN. and FIFORESET can be used to reset portions of the MSPI interface in order to clear error conditions. The remaining bits control clock frequency and TX/RX capture timings."
|
|
bitfld.long 0x0 31. "PRSTN,Peripheral reset. Master reset to the entire MSPI module (DMA XIP and transfer state machines). 1=normal operation 0=in reset." "0: in reset,1: normal operation"
|
|
newline
|
|
bitfld.long 0x0 30. "IPRSTN,IP block reset. Write to 0 to put the transfer module in reset or 1 for normal operation. This may be required after error conditions to clear the transfer on the bus." "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "FIFORESET,Reset MSPI FIFO (active high). 1=reset FIFO 0=normal operation. May be used to manually flush the FIFO in error handling." "0: normal operation,1: reset FIFO"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "IOMSEL,Selects which IOM is selected for CQ handshake status."
|
|
newline
|
|
bitfld.long 0x0 0. "APBCLK,Enable continuous APB clock. For power-efficient operation APBCLK should be set to 0." "0: Disable continuous clock.,1: Enable continuous clock."
|
|
group.long 0x44++0xB
|
|
line.long 0x0 "PADOUTEN,Enable bits for the MSPI output pads. Each active MSPI line should be set to 1 in the OUTEN field below."
|
|
bitfld.long 0x0 12. "CLKOND4,Output clock on MSPI data[4]" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--9. 1. "OUTEN,Output pad enable configuration. Indicates which pads should be driven. Bits [3:0] are Quad0 data [7:4] are Quad1 data and [8] is clock."
|
|
line.long 0x4 "PADOVEREN,Enables PIO-like pad override control"
|
|
hexmask.long.word 0x4 0.--9. 1. "OVERRIDEEN,Output pad override enable. Bit mask for pad outputs. When set to 1 the values in the OVERRIDE field are driven on the pad (output enable is implicitly set in this mode). [7:0]=data [8]=clock [9]=DM"
|
|
line.long 0x8 "PADOVER,Override data value"
|
|
hexmask.long.word 0x8 0.--9. 1. "OVERRIDE,Output pad override value. [7:0]=data [8]=clock [9]=DM"
|
|
group.long 0x80++0xB
|
|
line.long 0x0 "DEV0AXI,Specifies the base address and aperture range of the device as mapped onto the AXI bus"
|
|
hexmask.long.word 0x0 16.--25. 1. "BASE0,XIPEN has to be enabled to enable aperture"
|
|
newline
|
|
bitfld.long 0x0 4. "READONLY0,Indicates the AXI aperture is read-only" "0: Indicates AXI aperture supports read and write..,1: Indicates AXI aperture only supports read.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SIZE0,Indicates the AXI aperture size"
|
|
line.long 0x4 "DEV0CFG,Command formatting for PIO based transactions (initiated by writes to CTRL register)"
|
|
hexmask.long.byte 0x4 26.--31. 1. "WRITELATENCY0,Number of write Latency cycles. Qualified by ENTURN bit field."
|
|
newline
|
|
bitfld.long 0x4 24. "TXNEG0,Launches TX data a half clock cycle (~10ns) early. This should normally be programmed to zero (NORMAL)." "0: TX launched from posedge internal clock,1: TX data launched from negedge of internal clock"
|
|
newline
|
|
bitfld.long 0x4 23. "RXNEG0,Adjusts the RX capture phase to the negedge of the 48MHz internal clock (~10ns early). For normal operation it is expected that RXNEG will be set to 0." "0: RX data sampled on posedge of internal clock,1: RX data sampled on negedge of internal clock"
|
|
newline
|
|
bitfld.long 0x4 22. "RXCAP0,Controls RX data capture phase. A setting of 0 (NORMAL) captures read data at the normal capture point relative to the internal clock launch point. However to accomodate chip/pad/board delays a setting of RXCAP of 1 is expected to be used to.." "0: RX Capture phase aligns with CPHA setting,1: RX Capture phase is delayed from CPHA setting by.."
|
|
newline
|
|
hexmask.long.byte 0x4 16.--21. 1. "CLKDIV0,Clock Divider. Allows dividing 96 MHz base clock by integer multiples. Enumerations are provided for common frequency but any integer divide from 96 MHz is allowed. Odd divide ratios will result in a 33/66 percent duty cycle with a long low.."
|
|
newline
|
|
bitfld.long 0x4 15. "CPOL0,Serial clock polarity." "0: Clock inactive state is low.,1: Clock inactive state is high."
|
|
newline
|
|
bitfld.long 0x4 14. "CPHA0,Serial clock phase." "0: Clock toggles in middle of data bit.,1: Clock toggles at start of data bit."
|
|
newline
|
|
hexmask.long.byte 0x4 8.--13. 1. "TURNAROUND0,Number of turnaound cycles (for TX->RX transitions). Qualified by ENTURN bit field."
|
|
newline
|
|
bitfld.long 0x4 7. "SEPIO0,Separate IO configuration. This bit should be set when the target device has separate MOSI and MISO pins. Respective IN/OUT bits below should be set to map pins." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "ISIZE0,Instruction Size" "0: Instruction is 1 byte,1: Instruction is 2 bytes"
|
|
newline
|
|
bitfld.long 0x4 4.--5. "ASIZE0,Address Size. Address bytes to send from ADDR register" "0: Send one address byte,1: Send two address bytes,2: Send three address bytes,3: Send four address bytes"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DEVCFG0,Flash configuration for XIP and AUTO DMA operations. Controls value for SER (Slave Enable) for XIP operations and address generation for DMA/XIP modes. Also used to configure SPIFRF (frame format)."
|
|
line.long 0x8 "DEV0DDR,Timing configuration bits for DDR operation of the MSPI module."
|
|
hexmask.long.byte 0x8 16.--20. 1. "TXDQSDELAY0,When OVERRIDEDQSDELAY is set this sets the DQS delay line value. In ENABLEDQS mode this acts as an offset to the computed value (should be set to 0 by default)"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--12. 1. "RXDQSDELAY0,When OVERRIDEDQSDELAY is set this sets the DQS delay line value. In ENABLEDQS mode this acts as an offset to the computed value (should be set to 0 by default)"
|
|
newline
|
|
bitfld.long 0x8 6. "ENABLEFINEDELAY0,Enables use of delay line to provide fine control over traditional RX capture clock." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERRIDEDDRCLKOUTDELAY0,Override TX delay line with the value in DQSDELAY (for TX clock offset when in QUADDDR mode)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "OVERRIDERXDQSDELAY0,Override DQS delay line with the value in DQSDELAY (for RX capture in QUADDDR mode)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "DQSSYNCNEG0,Use negative edge of clock for DDR data sync" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ENABLEDQS0,In EMULATEDDR mode enable DQS for read capture" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "QUADDDR0,Enables use of delay line to provide fine control over traditional RX capture clock." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "EMULATEDDR0,Drive external clock at 1/2 rate to emulate DDR mode" "0,1"
|
|
group.long 0x90++0x13
|
|
line.long 0x0 "DEV0XIP,When any SPI flash is configured. this register must be properly programmed before XIP or AUTO DMA operations commence."
|
|
hexmask.long.byte 0x0 19.--24. 1. "XIPWRITELATENCY0,Number of write Latency cycles. Qualified by XIPENWLAT bit field."
|
|
newline
|
|
hexmask.long.byte 0x0 13.--18. 1. "XIPTURNAROUND0,Number of turnaound cycles (for TX->RX transitions). Qualified by XIPENTURN bit field."
|
|
newline
|
|
bitfld.long 0x0 12. "XIPENWLAT0,Enable Write Latency counter for XIP write transactions" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "XIPENDCX0,Enable DCX signal on data [1] for XIP/DMA operations" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "XIPMIXED0,Provides override controls for data operations where instruction address and data may transfer in different rates." "0: Transfers all proceed using the settings in..,1: Data operations proceed in dual data rate,?,3: Address and Data operations proceed in dual data..,?,5: Data operations proceed in quad data rate,?,7: Address and Data operations proceed in quad data.."
|
|
newline
|
|
bitfld.long 0x0 7. "XIPSENDI0,Indicates whether XIP/AUTO DMA operations should send an instruction (see READINSTR field and ISIZE field in CFG)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "XIPSENDA0,Indicates whether XIP/AUTO DMA operations should send an an address phase (see DMADEVADDR register and ASIZE field in CFG)" "0,1"
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|
newline
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bitfld.long 0x0 5. "XIPENTURN0,Indicates whether XIP/AUTO DMA operations should enable TX->RX turnaround cycles" "0,1"
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bitfld.long 0x0 4. "XIPBIGENDIAN0,Indicates whether XIP/AUTO DMA data transfers are in big or little endian format" "0,1"
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|
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bitfld.long 0x0 2.--3. "XIPACK0,Controls transmission of Micron XIP acknowledge cycles (Micron Flash devices only)" "0: No acknowledege sent. Data IOs are tristated the..,?,2: Positive acknowledege sent. Data IOs are driven..,3: Negative acknowledege sent. Data IOs are driven.."
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newline
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bitfld.long 0x0 0. "XIPEN0,Enable the XIP (eXecute In Place) function which effectively enables the address decoding of the MSPI device in the flash/cache address space at address 0x04000000-0x07FFFFFF." "0,1"
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|
line.long 0x4 "DEV0INSTR,When any SPI flash is configured. this register must be properly programmed before XIP or AUTO DMA operations commence."
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|
hexmask.long.word 0x4 16.--31. 1. "READINSTR0,Read command sent to flash for DMA/XIP operations"
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|
newline
|
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hexmask.long.word 0x4 0.--15. 1. "WRITEINSTR0,Write command sent for DMA operations"
|
|
line.long 0x8 "DEV0BOUNDARY,Allows large transfers to be broken up into smaller ones in hardware to accommodate needs of external devices and allow XIP/XIPMM. Only applicable for memory-mapped devices (PSRAM. Flash. etc) where address can be retransmitted without side.."
|
|
hexmask.long.byte 0x8 12.--15. 1. "DMABOUND0,DMA Address boundary"
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|
newline
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hexmask.long.word 0x8 0.--11. 1. "DMATIMELIMIT0,DMA time limit. Can be used to limit the transaction time on the MSPI bus. The count is in 50 ns increments for the 96 MHz clock input on rev B silicon (100 ns increments for the 48 MHz clock on rev A). A value of 0 disables the counter."
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|
line.long 0xC "DEV0SCRAMBLING,Enables data scrambling for the specified range external flash addresses. Scrambling does not impact flash access performance."
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bitfld.long 0xC 31. "SCRENABLE0,Enables Data Scrambling Region. When 1 reads and writes to the range will be scrambled. When 0 data will be read/written unmodified. Address range is specified in 64K granularity and the START/END ranges are included within the range." "0,1"
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|
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hexmask.long.word 0xC 16.--25. 1. "SCREND0,Scrambling region end address [25:16] (64K block granularity). The END block is the LAST block included in the scrambled address range."
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|
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hexmask.long.word 0xC 0.--9. 1. "SCRSTART0,Scrambling region start address [25:16] (64K block granularity). The START block is the FIRST block included in the scrambled address range."
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|
line.long 0x10 "DEV0XIPMISC,Miscellaneous XIP control registers for AXI logic"
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bitfld.long 0x10 21. "APNDODD0,Append dummy byte to odd number of write" "0: No appending byte,1: Append one dummy byte"
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|
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hexmask.long.byte 0x10 16.--20. 1. "AFIFOLVL0,AFIFOLVL0 register description needed."
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|
newline
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bitfld.long 0x10 15. "XIPBOUNDARY0,Control DMAxBOUNDARY to AXI" "0: ERROR: desc VALUE MISSING,1: ERROR: desc VALUE MISSING"
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|
newline
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bitfld.long 0x10 14. "BEON0,Byte enable always on for all lanes" "0: Byte enable is calculated on the fly,1: Byte enable of all bytes are always on"
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|
newline
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bitfld.long 0x10 13. "BEPOL0,byte mask polarity to MSPI xfer" "0,1"
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|
newline
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bitfld.long 0x10 12. "XIPODD0,Convert odd starting address to even starting address with bytemask" "0: No conversion,1: Enable the conversion"
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|
newline
|
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hexmask.long.word 0x10 0.--11. 1. "CEBREAK0,CEBREAK0 field description needed."
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|
group.long 0x100++0x1B
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|
line.long 0x0 "DMACFG,DMA Configuration"
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|
bitfld.long 0x0 18. "DMAPWROFF,Power off MSPI domain upon completion of DMA operation." "0,1"
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newline
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bitfld.long 0x0 4.--5. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately),2: Auto Priority (priority raised once TX FIFO..,?"
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newline
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bitfld.long 0x0 3. "DMADEV,DMA Device Select" "0: Select Device 0 for DMA,?"
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newline
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bitfld.long 0x0 2. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction,1: Memory to Peripheral transaction"
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newline
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bitfld.long 0x0 0.--1. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation" "0: Disable DMA Function,?,?,3: Enable HW controlled DMA Function to manage DMA.."
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line.long 0x4 "DMASTAT,DMA Status"
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bitfld.long 0x4 3. "SCRERR,Scrambling Access Alignment Error. This active high bit signals that a scrambling operation was specified for a non-word aligned DEVADDR." "0,1"
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newline
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bitfld.long 0x4 2. "DMAERR,DMA Error. This active high bit signals that an error was encountered during the DMA operation." "0,1"
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newline
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bitfld.long 0x4 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation." "0,1"
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|
newline
|
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bitfld.long 0x4 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority. All of these will be indicated with a 1. A 0 will indicate that the DMA is.." "0,1"
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line.long 0x8 "DMATARGADDR,DMA Target Address"
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hexmask.long 0x8 0.--31. 1. "TARGADDR,Target byte address for source of DMA (either read or write). In cases of non-word aligned addresses the DMA logic will take care for ensuring only the target bytes are read/written."
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line.long 0xC "DMADEVADDR,DMA Device Address"
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hexmask.long 0xC 0.--31. 1. "DEVADDR,SPI Device address for automated DMA transactions (both read and write)."
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line.long 0x10 "DMATOTCOUNT,DMA Total Transfer Count"
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hexmask.long.tbyte 0x10 0.--23. 1. "TOTCOUNT,Total Transfer Count in bytes."
|
|
line.long 0x14 "DMABCOUNT,DMA BYTE Transfer Count"
|
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hexmask.long.byte 0x14 0.--7. 1. "BCOUNT,Burst transfer size in bytes. This is the number of bytes transferred when a FIFO trigger event occurs. Recommended value is 32."
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line.long 0x18 "DMATHRESH,Indicates FIFO level at which a DMA should be triggered. For most configurations. a setting of 8 is recommended for both read and write operations."
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hexmask.long.byte 0x18 8.--12. 1. "DMARXTHRESH,DMA transfer FIFO level trigger. For read operations DMA is triggered when the FIFO level is greater than this value. For write operations DMA is triggered when the FIFO level is less than this level. Each DMA operation will consist of.."
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|
newline
|
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hexmask.long.byte 0x18 0.--4. 1. "DMATXTHRESH,DMA transfer FIFO level trigger. For read operations DMA is triggered when the FIFO level is greater than this value. For write operations DMA is triggered when the FIFO level is less than this level. Each DMA operation will consist of.."
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|
group.long 0x200++0xF
|
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line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
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bitfld.long 0x0 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
|
|
newline
|
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bitfld.long 0x0 11. "CQERR,Command Queue Error Interrupt" "0,1"
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|
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bitfld.long 0x0 10. "CQPAUSED,Command Queue is Paused." "0,1"
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|
newline
|
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bitfld.long 0x0 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
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newline
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bitfld.long 0x0 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
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newline
|
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bitfld.long 0x0 7. "DERR,DMA Error Interrupt" "0,1"
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|
newline
|
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bitfld.long 0x0 6. "DCMP,DMA Complete Interrupt" "0,1"
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|
newline
|
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bitfld.long 0x0 5. "RXF,Receive FIFO full" "0,1"
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|
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|
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bitfld.long 0x0 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
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|
newline
|
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bitfld.long 0x0 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
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|
newline
|
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bitfld.long 0x0 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
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|
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bitfld.long 0x0 1. "TXE,Transmit FIFO empty." "0,1"
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bitfld.long 0x0 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
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line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
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bitfld.long 0x4 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
|
|
newline
|
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bitfld.long 0x4 11. "CQERR,Command Queue Error Interrupt" "0,1"
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|
newline
|
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bitfld.long 0x4 10. "CQPAUSED,Command Queue is Paused." "0,1"
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newline
|
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bitfld.long 0x4 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
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newline
|
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bitfld.long 0x4 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
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|
newline
|
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bitfld.long 0x4 7. "DERR,DMA Error Interrupt" "0,1"
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|
newline
|
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bitfld.long 0x4 6. "DCMP,DMA Complete Interrupt" "0,1"
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newline
|
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bitfld.long 0x4 5. "RXF,Receive FIFO full" "0,1"
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|
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bitfld.long 0x4 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
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|
newline
|
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bitfld.long 0x4 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
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|
newline
|
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bitfld.long 0x4 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
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|
newline
|
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bitfld.long 0x4 1. "TXE,Transmit FIFO empty." "0,1"
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|
newline
|
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bitfld.long 0x4 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
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line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
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bitfld.long 0x8 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
|
|
newline
|
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bitfld.long 0x8 11. "CQERR,Command Queue Error Interrupt" "0,1"
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|
newline
|
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bitfld.long 0x8 10. "CQPAUSED,Command Queue is Paused." "0,1"
|
|
newline
|
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bitfld.long 0x8 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
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|
newline
|
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bitfld.long 0x8 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
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|
newline
|
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bitfld.long 0x8 7. "DERR,DMA Error Interrupt" "0,1"
|
|
newline
|
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bitfld.long 0x8 6. "DCMP,DMA Complete Interrupt" "0,1"
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|
newline
|
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bitfld.long 0x8 5. "RXF,Receive FIFO full" "0,1"
|
|
newline
|
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bitfld.long 0x8 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
|
|
newline
|
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bitfld.long 0x8 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
|
|
newline
|
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bitfld.long 0x8 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
|
|
newline
|
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bitfld.long 0x8 1. "TXE,Transmit FIFO empty." "0,1"
|
|
newline
|
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bitfld.long 0x8 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "CQERR,Command Queue Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "CQPAUSED,Command Queue is Paused." "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "DERR,DMA Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "DCMP,DMA Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "RXF,Receive FIFO full" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "TXE,Transmit FIFO empty." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
|
|
group.long 0x2A0++0x3
|
|
line.long 0x0 "CQCFG,This register controls Command Queuing (CQ) operations in a manner similar to the DMACFG register."
|
|
bitfld.long 0x0 3. "CQAUTOCLEARMASK,Enable clear of CQMASK after each pause operation. This may be useful when using software flags to pause CQ." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CQPWROFF,Power off MSPI domain upon completion of DMA operation." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CQPRI,Sets the Priority of the command queue DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
|
|
newline
|
|
bitfld.long 0x0 0. "CQEN,Command queue enable. When set will enable the processing of the command queue" "0: Disable CQ Function,1: Enable CQ Function"
|
|
group.long 0x2A8++0x13
|
|
line.long 0x0 "CQADDR,Location of the command queue in SRAM or flash memory. This register will increment as CQ operations commence. Software should only write CQADDR when CQEN is disabled. however the command queue script itself may update CQADDR in order to perform.."
|
|
hexmask.long 0x0 0.--28. 1. "CQADDR,Address of command queue buffer in SRAM or flash. The buffer address must be aligned to a word boundary."
|
|
line.long 0x4 "CQSTAT,Command Queue Status"
|
|
bitfld.long 0x4 3. "CQPAUSED,Command queue is currently paused status." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CQCPL,Command queue operation Complete. This signals the end of the command queue operation." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
|
|
line.long 0x8 "CQFLAGS,Command Queue Flags"
|
|
hexmask.long.word 0x8 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
|
|
line.long 0xC "CQSETCLEAR,Command Queue Flag Set/Clear"
|
|
hexmask.long.byte 0xC 16.--23. 1. "CQFCLR,Clear CQFlag status bits."
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "CQFTOGGLE,Toggle CQFlag status bits"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CQFSET,Set CQFlag status bits. Set has priority over clear if both are high."
|
|
line.long 0x10 "CQPAUSE,Command Queue Pause Mask"
|
|
hexmask.long.word 0x10 0.--15. 1. "CQMASK,CQ will pause processing when ALL specified events are satisfied -- i.e. when (CQMASK and CQPAUSE)==CQMASK."
|
|
group.long 0x2C0++0x7
|
|
line.long 0x0 "CQCURIDX,This register can be used in conjunction with the CQENDIDX register to manage the command queue. Typically software will initialize the CQCURIDX and CQENDIDX to the same value. which will cause the CQ to be paused when enabled. Software may then.."
|
|
hexmask.long.byte 0x0 0.--7. 1. "CQCURIDX,Can be used to indicate the current position of the command queue by having CQ operations write this field. A CQ hardware status flag indicates when CURIDX and ENDIDX are not equal allowing SW to pause the CQ processing until the end index is.."
|
|
line.long 0x4 "CQENDIDX,Command Queue End Index"
|
|
hexmask.long.byte 0x4 0.--7. 1. "CQENDIDX,Can be used to indicate the end position of the command queue. A CQ hardware status bit indices when CURIDX != ENDIDX so that the CQ can be paused when it reaches the end pointer."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
tree "MSPI0"
|
|
base ad:0x40060000
|
|
group.long 0x0++0x23
|
|
line.long 0x0 "CTRL,This register is used to enable individual PIO based transactions to a device on the bus. The CFG register must be programmed properly for the transfer. and the ADDR and INSTR registers should be programmed if the SENDI and SENDA fields are enabled."
|
|
hexmask.long.word 0x0 16.--31. 1. "XFERBYTES,Number of bytes to transmit or receive (based on TXRX bit)"
|
|
newline
|
|
bitfld.long 0x0 12. "ENWLAT,Enable Write Latency Counter (time between address and first data byte). Counter value is WRITELATENCY." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "ENDCX,Enable DCX signal on data [1]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ENTURN,Indicates whether TX->RX turnaround cycles should be enabled for this operation (see TURNAROUND field in CFG register)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PIOSCRAMBLE,Enables data scrambling for PIO opertions. This should only be used for data operations and never for commands to a device." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "BIGENDIAN,1 indicates data in FIFO is in big endian format (MSB first); 0 indicates little endian data (default LSB first)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXRX,1 Indicates a TX operation 0 indicates an RX operation of XFERBYTES" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "SENDI,Indicates whether an instruction phase should be sent (see INSTR field and ISIZE field in CFG register)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SENDA,Indicates whether an address phase should be sent (see ADDR register and ASIZE field in CFG register)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PIODEV,Selects the Device configutation to use for PIO requests" "0: Use DEVICE0 Configuration,1: Use DEVICE1 CONFIGURATION"
|
|
newline
|
|
bitfld.long 0x0 2. "BUSY,Command status: 1 indicates controller is busy (command in progress)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STATUS,Command status: 1 indicates command has completed. Cleared by writing 1 to this bit or starting a new transfer." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Write to 1 to initiate a PIO transaction on the bus (typically the entire register should be written at once with this bit set)." "0,1"
|
|
line.long 0x4 "CTRL1,These registers are used to enable individual PIO based transactions to a device on the bus. The CFG register must be programmed properly for the transfer. and the ADDR and INSTR registers should be programmed if the SENDI and SENDA fields are.."
|
|
hexmask.long.byte 0x4 0.--3. 1. "PIOMIXED,Provides override controls for data operations where instruction address and data may transfer in different rates."
|
|
line.long 0x8 "ADDR,Optional Address field to send for PIO transfers"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,Optional Address field to send (after optional instruction field) - qualified by ASIZE in CMD register. NOTE: This register is aliased to DMADEVADDR."
|
|
line.long 0xC "INSTR,Optional Instruction field to send for PIO transfers"
|
|
hexmask.long.word 0xC 0.--15. 1. "INSTR,Optional Instruction field to send (1st byte) - qualified by ISEND/ISIZE"
|
|
line.long 0x10 "TXFIFO,TX Data FIFO"
|
|
hexmask.long 0x10 0.--31. 1. "TXFIFO,Data to be transmitted. Data should normally be aligned to the LSB (pad the upper bits with zeros) unless BIGENDIAN is set."
|
|
line.long 0x14 "RXFIFO,RX Data FIFO"
|
|
hexmask.long 0x14 0.--31. 1. "RXFIFO,Receive data. Data is aligned to the LSB (padded zeros on upper bits) unless BIGENDIAN is set."
|
|
line.long 0x18 "TXENTRIES,Number of words in TX FIFO"
|
|
hexmask.long.byte 0x18 0.--5. 1. "TXENTRIES,Number of 32-bit words/entries in TX FIFO"
|
|
line.long 0x1C "RXENTRIES,Number of words in RX FIFO"
|
|
hexmask.long.byte 0x1C 0.--5. 1. "RXENTRIES,Number of 32-bit words/entries in RX FIFO"
|
|
line.long 0x20 "THRESHOLD,Threshold levels that trigger RXFull and TXEmpty interrupts"
|
|
hexmask.long.byte 0x20 8.--13. 1. "RXTHRESH,Number of entries in TX FIFO that cause RXE interrupt"
|
|
newline
|
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hexmask.long.byte 0x20 0.--5. 1. "TXTHRESH,Number of entries in TX FIFO that cause TXF interrupt"
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group.long 0x30++0x3
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line.long 0x0 "MSPICFG,Timing configuration bits for the MSPI module. PRSTN. IPRSTN. and FIFORESET can be used to reset portions of the MSPI interface in order to clear error conditions. The remaining bits control clock frequency and TX/RX capture timings."
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bitfld.long 0x0 31. "PRSTN,Peripheral reset. Master reset to the entire MSPI module (DMA XIP and transfer state machines). 1=normal operation 0=in reset." "0: in reset,1: normal operation"
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bitfld.long 0x0 30. "IPRSTN,IP block reset. Write to 0 to put the transfer module in reset or 1 for normal operation. This may be required after error conditions to clear the transfer on the bus." "0,1"
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bitfld.long 0x0 29. "FIFORESET,Reset MSPI FIFO (active high). 1=reset FIFO 0=normal operation. May be used to manually flush the FIFO in error handling." "0: normal operation,1: reset FIFO"
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hexmask.long.byte 0x0 4.--7. 1. "IOMSEL,Selects which IOM is selected for CQ handshake status."
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bitfld.long 0x0 0. "APBCLK,Enable continuous APB clock. For power-efficient operation APBCLK should be set to 0." "0: Disable continuous clock.,1: Enable continuous clock."
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group.long 0x44++0xB
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line.long 0x0 "PADOUTEN,Enable bits for the MSPI output pads. Each active MSPI line should be set to 1 in the OUTEN field below."
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bitfld.long 0x0 31. "CLKOND4,Output clock on MSPI data[4]" "0,1"
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bitfld.long 0x0 30. "PADSET1,Only applicable on mspi1. When set use gpio95 .. gpio 104 as the pads. This extra set of pads is to run mspi0 on HEX and mspi1 concurrently. Note that the timing of this extra pads may not be as good as the origianl pads." "0,1"
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hexmask.long.tbyte 0x0 0.--19. 1. "OUTEN,Output pad enable configuration. Indicates which pads should be driven. Bits [3:0] are Quad0 data. Bits [7:4] are Quad1 data. Bit [8] is clock. Bit [9] is BM/DQS. Bit [10:17] are data for 16-bit. Bit[18] is BM/DQS for 16-bit. Bit[19] is not used."
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line.long 0x4 "PADOVEREN,Enables PIO-like pad override control"
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hexmask.long.tbyte 0x4 0.--19. 1. "OVERRIDEEN,Output pad override enable. Bit mask for pad outputs. When set to 1 the values in the OVERRIDE field are driven on the pad (output enable is implicitly set in this mode). [7:0]=data [8]=clock [9]=DM"
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line.long 0x8 "PADOVER,Override data value"
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hexmask.long.tbyte 0x8 0.--19. 1. "OVERRIDE,Output pad override value. [7:0]=data [8]=clock [9]=DM"
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group.long 0x80++0x23
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line.long 0x0 "DEV0AXI,Specifies the base address and aperture range of the device as mapped onto the AXI bus"
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hexmask.long.word 0x0 16.--25. 1. "BASE0,XIPEN has to be enabled to enable aperture. The BASE address needs to be SIZE aligned."
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bitfld.long 0x0 4. "READONLY0,Indicates the AXI aperture is read-only" "0: Indicates AXI aperture supports read and write..,1: Indicates AXI aperture only supports read.."
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hexmask.long.byte 0x0 0.--3. 1. "SIZE0,Indicates the AXI aperture size"
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line.long 0x4 "DEV0CFG,Command formatting for PIO based transactions (initiated by writes to CTRL register)"
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hexmask.long.byte 0x4 26.--31. 1. "WRITELATENCY0,Number of write Latency cycles. Qualified by ENTURN bit field."
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bitfld.long 0x4 25. "SEPIO0,Separate IO configuration. This bit should be set when the target device has separate MOSI and MISO pins. Respective IN/OUT bits below should be set to map pins." "0,1"
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bitfld.long 0x4 24. "TXNEG0,Launches TX data a half clock cycle (~10ns) early. This should normally be programmed to zero (NORMAL)." "0: TX launched from posedge internal clock,1: TX data launched from negedge of internal clock"
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bitfld.long 0x4 23. "RXNEG0,Adjusts the RX capture phase to the negedge of the 48MHz internal clock (~10ns early). For normal operation it is expected that RXNEG will be set to 0." "0: RX data sampled on posedge of internal clock,1: RX data sampled on negedge of internal clock"
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bitfld.long 0x4 22. "RXCAP0,Controls RX data capture phase. A setting of 0 (NORMAL) captures read data at the normal capture point relative to the internal clock launch point. However to accomodate chip/pad/board delays a setting of RXCAP of 1 is expected to be used to.." "0: RX Capture phase aligns with CPHA setting,1: RX Capture phase is delayed from CPHA setting by.."
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hexmask.long.byte 0x4 16.--21. 1. "CLKDIV0,Clock Divider. Allows dividing 96 MHz base clock by integer multiples. Enumerations are provided for common frequency but any integer divide from 96 MHz is allowed. Odd divide ratios will result in a 33/66 percent duty cycle with a long low.."
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bitfld.long 0x4 15. "CPOL0,Serial clock polarity." "0: Clock inactive state is low.,1: Clock inactive state is high."
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bitfld.long 0x4 14. "CPHA0,Serial clock phase." "0: Clock toggles in middle of data bit.,1: Clock toggles at start of data bit."
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hexmask.long.byte 0x4 8.--13. 1. "TURNAROUND0,Number of turnaound cycles (for TX->RX transitions). Qualified by ENTURN bit field."
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bitfld.long 0x4 7. "ISIZE0,Instruction Size" "0: Instruction is 1 byte,1: Instruction is 2 bytes"
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bitfld.long 0x4 5.--6. "ASIZE0,Address Size. Address bytes to send from ADDR register" "0: Send one address byte,1: Send two address bytes,2: Send three address bytes,3: Send four address bytes"
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hexmask.long.byte 0x4 0.--4. 1. "DEVCFG0,Flash configuration for XIP and AUTO DMA operations. Controls value for SER (Slave Enable) for XIP operations and address generation for DMA/XIP modes. Also used to configure SPIFRF (frame format)."
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line.long 0x8 "DEV0DDR,Timing configuration bits for DDR operation of the MSPI module."
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bitfld.long 0x8 31. "RXDQSDELAYHIEN0,When 1 RXDQSDELAYHI and RXDQSDELAYNEGHI is used for falling edge of the clock." "0,1"
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hexmask.long.byte 0x8 26.--30. 1. "RXDQSDELAYNEGHI0,This acts as an offset to the computed value (should be set to 0 by default) of falling edge for 2nd DQS on HEX mode."
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hexmask.long.byte 0x8 21.--25. 1. "RXDQSDELAYHI0,This acts as an offset to the computed value (should be set to 0 by default) for 2nd DQS on HEX mode."
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bitfld.long 0x8 20. "RXDQSDELAYNEGEN0,When 1 RXDQSDELAYNEG is used for falling edge of the clock." "0,1"
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hexmask.long.byte 0x8 15.--19. 1. "RXDQSDELAYNEG0,This acts as an offset to the computed value (should be set to 0 by default) of falling edge."
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hexmask.long.byte 0x8 10.--14. 1. "RXDQSDELAY0,This acts as an offset to the computed value (should be set to 0 by default)"
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hexmask.long.byte 0x8 5.--9. 1. "TXDQSDELAY0,This acts as an offset to the computed value (should be set to 0 by default)"
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bitfld.long 0x8 4. "ENABLEFINEDELAY0,Enables use of delay line to provide fine control over traditional RX capture clock." "0,1"
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bitfld.long 0x8 3. "DQSSYNCNEG0,Use negative edge of clock for DDR data sync" "0,1"
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bitfld.long 0x8 2. "ENABLEDQS0,In EMULATEDDR mode enable DQS for read capture" "0,1"
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bitfld.long 0x8 1. "QUADDDR0,Deprecated. No effect on RevC." "0,1"
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bitfld.long 0x8 0. "EMULATEDDR0,Drive external clock at 1/2 rate to emulate DDR mode" "0,1"
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line.long 0xC "DEV0CFG1,Timing and mode configuration bits for the MSPI module."
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bitfld.long 0xC 14.--16. "DQSTURN0,In DQS mode the internal cycle count to enable DQS path." "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 13. "RXHI0,Force st_rx to start at clock high of mspi_clk" "0,1"
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bitfld.long 0xC 12. "TAFOURTH0,Add 1/4th mspi_clk in DDR to turnaround. Recommended set this to 1 when EMULATEDDR is set in non-DQS mode (ENABLEDQS = 0)." "0,1"
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bitfld.long 0xC 11. "HYPERIO0,When using Windbond set this bit to 1 to generate CA[47:0] in hardware." "0,1"
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bitfld.long 0xC 9.--10. "RXSMP0,Sampling edge based on sclk edge. No effect when div1" "0,1,2,3"
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bitfld.long 0xC 8. "RBX0,Enable the support of RBX ( page boundary crossing on read )" "0,1"
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bitfld.long 0xC 7. "WBX0,Enable the support of WBX ( page boundary crossing on write )" "0,1"
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bitfld.long 0xC 5. "SCLKRXHALT0,Halt sclk based on xfer_count" "0,1"
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bitfld.long 0xC 4. "RXCAPEXT0,Specify the number of apb_clk of RX capture phse {RXCAPEXT RXCAP}" "0,1"
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hexmask.long.byte 0xC 0.--3. 1. "SFTURN0,Subtract from internal counter of write latency and turnaround"
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line.long 0x10 "DEV0XIP,When any SPI flash is configured. this register must be properly programmed before XIP or AUTO DMA operations commence."
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hexmask.long.byte 0x10 20.--25. 1. "XIPWRITELATENCY0,Number of write Latency cycles. Qualified by XIPENWLAT bit field."
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hexmask.long.byte 0x10 14.--19. 1. "XIPTURNAROUND0,Number of turnaound cycles (for TX->RX transitions). Qualified by XIPENTURN bit field."
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bitfld.long 0x10 13. "XIPENWLAT0,Enable Write Latency counter for XIP write transactions" "0,1"
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bitfld.long 0x10 12. "XIPENDCX0,Enable DCX signal on data [1] for XIP/DMA operations" "0,1"
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hexmask.long.byte 0x10 8.--11. 1. "XIPMIXED0,Provides override controls for data operations where instruction address and data may transfer in different rates."
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bitfld.long 0x10 7. "XIPSENDI0,Indicates whether XIP/AUTO DMA operations should send an instruction (see READINSTR field and ISIZE field in CFG)" "0,1"
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bitfld.long 0x10 6. "XIPSENDA0,Indicates whether XIP/AUTO DMA operations should send an an address phase (see DMADEVADDR register and ASIZE field in CFG)" "0,1"
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bitfld.long 0x10 5. "XIPENTURN0,Indicates whether XIP/AUTO DMA operations should enable TX->RX turnaround cycles" "0,1"
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bitfld.long 0x10 4. "XIPBIGENDIAN0,Indicates whether XIP/AUTO DMA data transfers are in big or little endian format" "0,1"
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bitfld.long 0x10 2.--3. "XIPACK0,Controls transmission of Micron XIP acknowledge cycles (Micron Flash devices only)" "0: No acknowledege sent. Data IOs are tristated the..,?,2: Positive acknowledege sent. Data IOs are driven..,3: Negative acknowledege sent. Data IOs are driven.."
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bitfld.long 0x10 0. "XIPEN0,Enable the XIP (eXecute In Place) function which effectively enables the address decoding of the MSPI device in the flash/cache address space at address 0x04000000-0x07FFFFFF." "0,1"
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line.long 0x14 "DEV0INSTR,When any SPI flash is configured. this register must be properly programmed before XIP or AUTO DMA operations commence."
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hexmask.long.word 0x14 16.--31. 1. "READINSTR0,Read command sent to flash for DMA/XIP operations"
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hexmask.long.word 0x14 0.--15. 1. "WRITEINSTR0,Write command sent for DMA operations"
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line.long 0x18 "DEV0BOUNDARY,Allows large transfers to be broken up into smaller ones in hardware to accommodate needs of external devices and allow XIP/XIPMM. Only applicable for memory-mapped devices (PSRAM. Flash. etc) where address can be retransmitted without side.."
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hexmask.long.byte 0x18 12.--15. 1. "DMABOUND0,DMA Address boundary"
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hexmask.long.word 0x18 0.--11. 1. "DMATIMELIMIT0,DMA time limit. Can be used to limit the transaction time on the MSPI bus. The count is in ~100 ns increments for the 96 MHz clock input. A value of 0 disables the counter."
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line.long 0x1C "DEV0SCRAMBLING,Enables data scrambling for the specified range external flash addresses. Scrambling does not impact flash access performance."
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bitfld.long 0x1C 31. "SCRENABLE0,Enables Data Scrambling Region. When 1 reads and writes to the range will be scrambled. When 0 data will be read/written unmodified. Address range is specified in 64K granularity and the START/END ranges are included within the range." "0,1"
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hexmask.long.word 0x1C 16.--25. 1. "SCREND0,Scrambling region end address [25:16] (64K block granularity). The END block is the LAST block included in the scrambled address range."
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hexmask.long.word 0x1C 0.--9. 1. "SCRSTART0,Scrambling region start address [25:16] (64K block granularity). The START block is the FIRST block included in the scrambled address range."
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line.long 0x20 "DEV0XIPMISC,Miscellaneous XIP control registers for AXI logic"
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bitfld.long 0x20 21. "APNDODD0,Append dummy byte to odd number of write" "0: No appending byte,1: Append one dummy byte"
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bitfld.long 0x20 15. "XIPBOUNDARY0,Deprecated. No effect on RevC." "0: ERROR: desc VALUE MISSING,1: ERROR: desc VALUE MISSING"
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bitfld.long 0x20 14. "BEON0,Byte enable always on for all lanes" "0: Byte enable is calculated on the fly,1: Byte enable of all bytes are always on"
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bitfld.long 0x20 13. "BEPOL0,byte mask polarity to MSPI xfer" "0,1"
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bitfld.long 0x20 12. "XIPODD0,Convert odd starting address to word-aligned starting address with byte-enables for holes. For example an AXI transaction with wstrb of 0x0600 results in mspi transaction of addr=8 and BE=0b1001 ( active low )." "0: No conversion,1: Enable the conversion"
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hexmask.long.word 0x20 0.--11. 1. "CEBREAK0,CEBREAK0 field description needed."
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group.long 0x100++0x1B
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line.long 0x0 "DMACFG,DMA Configuration"
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bitfld.long 0x0 18. "DMAPWROFF,Power off MSPI domain upon completion of DMA operation." "0,1"
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bitfld.long 0x0 17. "DMATXEMPT,For DMA_M2P only start when DMA fifo is not empty." "0,1"
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bitfld.long 0x0 4.--5. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately),2: Auto Priority (priority raised once TX FIFO..,?"
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bitfld.long 0x0 3. "DMADEV,DMA Device Select" "0: Select Device 0 for DMA,?"
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bitfld.long 0x0 2. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction,1: Memory to Peripheral transaction"
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bitfld.long 0x0 0.--1. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation" "0: Disable DMA Function,?,?,3: Enable HW controlled DMA Function to manage DMA.."
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line.long 0x4 "DMASTAT,DMA Status"
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bitfld.long 0x4 3. "SCRERR,Scrambling Access Alignment Error. This active high bit signals that a scrambling operation was specified for a non-word aligned DEVADDR." "0,1"
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bitfld.long 0x4 2. "DMAERR,DMA Error. This active high bit signals that an error was encountered during the DMA operation." "0,1"
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bitfld.long 0x4 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation." "0,1"
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bitfld.long 0x4 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority. All of these will be indicated with a 1. A 0 will indicate that the DMA is.." "0,1"
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line.long 0x8 "DMATARGADDR,DMA Target Address"
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hexmask.long 0x8 0.--31. 1. "TARGADDR,Target byte address for source of DMA (either read or write). In cases of non-word aligned addresses the DMA logic will take care for ensuring only the target bytes are read/written."
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line.long 0xC "DMADEVADDR,DMA Device Address"
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hexmask.long 0xC 0.--31. 1. "DEVADDR,SPI Device address for automated DMA transactions (both read and write)."
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line.long 0x10 "DMATOTCOUNT,DMA Total Transfer Count"
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hexmask.long.tbyte 0x10 0.--23. 1. "TOTCOUNT,Total Transfer Count in bytes."
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line.long 0x14 "DMABCOUNT,DMA BYTE Transfer Count"
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hexmask.long.byte 0x14 0.--7. 1. "BCOUNT,Burst transfer size in bytes. This is the number of bytes transferred when a FIFO trigger event occurs. Recommended value is 32."
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line.long 0x18 "DMATHRESH,Indicates FIFO level at which a DMA should be triggered. For most configurations. a setting of 8 is recommended for both read and write operations."
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hexmask.long.byte 0x18 8.--12. 1. "DMARXTHRESH,DMA transfer FIFO level trigger. For read operations DMA is triggered when the FIFO level is greater than this value. For write operations DMA is triggered when the FIFO level is less than this level. Each DMA operation will consist of.."
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hexmask.long.byte 0x18 0.--4. 1. "DMATXTHRESH,DMA transfer FIFO level trigger. For read operations DMA is triggered when the FIFO level is greater than this value. For write operations DMA is triggered when the FIFO level is less than this level. Each DMA operation will consist of.."
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group.long 0x200++0xF
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line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
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bitfld.long 0x0 13. "APBDMAERR,MSPI is dma target as well as dma source which may result in deadlock." "0,1"
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bitfld.long 0x0 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
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bitfld.long 0x0 11. "CQERR,Command Queue Error Interrupt" "0,1"
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bitfld.long 0x0 10. "CQPAUSED,Command Queue is Paused." "0,1"
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bitfld.long 0x0 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
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bitfld.long 0x0 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
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bitfld.long 0x0 7. "DERR,DMA Error Interrupt" "0,1"
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bitfld.long 0x0 6. "DCMP,DMA Complete Interrupt" "0,1"
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bitfld.long 0x0 5. "RXF,Receive FIFO full" "0,1"
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bitfld.long 0x0 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
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bitfld.long 0x0 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
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bitfld.long 0x0 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
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bitfld.long 0x0 1. "TXE,Transmit FIFO empty." "0,1"
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bitfld.long 0x0 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
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line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
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bitfld.long 0x4 13. "APBDMAERR,MSPI is dma target as well as dma source which may result in deadlock." "0,1"
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bitfld.long 0x4 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
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bitfld.long 0x4 11. "CQERR,Command Queue Error Interrupt" "0,1"
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bitfld.long 0x4 10. "CQPAUSED,Command Queue is Paused." "0,1"
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bitfld.long 0x4 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
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bitfld.long 0x4 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
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bitfld.long 0x4 7. "DERR,DMA Error Interrupt" "0,1"
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bitfld.long 0x4 6. "DCMP,DMA Complete Interrupt" "0,1"
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bitfld.long 0x4 5. "RXF,Receive FIFO full" "0,1"
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bitfld.long 0x4 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
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bitfld.long 0x4 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
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bitfld.long 0x4 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
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bitfld.long 0x4 1. "TXE,Transmit FIFO empty." "0,1"
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bitfld.long 0x4 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
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line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
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bitfld.long 0x8 13. "APBDMAERR,MSPI is dma target as well as dma source which may result in deadlock." "0,1"
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bitfld.long 0x8 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
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bitfld.long 0x8 11. "CQERR,Command Queue Error Interrupt" "0,1"
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bitfld.long 0x8 10. "CQPAUSED,Command Queue is Paused." "0,1"
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bitfld.long 0x8 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "DERR,DMA Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "DCMP,DMA Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "RXF,Receive FIFO full" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "TXE,Transmit FIFO empty." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 13. "APBDMAERR,MSPI is dma target as well as dma source which may result in deadlock." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "CQERR,Command Queue Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "CQPAUSED,Command Queue is Paused." "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "DERR,DMA Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "DCMP,DMA Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "RXF,Receive FIFO full" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "TXE,Transmit FIFO empty." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
|
|
group.long 0x2A0++0x3
|
|
line.long 0x0 "CQCFG,This register controls Command Queuing (CQ) operations in a manner similar to the DMACFG register."
|
|
bitfld.long 0x0 4. "CQPAUSEOP,CQPAUSEOP register description needed." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CQAUTOCLEARMASK,Enable clear of CQMASK after each pause operation. This may be useful when using software flags to pause CQ." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CQPWROFF,Power off MSPI domain upon completion of DMA operation." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CQPRI,Sets the Priority of the command queue DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
|
|
newline
|
|
bitfld.long 0x0 0. "CQEN,Command queue enable. When set will enable the processing of the command queue" "0: Disable CQ Function,1: Enable CQ Function"
|
|
group.long 0x2A8++0x13
|
|
line.long 0x0 "CQADDR,Location of the command queue in SRAM or flash memory. This register will increment as CQ operations commence. Software should only write CQADDR when CQEN is disabled. however the command queue script itself may update CQADDR in order to perform.."
|
|
hexmask.long 0x0 0.--28. 1. "CQADDR,Address of command queue buffer in SRAM or flash. The buffer address must be aligned to a word boundary."
|
|
line.long 0x4 "CQSTAT,Command Queue Status"
|
|
bitfld.long 0x4 3. "CQPAUSED,Command queue is currently paused status." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CQCPL,Command queue operation Complete. This signals the end of the command queue operation." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
|
|
line.long 0x8 "CQFLAGS,Command Queue Flags"
|
|
hexmask.long.word 0x8 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
|
|
line.long 0xC "CQSETCLEAR,Command Queue Flag Set/Clear"
|
|
hexmask.long.byte 0xC 16.--23. 1. "CQFCLR,Clear CQFlag status bits."
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "CQFTOGGLE,Toggle CQFlag status bits"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CQFSET,Set CQFlag status bits. Set has priority over clear if both are high."
|
|
line.long 0x10 "CQPAUSE,Command Queue Pause Mask"
|
|
hexmask.long.word 0x10 0.--15. 1. "CQMASK,CQ will pause processing when ALL specified events are satisfied -- i.e. when (CQMASK and CQPAUSE)==CQMASK."
|
|
group.long 0x2C0++0x7
|
|
line.long 0x0 "CQCURIDX,This register can be used in conjunction with the CQENDIDX register to manage the command queue. Typically software will initialize the CQCURIDX and CQENDIDX to the same value. which will cause the CQ to be paused when enabled. Software may then.."
|
|
hexmask.long.byte 0x0 0.--7. 1. "CQCURIDX,Can be used to indicate the current position of the command queue by having CQ operations write this field. A CQ hardware status flag indicates when CURIDX and ENDIDX are not equal allowing SW to pause the CQ processing until the end index is.."
|
|
line.long 0x4 "CQENDIDX,Command Queue End Index"
|
|
hexmask.long.byte 0x4 0.--7. 1. "CQENDIDX,Can be used to indicate the end position of the command queue. A CQ hardware status bit indices when CURIDX != ENDIDX so that the CQ can be paused when it reaches the end pointer."
|
|
group.long 0x310++0x3
|
|
line.long 0x0 "STATXIPDMA,Debug XIP DMA State"
|
|
hexmask.long 0x0 0.--31. 1. "FLD32,XIP/DMA module debug"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
tree "MSPI1"
|
|
base ad:0x40061000
|
|
group.long 0x0++0x23
|
|
line.long 0x0 "CTRL,This register is used to enable individual PIO based transactions to a device on the bus. The CFG register must be programmed properly for the transfer. and the ADDR and INSTR registers should be programmed if the SENDI and SENDA fields are enabled."
|
|
hexmask.long.word 0x0 16.--31. 1. "XFERBYTES,Number of bytes to transmit or receive (based on TXRX bit)"
|
|
newline
|
|
bitfld.long 0x0 12. "ENWLAT,Enable Write Latency Counter (time between address and first data byte). Counter value is WRITELATENCY." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "ENDCX,Enable DCX signal on data [1]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ENTURN,Indicates whether TX->RX turnaround cycles should be enabled for this operation (see TURNAROUND field in CFG register)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PIOSCRAMBLE,Enables data scrambling for PIO opertions. This should only be used for data operations and never for commands to a device." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "BIGENDIAN,1 indicates data in FIFO is in big endian format (MSB first); 0 indicates little endian data (default LSB first)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXRX,1 Indicates a TX operation 0 indicates an RX operation of XFERBYTES" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "SENDI,Indicates whether an instruction phase should be sent (see INSTR field and ISIZE field in CFG register)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SENDA,Indicates whether an address phase should be sent (see ADDR register and ASIZE field in CFG register)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PIODEV,Selects the Device configutation to use for PIO requests" "0: Use DEVICE0 Configuration,1: Use DEVICE1 CONFIGURATION"
|
|
newline
|
|
bitfld.long 0x0 2. "BUSY,Command status: 1 indicates controller is busy (command in progress)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STATUS,Command status: 1 indicates command has completed. Cleared by writing 1 to this bit or starting a new transfer." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Write to 1 to initiate a PIO transaction on the bus (typically the entire register should be written at once with this bit set)." "0,1"
|
|
line.long 0x4 "CTRL1,These registers are used to enable individual PIO based transactions to a device on the bus. The CFG register must be programmed properly for the transfer. and the ADDR and INSTR registers should be programmed if the SENDI and SENDA fields are.."
|
|
hexmask.long.byte 0x4 0.--3. 1. "PIOMIXED,Provides override controls for data operations where instruction address and data may transfer in different rates."
|
|
line.long 0x8 "ADDR,Optional Address field to send for PIO transfers"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,Optional Address field to send (after optional instruction field) - qualified by ASIZE in CMD register. NOTE: This register is aliased to DMADEVADDR."
|
|
line.long 0xC "INSTR,Optional Instruction field to send for PIO transfers"
|
|
hexmask.long.word 0xC 0.--15. 1. "INSTR,Optional Instruction field to send (1st byte) - qualified by ISEND/ISIZE"
|
|
line.long 0x10 "TXFIFO,TX Data FIFO"
|
|
hexmask.long 0x10 0.--31. 1. "TXFIFO,Data to be transmitted. Data should normally be aligned to the LSB (pad the upper bits with zeros) unless BIGENDIAN is set."
|
|
line.long 0x14 "RXFIFO,RX Data FIFO"
|
|
hexmask.long 0x14 0.--31. 1. "RXFIFO,Receive data. Data is aligned to the LSB (padded zeros on upper bits) unless BIGENDIAN is set."
|
|
line.long 0x18 "TXENTRIES,Number of words in TX FIFO"
|
|
hexmask.long.byte 0x18 0.--5. 1. "TXENTRIES,Number of 32-bit words/entries in TX FIFO"
|
|
line.long 0x1C "RXENTRIES,Number of words in RX FIFO"
|
|
hexmask.long.byte 0x1C 0.--5. 1. "RXENTRIES,Number of 32-bit words/entries in RX FIFO"
|
|
line.long 0x20 "THRESHOLD,Threshold levels that trigger RXFull and TXEmpty interrupts"
|
|
hexmask.long.byte 0x20 8.--13. 1. "RXTHRESH,Number of entries in TX FIFO that cause RXE interrupt"
|
|
newline
|
|
hexmask.long.byte 0x20 0.--5. 1. "TXTHRESH,Number of entries in TX FIFO that cause TXF interrupt"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "MSPICFG,Timing configuration bits for the MSPI module. PRSTN. IPRSTN. and FIFORESET can be used to reset portions of the MSPI interface in order to clear error conditions. The remaining bits control clock frequency and TX/RX capture timings."
|
|
bitfld.long 0x0 31. "PRSTN,Peripheral reset. Master reset to the entire MSPI module (DMA XIP and transfer state machines). 1=normal operation 0=in reset." "0: in reset,1: normal operation"
|
|
newline
|
|
bitfld.long 0x0 30. "IPRSTN,IP block reset. Write to 0 to put the transfer module in reset or 1 for normal operation. This may be required after error conditions to clear the transfer on the bus." "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "FIFORESET,Reset MSPI FIFO (active high). 1=reset FIFO 0=normal operation. May be used to manually flush the FIFO in error handling." "0: normal operation,1: reset FIFO"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "IOMSEL,Selects which IOM is selected for CQ handshake status."
|
|
newline
|
|
bitfld.long 0x0 0. "APBCLK,Enable continuous APB clock. For power-efficient operation APBCLK should be set to 0." "0: Disable continuous clock.,1: Enable continuous clock."
|
|
group.long 0x44++0xB
|
|
line.long 0x0 "PADOUTEN,Enable bits for the MSPI output pads. Each active MSPI line should be set to 1 in the OUTEN field below."
|
|
bitfld.long 0x0 31. "CLKOND4,Output clock on MSPI data[4]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "PADSET1,Only applicable on mspi1. When set use gpio95 .. gpio 104 as the pads. This extra set of pads is to run mspi0 on HEX and mspi1 concurrently. Note that the timing of this extra pads may not be as good as the origianl pads." "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "OUTEN,Output pad enable configuration. Indicates which pads should be driven. Bits [3:0] are Quad0 data. Bits [7:4] are Quad1 data. Bit [8] is clock. Bit [9] is BM/DQS. Bit [10:17] are data for 16-bit. Bit[18] is BM/DQS for 16-bit. Bit[19] is not used."
|
|
line.long 0x4 "PADOVEREN,Enables PIO-like pad override control"
|
|
hexmask.long.tbyte 0x4 0.--19. 1. "OVERRIDEEN,Output pad override enable. Bit mask for pad outputs. When set to 1 the values in the OVERRIDE field are driven on the pad (output enable is implicitly set in this mode). [7:0]=data [8]=clock [9]=DM"
|
|
line.long 0x8 "PADOVER,Override data value"
|
|
hexmask.long.tbyte 0x8 0.--19. 1. "OVERRIDE,Output pad override value. [7:0]=data [8]=clock [9]=DM"
|
|
group.long 0x80++0x23
|
|
line.long 0x0 "DEV0AXI,Specifies the base address and aperture range of the device as mapped onto the AXI bus"
|
|
hexmask.long.word 0x0 16.--25. 1. "BASE0,XIPEN has to be enabled to enable aperture. The BASE address needs to be SIZE aligned."
|
|
newline
|
|
bitfld.long 0x0 4. "READONLY0,Indicates the AXI aperture is read-only" "0: Indicates AXI aperture supports read and write..,1: Indicates AXI aperture only supports read.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SIZE0,Indicates the AXI aperture size"
|
|
line.long 0x4 "DEV0CFG,Command formatting for PIO based transactions (initiated by writes to CTRL register)"
|
|
hexmask.long.byte 0x4 26.--31. 1. "WRITELATENCY0,Number of write Latency cycles. Qualified by ENTURN bit field."
|
|
newline
|
|
bitfld.long 0x4 25. "SEPIO0,Separate IO configuration. This bit should be set when the target device has separate MOSI and MISO pins. Respective IN/OUT bits below should be set to map pins." "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "TXNEG0,Launches TX data a half clock cycle (~10ns) early. This should normally be programmed to zero (NORMAL)." "0: TX launched from posedge internal clock,1: TX data launched from negedge of internal clock"
|
|
newline
|
|
bitfld.long 0x4 23. "RXNEG0,Adjusts the RX capture phase to the negedge of the 48MHz internal clock (~10ns early). For normal operation it is expected that RXNEG will be set to 0." "0: RX data sampled on posedge of internal clock,1: RX data sampled on negedge of internal clock"
|
|
newline
|
|
bitfld.long 0x4 22. "RXCAP0,Controls RX data capture phase. A setting of 0 (NORMAL) captures read data at the normal capture point relative to the internal clock launch point. However to accomodate chip/pad/board delays a setting of RXCAP of 1 is expected to be used to.." "0: RX Capture phase aligns with CPHA setting,1: RX Capture phase is delayed from CPHA setting by.."
|
|
newline
|
|
hexmask.long.byte 0x4 16.--21. 1. "CLKDIV0,Clock Divider. Allows dividing 96 MHz base clock by integer multiples. Enumerations are provided for common frequency but any integer divide from 96 MHz is allowed. Odd divide ratios will result in a 33/66 percent duty cycle with a long low.."
|
|
newline
|
|
bitfld.long 0x4 15. "CPOL0,Serial clock polarity." "0: Clock inactive state is low.,1: Clock inactive state is high."
|
|
newline
|
|
bitfld.long 0x4 14. "CPHA0,Serial clock phase." "0: Clock toggles in middle of data bit.,1: Clock toggles at start of data bit."
|
|
newline
|
|
hexmask.long.byte 0x4 8.--13. 1. "TURNAROUND0,Number of turnaound cycles (for TX->RX transitions). Qualified by ENTURN bit field."
|
|
newline
|
|
bitfld.long 0x4 7. "ISIZE0,Instruction Size" "0: Instruction is 1 byte,1: Instruction is 2 bytes"
|
|
newline
|
|
bitfld.long 0x4 5.--6. "ASIZE0,Address Size. Address bytes to send from ADDR register" "0: Send one address byte,1: Send two address bytes,2: Send three address bytes,3: Send four address bytes"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "DEVCFG0,Flash configuration for XIP and AUTO DMA operations. Controls value for SER (Slave Enable) for XIP operations and address generation for DMA/XIP modes. Also used to configure SPIFRF (frame format)."
|
|
line.long 0x8 "DEV0DDR,Timing configuration bits for DDR operation of the MSPI module."
|
|
bitfld.long 0x8 31. "RXDQSDELAYHIEN0,When 1 RXDQSDELAYHI and RXDQSDELAYNEGHI is used for falling edge of the clock." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 26.--30. 1. "RXDQSDELAYNEGHI0,This acts as an offset to the computed value (should be set to 0 by default) of falling edge for 2nd DQS on HEX mode."
|
|
newline
|
|
hexmask.long.byte 0x8 21.--25. 1. "RXDQSDELAYHI0,This acts as an offset to the computed value (should be set to 0 by default) for 2nd DQS on HEX mode."
|
|
newline
|
|
bitfld.long 0x8 20. "RXDQSDELAYNEGEN0,When 1 RXDQSDELAYNEG is used for falling edge of the clock." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 15.--19. 1. "RXDQSDELAYNEG0,This acts as an offset to the computed value (should be set to 0 by default) of falling edge."
|
|
newline
|
|
hexmask.long.byte 0x8 10.--14. 1. "RXDQSDELAY0,This acts as an offset to the computed value (should be set to 0 by default)"
|
|
newline
|
|
hexmask.long.byte 0x8 5.--9. 1. "TXDQSDELAY0,This acts as an offset to the computed value (should be set to 0 by default)"
|
|
newline
|
|
bitfld.long 0x8 4. "ENABLEFINEDELAY0,Enables use of delay line to provide fine control over traditional RX capture clock." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "DQSSYNCNEG0,Use negative edge of clock for DDR data sync" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ENABLEDQS0,In EMULATEDDR mode enable DQS for read capture" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "QUADDDR0,Deprecated. No effect on RevC." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "EMULATEDDR0,Drive external clock at 1/2 rate to emulate DDR mode" "0,1"
|
|
line.long 0xC "DEV0CFG1,Timing and mode configuration bits for the MSPI module."
|
|
bitfld.long 0xC 14.--16. "DQSTURN0,In DQS mode the internal cycle count to enable DQS path." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0xC 13. "RXHI0,Force st_rx to start at clock high of mspi_clk" "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "TAFOURTH0,Add 1/4th mspi_clk in DDR to turnaround. Recommended set this to 1 when EMULATEDDR is set in non-DQS mode (ENABLEDQS = 0)." "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "HYPERIO0,When using Windbond set this bit to 1 to generate CA[47:0] in hardware." "0,1"
|
|
newline
|
|
bitfld.long 0xC 9.--10. "RXSMP0,Sampling edge based on sclk edge. No effect when div1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 8. "RBX0,Enable the support of RBX ( page boundary crossing on read )" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "WBX0,Enable the support of WBX ( page boundary crossing on write )" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "SCLKRXHALT0,Halt sclk based on xfer_count" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "RXCAPEXT0,Specify the number of apb_clk of RX capture phse {RXCAPEXT RXCAP}" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--3. 1. "SFTURN0,Subtract from internal counter of write latency and turnaround"
|
|
line.long 0x10 "DEV0XIP,When any SPI flash is configured. this register must be properly programmed before XIP or AUTO DMA operations commence."
|
|
hexmask.long.byte 0x10 20.--25. 1. "XIPWRITELATENCY0,Number of write Latency cycles. Qualified by XIPENWLAT bit field."
|
|
newline
|
|
hexmask.long.byte 0x10 14.--19. 1. "XIPTURNAROUND0,Number of turnaound cycles (for TX->RX transitions). Qualified by XIPENTURN bit field."
|
|
newline
|
|
bitfld.long 0x10 13. "XIPENWLAT0,Enable Write Latency counter for XIP write transactions" "0,1"
|
|
newline
|
|
bitfld.long 0x10 12. "XIPENDCX0,Enable DCX signal on data [1] for XIP/DMA operations" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--11. 1. "XIPMIXED0,Provides override controls for data operations where instruction address and data may transfer in different rates."
|
|
newline
|
|
bitfld.long 0x10 7. "XIPSENDI0,Indicates whether XIP/AUTO DMA operations should send an instruction (see READINSTR field and ISIZE field in CFG)" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. "XIPSENDA0,Indicates whether XIP/AUTO DMA operations should send an an address phase (see DMADEVADDR register and ASIZE field in CFG)" "0,1"
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bitfld.long 0x10 5. "XIPENTURN0,Indicates whether XIP/AUTO DMA operations should enable TX->RX turnaround cycles" "0,1"
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bitfld.long 0x10 4. "XIPBIGENDIAN0,Indicates whether XIP/AUTO DMA data transfers are in big or little endian format" "0,1"
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|
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bitfld.long 0x10 2.--3. "XIPACK0,Controls transmission of Micron XIP acknowledge cycles (Micron Flash devices only)" "0: No acknowledege sent. Data IOs are tristated the..,?,2: Positive acknowledege sent. Data IOs are driven..,3: Negative acknowledege sent. Data IOs are driven.."
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bitfld.long 0x10 0. "XIPEN0,Enable the XIP (eXecute In Place) function which effectively enables the address decoding of the MSPI device in the flash/cache address space at address 0x04000000-0x07FFFFFF." "0,1"
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|
line.long 0x14 "DEV0INSTR,When any SPI flash is configured. this register must be properly programmed before XIP or AUTO DMA operations commence."
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hexmask.long.word 0x14 16.--31. 1. "READINSTR0,Read command sent to flash for DMA/XIP operations"
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|
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hexmask.long.word 0x14 0.--15. 1. "WRITEINSTR0,Write command sent for DMA operations"
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|
line.long 0x18 "DEV0BOUNDARY,Allows large transfers to be broken up into smaller ones in hardware to accommodate needs of external devices and allow XIP/XIPMM. Only applicable for memory-mapped devices (PSRAM. Flash. etc) where address can be retransmitted without side.."
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|
hexmask.long.byte 0x18 12.--15. 1. "DMABOUND0,DMA Address boundary"
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hexmask.long.word 0x18 0.--11. 1. "DMATIMELIMIT0,DMA time limit. Can be used to limit the transaction time on the MSPI bus. The count is in ~100 ns increments for the 96 MHz clock input. A value of 0 disables the counter."
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line.long 0x1C "DEV0SCRAMBLING,Enables data scrambling for the specified range external flash addresses. Scrambling does not impact flash access performance."
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bitfld.long 0x1C 31. "SCRENABLE0,Enables Data Scrambling Region. When 1 reads and writes to the range will be scrambled. When 0 data will be read/written unmodified. Address range is specified in 64K granularity and the START/END ranges are included within the range." "0,1"
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|
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hexmask.long.word 0x1C 16.--25. 1. "SCREND0,Scrambling region end address [25:16] (64K block granularity). The END block is the LAST block included in the scrambled address range."
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hexmask.long.word 0x1C 0.--9. 1. "SCRSTART0,Scrambling region start address [25:16] (64K block granularity). The START block is the FIRST block included in the scrambled address range."
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line.long 0x20 "DEV0XIPMISC,Miscellaneous XIP control registers for AXI logic"
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bitfld.long 0x20 21. "APNDODD0,Append dummy byte to odd number of write" "0: No appending byte,1: Append one dummy byte"
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bitfld.long 0x20 15. "XIPBOUNDARY0,Deprecated. No effect on RevC." "0: ERROR: desc VALUE MISSING,1: ERROR: desc VALUE MISSING"
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newline
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bitfld.long 0x20 14. "BEON0,Byte enable always on for all lanes" "0: Byte enable is calculated on the fly,1: Byte enable of all bytes are always on"
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bitfld.long 0x20 13. "BEPOL0,byte mask polarity to MSPI xfer" "0,1"
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bitfld.long 0x20 12. "XIPODD0,Convert odd starting address to word-aligned starting address with byte-enables for holes. For example an AXI transaction with wstrb of 0x0600 results in mspi transaction of addr=8 and BE=0b1001 ( active low )." "0: No conversion,1: Enable the conversion"
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hexmask.long.word 0x20 0.--11. 1. "CEBREAK0,CEBREAK0 field description needed."
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|
group.long 0x100++0x1B
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line.long 0x0 "DMACFG,DMA Configuration"
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bitfld.long 0x0 18. "DMAPWROFF,Power off MSPI domain upon completion of DMA operation." "0,1"
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bitfld.long 0x0 17. "DMATXEMPT,For DMA_M2P only start when DMA fifo is not empty." "0,1"
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bitfld.long 0x0 4.--5. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately),2: Auto Priority (priority raised once TX FIFO..,?"
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bitfld.long 0x0 3. "DMADEV,DMA Device Select" "0: Select Device 0 for DMA,?"
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bitfld.long 0x0 2. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction,1: Memory to Peripheral transaction"
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bitfld.long 0x0 0.--1. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation" "0: Disable DMA Function,?,?,3: Enable HW controlled DMA Function to manage DMA.."
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line.long 0x4 "DMASTAT,DMA Status"
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bitfld.long 0x4 3. "SCRERR,Scrambling Access Alignment Error. This active high bit signals that a scrambling operation was specified for a non-word aligned DEVADDR." "0,1"
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bitfld.long 0x4 2. "DMAERR,DMA Error. This active high bit signals that an error was encountered during the DMA operation." "0,1"
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bitfld.long 0x4 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation." "0,1"
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bitfld.long 0x4 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority. All of these will be indicated with a 1. A 0 will indicate that the DMA is.." "0,1"
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line.long 0x8 "DMATARGADDR,DMA Target Address"
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hexmask.long 0x8 0.--31. 1. "TARGADDR,Target byte address for source of DMA (either read or write). In cases of non-word aligned addresses the DMA logic will take care for ensuring only the target bytes are read/written."
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line.long 0xC "DMADEVADDR,DMA Device Address"
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hexmask.long 0xC 0.--31. 1. "DEVADDR,SPI Device address for automated DMA transactions (both read and write)."
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line.long 0x10 "DMATOTCOUNT,DMA Total Transfer Count"
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hexmask.long.tbyte 0x10 0.--23. 1. "TOTCOUNT,Total Transfer Count in bytes."
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line.long 0x14 "DMABCOUNT,DMA BYTE Transfer Count"
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hexmask.long.byte 0x14 0.--7. 1. "BCOUNT,Burst transfer size in bytes. This is the number of bytes transferred when a FIFO trigger event occurs. Recommended value is 32."
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line.long 0x18 "DMATHRESH,Indicates FIFO level at which a DMA should be triggered. For most configurations. a setting of 8 is recommended for both read and write operations."
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hexmask.long.byte 0x18 8.--12. 1. "DMARXTHRESH,DMA transfer FIFO level trigger. For read operations DMA is triggered when the FIFO level is greater than this value. For write operations DMA is triggered when the FIFO level is less than this level. Each DMA operation will consist of.."
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|
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hexmask.long.byte 0x18 0.--4. 1. "DMATXTHRESH,DMA transfer FIFO level trigger. For read operations DMA is triggered when the FIFO level is greater than this value. For write operations DMA is triggered when the FIFO level is less than this level. Each DMA operation will consist of.."
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group.long 0x200++0xF
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line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
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bitfld.long 0x0 13. "APBDMAERR,MSPI is dma target as well as dma source which may result in deadlock." "0,1"
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bitfld.long 0x0 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
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|
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bitfld.long 0x0 11. "CQERR,Command Queue Error Interrupt" "0,1"
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|
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|
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bitfld.long 0x0 10. "CQPAUSED,Command Queue is Paused." "0,1"
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|
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|
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bitfld.long 0x0 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
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bitfld.long 0x0 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
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bitfld.long 0x0 7. "DERR,DMA Error Interrupt" "0,1"
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|
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|
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bitfld.long 0x0 6. "DCMP,DMA Complete Interrupt" "0,1"
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|
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|
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bitfld.long 0x0 5. "RXF,Receive FIFO full" "0,1"
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bitfld.long 0x0 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
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bitfld.long 0x0 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
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bitfld.long 0x0 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
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bitfld.long 0x0 1. "TXE,Transmit FIFO empty." "0,1"
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bitfld.long 0x0 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
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line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
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bitfld.long 0x4 13. "APBDMAERR,MSPI is dma target as well as dma source which may result in deadlock." "0,1"
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|
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|
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bitfld.long 0x4 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
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newline
|
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bitfld.long 0x4 11. "CQERR,Command Queue Error Interrupt" "0,1"
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|
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|
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bitfld.long 0x4 10. "CQPAUSED,Command Queue is Paused." "0,1"
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bitfld.long 0x4 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
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newline
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bitfld.long 0x4 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
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bitfld.long 0x4 7. "DERR,DMA Error Interrupt" "0,1"
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|
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bitfld.long 0x4 6. "DCMP,DMA Complete Interrupt" "0,1"
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|
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bitfld.long 0x4 5. "RXF,Receive FIFO full" "0,1"
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bitfld.long 0x4 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
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bitfld.long 0x4 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
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bitfld.long 0x4 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
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bitfld.long 0x4 1. "TXE,Transmit FIFO empty." "0,1"
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|
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bitfld.long 0x4 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
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line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
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bitfld.long 0x8 13. "APBDMAERR,MSPI is dma target as well as dma source which may result in deadlock." "0,1"
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newline
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bitfld.long 0x8 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
|
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newline
|
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bitfld.long 0x8 11. "CQERR,Command Queue Error Interrupt" "0,1"
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|
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|
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bitfld.long 0x8 10. "CQPAUSED,Command Queue is Paused." "0,1"
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|
newline
|
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bitfld.long 0x8 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
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newline
|
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bitfld.long 0x8 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
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|
newline
|
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bitfld.long 0x8 7. "DERR,DMA Error Interrupt" "0,1"
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|
newline
|
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bitfld.long 0x8 6. "DCMP,DMA Complete Interrupt" "0,1"
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|
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bitfld.long 0x8 5. "RXF,Receive FIFO full" "0,1"
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|
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bitfld.long 0x8 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
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|
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|
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bitfld.long 0x8 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
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|
newline
|
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bitfld.long 0x8 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
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|
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|
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bitfld.long 0x8 1. "TXE,Transmit FIFO empty." "0,1"
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|
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|
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bitfld.long 0x8 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
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line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
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bitfld.long 0xC 13. "APBDMAERR,MSPI is dma target as well as dma source which may result in deadlock." "0,1"
|
|
newline
|
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bitfld.long 0xC 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
|
|
newline
|
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bitfld.long 0xC 11. "CQERR,Command Queue Error Interrupt" "0,1"
|
|
newline
|
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bitfld.long 0xC 10. "CQPAUSED,Command Queue is Paused." "0,1"
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|
newline
|
|
bitfld.long 0xC 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "DERR,DMA Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "DCMP,DMA Complete Interrupt" "0,1"
|
|
newline
|
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bitfld.long 0xC 5. "RXF,Receive FIFO full" "0,1"
|
|
newline
|
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bitfld.long 0xC 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
|
|
newline
|
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bitfld.long 0xC 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
|
|
newline
|
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bitfld.long 0xC 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
|
|
newline
|
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bitfld.long 0xC 1. "TXE,Transmit FIFO empty." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
|
|
group.long 0x2A0++0x3
|
|
line.long 0x0 "CQCFG,This register controls Command Queuing (CQ) operations in a manner similar to the DMACFG register."
|
|
bitfld.long 0x0 4. "CQPAUSEOP,CQPAUSEOP register description needed." "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "CQAUTOCLEARMASK,Enable clear of CQMASK after each pause operation. This may be useful when using software flags to pause CQ." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "CQPWROFF,Power off MSPI domain upon completion of DMA operation." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CQPRI,Sets the Priority of the command queue DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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|
newline
|
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bitfld.long 0x0 0. "CQEN,Command queue enable. When set will enable the processing of the command queue" "0: Disable CQ Function,1: Enable CQ Function"
|
|
group.long 0x2A8++0x13
|
|
line.long 0x0 "CQADDR,Location of the command queue in SRAM or flash memory. This register will increment as CQ operations commence. Software should only write CQADDR when CQEN is disabled. however the command queue script itself may update CQADDR in order to perform.."
|
|
hexmask.long 0x0 0.--28. 1. "CQADDR,Address of command queue buffer in SRAM or flash. The buffer address must be aligned to a word boundary."
|
|
line.long 0x4 "CQSTAT,Command Queue Status"
|
|
bitfld.long 0x4 3. "CQPAUSED,Command queue is currently paused status." "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "CQCPL,Command queue operation Complete. This signals the end of the command queue operation." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
|
|
line.long 0x8 "CQFLAGS,Command Queue Flags"
|
|
hexmask.long.word 0x8 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
|
|
line.long 0xC "CQSETCLEAR,Command Queue Flag Set/Clear"
|
|
hexmask.long.byte 0xC 16.--23. 1. "CQFCLR,Clear CQFlag status bits."
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "CQFTOGGLE,Toggle CQFlag status bits"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CQFSET,Set CQFlag status bits. Set has priority over clear if both are high."
|
|
line.long 0x10 "CQPAUSE,Command Queue Pause Mask"
|
|
hexmask.long.word 0x10 0.--15. 1. "CQMASK,CQ will pause processing when ALL specified events are satisfied -- i.e. when (CQMASK and CQPAUSE)==CQMASK."
|
|
group.long 0x2C0++0x7
|
|
line.long 0x0 "CQCURIDX,This register can be used in conjunction with the CQENDIDX register to manage the command queue. Typically software will initialize the CQCURIDX and CQENDIDX to the same value. which will cause the CQ to be paused when enabled. Software may then.."
|
|
hexmask.long.byte 0x0 0.--7. 1. "CQCURIDX,Can be used to indicate the current position of the command queue by having CQ operations write this field. A CQ hardware status flag indicates when CURIDX and ENDIDX are not equal allowing SW to pause the CQ processing until the end index is.."
|
|
line.long 0x4 "CQENDIDX,Command Queue End Index"
|
|
hexmask.long.byte 0x4 0.--7. 1. "CQENDIDX,Can be used to indicate the end position of the command queue. A CQ hardware status bit indices when CURIDX != ENDIDX so that the CQ can be paused when it reaches the end pointer."
|
|
group.long 0x310++0x3
|
|
line.long 0x0 "STATXIPDMA,Debug XIP DMA State"
|
|
hexmask.long 0x0 0.--31. 1. "FLD32,XIP/DMA module debug"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
tree "MSPI2"
|
|
base ad:0x40062000
|
|
group.long 0x0++0x23
|
|
line.long 0x0 "CTRL,This register is used to enable individual PIO based transactions to a device on the bus. The CFG register must be programmed properly for the transfer. and the ADDR and INSTR registers should be programmed if the SENDI and SENDA fields are enabled."
|
|
hexmask.long.word 0x0 16.--31. 1. "XFERBYTES,Number of bytes to transmit or receive (based on TXRX bit)"
|
|
newline
|
|
bitfld.long 0x0 12. "ENWLAT,Enable Write Latency Counter (time between address and first data byte). Counter value is WRITELATENCY." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "ENDCX,Enable DCX signal on data [1]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ENTURN,Indicates whether TX->RX turnaround cycles should be enabled for this operation (see TURNAROUND field in CFG register)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PIOSCRAMBLE,Enables data scrambling for PIO opertions. This should only be used for data operations and never for commands to a device." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "BIGENDIAN,1 indicates data in FIFO is in big endian format (MSB first); 0 indicates little endian data (default LSB first)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXRX,1 Indicates a TX operation 0 indicates an RX operation of XFERBYTES" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "SENDI,Indicates whether an instruction phase should be sent (see INSTR field and ISIZE field in CFG register)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SENDA,Indicates whether an address phase should be sent (see ADDR register and ASIZE field in CFG register)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PIODEV,Selects the Device configutation to use for PIO requests" "0: Use DEVICE0 Configuration,1: Use DEVICE1 CONFIGURATION"
|
|
newline
|
|
bitfld.long 0x0 2. "BUSY,Command status: 1 indicates controller is busy (command in progress)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STATUS,Command status: 1 indicates command has completed. Cleared by writing 1 to this bit or starting a new transfer." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Write to 1 to initiate a PIO transaction on the bus (typically the entire register should be written at once with this bit set)." "0,1"
|
|
line.long 0x4 "CTRL1,These registers are used to enable individual PIO based transactions to a device on the bus. The CFG register must be programmed properly for the transfer. and the ADDR and INSTR registers should be programmed if the SENDI and SENDA fields are.."
|
|
hexmask.long.byte 0x4 0.--3. 1. "PIOMIXED,Provides override controls for data operations where instruction address and data may transfer in different rates."
|
|
line.long 0x8 "ADDR,Optional Address field to send for PIO transfers"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,Optional Address field to send (after optional instruction field) - qualified by ASIZE in CMD register. NOTE: This register is aliased to DMADEVADDR."
|
|
line.long 0xC "INSTR,Optional Instruction field to send for PIO transfers"
|
|
hexmask.long.word 0xC 0.--15. 1. "INSTR,Optional Instruction field to send (1st byte) - qualified by ISEND/ISIZE"
|
|
line.long 0x10 "TXFIFO,TX Data FIFO"
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hexmask.long 0x10 0.--31. 1. "TXFIFO,Data to be transmitted. Data should normally be aligned to the LSB (pad the upper bits with zeros) unless BIGENDIAN is set."
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line.long 0x14 "RXFIFO,RX Data FIFO"
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hexmask.long 0x14 0.--31. 1. "RXFIFO,Receive data. Data is aligned to the LSB (padded zeros on upper bits) unless BIGENDIAN is set."
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line.long 0x18 "TXENTRIES,Number of words in TX FIFO"
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hexmask.long.byte 0x18 0.--5. 1. "TXENTRIES,Number of 32-bit words/entries in TX FIFO"
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line.long 0x1C "RXENTRIES,Number of words in RX FIFO"
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hexmask.long.byte 0x1C 0.--5. 1. "RXENTRIES,Number of 32-bit words/entries in RX FIFO"
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line.long 0x20 "THRESHOLD,Threshold levels that trigger RXFull and TXEmpty interrupts"
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hexmask.long.byte 0x20 8.--13. 1. "RXTHRESH,Number of entries in TX FIFO that cause RXE interrupt"
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hexmask.long.byte 0x20 0.--5. 1. "TXTHRESH,Number of entries in TX FIFO that cause TXF interrupt"
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group.long 0x30++0x3
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line.long 0x0 "MSPICFG,Timing configuration bits for the MSPI module. PRSTN. IPRSTN. and FIFORESET can be used to reset portions of the MSPI interface in order to clear error conditions. The remaining bits control clock frequency and TX/RX capture timings."
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bitfld.long 0x0 31. "PRSTN,Peripheral reset. Master reset to the entire MSPI module (DMA XIP and transfer state machines). 1=normal operation 0=in reset." "0: in reset,1: normal operation"
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bitfld.long 0x0 30. "IPRSTN,IP block reset. Write to 0 to put the transfer module in reset or 1 for normal operation. This may be required after error conditions to clear the transfer on the bus." "0,1"
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bitfld.long 0x0 29. "FIFORESET,Reset MSPI FIFO (active high). 1=reset FIFO 0=normal operation. May be used to manually flush the FIFO in error handling." "0: normal operation,1: reset FIFO"
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hexmask.long.byte 0x0 4.--7. 1. "IOMSEL,Selects which IOM is selected for CQ handshake status."
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bitfld.long 0x0 0. "APBCLK,Enable continuous APB clock. For power-efficient operation APBCLK should be set to 0." "0: Disable continuous clock.,1: Enable continuous clock."
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group.long 0x44++0xB
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line.long 0x0 "PADOUTEN,Enable bits for the MSPI output pads. Each active MSPI line should be set to 1 in the OUTEN field below."
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bitfld.long 0x0 31. "CLKOND4,Output clock on MSPI data[4]" "0,1"
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bitfld.long 0x0 30. "PADSET1,Only applicable on mspi1. When set use gpio95 .. gpio 104 as the pads. This extra set of pads is to run mspi0 on HEX and mspi1 concurrently. Note that the timing of this extra pads may not be as good as the origianl pads." "0,1"
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hexmask.long.tbyte 0x0 0.--19. 1. "OUTEN,Output pad enable configuration. Indicates which pads should be driven. Bits [3:0] are Quad0 data. Bits [7:4] are Quad1 data. Bit [8] is clock. Bit [9] is BM/DQS. Bit [10:17] are data for 16-bit. Bit[18] is BM/DQS for 16-bit. Bit[19] is not used."
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line.long 0x4 "PADOVEREN,Enables PIO-like pad override control"
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hexmask.long.tbyte 0x4 0.--19. 1. "OVERRIDEEN,Output pad override enable. Bit mask for pad outputs. When set to 1 the values in the OVERRIDE field are driven on the pad (output enable is implicitly set in this mode). [7:0]=data [8]=clock [9]=DM"
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line.long 0x8 "PADOVER,Override data value"
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hexmask.long.tbyte 0x8 0.--19. 1. "OVERRIDE,Output pad override value. [7:0]=data [8]=clock [9]=DM"
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group.long 0x80++0x23
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line.long 0x0 "DEV0AXI,Specifies the base address and aperture range of the device as mapped onto the AXI bus"
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hexmask.long.word 0x0 16.--25. 1. "BASE0,XIPEN has to be enabled to enable aperture. The BASE address needs to be SIZE aligned."
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bitfld.long 0x0 4. "READONLY0,Indicates the AXI aperture is read-only" "0: Indicates AXI aperture supports read and write..,1: Indicates AXI aperture only supports read.."
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hexmask.long.byte 0x0 0.--3. 1. "SIZE0,Indicates the AXI aperture size"
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line.long 0x4 "DEV0CFG,Command formatting for PIO based transactions (initiated by writes to CTRL register)"
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hexmask.long.byte 0x4 26.--31. 1. "WRITELATENCY0,Number of write Latency cycles. Qualified by ENTURN bit field."
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bitfld.long 0x4 25. "SEPIO0,Separate IO configuration. This bit should be set when the target device has separate MOSI and MISO pins. Respective IN/OUT bits below should be set to map pins." "0,1"
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bitfld.long 0x4 24. "TXNEG0,Launches TX data a half clock cycle (~10ns) early. This should normally be programmed to zero (NORMAL)." "0: TX launched from posedge internal clock,1: TX data launched from negedge of internal clock"
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bitfld.long 0x4 23. "RXNEG0,Adjusts the RX capture phase to the negedge of the 48MHz internal clock (~10ns early). For normal operation it is expected that RXNEG will be set to 0." "0: RX data sampled on posedge of internal clock,1: RX data sampled on negedge of internal clock"
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bitfld.long 0x4 22. "RXCAP0,Controls RX data capture phase. A setting of 0 (NORMAL) captures read data at the normal capture point relative to the internal clock launch point. However to accomodate chip/pad/board delays a setting of RXCAP of 1 is expected to be used to.." "0: RX Capture phase aligns with CPHA setting,1: RX Capture phase is delayed from CPHA setting by.."
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hexmask.long.byte 0x4 16.--21. 1. "CLKDIV0,Clock Divider. Allows dividing 96 MHz base clock by integer multiples. Enumerations are provided for common frequency but any integer divide from 96 MHz is allowed. Odd divide ratios will result in a 33/66 percent duty cycle with a long low.."
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bitfld.long 0x4 15. "CPOL0,Serial clock polarity." "0: Clock inactive state is low.,1: Clock inactive state is high."
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bitfld.long 0x4 14. "CPHA0,Serial clock phase." "0: Clock toggles in middle of data bit.,1: Clock toggles at start of data bit."
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hexmask.long.byte 0x4 8.--13. 1. "TURNAROUND0,Number of turnaound cycles (for TX->RX transitions). Qualified by ENTURN bit field."
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bitfld.long 0x4 7. "ISIZE0,Instruction Size" "0: Instruction is 1 byte,1: Instruction is 2 bytes"
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bitfld.long 0x4 5.--6. "ASIZE0,Address Size. Address bytes to send from ADDR register" "0: Send one address byte,1: Send two address bytes,2: Send three address bytes,3: Send four address bytes"
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hexmask.long.byte 0x4 0.--4. 1. "DEVCFG0,Flash configuration for XIP and AUTO DMA operations. Controls value for SER (Slave Enable) for XIP operations and address generation for DMA/XIP modes. Also used to configure SPIFRF (frame format)."
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line.long 0x8 "DEV0DDR,Timing configuration bits for DDR operation of the MSPI module."
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bitfld.long 0x8 31. "RXDQSDELAYHIEN0,When 1 RXDQSDELAYHI and RXDQSDELAYNEGHI is used for falling edge of the clock." "0,1"
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hexmask.long.byte 0x8 26.--30. 1. "RXDQSDELAYNEGHI0,This acts as an offset to the computed value (should be set to 0 by default) of falling edge for 2nd DQS on HEX mode."
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hexmask.long.byte 0x8 21.--25. 1. "RXDQSDELAYHI0,This acts as an offset to the computed value (should be set to 0 by default) for 2nd DQS on HEX mode."
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bitfld.long 0x8 20. "RXDQSDELAYNEGEN0,When 1 RXDQSDELAYNEG is used for falling edge of the clock." "0,1"
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hexmask.long.byte 0x8 15.--19. 1. "RXDQSDELAYNEG0,This acts as an offset to the computed value (should be set to 0 by default) of falling edge."
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hexmask.long.byte 0x8 10.--14. 1. "RXDQSDELAY0,This acts as an offset to the computed value (should be set to 0 by default)"
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hexmask.long.byte 0x8 5.--9. 1. "TXDQSDELAY0,This acts as an offset to the computed value (should be set to 0 by default)"
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bitfld.long 0x8 4. "ENABLEFINEDELAY0,Enables use of delay line to provide fine control over traditional RX capture clock." "0,1"
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bitfld.long 0x8 3. "DQSSYNCNEG0,Use negative edge of clock for DDR data sync" "0,1"
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bitfld.long 0x8 2. "ENABLEDQS0,In EMULATEDDR mode enable DQS for read capture" "0,1"
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bitfld.long 0x8 1. "QUADDDR0,Deprecated. No effect on RevC." "0,1"
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bitfld.long 0x8 0. "EMULATEDDR0,Drive external clock at 1/2 rate to emulate DDR mode" "0,1"
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line.long 0xC "DEV0CFG1,Timing and mode configuration bits for the MSPI module."
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bitfld.long 0xC 14.--16. "DQSTURN0,In DQS mode the internal cycle count to enable DQS path." "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 13. "RXHI0,Force st_rx to start at clock high of mspi_clk" "0,1"
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bitfld.long 0xC 12. "TAFOURTH0,Add 1/4th mspi_clk in DDR to turnaround. Recommended set this to 1 when EMULATEDDR is set in non-DQS mode (ENABLEDQS = 0)." "0,1"
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bitfld.long 0xC 11. "HYPERIO0,When using Windbond set this bit to 1 to generate CA[47:0] in hardware." "0,1"
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bitfld.long 0xC 9.--10. "RXSMP0,Sampling edge based on sclk edge. No effect when div1" "0,1,2,3"
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bitfld.long 0xC 8. "RBX0,Enable the support of RBX ( page boundary crossing on read )" "0,1"
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bitfld.long 0xC 7. "WBX0,Enable the support of WBX ( page boundary crossing on write )" "0,1"
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bitfld.long 0xC 5. "SCLKRXHALT0,Halt sclk based on xfer_count" "0,1"
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bitfld.long 0xC 4. "RXCAPEXT0,Specify the number of apb_clk of RX capture phse {RXCAPEXT RXCAP}" "0,1"
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hexmask.long.byte 0xC 0.--3. 1. "SFTURN0,Subtract from internal counter of write latency and turnaround"
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line.long 0x10 "DEV0XIP,When any SPI flash is configured. this register must be properly programmed before XIP or AUTO DMA operations commence."
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hexmask.long.byte 0x10 20.--25. 1. "XIPWRITELATENCY0,Number of write Latency cycles. Qualified by XIPENWLAT bit field."
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hexmask.long.byte 0x10 14.--19. 1. "XIPTURNAROUND0,Number of turnaound cycles (for TX->RX transitions). Qualified by XIPENTURN bit field."
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bitfld.long 0x10 13. "XIPENWLAT0,Enable Write Latency counter for XIP write transactions" "0,1"
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bitfld.long 0x10 12. "XIPENDCX0,Enable DCX signal on data [1] for XIP/DMA operations" "0,1"
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hexmask.long.byte 0x10 8.--11. 1. "XIPMIXED0,Provides override controls for data operations where instruction address and data may transfer in different rates."
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bitfld.long 0x10 7. "XIPSENDI0,Indicates whether XIP/AUTO DMA operations should send an instruction (see READINSTR field and ISIZE field in CFG)" "0,1"
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bitfld.long 0x10 6. "XIPSENDA0,Indicates whether XIP/AUTO DMA operations should send an an address phase (see DMADEVADDR register and ASIZE field in CFG)" "0,1"
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bitfld.long 0x10 5. "XIPENTURN0,Indicates whether XIP/AUTO DMA operations should enable TX->RX turnaround cycles" "0,1"
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bitfld.long 0x10 4. "XIPBIGENDIAN0,Indicates whether XIP/AUTO DMA data transfers are in big or little endian format" "0,1"
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bitfld.long 0x10 2.--3. "XIPACK0,Controls transmission of Micron XIP acknowledge cycles (Micron Flash devices only)" "0: No acknowledege sent. Data IOs are tristated the..,?,2: Positive acknowledege sent. Data IOs are driven..,3: Negative acknowledege sent. Data IOs are driven.."
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bitfld.long 0x10 0. "XIPEN0,Enable the XIP (eXecute In Place) function which effectively enables the address decoding of the MSPI device in the flash/cache address space at address 0x04000000-0x07FFFFFF." "0,1"
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line.long 0x14 "DEV0INSTR,When any SPI flash is configured. this register must be properly programmed before XIP or AUTO DMA operations commence."
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hexmask.long.word 0x14 16.--31. 1. "READINSTR0,Read command sent to flash for DMA/XIP operations"
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hexmask.long.word 0x14 0.--15. 1. "WRITEINSTR0,Write command sent for DMA operations"
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line.long 0x18 "DEV0BOUNDARY,Allows large transfers to be broken up into smaller ones in hardware to accommodate needs of external devices and allow XIP/XIPMM. Only applicable for memory-mapped devices (PSRAM. Flash. etc) where address can be retransmitted without side.."
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hexmask.long.byte 0x18 12.--15. 1. "DMABOUND0,DMA Address boundary"
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hexmask.long.word 0x18 0.--11. 1. "DMATIMELIMIT0,DMA time limit. Can be used to limit the transaction time on the MSPI bus. The count is in ~100 ns increments for the 96 MHz clock input. A value of 0 disables the counter."
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line.long 0x1C "DEV0SCRAMBLING,Enables data scrambling for the specified range external flash addresses. Scrambling does not impact flash access performance."
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bitfld.long 0x1C 31. "SCRENABLE0,Enables Data Scrambling Region. When 1 reads and writes to the range will be scrambled. When 0 data will be read/written unmodified. Address range is specified in 64K granularity and the START/END ranges are included within the range." "0,1"
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hexmask.long.word 0x1C 16.--25. 1. "SCREND0,Scrambling region end address [25:16] (64K block granularity). The END block is the LAST block included in the scrambled address range."
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hexmask.long.word 0x1C 0.--9. 1. "SCRSTART0,Scrambling region start address [25:16] (64K block granularity). The START block is the FIRST block included in the scrambled address range."
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line.long 0x20 "DEV0XIPMISC,Miscellaneous XIP control registers for AXI logic"
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bitfld.long 0x20 21. "APNDODD0,Append dummy byte to odd number of write" "0: No appending byte,1: Append one dummy byte"
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bitfld.long 0x20 15. "XIPBOUNDARY0,Deprecated. No effect on RevC." "0: ERROR: desc VALUE MISSING,1: ERROR: desc VALUE MISSING"
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bitfld.long 0x20 14. "BEON0,Byte enable always on for all lanes" "0: Byte enable is calculated on the fly,1: Byte enable of all bytes are always on"
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bitfld.long 0x20 13. "BEPOL0,byte mask polarity to MSPI xfer" "0,1"
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bitfld.long 0x20 12. "XIPODD0,Convert odd starting address to word-aligned starting address with byte-enables for holes. For example an AXI transaction with wstrb of 0x0600 results in mspi transaction of addr=8 and BE=0b1001 ( active low )." "0: No conversion,1: Enable the conversion"
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hexmask.long.word 0x20 0.--11. 1. "CEBREAK0,CEBREAK0 field description needed."
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group.long 0x100++0x1B
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line.long 0x0 "DMACFG,DMA Configuration"
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bitfld.long 0x0 18. "DMAPWROFF,Power off MSPI domain upon completion of DMA operation." "0,1"
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bitfld.long 0x0 17. "DMATXEMPT,For DMA_M2P only start when DMA fifo is not empty." "0,1"
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bitfld.long 0x0 4.--5. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately),2: Auto Priority (priority raised once TX FIFO..,?"
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bitfld.long 0x0 3. "DMADEV,DMA Device Select" "0: Select Device 0 for DMA,?"
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bitfld.long 0x0 2. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction,1: Memory to Peripheral transaction"
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bitfld.long 0x0 0.--1. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation" "0: Disable DMA Function,?,?,3: Enable HW controlled DMA Function to manage DMA.."
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line.long 0x4 "DMASTAT,DMA Status"
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bitfld.long 0x4 3. "SCRERR,Scrambling Access Alignment Error. This active high bit signals that a scrambling operation was specified for a non-word aligned DEVADDR." "0,1"
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bitfld.long 0x4 2. "DMAERR,DMA Error. This active high bit signals that an error was encountered during the DMA operation." "0,1"
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bitfld.long 0x4 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation." "0,1"
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bitfld.long 0x4 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority. All of these will be indicated with a 1. A 0 will indicate that the DMA is.." "0,1"
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line.long 0x8 "DMATARGADDR,DMA Target Address"
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hexmask.long 0x8 0.--31. 1. "TARGADDR,Target byte address for source of DMA (either read or write). In cases of non-word aligned addresses the DMA logic will take care for ensuring only the target bytes are read/written."
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line.long 0xC "DMADEVADDR,DMA Device Address"
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hexmask.long 0xC 0.--31. 1. "DEVADDR,SPI Device address for automated DMA transactions (both read and write)."
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line.long 0x10 "DMATOTCOUNT,DMA Total Transfer Count"
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hexmask.long.tbyte 0x10 0.--23. 1. "TOTCOUNT,Total Transfer Count in bytes."
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line.long 0x14 "DMABCOUNT,DMA BYTE Transfer Count"
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hexmask.long.byte 0x14 0.--7. 1. "BCOUNT,Burst transfer size in bytes. This is the number of bytes transferred when a FIFO trigger event occurs. Recommended value is 32."
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line.long 0x18 "DMATHRESH,Indicates FIFO level at which a DMA should be triggered. For most configurations. a setting of 8 is recommended for both read and write operations."
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hexmask.long.byte 0x18 8.--12. 1. "DMARXTHRESH,DMA transfer FIFO level trigger. For read operations DMA is triggered when the FIFO level is greater than this value. For write operations DMA is triggered when the FIFO level is less than this level. Each DMA operation will consist of.."
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hexmask.long.byte 0x18 0.--4. 1. "DMATXTHRESH,DMA transfer FIFO level trigger. For read operations DMA is triggered when the FIFO level is greater than this value. For write operations DMA is triggered when the FIFO level is less than this level. Each DMA operation will consist of.."
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group.long 0x200++0xF
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line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
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bitfld.long 0x0 13. "APBDMAERR,MSPI is dma target as well as dma source which may result in deadlock." "0,1"
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bitfld.long 0x0 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
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bitfld.long 0x0 11. "CQERR,Command Queue Error Interrupt" "0,1"
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bitfld.long 0x0 10. "CQPAUSED,Command Queue is Paused." "0,1"
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bitfld.long 0x0 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
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bitfld.long 0x0 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
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bitfld.long 0x0 7. "DERR,DMA Error Interrupt" "0,1"
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bitfld.long 0x0 6. "DCMP,DMA Complete Interrupt" "0,1"
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bitfld.long 0x0 5. "RXF,Receive FIFO full" "0,1"
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bitfld.long 0x0 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
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bitfld.long 0x0 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
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bitfld.long 0x0 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
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bitfld.long 0x0 1. "TXE,Transmit FIFO empty." "0,1"
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bitfld.long 0x0 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
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line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
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bitfld.long 0x4 13. "APBDMAERR,MSPI is dma target as well as dma source which may result in deadlock." "0,1"
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bitfld.long 0x4 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
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bitfld.long 0x4 11. "CQERR,Command Queue Error Interrupt" "0,1"
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bitfld.long 0x4 10. "CQPAUSED,Command Queue is Paused." "0,1"
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bitfld.long 0x4 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
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bitfld.long 0x4 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
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bitfld.long 0x4 7. "DERR,DMA Error Interrupt" "0,1"
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bitfld.long 0x4 6. "DCMP,DMA Complete Interrupt" "0,1"
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bitfld.long 0x4 5. "RXF,Receive FIFO full" "0,1"
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bitfld.long 0x4 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
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bitfld.long 0x4 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
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bitfld.long 0x4 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
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|
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bitfld.long 0x4 1. "TXE,Transmit FIFO empty." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 13. "APBDMAERR,MSPI is dma target as well as dma source which may result in deadlock." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "CQERR,Command Queue Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "CQPAUSED,Command Queue is Paused." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "DERR,DMA Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "DCMP,DMA Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "RXF,Receive FIFO full" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "TXE,Transmit FIFO empty." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 13. "APBDMAERR,MSPI is dma target as well as dma source which may result in deadlock." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "CQERR,Command Queue Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "CQPAUSED,Command Queue is Paused." "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "DERR,DMA Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "DCMP,DMA Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "RXF,Receive FIFO full" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "TXE,Transmit FIFO empty." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
|
|
group.long 0x2A0++0x3
|
|
line.long 0x0 "CQCFG,This register controls Command Queuing (CQ) operations in a manner similar to the DMACFG register."
|
|
bitfld.long 0x0 4. "CQPAUSEOP,CQPAUSEOP register description needed." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CQAUTOCLEARMASK,Enable clear of CQMASK after each pause operation. This may be useful when using software flags to pause CQ." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CQPWROFF,Power off MSPI domain upon completion of DMA operation." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CQPRI,Sets the Priority of the command queue DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
|
|
newline
|
|
bitfld.long 0x0 0. "CQEN,Command queue enable. When set will enable the processing of the command queue" "0: Disable CQ Function,1: Enable CQ Function"
|
|
group.long 0x2A8++0x13
|
|
line.long 0x0 "CQADDR,Location of the command queue in SRAM or flash memory. This register will increment as CQ operations commence. Software should only write CQADDR when CQEN is disabled. however the command queue script itself may update CQADDR in order to perform.."
|
|
hexmask.long 0x0 0.--28. 1. "CQADDR,Address of command queue buffer in SRAM or flash. The buffer address must be aligned to a word boundary."
|
|
line.long 0x4 "CQSTAT,Command Queue Status"
|
|
bitfld.long 0x4 3. "CQPAUSED,Command queue is currently paused status." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CQCPL,Command queue operation Complete. This signals the end of the command queue operation." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
|
|
line.long 0x8 "CQFLAGS,Command Queue Flags"
|
|
hexmask.long.word 0x8 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
|
|
line.long 0xC "CQSETCLEAR,Command Queue Flag Set/Clear"
|
|
hexmask.long.byte 0xC 16.--23. 1. "CQFCLR,Clear CQFlag status bits."
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "CQFTOGGLE,Toggle CQFlag status bits"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CQFSET,Set CQFlag status bits. Set has priority over clear if both are high."
|
|
line.long 0x10 "CQPAUSE,Command Queue Pause Mask"
|
|
hexmask.long.word 0x10 0.--15. 1. "CQMASK,CQ will pause processing when ALL specified events are satisfied -- i.e. when (CQMASK and CQPAUSE)==CQMASK."
|
|
group.long 0x2C0++0x7
|
|
line.long 0x0 "CQCURIDX,This register can be used in conjunction with the CQENDIDX register to manage the command queue. Typically software will initialize the CQCURIDX and CQENDIDX to the same value. which will cause the CQ to be paused when enabled. Software may then.."
|
|
hexmask.long.byte 0x0 0.--7. 1. "CQCURIDX,Can be used to indicate the current position of the command queue by having CQ operations write this field. A CQ hardware status flag indicates when CURIDX and ENDIDX are not equal allowing SW to pause the CQ processing until the end index is.."
|
|
line.long 0x4 "CQENDIDX,Command Queue End Index"
|
|
hexmask.long.byte 0x4 0.--7. 1. "CQENDIDX,Can be used to indicate the end position of the command queue. A CQ hardware status bit indices when CURIDX != ENDIDX so that the CQ can be paused when it reaches the end pointer."
|
|
group.long 0x310++0x3
|
|
line.long 0x0 "STATXIPDMA,Debug XIP DMA State"
|
|
hexmask.long 0x0 0.--31. 1. "FLD32,XIP/DMA module debug"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("AMAP42KL")||cpuis("AMA4B2KL"))
|
|
tree "MSPI0"
|
|
base ad:0x40060000
|
|
group.long 0x0++0x23
|
|
line.long 0x0 "CTRL,This register is used to enable individual PIO based transactions to a device on the bus. The CFG register must be programmed properly for the transfer. and the ADDR and INSTR registers should be programmed if the SENDI and SENDA fields are enabled."
|
|
hexmask.long.word 0x0 16.--31. 1. "XFERBYTES,Number of bytes to transmit or receive (based on TXRX bit)"
|
|
newline
|
|
bitfld.long 0x0 13. "HALFWORDREVERSE,Reverse bytes in half-word. Little endian data: {[7:0] [15:8] [23:16] [31:24]} -> {[15:8] [7:0] [31:24] [23:16]}; big endian data: {[31:24] [23:16] [15:8] [7:0]} -> {[23:16] [31:24] [7:0] [15:8]}" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENWLAT,Enable Write Latency Counter (time between address and first data byte). Counter value is WRITELATENCY." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "ENDCX,Enable DCX signal on data [1]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ENTURN,Indicates whether TX->RX turnaround cycles should be enabled for this operation (see TURNAROUND field in CFG register)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PIOSCRAMBLE,Enables data scrambling for PIO opertions. This should only be used for data operations and never for commands to a device." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "BIGENDIAN,1 indicates data in FIFO is in big endian format (MSB first); 0 indicates little endian data (default LSB first)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXRX,1 Indicates a TX operation 0 indicates an RX operation of XFERBYTES" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "SENDI,Indicates whether an instruction phase should be sent (see INSTR field and ISIZE field in CFG register)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SENDA,Indicates whether an address phase should be sent (see ADDR register and ASIZE field in CFG register)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PIODEV,Selects the Device configutation to use for PIO requests" "0: Use DEVICE0 Configuration,1: Use DEVICE1 CONFIGURATION"
|
|
newline
|
|
bitfld.long 0x0 2. "BUSY,Command status: 1 indicates controller is busy (command in progress)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STATUS,Command status: 1 indicates command has completed. Cleared by writing 1 to this bit or starting a new transfer." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Write to 1 to initiate a PIO transaction on the bus (typically the entire register should be written at once with this bit set)." "0,1"
|
|
line.long 0x4 "CTRL1,These registers are used to enable individual PIO based transactions to a device on the bus. The CFG register must be programmed properly for the transfer. and the ADDR and INSTR registers should be programmed if the SENDI and SENDA fields are.."
|
|
hexmask.long.byte 0x4 0.--3. 1. "PIOMIXED,Provides override controls for data operations where instruction address and data may transfer in different rates."
|
|
line.long 0x8 "ADDR,Optional Address field to send for PIO transfers"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,Optional Address field to send (after optional instruction field) - qualified by ASIZE in CMD register. NOTE: This register is aliased to DMADEVADDR."
|
|
line.long 0xC "INSTR,Optional Instruction field to send for PIO transfers"
|
|
hexmask.long.word 0xC 0.--15. 1. "INSTR,Optional Instruction field to send (1st byte) - qualified by ISEND/ISIZE"
|
|
line.long 0x10 "TXFIFO,TX Data FIFO"
|
|
hexmask.long 0x10 0.--31. 1. "TXFIFO,Data to be transmitted. Data should normally be aligned to the LSB (pad the upper bits with zeros) unless BIGENDIAN is set."
|
|
line.long 0x14 "RXFIFO,RX Data FIFO"
|
|
hexmask.long 0x14 0.--31. 1. "RXFIFO,Receive data. Data is aligned to the LSB (padded zeros on upper bits) unless BIGENDIAN is set."
|
|
line.long 0x18 "TXENTRIES,Number of words in TX FIFO"
|
|
hexmask.long.byte 0x18 0.--5. 1. "TXENTRIES,Number of 32-bit words/entries in TX FIFO"
|
|
line.long 0x1C "RXENTRIES,Number of words in RX FIFO"
|
|
hexmask.long.byte 0x1C 0.--5. 1. "RXENTRIES,Number of 32-bit words/entries in RX FIFO"
|
|
line.long 0x20 "THRESHOLD,Threshold levels that trigger RXFull and TXEmpty interrupts"
|
|
hexmask.long.byte 0x20 8.--13. 1. "RXTHRESH,Number of entries in TX FIFO that cause RXE interrupt"
|
|
newline
|
|
hexmask.long.byte 0x20 0.--5. 1. "TXTHRESH,Number of entries in TX FIFO that cause TXF interrupt"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "MSPICFG,Timing configuration bits for the MSPI module. PRSTN. IPRSTN. and FIFORESET can be used to reset portions of the MSPI interface in order to clear error conditions. The remaining bits control clock frequency and TX/RX capture timings."
|
|
bitfld.long 0x0 31. "PRSTN,Peripheral reset. Master reset to the entire MSPI module (DMA XIP and transfer state machines). 1=normal operation 0=in reset." "0: in reset,1: normal operation"
|
|
newline
|
|
bitfld.long 0x0 30. "IPRSTN,IP block reset. Write to 0 to put the transfer module in reset or 1 for normal operation. This may be required after error conditions to clear the transfer on the bus." "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "FIFORESET,Reset MSPI FIFO (active high). 1=reset FIFO 0=normal operation. May be used to manually flush the FIFO in error handling." "0: normal operation,1: reset FIFO"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "IOMSEL,Selects which IOM is selected for CQ handshake status."
|
|
newline
|
|
bitfld.long 0x0 0. "APBCLK,Enable continuous APB clock. For power-efficient operation APBCLK should be set to 0." "0: Disable continuous clock.,1: Enable continuous clock."
|
|
group.long 0x44++0xB
|
|
line.long 0x0 "PADOUTEN,Enable bits for the MSPI output pads. Each active MSPI line should be set to 1 in the OUTEN field below."
|
|
bitfld.long 0x0 31. "CLKOND4,Output clock on MSPI data[4]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "PADSET1,Only applicable on mspi1. When set use gpio95 .. gpio 104 as the pads. This extra set of pads is to run mspi0 on HEX and mspi1 concurrently. Note that the timing of this extra pads may not be as good as the origianl pads." "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "OUTEN,Output pad enable configuration. Indicates which pads should be driven. Bits [3:0] are Quad0 data. Bits [7:4] are Quad1 data. Bit [8] is clock. Bit [9] is BM/DQS. Bit [10:17] are data for 16-bit. Bit[18] is BM/DQS for 16-bit. Bit[19] is not used."
|
|
line.long 0x4 "PADOVEREN,Enables PIO-like pad override control"
|
|
hexmask.long.tbyte 0x4 0.--19. 1. "OVERRIDEEN,Output pad override enable. Bit mask for pad outputs. When set to 1 the values in the OVERRIDE field are driven on the pad (output enable is implicitly set in this mode). [7:0]=data [8]=clock [9]=DM"
|
|
line.long 0x8 "PADOVER,Override data value"
|
|
hexmask.long.tbyte 0x8 0.--19. 1. "OVERRIDE,Output pad override value. [7:0]=data [8]=clock [9]=DM"
|
|
group.long 0x80++0x23
|
|
line.long 0x0 "DEV0AXI,Specifies the base address and aperture range of the device as mapped onto the AXI bus"
|
|
hexmask.long.word 0x0 16.--25. 1. "BASE0,XIPEN has to be enabled to enable aperture. The BASE address needs to be SIZE aligned."
|
|
newline
|
|
bitfld.long 0x0 4. "READONLY0,Indicates the AXI aperture is read-only" "0: Indicates AXI aperture supports read and write..,1: Indicates AXI aperture only supports read.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SIZE0,Indicates the AXI aperture size"
|
|
line.long 0x4 "DEV0CFG,Command formatting for PIO based transactions (initiated by writes to CTRL register)"
|
|
hexmask.long.byte 0x4 26.--31. 1. "WRITELATENCY0,Number of write Latency cycles. Qualified by ENTURN bit field."
|
|
newline
|
|
bitfld.long 0x4 25. "SEPIO0,Separate IO configuration. This bit should be set when the target device has separate MOSI and MISO pins. Respective IN/OUT bits below should be set to map pins." "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "TXNEG0,Launches TX data a half clock cycle (~10ns) early. This should normally be programmed to zero (NORMAL)." "0: TX launched from posedge internal clock,1: TX data launched from negedge of internal clock"
|
|
newline
|
|
bitfld.long 0x4 23. "RXNEG0,Adjusts the RX capture phase to the negedge of the 48MHz internal clock (~10ns early). For normal operation it is expected that RXNEG will be set to 0." "0: RX data sampled on posedge of internal clock,1: RX data sampled on negedge of internal clock"
|
|
newline
|
|
bitfld.long 0x4 22. "RXCAP0,Controls RX data capture phase. A setting of 0 (NORMAL) captures read data at the normal capture point relative to the internal clock launch point. However to accomodate chip/pad/board delays a setting of RXCAP of 1 is expected to be used to.." "0: RX Capture phase aligns with CPHA setting,1: RX Capture phase is delayed from CPHA setting by.."
|
|
newline
|
|
hexmask.long.byte 0x4 16.--21. 1. "CLKDIV0,Clock Divider. Allows dividing 96 MHz base clock by integer multiples. Enumerations are provided for common frequency but any integer divide from 96 MHz is allowed. Odd divide ratios will result in a 33/66 percent duty cycle with a long low.."
|
|
newline
|
|
bitfld.long 0x4 15. "CPOL0,Serial clock polarity." "0: Clock inactive state is low.,1: Clock inactive state is high."
|
|
newline
|
|
bitfld.long 0x4 14. "CPHA0,Serial clock phase." "0: Clock toggles in middle of data bit.,1: Clock toggles at start of data bit."
|
|
newline
|
|
hexmask.long.byte 0x4 8.--13. 1. "TURNAROUND0,Number of turnaound cycles (for TX->RX transitions). Qualified by ENTURN bit field."
|
|
newline
|
|
bitfld.long 0x4 7. "ISIZE0,Instruction Size" "0: Instruction is 1 byte,1: Instruction is 2 bytes"
|
|
newline
|
|
bitfld.long 0x4 5.--6. "ASIZE0,Address Size. Address bytes to send from ADDR register" "0: Send one address byte,1: Send two address bytes,2: Send three address bytes,3: Send four address bytes"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "DEVCFG0,Flash configuration for XIP and AUTO DMA operations. Controls value for SER (Slave Enable) for XIP operations and address generation for DMA/XIP modes. Also used to configure SPIFRF (frame format)."
|
|
line.long 0x8 "DEV0DDR,Timing configuration bits for DDR operation of the MSPI module."
|
|
bitfld.long 0x8 31. "RXDQSDELAYHIEN0,When 1 RXDQSDELAYHI and RXDQSDELAYNEGHI is used for falling edge of the clock." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 26.--30. 1. "RXDQSDELAYNEGHI0,This acts as an offset to the computed value (should be set to 0 by default) of falling edge for 2nd DQS on HEX mode."
|
|
newline
|
|
hexmask.long.byte 0x8 21.--25. 1. "RXDQSDELAYHI0,This acts as an offset to the computed value (should be set to 0 by default) for 2nd DQS on HEX mode."
|
|
newline
|
|
bitfld.long 0x8 20. "RXDQSDELAYNEGEN0,When 1 RXDQSDELAYNEG is used for falling edge of the clock." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 15.--19. 1. "RXDQSDELAYNEG0,This acts as an offset to the computed value (should be set to 0 by default) of falling edge."
|
|
newline
|
|
hexmask.long.byte 0x8 10.--14. 1. "RXDQSDELAY0,This acts as an offset to the computed value (should be set to 0 by default)"
|
|
newline
|
|
hexmask.long.byte 0x8 5.--9. 1. "TXDQSDELAY0,This acts as an offset to the computed value (should be set to 0 by default)"
|
|
newline
|
|
bitfld.long 0x8 4. "ENABLEFINEDELAY0,Enables use of delay line to provide fine control over traditional RX capture clock." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "DQSSYNCNEG0,Use negative edge of clock for DDR data sync" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ENABLEDQS0,In EMULATEDDR mode enable DQS for read capture" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "QUADDDR0,Deprecated. No effect on RevC." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "EMULATEDDR0,Drive external clock at 1/2 rate to emulate DDR mode" "0,1"
|
|
line.long 0xC "DEV0CFG1,Timing and mode configuration bits for the MSPI module."
|
|
bitfld.long 0xC 14.--16. "DQSTURN0,In DQS mode the internal cycle count to enable DQS path." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0xC 13. "RXHI0,Force st_rx to start at clock high of mspi_clk" "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "TAFOURTH0,Add 1/4th mspi_clk in DDR to turnaround. Recommended set this to 1 when EMULATEDDR is set in non-DQS mode (ENABLEDQS = 0)." "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "HYPERIO0,When using Windbond set this bit to 1 to generate CA[47:0] in hardware." "0,1"
|
|
newline
|
|
bitfld.long 0xC 9.--10. "RXSMP0,Sampling edge based on sclk edge. No effect when div1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 8. "RBX0,Enable the support of RBX ( page boundary crossing on read )" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "WBX0,Enable the support of WBX ( page boundary crossing on write )" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "SCLKRXHALT0,Halt sclk based on xfer_count" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "RXCAPEXT0,Specify the number of apb_clk of RX capture phse {RXCAPEXT RXCAP}" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--3. 1. "SFTURN0,Subtract from internal counter of write latency and turnaround"
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|
line.long 0x10 "DEV0XIP,When any SPI flash is configured. this register must be properly programmed before XIP or AUTO DMA operations commence."
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bitfld.long 0x10 26. "XIPHALFWORDREVERSE0,Indicates whether XIP/AUTO DMA data transfers are in Reverse bytes in half-word format" "0: No change,1: Indicates XIP/AUTO DMA data transfers are in.."
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|
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hexmask.long.byte 0x10 20.--25. 1. "XIPWRITELATENCY0,Number of write Latency cycles. Qualified by XIPENWLAT bit field."
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|
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hexmask.long.byte 0x10 14.--19. 1. "XIPTURNAROUND0,Number of turnaound cycles (for TX->RX transitions). Qualified by XIPENTURN bit field."
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bitfld.long 0x10 13. "XIPENWLAT0,Enable Write Latency counter for XIP write transactions" "0,1"
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bitfld.long 0x10 12. "XIPENDCX0,Enable DCX signal on data [1] for XIP/DMA operations" "0,1"
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hexmask.long.byte 0x10 8.--11. 1. "XIPMIXED0,Provides override controls for data operations where instruction address and data may transfer in different rates."
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bitfld.long 0x10 7. "XIPSENDI0,Indicates whether XIP/AUTO DMA operations should send an instruction (see READINSTR field and ISIZE field in CFG)" "0,1"
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bitfld.long 0x10 6. "XIPSENDA0,Indicates whether XIP/AUTO DMA operations should send an an address phase (see DMADEVADDR register and ASIZE field in CFG)" "0,1"
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bitfld.long 0x10 5. "XIPENTURN0,Indicates whether XIP/AUTO DMA operations should enable TX->RX turnaround cycles" "0,1"
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bitfld.long 0x10 4. "XIPBIGENDIAN0,Indicates whether XIP/AUTO DMA data transfers are in big or little endian format" "0,1"
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bitfld.long 0x10 2.--3. "XIPACK0,Controls transmission of Micron XIP acknowledge cycles (Micron Flash devices only)" "0: No acknowledege sent. Data IOs are tristated the..,?,2: Positive acknowledege sent. Data IOs are driven..,3: Negative acknowledege sent. Data IOs are driven.."
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bitfld.long 0x10 0. "XIPEN0,Enable the XIP (eXecute In Place) function which effectively enables the address decoding of the MSPI device in the flash/cache address space at address 0x04000000-0x07FFFFFF." "0,1"
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line.long 0x14 "DEV0INSTR,When any SPI flash is configured. this register must be properly programmed before XIP or AUTO DMA operations commence."
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hexmask.long.word 0x14 16.--31. 1. "READINSTR0,Read command sent to flash for DMA/XIP operations"
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hexmask.long.word 0x14 0.--15. 1. "WRITEINSTR0,Write command sent for DMA operations"
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|
line.long 0x18 "DEV0BOUNDARY,Allows large transfers to be broken up into smaller ones in hardware to accommodate needs of external devices and allow XIP/XIPMM. Only applicable for memory-mapped devices (PSRAM. Flash. etc) where address can be retransmitted without side.."
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hexmask.long.byte 0x18 12.--15. 1. "DMABOUND0,DMA Address boundary"
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hexmask.long.word 0x18 0.--11. 1. "DMATIMELIMIT0,DMA time limit. Can be used to limit the transaction time on the MSPI bus. The count is in ~100 ns increments for the 96 MHz clock input. A value of 0 disables the counter."
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line.long 0x1C "DEV0SCRAMBLING,Enables data scrambling for the specified range external flash addresses. Scrambling does not impact flash access performance."
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bitfld.long 0x1C 31. "SCRENABLE0,Enables Data Scrambling Region. When 1 reads and writes to the range will be scrambled. When 0 data will be read/written unmodified. Address range is specified in 64K granularity and the START/END ranges are included within the range." "0,1"
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hexmask.long.word 0x1C 16.--25. 1. "SCREND0,Scrambling region end address [25:16] (64K block granularity). The END block is the LAST block included in the scrambled address range."
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hexmask.long.word 0x1C 0.--9. 1. "SCRSTART0,Scrambling region start address [25:16] (64K block granularity). The START block is the FIRST block included in the scrambled address range."
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line.long 0x20 "DEV0XIPMISC,Miscellaneous XIP control registers for AXI logic"
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bitfld.long 0x20 21. "APNDODD0,Append dummy byte to odd number of write" "0: No appending byte,1: Append one dummy byte"
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bitfld.long 0x20 15. "XIPBOUNDARY0,Deprecated. No effect on RevC." "0: ERROR: desc VALUE MISSING,1: ERROR: desc VALUE MISSING"
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bitfld.long 0x20 14. "BEON0,Byte enable always on for all lanes" "0: Byte enable is calculated on the fly,1: Byte enable of all bytes are always on"
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bitfld.long 0x20 13. "BEPOL0,byte mask polarity to MSPI xfer" "0,1"
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bitfld.long 0x20 12. "XIPODD0,Convert odd starting address to word-aligned starting address with byte-enables for holes. For example an AXI transaction with wstrb of 0x0600 results in mspi transaction of addr=8 and BE=0b1001 ( active low )." "0: No conversion,1: Enable the conversion"
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hexmask.long.word 0x20 0.--11. 1. "CEBREAK0,CEBREAK0 field description needed."
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group.long 0x100++0x1B
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line.long 0x0 "DMACFG,DMA Configuration"
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bitfld.long 0x0 18. "DMAPWROFF,Power off MSPI domain upon completion of DMA operation." "0,1"
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bitfld.long 0x0 17. "DMATXEMPT,For DMA_M2P only start when DMA fifo is not empty." "0,1"
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bitfld.long 0x0 4.--5. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately),2: Auto Priority (priority raised once TX FIFO..,?"
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bitfld.long 0x0 3. "DMADEV,DMA Device Select" "0: Select Device 0 for DMA,?"
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bitfld.long 0x0 2. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction,1: Memory to Peripheral transaction"
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bitfld.long 0x0 0.--1. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation" "0: Disable DMA Function,?,?,3: Enable HW controlled DMA Function to manage DMA.."
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line.long 0x4 "DMASTAT,DMA Status"
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bitfld.long 0x4 3. "SCRERR,Scrambling Access Alignment Error. This active high bit signals that a scrambling operation was specified for a non-word aligned DEVADDR." "0,1"
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bitfld.long 0x4 2. "DMAERR,DMA Error. This active high bit signals that an error was encountered during the DMA operation." "0,1"
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bitfld.long 0x4 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation." "0,1"
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bitfld.long 0x4 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority. All of these will be indicated with a 1. A 0 will indicate that the DMA is.." "0,1"
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line.long 0x8 "DMATARGADDR,DMA Target Address"
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hexmask.long 0x8 0.--31. 1. "TARGADDR,Target byte address for source of DMA (either read or write). In cases of non-word aligned addresses the DMA logic will take care for ensuring only the target bytes are read/written."
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line.long 0xC "DMADEVADDR,DMA Device Address"
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hexmask.long 0xC 0.--31. 1. "DEVADDR,SPI Device address for automated DMA transactions (both read and write)."
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line.long 0x10 "DMATOTCOUNT,DMA Total Transfer Count"
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hexmask.long.tbyte 0x10 0.--23. 1. "TOTCOUNT,Total Transfer Count in bytes."
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line.long 0x14 "DMABCOUNT,DMA BYTE Transfer Count"
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hexmask.long.byte 0x14 0.--7. 1. "BCOUNT,Burst transfer size in bytes. This is the number of bytes transferred when a FIFO trigger event occurs. Recommended value is 32."
|
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line.long 0x18 "DMATHRESH,Indicates FIFO level at which a DMA should be triggered. For most configurations. a setting of 8 is recommended for both read and write operations."
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hexmask.long.byte 0x18 8.--12. 1. "DMARXTHRESH,DMA transfer FIFO level trigger. For read operations DMA is triggered when the FIFO level is greater than this value. For write operations DMA is triggered when the FIFO level is less than this level. Each DMA operation will consist of.."
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hexmask.long.byte 0x18 0.--4. 1. "DMATXTHRESH,DMA transfer FIFO level trigger. For read operations DMA is triggered when the FIFO level is greater than this value. For write operations DMA is triggered when the FIFO level is less than this level. Each DMA operation will consist of.."
|
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group.long 0x200++0xF
|
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line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
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bitfld.long 0x0 13. "APBDMAERR,MSPI is dma target as well as dma source which may result in deadlock." "0,1"
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bitfld.long 0x0 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
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|
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bitfld.long 0x0 11. "CQERR,Command Queue Error Interrupt" "0,1"
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bitfld.long 0x0 10. "CQPAUSED,Command Queue is Paused." "0,1"
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bitfld.long 0x0 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
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bitfld.long 0x0 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
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bitfld.long 0x0 7. "DERR,DMA Error Interrupt" "0,1"
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bitfld.long 0x0 6. "DCMP,DMA Complete Interrupt" "0,1"
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bitfld.long 0x0 5. "RXF,Receive FIFO full" "0,1"
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bitfld.long 0x0 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
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bitfld.long 0x0 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
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bitfld.long 0x0 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
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bitfld.long 0x0 1. "TXE,Transmit FIFO empty." "0,1"
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bitfld.long 0x0 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
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line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
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bitfld.long 0x4 13. "APBDMAERR,MSPI is dma target as well as dma source which may result in deadlock." "0,1"
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|
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bitfld.long 0x4 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
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|
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bitfld.long 0x4 11. "CQERR,Command Queue Error Interrupt" "0,1"
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|
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|
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bitfld.long 0x4 10. "CQPAUSED,Command Queue is Paused." "0,1"
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|
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bitfld.long 0x4 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
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bitfld.long 0x4 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
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|
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bitfld.long 0x4 7. "DERR,DMA Error Interrupt" "0,1"
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|
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bitfld.long 0x4 6. "DCMP,DMA Complete Interrupt" "0,1"
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|
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bitfld.long 0x4 5. "RXF,Receive FIFO full" "0,1"
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|
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bitfld.long 0x4 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
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|
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bitfld.long 0x4 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
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|
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bitfld.long 0x4 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
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|
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bitfld.long 0x4 1. "TXE,Transmit FIFO empty." "0,1"
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|
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bitfld.long 0x4 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
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line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
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bitfld.long 0x8 13. "APBDMAERR,MSPI is dma target as well as dma source which may result in deadlock." "0,1"
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|
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bitfld.long 0x8 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
|
|
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|
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bitfld.long 0x8 11. "CQERR,Command Queue Error Interrupt" "0,1"
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|
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|
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bitfld.long 0x8 10. "CQPAUSED,Command Queue is Paused." "0,1"
|
|
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|
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bitfld.long 0x8 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
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|
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bitfld.long 0x8 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
|
|
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|
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bitfld.long 0x8 7. "DERR,DMA Error Interrupt" "0,1"
|
|
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|
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bitfld.long 0x8 6. "DCMP,DMA Complete Interrupt" "0,1"
|
|
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|
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bitfld.long 0x8 5. "RXF,Receive FIFO full" "0,1"
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|
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|
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bitfld.long 0x8 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
|
|
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|
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bitfld.long 0x8 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
|
|
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|
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bitfld.long 0x8 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
|
|
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|
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bitfld.long 0x8 1. "TXE,Transmit FIFO empty." "0,1"
|
|
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|
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bitfld.long 0x8 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 13. "APBDMAERR,MSPI is dma target as well as dma source which may result in deadlock." "0,1"
|
|
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|
|
bitfld.long 0xC 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
|
|
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|
|
bitfld.long 0xC 11. "CQERR,Command Queue Error Interrupt" "0,1"
|
|
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|
|
bitfld.long 0xC 10. "CQPAUSED,Command Queue is Paused." "0,1"
|
|
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|
|
bitfld.long 0xC 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "DERR,DMA Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "DCMP,DMA Complete Interrupt" "0,1"
|
|
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|
|
bitfld.long 0xC 5. "RXF,Receive FIFO full" "0,1"
|
|
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|
|
bitfld.long 0xC 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
|
|
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|
|
bitfld.long 0xC 1. "TXE,Transmit FIFO empty." "0,1"
|
|
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|
|
bitfld.long 0xC 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
|
|
group.long 0x2A0++0x3
|
|
line.long 0x0 "CQCFG,This register controls Command Queuing (CQ) operations in a manner similar to the DMACFG register."
|
|
bitfld.long 0x0 4. "CQPAUSEOP,CQPAUSEOP register description needed." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CQAUTOCLEARMASK,Enable clear of CQMASK after each pause operation. This may be useful when using software flags to pause CQ." "0,1"
|
|
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|
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bitfld.long 0x0 2. "CQPWROFF,Power off MSPI domain upon completion of DMA operation." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CQPRI,Sets the Priority of the command queue DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
|
|
newline
|
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bitfld.long 0x0 0. "CQEN,Command queue enable. When set will enable the processing of the command queue" "0: Disable CQ Function,1: Enable CQ Function"
|
|
group.long 0x2A8++0x13
|
|
line.long 0x0 "CQADDR,Location of the command queue in SRAM or flash memory. This register will increment as CQ operations commence. Software should only write CQADDR when CQEN is disabled. however the command queue script itself may update CQADDR in order to perform.."
|
|
hexmask.long 0x0 0.--28. 1. "CQADDR,Address of command queue buffer in SRAM or flash. The buffer address must be aligned to a word boundary."
|
|
line.long 0x4 "CQSTAT,Command Queue Status"
|
|
bitfld.long 0x4 3. "CQPAUSED,Command queue is currently paused status." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CQCPL,Command queue operation Complete. This signals the end of the command queue operation." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
|
|
line.long 0x8 "CQFLAGS,Command Queue Flags"
|
|
hexmask.long.word 0x8 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
|
|
line.long 0xC "CQSETCLEAR,Command Queue Flag Set/Clear"
|
|
hexmask.long.byte 0xC 16.--23. 1. "CQFCLR,Clear CQFlag status bits."
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "CQFTOGGLE,Toggle CQFlag status bits"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CQFSET,Set CQFlag status bits. Set has priority over clear if both are high."
|
|
line.long 0x10 "CQPAUSE,Command Queue Pause Mask"
|
|
hexmask.long.word 0x10 0.--15. 1. "CQMASK,CQ will pause processing when ALL specified events are satisfied -- i.e. when (CQMASK and CQPAUSE)==CQMASK."
|
|
group.long 0x2C0++0x7
|
|
line.long 0x0 "CQCURIDX,This register can be used in conjunction with the CQENDIDX register to manage the command queue. Typically software will initialize the CQCURIDX and CQENDIDX to the same value. which will cause the CQ to be paused when enabled. Software may then.."
|
|
hexmask.long.byte 0x0 0.--7. 1. "CQCURIDX,Can be used to indicate the current position of the command queue by having CQ operations write this field. A CQ hardware status flag indicates when CURIDX and ENDIDX are not equal allowing SW to pause the CQ processing until the end index is.."
|
|
line.long 0x4 "CQENDIDX,Command Queue End Index"
|
|
hexmask.long.byte 0x4 0.--7. 1. "CQENDIDX,Can be used to indicate the end position of the command queue. A CQ hardware status bit indices when CURIDX != ENDIDX so that the CQ can be paused when it reaches the end pointer."
|
|
group.long 0x310++0x3
|
|
line.long 0x0 "STATXIPDMA,Debug XIP DMA State"
|
|
hexmask.long 0x0 0.--31. 1. "FLD32,XIP/DMA module debug"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("AMAP42KL")||cpuis("AMA4B2KL"))
|
|
tree "MSPI1"
|
|
base ad:0x40061000
|
|
group.long 0x0++0x23
|
|
line.long 0x0 "CTRL,This register is used to enable individual PIO based transactions to a device on the bus. The CFG register must be programmed properly for the transfer. and the ADDR and INSTR registers should be programmed if the SENDI and SENDA fields are enabled."
|
|
hexmask.long.word 0x0 16.--31. 1. "XFERBYTES,Number of bytes to transmit or receive (based on TXRX bit)"
|
|
newline
|
|
bitfld.long 0x0 13. "HALFWORDREVERSE,Reverse bytes in half-word. Little endian data: {[7:0] [15:8] [23:16] [31:24]} -> {[15:8] [7:0] [31:24] [23:16]}; big endian data: {[31:24] [23:16] [15:8] [7:0]} -> {[23:16] [31:24] [7:0] [15:8]}" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENWLAT,Enable Write Latency Counter (time between address and first data byte). Counter value is WRITELATENCY." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "ENDCX,Enable DCX signal on data [1]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ENTURN,Indicates whether TX->RX turnaround cycles should be enabled for this operation (see TURNAROUND field in CFG register)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PIOSCRAMBLE,Enables data scrambling for PIO opertions. This should only be used for data operations and never for commands to a device." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "BIGENDIAN,1 indicates data in FIFO is in big endian format (MSB first); 0 indicates little endian data (default LSB first)." "0,1"
|
|
newline
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bitfld.long 0x0 7. "TXRX,1 Indicates a TX operation 0 indicates an RX operation of XFERBYTES" "0,1"
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bitfld.long 0x0 6. "SENDI,Indicates whether an instruction phase should be sent (see INSTR field and ISIZE field in CFG register)" "0,1"
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bitfld.long 0x0 5. "SENDA,Indicates whether an address phase should be sent (see ADDR register and ASIZE field in CFG register)" "0,1"
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bitfld.long 0x0 4. "PIODEV,Selects the Device configutation to use for PIO requests" "0: Use DEVICE0 Configuration,1: Use DEVICE1 CONFIGURATION"
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bitfld.long 0x0 2. "BUSY,Command status: 1 indicates controller is busy (command in progress)" "0,1"
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bitfld.long 0x0 1. "STATUS,Command status: 1 indicates command has completed. Cleared by writing 1 to this bit or starting a new transfer." "0,1"
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bitfld.long 0x0 0. "START,Write to 1 to initiate a PIO transaction on the bus (typically the entire register should be written at once with this bit set)." "0,1"
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line.long 0x4 "CTRL1,These registers are used to enable individual PIO based transactions to a device on the bus. The CFG register must be programmed properly for the transfer. and the ADDR and INSTR registers should be programmed if the SENDI and SENDA fields are.."
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hexmask.long.byte 0x4 0.--3. 1. "PIOMIXED,Provides override controls for data operations where instruction address and data may transfer in different rates."
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line.long 0x8 "ADDR,Optional Address field to send for PIO transfers"
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hexmask.long 0x8 0.--31. 1. "ADDR,Optional Address field to send (after optional instruction field) - qualified by ASIZE in CMD register. NOTE: This register is aliased to DMADEVADDR."
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line.long 0xC "INSTR,Optional Instruction field to send for PIO transfers"
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hexmask.long.word 0xC 0.--15. 1. "INSTR,Optional Instruction field to send (1st byte) - qualified by ISEND/ISIZE"
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line.long 0x10 "TXFIFO,TX Data FIFO"
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hexmask.long 0x10 0.--31. 1. "TXFIFO,Data to be transmitted. Data should normally be aligned to the LSB (pad the upper bits with zeros) unless BIGENDIAN is set."
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line.long 0x14 "RXFIFO,RX Data FIFO"
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hexmask.long 0x14 0.--31. 1. "RXFIFO,Receive data. Data is aligned to the LSB (padded zeros on upper bits) unless BIGENDIAN is set."
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line.long 0x18 "TXENTRIES,Number of words in TX FIFO"
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hexmask.long.byte 0x18 0.--5. 1. "TXENTRIES,Number of 32-bit words/entries in TX FIFO"
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line.long 0x1C "RXENTRIES,Number of words in RX FIFO"
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hexmask.long.byte 0x1C 0.--5. 1. "RXENTRIES,Number of 32-bit words/entries in RX FIFO"
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line.long 0x20 "THRESHOLD,Threshold levels that trigger RXFull and TXEmpty interrupts"
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hexmask.long.byte 0x20 8.--13. 1. "RXTHRESH,Number of entries in TX FIFO that cause RXE interrupt"
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hexmask.long.byte 0x20 0.--5. 1. "TXTHRESH,Number of entries in TX FIFO that cause TXF interrupt"
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group.long 0x30++0x3
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line.long 0x0 "MSPICFG,Timing configuration bits for the MSPI module. PRSTN. IPRSTN. and FIFORESET can be used to reset portions of the MSPI interface in order to clear error conditions. The remaining bits control clock frequency and TX/RX capture timings."
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bitfld.long 0x0 31. "PRSTN,Peripheral reset. Master reset to the entire MSPI module (DMA XIP and transfer state machines). 1=normal operation 0=in reset." "0: in reset,1: normal operation"
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bitfld.long 0x0 30. "IPRSTN,IP block reset. Write to 0 to put the transfer module in reset or 1 for normal operation. This may be required after error conditions to clear the transfer on the bus." "0,1"
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bitfld.long 0x0 29. "FIFORESET,Reset MSPI FIFO (active high). 1=reset FIFO 0=normal operation. May be used to manually flush the FIFO in error handling." "0: normal operation,1: reset FIFO"
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hexmask.long.byte 0x0 4.--7. 1. "IOMSEL,Selects which IOM is selected for CQ handshake status."
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bitfld.long 0x0 0. "APBCLK,Enable continuous APB clock. For power-efficient operation APBCLK should be set to 0." "0: Disable continuous clock.,1: Enable continuous clock."
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group.long 0x44++0xB
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line.long 0x0 "PADOUTEN,Enable bits for the MSPI output pads. Each active MSPI line should be set to 1 in the OUTEN field below."
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bitfld.long 0x0 31. "CLKOND4,Output clock on MSPI data[4]" "0,1"
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bitfld.long 0x0 30. "PADSET1,Only applicable on mspi1. When set use gpio95 .. gpio 104 as the pads. This extra set of pads is to run mspi0 on HEX and mspi1 concurrently. Note that the timing of this extra pads may not be as good as the origianl pads." "0,1"
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hexmask.long.tbyte 0x0 0.--19. 1. "OUTEN,Output pad enable configuration. Indicates which pads should be driven. Bits [3:0] are Quad0 data. Bits [7:4] are Quad1 data. Bit [8] is clock. Bit [9] is BM/DQS. Bit [10:17] are data for 16-bit. Bit[18] is BM/DQS for 16-bit. Bit[19] is not used."
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line.long 0x4 "PADOVEREN,Enables PIO-like pad override control"
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hexmask.long.tbyte 0x4 0.--19. 1. "OVERRIDEEN,Output pad override enable. Bit mask for pad outputs. When set to 1 the values in the OVERRIDE field are driven on the pad (output enable is implicitly set in this mode). [7:0]=data [8]=clock [9]=DM"
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line.long 0x8 "PADOVER,Override data value"
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hexmask.long.tbyte 0x8 0.--19. 1. "OVERRIDE,Output pad override value. [7:0]=data [8]=clock [9]=DM"
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group.long 0x80++0x23
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line.long 0x0 "DEV0AXI,Specifies the base address and aperture range of the device as mapped onto the AXI bus"
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hexmask.long.word 0x0 16.--25. 1. "BASE0,XIPEN has to be enabled to enable aperture. The BASE address needs to be SIZE aligned."
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bitfld.long 0x0 4. "READONLY0,Indicates the AXI aperture is read-only" "0: Indicates AXI aperture supports read and write..,1: Indicates AXI aperture only supports read.."
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hexmask.long.byte 0x0 0.--3. 1. "SIZE0,Indicates the AXI aperture size"
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line.long 0x4 "DEV0CFG,Command formatting for PIO based transactions (initiated by writes to CTRL register)"
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hexmask.long.byte 0x4 26.--31. 1. "WRITELATENCY0,Number of write Latency cycles. Qualified by ENTURN bit field."
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bitfld.long 0x4 25. "SEPIO0,Separate IO configuration. This bit should be set when the target device has separate MOSI and MISO pins. Respective IN/OUT bits below should be set to map pins." "0,1"
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bitfld.long 0x4 24. "TXNEG0,Launches TX data a half clock cycle (~10ns) early. This should normally be programmed to zero (NORMAL)." "0: TX launched from posedge internal clock,1: TX data launched from negedge of internal clock"
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bitfld.long 0x4 23. "RXNEG0,Adjusts the RX capture phase to the negedge of the 48MHz internal clock (~10ns early). For normal operation it is expected that RXNEG will be set to 0." "0: RX data sampled on posedge of internal clock,1: RX data sampled on negedge of internal clock"
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bitfld.long 0x4 22. "RXCAP0,Controls RX data capture phase. A setting of 0 (NORMAL) captures read data at the normal capture point relative to the internal clock launch point. However to accomodate chip/pad/board delays a setting of RXCAP of 1 is expected to be used to.." "0: RX Capture phase aligns with CPHA setting,1: RX Capture phase is delayed from CPHA setting by.."
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hexmask.long.byte 0x4 16.--21. 1. "CLKDIV0,Clock Divider. Allows dividing 96 MHz base clock by integer multiples. Enumerations are provided for common frequency but any integer divide from 96 MHz is allowed. Odd divide ratios will result in a 33/66 percent duty cycle with a long low.."
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bitfld.long 0x4 15. "CPOL0,Serial clock polarity." "0: Clock inactive state is low.,1: Clock inactive state is high."
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bitfld.long 0x4 14. "CPHA0,Serial clock phase." "0: Clock toggles in middle of data bit.,1: Clock toggles at start of data bit."
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hexmask.long.byte 0x4 8.--13. 1. "TURNAROUND0,Number of turnaound cycles (for TX->RX transitions). Qualified by ENTURN bit field."
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bitfld.long 0x4 7. "ISIZE0,Instruction Size" "0: Instruction is 1 byte,1: Instruction is 2 bytes"
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bitfld.long 0x4 5.--6. "ASIZE0,Address Size. Address bytes to send from ADDR register" "0: Send one address byte,1: Send two address bytes,2: Send three address bytes,3: Send four address bytes"
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hexmask.long.byte 0x4 0.--4. 1. "DEVCFG0,Flash configuration for XIP and AUTO DMA operations. Controls value for SER (Slave Enable) for XIP operations and address generation for DMA/XIP modes. Also used to configure SPIFRF (frame format)."
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line.long 0x8 "DEV0DDR,Timing configuration bits for DDR operation of the MSPI module."
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bitfld.long 0x8 31. "RXDQSDELAYHIEN0,When 1 RXDQSDELAYHI and RXDQSDELAYNEGHI is used for falling edge of the clock." "0,1"
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hexmask.long.byte 0x8 26.--30. 1. "RXDQSDELAYNEGHI0,This acts as an offset to the computed value (should be set to 0 by default) of falling edge for 2nd DQS on HEX mode."
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hexmask.long.byte 0x8 21.--25. 1. "RXDQSDELAYHI0,This acts as an offset to the computed value (should be set to 0 by default) for 2nd DQS on HEX mode."
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bitfld.long 0x8 20. "RXDQSDELAYNEGEN0,When 1 RXDQSDELAYNEG is used for falling edge of the clock." "0,1"
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hexmask.long.byte 0x8 15.--19. 1. "RXDQSDELAYNEG0,This acts as an offset to the computed value (should be set to 0 by default) of falling edge."
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hexmask.long.byte 0x8 10.--14. 1. "RXDQSDELAY0,This acts as an offset to the computed value (should be set to 0 by default)"
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hexmask.long.byte 0x8 5.--9. 1. "TXDQSDELAY0,This acts as an offset to the computed value (should be set to 0 by default)"
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bitfld.long 0x8 4. "ENABLEFINEDELAY0,Enables use of delay line to provide fine control over traditional RX capture clock." "0,1"
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bitfld.long 0x8 3. "DQSSYNCNEG0,Use negative edge of clock for DDR data sync" "0,1"
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bitfld.long 0x8 2. "ENABLEDQS0,In EMULATEDDR mode enable DQS for read capture" "0,1"
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bitfld.long 0x8 1. "QUADDDR0,Deprecated. No effect on RevC." "0,1"
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bitfld.long 0x8 0. "EMULATEDDR0,Drive external clock at 1/2 rate to emulate DDR mode" "0,1"
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line.long 0xC "DEV0CFG1,Timing and mode configuration bits for the MSPI module."
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bitfld.long 0xC 14.--16. "DQSTURN0,In DQS mode the internal cycle count to enable DQS path." "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 13. "RXHI0,Force st_rx to start at clock high of mspi_clk" "0,1"
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bitfld.long 0xC 12. "TAFOURTH0,Add 1/4th mspi_clk in DDR to turnaround. Recommended set this to 1 when EMULATEDDR is set in non-DQS mode (ENABLEDQS = 0)." "0,1"
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bitfld.long 0xC 11. "HYPERIO0,When using Windbond set this bit to 1 to generate CA[47:0] in hardware." "0,1"
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bitfld.long 0xC 9.--10. "RXSMP0,Sampling edge based on sclk edge. No effect when div1" "0,1,2,3"
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bitfld.long 0xC 8. "RBX0,Enable the support of RBX ( page boundary crossing on read )" "0,1"
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bitfld.long 0xC 7. "WBX0,Enable the support of WBX ( page boundary crossing on write )" "0,1"
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bitfld.long 0xC 5. "SCLKRXHALT0,Halt sclk based on xfer_count" "0,1"
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bitfld.long 0xC 4. "RXCAPEXT0,Specify the number of apb_clk of RX capture phse {RXCAPEXT RXCAP}" "0,1"
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hexmask.long.byte 0xC 0.--3. 1. "SFTURN0,Subtract from internal counter of write latency and turnaround"
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line.long 0x10 "DEV0XIP,When any SPI flash is configured. this register must be properly programmed before XIP or AUTO DMA operations commence."
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bitfld.long 0x10 26. "XIPHALFWORDREVERSE0,Indicates whether XIP/AUTO DMA data transfers are in Reverse bytes in half-word format" "0: No change,1: Indicates XIP/AUTO DMA data transfers are in.."
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hexmask.long.byte 0x10 20.--25. 1. "XIPWRITELATENCY0,Number of write Latency cycles. Qualified by XIPENWLAT bit field."
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hexmask.long.byte 0x10 14.--19. 1. "XIPTURNAROUND0,Number of turnaound cycles (for TX->RX transitions). Qualified by XIPENTURN bit field."
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bitfld.long 0x10 13. "XIPENWLAT0,Enable Write Latency counter for XIP write transactions" "0,1"
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bitfld.long 0x10 12. "XIPENDCX0,Enable DCX signal on data [1] for XIP/DMA operations" "0,1"
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hexmask.long.byte 0x10 8.--11. 1. "XIPMIXED0,Provides override controls for data operations where instruction address and data may transfer in different rates."
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bitfld.long 0x10 7. "XIPSENDI0,Indicates whether XIP/AUTO DMA operations should send an instruction (see READINSTR field and ISIZE field in CFG)" "0,1"
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bitfld.long 0x10 6. "XIPSENDA0,Indicates whether XIP/AUTO DMA operations should send an an address phase (see DMADEVADDR register and ASIZE field in CFG)" "0,1"
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bitfld.long 0x10 5. "XIPENTURN0,Indicates whether XIP/AUTO DMA operations should enable TX->RX turnaround cycles" "0,1"
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bitfld.long 0x10 4. "XIPBIGENDIAN0,Indicates whether XIP/AUTO DMA data transfers are in big or little endian format" "0,1"
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bitfld.long 0x10 2.--3. "XIPACK0,Controls transmission of Micron XIP acknowledge cycles (Micron Flash devices only)" "0: No acknowledege sent. Data IOs are tristated the..,?,2: Positive acknowledege sent. Data IOs are driven..,3: Negative acknowledege sent. Data IOs are driven.."
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bitfld.long 0x10 0. "XIPEN0,Enable the XIP (eXecute In Place) function which effectively enables the address decoding of the MSPI device in the flash/cache address space at address 0x04000000-0x07FFFFFF." "0,1"
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line.long 0x14 "DEV0INSTR,When any SPI flash is configured. this register must be properly programmed before XIP or AUTO DMA operations commence."
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hexmask.long.word 0x14 16.--31. 1. "READINSTR0,Read command sent to flash for DMA/XIP operations"
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hexmask.long.word 0x14 0.--15. 1. "WRITEINSTR0,Write command sent for DMA operations"
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line.long 0x18 "DEV0BOUNDARY,Allows large transfers to be broken up into smaller ones in hardware to accommodate needs of external devices and allow XIP/XIPMM. Only applicable for memory-mapped devices (PSRAM. Flash. etc) where address can be retransmitted without side.."
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hexmask.long.byte 0x18 12.--15. 1. "DMABOUND0,DMA Address boundary"
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hexmask.long.word 0x18 0.--11. 1. "DMATIMELIMIT0,DMA time limit. Can be used to limit the transaction time on the MSPI bus. The count is in ~100 ns increments for the 96 MHz clock input. A value of 0 disables the counter."
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line.long 0x1C "DEV0SCRAMBLING,Enables data scrambling for the specified range external flash addresses. Scrambling does not impact flash access performance."
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bitfld.long 0x1C 31. "SCRENABLE0,Enables Data Scrambling Region. When 1 reads and writes to the range will be scrambled. When 0 data will be read/written unmodified. Address range is specified in 64K granularity and the START/END ranges are included within the range." "0,1"
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hexmask.long.word 0x1C 16.--25. 1. "SCREND0,Scrambling region end address [25:16] (64K block granularity). The END block is the LAST block included in the scrambled address range."
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hexmask.long.word 0x1C 0.--9. 1. "SCRSTART0,Scrambling region start address [25:16] (64K block granularity). The START block is the FIRST block included in the scrambled address range."
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line.long 0x20 "DEV0XIPMISC,Miscellaneous XIP control registers for AXI logic"
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bitfld.long 0x20 21. "APNDODD0,Append dummy byte to odd number of write" "0: No appending byte,1: Append one dummy byte"
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bitfld.long 0x20 15. "XIPBOUNDARY0,Deprecated. No effect on RevC." "0: ERROR: desc VALUE MISSING,1: ERROR: desc VALUE MISSING"
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bitfld.long 0x20 14. "BEON0,Byte enable always on for all lanes" "0: Byte enable is calculated on the fly,1: Byte enable of all bytes are always on"
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bitfld.long 0x20 13. "BEPOL0,byte mask polarity to MSPI xfer" "0,1"
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bitfld.long 0x20 12. "XIPODD0,Convert odd starting address to word-aligned starting address with byte-enables for holes. For example an AXI transaction with wstrb of 0x0600 results in mspi transaction of addr=8 and BE=0b1001 ( active low )." "0: No conversion,1: Enable the conversion"
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hexmask.long.word 0x20 0.--11. 1. "CEBREAK0,CEBREAK0 field description needed."
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group.long 0x100++0x1B
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line.long 0x0 "DMACFG,DMA Configuration"
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bitfld.long 0x0 18. "DMAPWROFF,Power off MSPI domain upon completion of DMA operation." "0,1"
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bitfld.long 0x0 17. "DMATXEMPT,For DMA_M2P only start when DMA fifo is not empty." "0,1"
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bitfld.long 0x0 4.--5. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately),2: Auto Priority (priority raised once TX FIFO..,?"
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bitfld.long 0x0 3. "DMADEV,DMA Device Select" "0: Select Device 0 for DMA,?"
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bitfld.long 0x0 2. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction,1: Memory to Peripheral transaction"
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bitfld.long 0x0 0.--1. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation" "0: Disable DMA Function,?,?,3: Enable HW controlled DMA Function to manage DMA.."
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line.long 0x4 "DMASTAT,DMA Status"
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bitfld.long 0x4 3. "SCRERR,Scrambling Access Alignment Error. This active high bit signals that a scrambling operation was specified for a non-word aligned DEVADDR." "0,1"
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bitfld.long 0x4 2. "DMAERR,DMA Error. This active high bit signals that an error was encountered during the DMA operation." "0,1"
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bitfld.long 0x4 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation." "0,1"
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bitfld.long 0x4 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority. All of these will be indicated with a 1. A 0 will indicate that the DMA is.." "0,1"
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line.long 0x8 "DMATARGADDR,DMA Target Address"
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hexmask.long 0x8 0.--31. 1. "TARGADDR,Target byte address for source of DMA (either read or write). In cases of non-word aligned addresses the DMA logic will take care for ensuring only the target bytes are read/written."
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line.long 0xC "DMADEVADDR,DMA Device Address"
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hexmask.long 0xC 0.--31. 1. "DEVADDR,SPI Device address for automated DMA transactions (both read and write)."
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line.long 0x10 "DMATOTCOUNT,DMA Total Transfer Count"
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hexmask.long.tbyte 0x10 0.--23. 1. "TOTCOUNT,Total Transfer Count in bytes."
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line.long 0x14 "DMABCOUNT,DMA BYTE Transfer Count"
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hexmask.long.byte 0x14 0.--7. 1. "BCOUNT,Burst transfer size in bytes. This is the number of bytes transferred when a FIFO trigger event occurs. Recommended value is 32."
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line.long 0x18 "DMATHRESH,Indicates FIFO level at which a DMA should be triggered. For most configurations. a setting of 8 is recommended for both read and write operations."
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hexmask.long.byte 0x18 8.--12. 1. "DMARXTHRESH,DMA transfer FIFO level trigger. For read operations DMA is triggered when the FIFO level is greater than this value. For write operations DMA is triggered when the FIFO level is less than this level. Each DMA operation will consist of.."
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hexmask.long.byte 0x18 0.--4. 1. "DMATXTHRESH,DMA transfer FIFO level trigger. For read operations DMA is triggered when the FIFO level is greater than this value. For write operations DMA is triggered when the FIFO level is less than this level. Each DMA operation will consist of.."
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group.long 0x200++0xF
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line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
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bitfld.long 0x0 13. "APBDMAERR,MSPI is dma target as well as dma source which may result in deadlock." "0,1"
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bitfld.long 0x0 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
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bitfld.long 0x0 11. "CQERR,Command Queue Error Interrupt" "0,1"
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bitfld.long 0x0 10. "CQPAUSED,Command Queue is Paused." "0,1"
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bitfld.long 0x0 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
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bitfld.long 0x0 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
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bitfld.long 0x0 7. "DERR,DMA Error Interrupt" "0,1"
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bitfld.long 0x0 6. "DCMP,DMA Complete Interrupt" "0,1"
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bitfld.long 0x0 5. "RXF,Receive FIFO full" "0,1"
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bitfld.long 0x0 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
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bitfld.long 0x0 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
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|
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bitfld.long 0x0 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXE,Transmit FIFO empty." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 13. "APBDMAERR,MSPI is dma target as well as dma source which may result in deadlock." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CQERR,Command Queue Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "CQPAUSED,Command Queue is Paused." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "DERR,DMA Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "DCMP,DMA Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXF,Receive FIFO full" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXE,Transmit FIFO empty." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 13. "APBDMAERR,MSPI is dma target as well as dma source which may result in deadlock." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "CQERR,Command Queue Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "CQPAUSED,Command Queue is Paused." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "DERR,DMA Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "DCMP,DMA Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "RXF,Receive FIFO full" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "TXE,Transmit FIFO empty." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 13. "APBDMAERR,MSPI is dma target as well as dma source which may result in deadlock." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "CQERR,Command Queue Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "CQPAUSED,Command Queue is Paused." "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "DERR,DMA Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "DCMP,DMA Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "RXF,Receive FIFO full" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "TXE,Transmit FIFO empty." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
|
|
group.long 0x2A0++0x3
|
|
line.long 0x0 "CQCFG,This register controls Command Queuing (CQ) operations in a manner similar to the DMACFG register."
|
|
bitfld.long 0x0 4. "CQPAUSEOP,CQPAUSEOP register description needed." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CQAUTOCLEARMASK,Enable clear of CQMASK after each pause operation. This may be useful when using software flags to pause CQ." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CQPWROFF,Power off MSPI domain upon completion of DMA operation." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CQPRI,Sets the Priority of the command queue DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
|
|
newline
|
|
bitfld.long 0x0 0. "CQEN,Command queue enable. When set will enable the processing of the command queue" "0: Disable CQ Function,1: Enable CQ Function"
|
|
group.long 0x2A8++0x13
|
|
line.long 0x0 "CQADDR,Location of the command queue in SRAM or flash memory. This register will increment as CQ operations commence. Software should only write CQADDR when CQEN is disabled. however the command queue script itself may update CQADDR in order to perform.."
|
|
hexmask.long 0x0 0.--28. 1. "CQADDR,Address of command queue buffer in SRAM or flash. The buffer address must be aligned to a word boundary."
|
|
line.long 0x4 "CQSTAT,Command Queue Status"
|
|
bitfld.long 0x4 3. "CQPAUSED,Command queue is currently paused status." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CQCPL,Command queue operation Complete. This signals the end of the command queue operation." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
|
|
line.long 0x8 "CQFLAGS,Command Queue Flags"
|
|
hexmask.long.word 0x8 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
|
|
line.long 0xC "CQSETCLEAR,Command Queue Flag Set/Clear"
|
|
hexmask.long.byte 0xC 16.--23. 1. "CQFCLR,Clear CQFlag status bits."
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "CQFTOGGLE,Toggle CQFlag status bits"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CQFSET,Set CQFlag status bits. Set has priority over clear if both are high."
|
|
line.long 0x10 "CQPAUSE,Command Queue Pause Mask"
|
|
hexmask.long.word 0x10 0.--15. 1. "CQMASK,CQ will pause processing when ALL specified events are satisfied -- i.e. when (CQMASK and CQPAUSE)==CQMASK."
|
|
group.long 0x2C0++0x7
|
|
line.long 0x0 "CQCURIDX,This register can be used in conjunction with the CQENDIDX register to manage the command queue. Typically software will initialize the CQCURIDX and CQENDIDX to the same value. which will cause the CQ to be paused when enabled. Software may then.."
|
|
hexmask.long.byte 0x0 0.--7. 1. "CQCURIDX,Can be used to indicate the current position of the command queue by having CQ operations write this field. A CQ hardware status flag indicates when CURIDX and ENDIDX are not equal allowing SW to pause the CQ processing until the end index is.."
|
|
line.long 0x4 "CQENDIDX,Command Queue End Index"
|
|
hexmask.long.byte 0x4 0.--7. 1. "CQENDIDX,Can be used to indicate the end position of the command queue. A CQ hardware status bit indices when CURIDX != ENDIDX so that the CQ can be paused when it reaches the end pointer."
|
|
group.long 0x310++0x3
|
|
line.long 0x0 "STATXIPDMA,Debug XIP DMA State"
|
|
hexmask.long 0x0 0.--31. 1. "FLD32,XIP/DMA module debug"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("AMAP42KL")||cpuis("AMA4B2KL"))
|
|
tree "MSPI2"
|
|
base ad:0x40062000
|
|
group.long 0x0++0x23
|
|
line.long 0x0 "CTRL,This register is used to enable individual PIO based transactions to a device on the bus. The CFG register must be programmed properly for the transfer. and the ADDR and INSTR registers should be programmed if the SENDI and SENDA fields are enabled."
|
|
hexmask.long.word 0x0 16.--31. 1. "XFERBYTES,Number of bytes to transmit or receive (based on TXRX bit)"
|
|
newline
|
|
bitfld.long 0x0 13. "HALFWORDREVERSE,Reverse bytes in half-word. Little endian data: {[7:0] [15:8] [23:16] [31:24]} -> {[15:8] [7:0] [31:24] [23:16]}; big endian data: {[31:24] [23:16] [15:8] [7:0]} -> {[23:16] [31:24] [7:0] [15:8]}" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENWLAT,Enable Write Latency Counter (time between address and first data byte). Counter value is WRITELATENCY." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "ENDCX,Enable DCX signal on data [1]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ENTURN,Indicates whether TX->RX turnaround cycles should be enabled for this operation (see TURNAROUND field in CFG register)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PIOSCRAMBLE,Enables data scrambling for PIO opertions. This should only be used for data operations and never for commands to a device." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "BIGENDIAN,1 indicates data in FIFO is in big endian format (MSB first); 0 indicates little endian data (default LSB first)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXRX,1 Indicates a TX operation 0 indicates an RX operation of XFERBYTES" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "SENDI,Indicates whether an instruction phase should be sent (see INSTR field and ISIZE field in CFG register)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SENDA,Indicates whether an address phase should be sent (see ADDR register and ASIZE field in CFG register)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PIODEV,Selects the Device configutation to use for PIO requests" "0: Use DEVICE0 Configuration,1: Use DEVICE1 CONFIGURATION"
|
|
newline
|
|
bitfld.long 0x0 2. "BUSY,Command status: 1 indicates controller is busy (command in progress)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STATUS,Command status: 1 indicates command has completed. Cleared by writing 1 to this bit or starting a new transfer." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Write to 1 to initiate a PIO transaction on the bus (typically the entire register should be written at once with this bit set)." "0,1"
|
|
line.long 0x4 "CTRL1,These registers are used to enable individual PIO based transactions to a device on the bus. The CFG register must be programmed properly for the transfer. and the ADDR and INSTR registers should be programmed if the SENDI and SENDA fields are.."
|
|
hexmask.long.byte 0x4 0.--3. 1. "PIOMIXED,Provides override controls for data operations where instruction address and data may transfer in different rates."
|
|
line.long 0x8 "ADDR,Optional Address field to send for PIO transfers"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,Optional Address field to send (after optional instruction field) - qualified by ASIZE in CMD register. NOTE: This register is aliased to DMADEVADDR."
|
|
line.long 0xC "INSTR,Optional Instruction field to send for PIO transfers"
|
|
hexmask.long.word 0xC 0.--15. 1. "INSTR,Optional Instruction field to send (1st byte) - qualified by ISEND/ISIZE"
|
|
line.long 0x10 "TXFIFO,TX Data FIFO"
|
|
hexmask.long 0x10 0.--31. 1. "TXFIFO,Data to be transmitted. Data should normally be aligned to the LSB (pad the upper bits with zeros) unless BIGENDIAN is set."
|
|
line.long 0x14 "RXFIFO,RX Data FIFO"
|
|
hexmask.long 0x14 0.--31. 1. "RXFIFO,Receive data. Data is aligned to the LSB (padded zeros on upper bits) unless BIGENDIAN is set."
|
|
line.long 0x18 "TXENTRIES,Number of words in TX FIFO"
|
|
hexmask.long.byte 0x18 0.--5. 1. "TXENTRIES,Number of 32-bit words/entries in TX FIFO"
|
|
line.long 0x1C "RXENTRIES,Number of words in RX FIFO"
|
|
hexmask.long.byte 0x1C 0.--5. 1. "RXENTRIES,Number of 32-bit words/entries in RX FIFO"
|
|
line.long 0x20 "THRESHOLD,Threshold levels that trigger RXFull and TXEmpty interrupts"
|
|
hexmask.long.byte 0x20 8.--13. 1. "RXTHRESH,Number of entries in TX FIFO that cause RXE interrupt"
|
|
newline
|
|
hexmask.long.byte 0x20 0.--5. 1. "TXTHRESH,Number of entries in TX FIFO that cause TXF interrupt"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "MSPICFG,Timing configuration bits for the MSPI module. PRSTN. IPRSTN. and FIFORESET can be used to reset portions of the MSPI interface in order to clear error conditions. The remaining bits control clock frequency and TX/RX capture timings."
|
|
bitfld.long 0x0 31. "PRSTN,Peripheral reset. Master reset to the entire MSPI module (DMA XIP and transfer state machines). 1=normal operation 0=in reset." "0: in reset,1: normal operation"
|
|
newline
|
|
bitfld.long 0x0 30. "IPRSTN,IP block reset. Write to 0 to put the transfer module in reset or 1 for normal operation. This may be required after error conditions to clear the transfer on the bus." "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "FIFORESET,Reset MSPI FIFO (active high). 1=reset FIFO 0=normal operation. May be used to manually flush the FIFO in error handling." "0: normal operation,1: reset FIFO"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "IOMSEL,Selects which IOM is selected for CQ handshake status."
|
|
newline
|
|
bitfld.long 0x0 0. "APBCLK,Enable continuous APB clock. For power-efficient operation APBCLK should be set to 0." "0: Disable continuous clock.,1: Enable continuous clock."
|
|
group.long 0x44++0xB
|
|
line.long 0x0 "PADOUTEN,Enable bits for the MSPI output pads. Each active MSPI line should be set to 1 in the OUTEN field below."
|
|
bitfld.long 0x0 31. "CLKOND4,Output clock on MSPI data[4]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "PADSET1,Only applicable on mspi1. When set use gpio95 .. gpio 104 as the pads. This extra set of pads is to run mspi0 on HEX and mspi1 concurrently. Note that the timing of this extra pads may not be as good as the origianl pads." "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "OUTEN,Output pad enable configuration. Indicates which pads should be driven. Bits [3:0] are Quad0 data. Bits [7:4] are Quad1 data. Bit [8] is clock. Bit [9] is BM/DQS. Bit [10:17] are data for 16-bit. Bit[18] is BM/DQS for 16-bit. Bit[19] is not used."
|
|
line.long 0x4 "PADOVEREN,Enables PIO-like pad override control"
|
|
hexmask.long.tbyte 0x4 0.--19. 1. "OVERRIDEEN,Output pad override enable. Bit mask for pad outputs. When set to 1 the values in the OVERRIDE field are driven on the pad (output enable is implicitly set in this mode). [7:0]=data [8]=clock [9]=DM"
|
|
line.long 0x8 "PADOVER,Override data value"
|
|
hexmask.long.tbyte 0x8 0.--19. 1. "OVERRIDE,Output pad override value. [7:0]=data [8]=clock [9]=DM"
|
|
group.long 0x80++0x23
|
|
line.long 0x0 "DEV0AXI,Specifies the base address and aperture range of the device as mapped onto the AXI bus"
|
|
hexmask.long.word 0x0 16.--25. 1. "BASE0,XIPEN has to be enabled to enable aperture. The BASE address needs to be SIZE aligned."
|
|
newline
|
|
bitfld.long 0x0 4. "READONLY0,Indicates the AXI aperture is read-only" "0: Indicates AXI aperture supports read and write..,1: Indicates AXI aperture only supports read.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SIZE0,Indicates the AXI aperture size"
|
|
line.long 0x4 "DEV0CFG,Command formatting for PIO based transactions (initiated by writes to CTRL register)"
|
|
hexmask.long.byte 0x4 26.--31. 1. "WRITELATENCY0,Number of write Latency cycles. Qualified by ENTURN bit field."
|
|
newline
|
|
bitfld.long 0x4 25. "SEPIO0,Separate IO configuration. This bit should be set when the target device has separate MOSI and MISO pins. Respective IN/OUT bits below should be set to map pins." "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "TXNEG0,Launches TX data a half clock cycle (~10ns) early. This should normally be programmed to zero (NORMAL)." "0: TX launched from posedge internal clock,1: TX data launched from negedge of internal clock"
|
|
newline
|
|
bitfld.long 0x4 23. "RXNEG0,Adjusts the RX capture phase to the negedge of the 48MHz internal clock (~10ns early). For normal operation it is expected that RXNEG will be set to 0." "0: RX data sampled on posedge of internal clock,1: RX data sampled on negedge of internal clock"
|
|
newline
|
|
bitfld.long 0x4 22. "RXCAP0,Controls RX data capture phase. A setting of 0 (NORMAL) captures read data at the normal capture point relative to the internal clock launch point. However to accomodate chip/pad/board delays a setting of RXCAP of 1 is expected to be used to.." "0: RX Capture phase aligns with CPHA setting,1: RX Capture phase is delayed from CPHA setting by.."
|
|
newline
|
|
hexmask.long.byte 0x4 16.--21. 1. "CLKDIV0,Clock Divider. Allows dividing 96 MHz base clock by integer multiples. Enumerations are provided for common frequency but any integer divide from 96 MHz is allowed. Odd divide ratios will result in a 33/66 percent duty cycle with a long low.."
|
|
newline
|
|
bitfld.long 0x4 15. "CPOL0,Serial clock polarity." "0: Clock inactive state is low.,1: Clock inactive state is high."
|
|
newline
|
|
bitfld.long 0x4 14. "CPHA0,Serial clock phase." "0: Clock toggles in middle of data bit.,1: Clock toggles at start of data bit."
|
|
newline
|
|
hexmask.long.byte 0x4 8.--13. 1. "TURNAROUND0,Number of turnaound cycles (for TX->RX transitions). Qualified by ENTURN bit field."
|
|
newline
|
|
bitfld.long 0x4 7. "ISIZE0,Instruction Size" "0: Instruction is 1 byte,1: Instruction is 2 bytes"
|
|
newline
|
|
bitfld.long 0x4 5.--6. "ASIZE0,Address Size. Address bytes to send from ADDR register" "0: Send one address byte,1: Send two address bytes,2: Send three address bytes,3: Send four address bytes"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "DEVCFG0,Flash configuration for XIP and AUTO DMA operations. Controls value for SER (Slave Enable) for XIP operations and address generation for DMA/XIP modes. Also used to configure SPIFRF (frame format)."
|
|
line.long 0x8 "DEV0DDR,Timing configuration bits for DDR operation of the MSPI module."
|
|
bitfld.long 0x8 31. "RXDQSDELAYHIEN0,When 1 RXDQSDELAYHI and RXDQSDELAYNEGHI is used for falling edge of the clock." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 26.--30. 1. "RXDQSDELAYNEGHI0,This acts as an offset to the computed value (should be set to 0 by default) of falling edge for 2nd DQS on HEX mode."
|
|
newline
|
|
hexmask.long.byte 0x8 21.--25. 1. "RXDQSDELAYHI0,This acts as an offset to the computed value (should be set to 0 by default) for 2nd DQS on HEX mode."
|
|
newline
|
|
bitfld.long 0x8 20. "RXDQSDELAYNEGEN0,When 1 RXDQSDELAYNEG is used for falling edge of the clock." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 15.--19. 1. "RXDQSDELAYNEG0,This acts as an offset to the computed value (should be set to 0 by default) of falling edge."
|
|
newline
|
|
hexmask.long.byte 0x8 10.--14. 1. "RXDQSDELAY0,This acts as an offset to the computed value (should be set to 0 by default)"
|
|
newline
|
|
hexmask.long.byte 0x8 5.--9. 1. "TXDQSDELAY0,This acts as an offset to the computed value (should be set to 0 by default)"
|
|
newline
|
|
bitfld.long 0x8 4. "ENABLEFINEDELAY0,Enables use of delay line to provide fine control over traditional RX capture clock." "0,1"
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bitfld.long 0x8 3. "DQSSYNCNEG0,Use negative edge of clock for DDR data sync" "0,1"
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bitfld.long 0x8 2. "ENABLEDQS0,In EMULATEDDR mode enable DQS for read capture" "0,1"
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bitfld.long 0x8 1. "QUADDDR0,Deprecated. No effect on RevC." "0,1"
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bitfld.long 0x8 0. "EMULATEDDR0,Drive external clock at 1/2 rate to emulate DDR mode" "0,1"
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line.long 0xC "DEV0CFG1,Timing and mode configuration bits for the MSPI module."
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bitfld.long 0xC 14.--16. "DQSTURN0,In DQS mode the internal cycle count to enable DQS path." "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 13. "RXHI0,Force st_rx to start at clock high of mspi_clk" "0,1"
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bitfld.long 0xC 12. "TAFOURTH0,Add 1/4th mspi_clk in DDR to turnaround. Recommended set this to 1 when EMULATEDDR is set in non-DQS mode (ENABLEDQS = 0)." "0,1"
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bitfld.long 0xC 11. "HYPERIO0,When using Windbond set this bit to 1 to generate CA[47:0] in hardware." "0,1"
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bitfld.long 0xC 9.--10. "RXSMP0,Sampling edge based on sclk edge. No effect when div1" "0,1,2,3"
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bitfld.long 0xC 8. "RBX0,Enable the support of RBX ( page boundary crossing on read )" "0,1"
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bitfld.long 0xC 7. "WBX0,Enable the support of WBX ( page boundary crossing on write )" "0,1"
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bitfld.long 0xC 5. "SCLKRXHALT0,Halt sclk based on xfer_count" "0,1"
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bitfld.long 0xC 4. "RXCAPEXT0,Specify the number of apb_clk of RX capture phse {RXCAPEXT RXCAP}" "0,1"
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hexmask.long.byte 0xC 0.--3. 1. "SFTURN0,Subtract from internal counter of write latency and turnaround"
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line.long 0x10 "DEV0XIP,When any SPI flash is configured. this register must be properly programmed before XIP or AUTO DMA operations commence."
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bitfld.long 0x10 26. "XIPHALFWORDREVERSE0,Indicates whether XIP/AUTO DMA data transfers are in Reverse bytes in half-word format" "0: No change,1: Indicates XIP/AUTO DMA data transfers are in.."
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hexmask.long.byte 0x10 20.--25. 1. "XIPWRITELATENCY0,Number of write Latency cycles. Qualified by XIPENWLAT bit field."
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hexmask.long.byte 0x10 14.--19. 1. "XIPTURNAROUND0,Number of turnaound cycles (for TX->RX transitions). Qualified by XIPENTURN bit field."
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bitfld.long 0x10 13. "XIPENWLAT0,Enable Write Latency counter for XIP write transactions" "0,1"
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bitfld.long 0x10 12. "XIPENDCX0,Enable DCX signal on data [1] for XIP/DMA operations" "0,1"
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hexmask.long.byte 0x10 8.--11. 1. "XIPMIXED0,Provides override controls for data operations where instruction address and data may transfer in different rates."
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bitfld.long 0x10 7. "XIPSENDI0,Indicates whether XIP/AUTO DMA operations should send an instruction (see READINSTR field and ISIZE field in CFG)" "0,1"
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bitfld.long 0x10 6. "XIPSENDA0,Indicates whether XIP/AUTO DMA operations should send an an address phase (see DMADEVADDR register and ASIZE field in CFG)" "0,1"
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bitfld.long 0x10 5. "XIPENTURN0,Indicates whether XIP/AUTO DMA operations should enable TX->RX turnaround cycles" "0,1"
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bitfld.long 0x10 4. "XIPBIGENDIAN0,Indicates whether XIP/AUTO DMA data transfers are in big or little endian format" "0,1"
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bitfld.long 0x10 2.--3. "XIPACK0,Controls transmission of Micron XIP acknowledge cycles (Micron Flash devices only)" "0: No acknowledege sent. Data IOs are tristated the..,?,2: Positive acknowledege sent. Data IOs are driven..,3: Negative acknowledege sent. Data IOs are driven.."
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bitfld.long 0x10 0. "XIPEN0,Enable the XIP (eXecute In Place) function which effectively enables the address decoding of the MSPI device in the flash/cache address space at address 0x04000000-0x07FFFFFF." "0,1"
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line.long 0x14 "DEV0INSTR,When any SPI flash is configured. this register must be properly programmed before XIP or AUTO DMA operations commence."
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hexmask.long.word 0x14 16.--31. 1. "READINSTR0,Read command sent to flash for DMA/XIP operations"
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hexmask.long.word 0x14 0.--15. 1. "WRITEINSTR0,Write command sent for DMA operations"
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line.long 0x18 "DEV0BOUNDARY,Allows large transfers to be broken up into smaller ones in hardware to accommodate needs of external devices and allow XIP/XIPMM. Only applicable for memory-mapped devices (PSRAM. Flash. etc) where address can be retransmitted without side.."
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hexmask.long.byte 0x18 12.--15. 1. "DMABOUND0,DMA Address boundary"
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hexmask.long.word 0x18 0.--11. 1. "DMATIMELIMIT0,DMA time limit. Can be used to limit the transaction time on the MSPI bus. The count is in ~100 ns increments for the 96 MHz clock input. A value of 0 disables the counter."
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line.long 0x1C "DEV0SCRAMBLING,Enables data scrambling for the specified range external flash addresses. Scrambling does not impact flash access performance."
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bitfld.long 0x1C 31. "SCRENABLE0,Enables Data Scrambling Region. When 1 reads and writes to the range will be scrambled. When 0 data will be read/written unmodified. Address range is specified in 64K granularity and the START/END ranges are included within the range." "0,1"
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hexmask.long.word 0x1C 16.--25. 1. "SCREND0,Scrambling region end address [25:16] (64K block granularity). The END block is the LAST block included in the scrambled address range."
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hexmask.long.word 0x1C 0.--9. 1. "SCRSTART0,Scrambling region start address [25:16] (64K block granularity). The START block is the FIRST block included in the scrambled address range."
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line.long 0x20 "DEV0XIPMISC,Miscellaneous XIP control registers for AXI logic"
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bitfld.long 0x20 21. "APNDODD0,Append dummy byte to odd number of write" "0: No appending byte,1: Append one dummy byte"
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bitfld.long 0x20 15. "XIPBOUNDARY0,Deprecated. No effect on RevC." "0: ERROR: desc VALUE MISSING,1: ERROR: desc VALUE MISSING"
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bitfld.long 0x20 14. "BEON0,Byte enable always on for all lanes" "0: Byte enable is calculated on the fly,1: Byte enable of all bytes are always on"
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bitfld.long 0x20 13. "BEPOL0,byte mask polarity to MSPI xfer" "0,1"
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bitfld.long 0x20 12. "XIPODD0,Convert odd starting address to word-aligned starting address with byte-enables for holes. For example an AXI transaction with wstrb of 0x0600 results in mspi transaction of addr=8 and BE=0b1001 ( active low )." "0: No conversion,1: Enable the conversion"
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hexmask.long.word 0x20 0.--11. 1. "CEBREAK0,CEBREAK0 field description needed."
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group.long 0x100++0x1B
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line.long 0x0 "DMACFG,DMA Configuration"
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bitfld.long 0x0 18. "DMAPWROFF,Power off MSPI domain upon completion of DMA operation." "0,1"
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bitfld.long 0x0 17. "DMATXEMPT,For DMA_M2P only start when DMA fifo is not empty." "0,1"
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bitfld.long 0x0 4.--5. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately),2: Auto Priority (priority raised once TX FIFO..,?"
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bitfld.long 0x0 3. "DMADEV,DMA Device Select" "0: Select Device 0 for DMA,?"
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bitfld.long 0x0 2. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction,1: Memory to Peripheral transaction"
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bitfld.long 0x0 0.--1. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation" "0: Disable DMA Function,?,?,3: Enable HW controlled DMA Function to manage DMA.."
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line.long 0x4 "DMASTAT,DMA Status"
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bitfld.long 0x4 3. "SCRERR,Scrambling Access Alignment Error. This active high bit signals that a scrambling operation was specified for a non-word aligned DEVADDR." "0,1"
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bitfld.long 0x4 2. "DMAERR,DMA Error. This active high bit signals that an error was encountered during the DMA operation." "0,1"
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bitfld.long 0x4 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation." "0,1"
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bitfld.long 0x4 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority. All of these will be indicated with a 1. A 0 will indicate that the DMA is.." "0,1"
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line.long 0x8 "DMATARGADDR,DMA Target Address"
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hexmask.long 0x8 0.--31. 1. "TARGADDR,Target byte address for source of DMA (either read or write). In cases of non-word aligned addresses the DMA logic will take care for ensuring only the target bytes are read/written."
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line.long 0xC "DMADEVADDR,DMA Device Address"
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hexmask.long 0xC 0.--31. 1. "DEVADDR,SPI Device address for automated DMA transactions (both read and write)."
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line.long 0x10 "DMATOTCOUNT,DMA Total Transfer Count"
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hexmask.long.tbyte 0x10 0.--23. 1. "TOTCOUNT,Total Transfer Count in bytes."
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line.long 0x14 "DMABCOUNT,DMA BYTE Transfer Count"
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hexmask.long.byte 0x14 0.--7. 1. "BCOUNT,Burst transfer size in bytes. This is the number of bytes transferred when a FIFO trigger event occurs. Recommended value is 32."
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line.long 0x18 "DMATHRESH,Indicates FIFO level at which a DMA should be triggered. For most configurations. a setting of 8 is recommended for both read and write operations."
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hexmask.long.byte 0x18 8.--12. 1. "DMARXTHRESH,DMA transfer FIFO level trigger. For read operations DMA is triggered when the FIFO level is greater than this value. For write operations DMA is triggered when the FIFO level is less than this level. Each DMA operation will consist of.."
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hexmask.long.byte 0x18 0.--4. 1. "DMATXTHRESH,DMA transfer FIFO level trigger. For read operations DMA is triggered when the FIFO level is greater than this value. For write operations DMA is triggered when the FIFO level is less than this level. Each DMA operation will consist of.."
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group.long 0x200++0xF
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line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
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bitfld.long 0x0 13. "APBDMAERR,MSPI is dma target as well as dma source which may result in deadlock." "0,1"
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bitfld.long 0x0 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
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bitfld.long 0x0 11. "CQERR,Command Queue Error Interrupt" "0,1"
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bitfld.long 0x0 10. "CQPAUSED,Command Queue is Paused." "0,1"
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bitfld.long 0x0 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
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bitfld.long 0x0 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
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bitfld.long 0x0 7. "DERR,DMA Error Interrupt" "0,1"
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bitfld.long 0x0 6. "DCMP,DMA Complete Interrupt" "0,1"
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bitfld.long 0x0 5. "RXF,Receive FIFO full" "0,1"
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bitfld.long 0x0 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
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bitfld.long 0x0 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
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bitfld.long 0x0 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
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bitfld.long 0x0 1. "TXE,Transmit FIFO empty." "0,1"
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bitfld.long 0x0 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
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line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
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bitfld.long 0x4 13. "APBDMAERR,MSPI is dma target as well as dma source which may result in deadlock." "0,1"
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bitfld.long 0x4 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
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bitfld.long 0x4 11. "CQERR,Command Queue Error Interrupt" "0,1"
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bitfld.long 0x4 10. "CQPAUSED,Command Queue is Paused." "0,1"
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bitfld.long 0x4 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
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bitfld.long 0x4 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
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bitfld.long 0x4 7. "DERR,DMA Error Interrupt" "0,1"
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bitfld.long 0x4 6. "DCMP,DMA Complete Interrupt" "0,1"
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bitfld.long 0x4 5. "RXF,Receive FIFO full" "0,1"
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bitfld.long 0x4 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
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bitfld.long 0x4 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
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bitfld.long 0x4 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
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bitfld.long 0x4 1. "TXE,Transmit FIFO empty." "0,1"
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bitfld.long 0x4 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
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line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
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bitfld.long 0x8 13. "APBDMAERR,MSPI is dma target as well as dma source which may result in deadlock." "0,1"
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bitfld.long 0x8 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
|
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|
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bitfld.long 0x8 11. "CQERR,Command Queue Error Interrupt" "0,1"
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|
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bitfld.long 0x8 10. "CQPAUSED,Command Queue is Paused." "0,1"
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bitfld.long 0x8 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
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bitfld.long 0x8 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
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bitfld.long 0x8 7. "DERR,DMA Error Interrupt" "0,1"
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bitfld.long 0x8 6. "DCMP,DMA Complete Interrupt" "0,1"
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|
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bitfld.long 0x8 5. "RXF,Receive FIFO full" "0,1"
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bitfld.long 0x8 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
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bitfld.long 0x8 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
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|
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bitfld.long 0x8 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
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|
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bitfld.long 0x8 1. "TXE,Transmit FIFO empty." "0,1"
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|
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bitfld.long 0x8 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
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line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
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bitfld.long 0xC 13. "APBDMAERR,MSPI is dma target as well as dma source which may result in deadlock." "0,1"
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|
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bitfld.long 0xC 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
|
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|
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bitfld.long 0xC 11. "CQERR,Command Queue Error Interrupt" "0,1"
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|
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bitfld.long 0xC 10. "CQPAUSED,Command Queue is Paused." "0,1"
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|
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bitfld.long 0xC 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
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|
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bitfld.long 0xC 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
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|
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bitfld.long 0xC 7. "DERR,DMA Error Interrupt" "0,1"
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|
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|
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bitfld.long 0xC 6. "DCMP,DMA Complete Interrupt" "0,1"
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|
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bitfld.long 0xC 5. "RXF,Receive FIFO full" "0,1"
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bitfld.long 0xC 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
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|
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bitfld.long 0xC 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
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|
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|
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bitfld.long 0xC 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
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|
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bitfld.long 0xC 1. "TXE,Transmit FIFO empty." "0,1"
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|
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bitfld.long 0xC 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
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group.long 0x2A0++0x3
|
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line.long 0x0 "CQCFG,This register controls Command Queuing (CQ) operations in a manner similar to the DMACFG register."
|
|
bitfld.long 0x0 4. "CQPAUSEOP,CQPAUSEOP register description needed." "0,1"
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bitfld.long 0x0 3. "CQAUTOCLEARMASK,Enable clear of CQMASK after each pause operation. This may be useful when using software flags to pause CQ." "0,1"
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|
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bitfld.long 0x0 2. "CQPWROFF,Power off MSPI domain upon completion of DMA operation." "0,1"
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|
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|
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bitfld.long 0x0 1. "CQPRI,Sets the Priority of the command queue DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x0 0. "CQEN,Command queue enable. When set will enable the processing of the command queue" "0: Disable CQ Function,1: Enable CQ Function"
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group.long 0x2A8++0x13
|
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line.long 0x0 "CQADDR,Location of the command queue in SRAM or flash memory. This register will increment as CQ operations commence. Software should only write CQADDR when CQEN is disabled. however the command queue script itself may update CQADDR in order to perform.."
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hexmask.long 0x0 0.--28. 1. "CQADDR,Address of command queue buffer in SRAM or flash. The buffer address must be aligned to a word boundary."
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line.long 0x4 "CQSTAT,Command Queue Status"
|
|
bitfld.long 0x4 3. "CQPAUSED,Command queue is currently paused status." "0,1"
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|
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bitfld.long 0x4 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
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|
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bitfld.long 0x4 1. "CQCPL,Command queue operation Complete. This signals the end of the command queue operation." "0,1"
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|
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|
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bitfld.long 0x4 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
|
|
line.long 0x8 "CQFLAGS,Command Queue Flags"
|
|
hexmask.long.word 0x8 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
|
|
line.long 0xC "CQSETCLEAR,Command Queue Flag Set/Clear"
|
|
hexmask.long.byte 0xC 16.--23. 1. "CQFCLR,Clear CQFlag status bits."
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|
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hexmask.long.byte 0xC 8.--15. 1. "CQFTOGGLE,Toggle CQFlag status bits"
|
|
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|
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hexmask.long.byte 0xC 0.--7. 1. "CQFSET,Set CQFlag status bits. Set has priority over clear if both are high."
|
|
line.long 0x10 "CQPAUSE,Command Queue Pause Mask"
|
|
hexmask.long.word 0x10 0.--15. 1. "CQMASK,CQ will pause processing when ALL specified events are satisfied -- i.e. when (CQMASK and CQPAUSE)==CQMASK."
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|
group.long 0x2C0++0x7
|
|
line.long 0x0 "CQCURIDX,This register can be used in conjunction with the CQENDIDX register to manage the command queue. Typically software will initialize the CQCURIDX and CQENDIDX to the same value. which will cause the CQ to be paused when enabled. Software may then.."
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hexmask.long.byte 0x0 0.--7. 1. "CQCURIDX,Can be used to indicate the current position of the command queue by having CQ operations write this field. A CQ hardware status flag indicates when CURIDX and ENDIDX are not equal allowing SW to pause the CQ processing until the end index is.."
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|
line.long 0x4 "CQENDIDX,Command Queue End Index"
|
|
hexmask.long.byte 0x4 0.--7. 1. "CQENDIDX,Can be used to indicate the end position of the command queue. A CQ hardware status bit indices when CURIDX != ENDIDX so that the CQ can be paused when it reaches the end pointer."
|
|
group.long 0x310++0x3
|
|
line.long 0x0 "STATXIPDMA,Debug XIP DMA State"
|
|
hexmask.long 0x0 0.--31. 1. "FLD32,XIP/DMA module debug"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "PDM (PDM Audio)"
|
|
base ad:0x0
|
|
tree "PDM0"
|
|
base ad:0x40201000
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "CTRL,PDM Control"
|
|
bitfld.long 0x0 6. "EN,PDM enable register" "0: Disable PDM.,1: Enable PDM."
|
|
bitfld.long 0x0 5. "PCMPACK,Enable PCM packing. Only 24-bit unpacked mode supported." "0: Disable PCM packing.,1: Enable PCM packing."
|
|
newline
|
|
bitfld.long 0x0 4. "RSTB,Reset IP core. 0 puts the core in reset; 1 takes the core out of reset." "0: Put the core in reset.,1: Core not in reset."
|
|
bitfld.long 0x0 1.--2. "CLKSEL,PDM Master Clock select (24.576MHz)." "0: HFRC2_192MHz div8 with HFAdj2,1: XTAL_HS Byapss,2: HFRC_96MHz div4,?"
|
|
newline
|
|
bitfld.long 0x0 0. "CLKEN,PDM Clock enable." "0: Disable serial clock,1: Enable serial clock"
|
|
line.long 0x4 "CORECFG0,PDM to PCM Core Configuration"
|
|
hexmask.long.byte 0x4 26.--30. 1. "PGAR,Right Channel PGA Gain:"
|
|
hexmask.long.byte 0x4 21.--25. 1. "PGAL,Left Channel PGA Gain:"
|
|
newline
|
|
hexmask.long.byte 0x4 14.--20. 1. "SINCRATE,Sinc decimation rate."
|
|
hexmask.long.byte 0x4 10.--13. 1. "MCLKDIV,PDMA_CKO frequency divisor."
|
|
newline
|
|
bitfld.long 0x4 9. "ADCHPD,Disable high pass filter when = 1" "0: Disable high pass filter.,1: Enable high pass filter."
|
|
hexmask.long.byte 0x4 5.--8. 1. "HPGAIN,Adjust High Pass filter coefficients"
|
|
newline
|
|
bitfld.long 0x4 2.--4. "SCYCLES,Set number of PDMA_CKO cycles during gain setting changes or soft mute" "0: Zero PDMA_CK0 clock cycles during gain setting..,1: One PDMA_CK0 clock cycle during gain setting..,2: Two PDMA_CK0 clock cycles during gain setting..,3: Three PDMA_CK0 clock cycles during gain setting..,4: Four PDMA_CK0 clock cycles during gain setting..,5: Five PDMA_CK0 clock cycles during gain setting..,6: Six PDMA_CK0 clock cycles during gain setting..,7: Seven PDMA_CK0 clock cycles during gain setting.."
|
|
bitfld.long 0x4 1. "SOFTMUTE,Soft mute enable when = 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "LRSWAP,Left/Right channel swap when = 1" "0: Disable left/right channel swapping.,1: Enable left/right channel swapping."
|
|
line.long 0x8 "CORECFG1,PDM to PCM Extra Configuration"
|
|
bitfld.long 0x8 7. "SELSTEP,Fine grain step size for smooth PGA or Softmute attenuation transition" "0: 0.13dB fine grain step size.,1: 0.26dB fine grain step size."
|
|
bitfld.long 0x8 4.--6. "CKODLY,PDMA_CKO clock phase delay in terms of PDMCLK period to internal sampler" "0: No extra PDMCLK cycle delays.,1: One xtra PDMCLK cycle delay.,2: Two extra PDMCLK cycle delays.,3: Three extra PDMCLK cycle delays.,4: Four extra PDMCLK cycle delays.,5: Five extra PDMCLK cycle delays.,6: Six extra PDMCLK cycle delays.,7: Seven extra PDMCLK cycle delays."
|
|
newline
|
|
bitfld.long 0x8 2.--3. "DIVMCLKQ,Divide down ratio for generating internal master MCLKQ." "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "PCMCHSET,PCM output chanel 0xsetting" "0: Channel Disabled,1: MONO Left,2: MONO right,3: Stereo"
|
|
line.long 0xC "CORECTRL,PDM to PCM Control"
|
|
hexmask.long 0xC 0.--31. 1. "CORECTRL,Overall control of PDM core. Internal use only"
|
|
line.long 0x10 "FIFOCNT,FIFO count"
|
|
hexmask.long.byte 0x10 0.--5. 1. "FIFOCNT,Valid 32-bit entries currently in the FIFO."
|
|
line.long 0x14 "FIFOREAD,FIFO Read"
|
|
hexmask.long 0x14 0.--31. 1. "FIFOREAD,FIFO read data."
|
|
line.long 0x18 "FIFOFLUSH,FIFO Flush"
|
|
bitfld.long 0x18 0. "FIFOFLUSH,FIFO FLUSH." "0,1"
|
|
line.long 0x1C "FIFOTHR,FIFO Threshold"
|
|
hexmask.long.byte 0x1C 0.--4. 1. "FIFOTHR,FIFO Threshold value. When the FIFO count is equal to or larger than this value (in words) a THR interrupt is generated (if enabled). If used for DMA purposes then only supported values are 0x4 0x8 0xc 0x10 0x14 0x18 and 0x1C."
|
|
group.long 0x100++0xF
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 4. "DERR,DMA Error receieved" "0,1"
|
|
bitfld.long 0x0 3. "DCMP,DMA completed a transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "UNDFL,This is the FIFO underflow interrupt." "0,1"
|
|
bitfld.long 0x0 1. "OVF,This is the FIFO overflow interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "THR,This is the FIFO threshold interrupt." "0,1"
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 4. "DERR,DMA Error receieved" "0,1"
|
|
bitfld.long 0x4 3. "DCMP,DMA completed a transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "UNDFL,This is the FIFO underflow interrupt." "0,1"
|
|
bitfld.long 0x4 1. "OVF,This is the FIFO overflow interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "THR,This is the FIFO threshold interrupt." "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 4. "DERR,DMA Error receieved" "0,1"
|
|
bitfld.long 0x8 3. "DCMP,DMA completed a transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "UNDFL,This is the FIFO underflow interrupt." "0,1"
|
|
bitfld.long 0x8 1. "OVF,This is the FIFO overflow interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "THR,This is the FIFO threshold interrupt." "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 4. "DERR,DMA Error receieved" "0,1"
|
|
bitfld.long 0xC 3. "DCMP,DMA completed a transfer" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "UNDFL,This is the FIFO underflow interrupt." "0,1"
|
|
bitfld.long 0xC 1. "OVF,This is the FIFO overflow interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "THR,This is the FIFO threshold interrupt." "0,1"
|
|
group.long 0x140++0xB
|
|
line.long 0x0 "DMATRIGEN,DMA Trigger Enable"
|
|
bitfld.long 0x0 1. "DTHR90,Trigger DMA at FIFO 90 percent full. This signal is also used internally for AUTOHIP function" "0,1"
|
|
bitfld.long 0x0 0. "DTHR,Trigger DMA upon when FIFO iss filled to level indicated by the FIFO THRESHOLD at granularity of 16 bytes only" "0,1"
|
|
line.long 0x4 "DMATRIGSTAT,DMA Trigger Status"
|
|
bitfld.long 0x4 1. "DTHR90STAT,Triggered DMA from FIFO reaching 90 percent full" "0,1"
|
|
bitfld.long 0x4 0. "DTHRSTAT,Triggered DMA from FIFO reaching threshold" "0,1"
|
|
line.long 0x8 "DMACFG,DMA Configuration"
|
|
bitfld.long 0x8 10. "DPWROFF,Power Off the ADC System upon DMACPL." "0,1"
|
|
bitfld.long 0x8 9. "DAUTOHIP,Raise priority to high on fifo full and DMAPRI set to low" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
|
|
bitfld.long 0x8 2. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction. THe PDM..,1: Memory to Peripheral transaction. Not available.."
|
|
newline
|
|
bitfld.long 0x8 0. "DMAEN,DMA Enable" "0: Disable DMA Function,1: Enable DMA Function"
|
|
group.long 0x154++0x7
|
|
line.long 0x0 "DMATARGADDR,DMA Target Address"
|
|
hexmask.long.byte 0x0 28.--31. 1. "UTARGADDR,SRAM Target"
|
|
hexmask.long 0x0 0.--27. 1. "LTARGADDR,DMA Target Address. This register is not updated with the current address of the DMA but will remain static with the original address during the DMA transfer."
|
|
line.long 0x4 "DMASTAT,DMA Status"
|
|
bitfld.long 0x4 2. "DMAERR,DMA Error" "0,1"
|
|
bitfld.long 0x4 1. "DMACPL,DMA Transfer Complete" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DMATIP,DMA Transfer In Progress" "0,1"
|
|
group.long 0x250++0x3
|
|
line.long 0x0 "DMATOTCOUNT,DMA Total Transfer Count"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "TOTCOUNT,Total Transfer Count. The transfer count must be a multiple of the THR setting to avoid DMA overruns."
|
|
tree.end
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMA4B2KP")||cpuis("AMAP42KK")||cpuis("AMAP42KP"))
|
|
tree "PDM1"
|
|
base ad:0x40202000
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "CTRL,PDM Control"
|
|
bitfld.long 0x0 6. "EN,PDM enable register" "0: Disable PDM.,1: Enable PDM."
|
|
bitfld.long 0x0 5. "PCMPACK,Enable PCM packing. Only 24-bit unpacked mode supported." "0: Disable PCM packing.,1: Enable PCM packing."
|
|
newline
|
|
bitfld.long 0x0 4. "RSTB,Reset IP core. 0 puts the core in reset; 1 takes the core out of reset." "0: Put the core in reset.,1: Core not in reset."
|
|
bitfld.long 0x0 1.--2. "CLKSEL,PDM Master Clock select (24.576MHz)." "0: HFRC2_192MHz div8 with HFAdj2,1: XTAL_HS Byapss,2: HFRC_96MHz div4,?"
|
|
newline
|
|
bitfld.long 0x0 0. "CLKEN,PDM Clock enable." "0: Disable serial clock,1: Enable serial clock"
|
|
line.long 0x4 "CORECFG0,PDM to PCM Core Configuration"
|
|
hexmask.long.byte 0x4 26.--30. 1. "PGAR,Right Channel PGA Gain:"
|
|
hexmask.long.byte 0x4 21.--25. 1. "PGAL,Left Channel PGA Gain:"
|
|
newline
|
|
hexmask.long.byte 0x4 14.--20. 1. "SINCRATE,Sinc decimation rate."
|
|
hexmask.long.byte 0x4 10.--13. 1. "MCLKDIV,PDMA_CKO frequency divisor."
|
|
newline
|
|
bitfld.long 0x4 9. "ADCHPD,Disable high pass filter when = 1" "0: Disable high pass filter.,1: Enable high pass filter."
|
|
hexmask.long.byte 0x4 5.--8. 1. "HPGAIN,Adjust High Pass filter coefficients"
|
|
newline
|
|
bitfld.long 0x4 2.--4. "SCYCLES,Set number of PDMA_CKO cycles during gain setting changes or soft mute" "0: Zero PDMA_CK0 clock cycles during gain setting..,1: One PDMA_CK0 clock cycle during gain setting..,2: Two PDMA_CK0 clock cycles during gain setting..,3: Three PDMA_CK0 clock cycles during gain setting..,4: Four PDMA_CK0 clock cycles during gain setting..,5: Five PDMA_CK0 clock cycles during gain setting..,6: Six PDMA_CK0 clock cycles during gain setting..,7: Seven PDMA_CK0 clock cycles during gain setting.."
|
|
bitfld.long 0x4 1. "SOFTMUTE,Soft mute enable when = 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "LRSWAP,Left/Right channel swap when = 1" "0: Disable left/right channel swapping.,1: Enable left/right channel swapping."
|
|
line.long 0x8 "CORECFG1,PDM to PCM Extra Configuration"
|
|
bitfld.long 0x8 7. "SELSTEP,Fine grain step size for smooth PGA or Softmute attenuation transition" "0: 0.13dB fine grain step size.,1: 0.26dB fine grain step size."
|
|
bitfld.long 0x8 4.--6. "CKODLY,PDMA_CKO clock phase delay in terms of PDMCLK period to internal sampler" "0: No extra PDMCLK cycle delays.,1: One xtra PDMCLK cycle delay.,2: Two extra PDMCLK cycle delays.,3: Three extra PDMCLK cycle delays.,4: Four extra PDMCLK cycle delays.,5: Five extra PDMCLK cycle delays.,6: Six extra PDMCLK cycle delays.,7: Seven extra PDMCLK cycle delays."
|
|
newline
|
|
bitfld.long 0x8 2.--3. "DIVMCLKQ,Divide down ratio for generating internal master MCLKQ." "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "PCMCHSET,PCM output chanel 0xsetting" "0: Channel Disabled,1: MONO Left,2: MONO right,3: Stereo"
|
|
line.long 0xC "CORECTRL,PDM to PCM Control"
|
|
hexmask.long 0xC 0.--31. 1. "CORECTRL,Overall control of PDM core. Internal use only"
|
|
line.long 0x10 "FIFOCNT,FIFO count"
|
|
hexmask.long.byte 0x10 0.--5. 1. "FIFOCNT,Valid 32-bit entries currently in the FIFO."
|
|
line.long 0x14 "FIFOREAD,FIFO Read"
|
|
hexmask.long 0x14 0.--31. 1. "FIFOREAD,FIFO read data."
|
|
line.long 0x18 "FIFOFLUSH,FIFO Flush"
|
|
bitfld.long 0x18 0. "FIFOFLUSH,FIFO FLUSH." "0,1"
|
|
line.long 0x1C "FIFOTHR,FIFO Threshold"
|
|
hexmask.long.byte 0x1C 0.--4. 1. "FIFOTHR,FIFO Threshold value. When the FIFO count is equal to or larger than this value (in words) a THR interrupt is generated (if enabled). If used for DMA purposes then only supported values are 0x4 0x8 0xc 0x10 0x14 0x18 and 0x1C."
|
|
group.long 0x100++0xF
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 4. "DERR,DMA Error receieved" "0,1"
|
|
bitfld.long 0x0 3. "DCMP,DMA completed a transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "UNDFL,This is the FIFO underflow interrupt." "0,1"
|
|
bitfld.long 0x0 1. "OVF,This is the FIFO overflow interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "THR,This is the FIFO threshold interrupt." "0,1"
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 4. "DERR,DMA Error receieved" "0,1"
|
|
bitfld.long 0x4 3. "DCMP,DMA completed a transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "UNDFL,This is the FIFO underflow interrupt." "0,1"
|
|
bitfld.long 0x4 1. "OVF,This is the FIFO overflow interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "THR,This is the FIFO threshold interrupt." "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 4. "DERR,DMA Error receieved" "0,1"
|
|
bitfld.long 0x8 3. "DCMP,DMA completed a transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "UNDFL,This is the FIFO underflow interrupt." "0,1"
|
|
bitfld.long 0x8 1. "OVF,This is the FIFO overflow interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "THR,This is the FIFO threshold interrupt." "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 4. "DERR,DMA Error receieved" "0,1"
|
|
bitfld.long 0xC 3. "DCMP,DMA completed a transfer" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "UNDFL,This is the FIFO underflow interrupt." "0,1"
|
|
bitfld.long 0xC 1. "OVF,This is the FIFO overflow interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "THR,This is the FIFO threshold interrupt." "0,1"
|
|
group.long 0x140++0xB
|
|
line.long 0x0 "DMATRIGEN,DMA Trigger Enable"
|
|
bitfld.long 0x0 1. "DTHR90,Trigger DMA at FIFO 90 percent full. This signal is also used internally for AUTOHIP function" "0,1"
|
|
bitfld.long 0x0 0. "DTHR,Trigger DMA upon when FIFO iss filled to level indicated by the FIFO THRESHOLD at granularity of 16 bytes only" "0,1"
|
|
line.long 0x4 "DMATRIGSTAT,DMA Trigger Status"
|
|
bitfld.long 0x4 1. "DTHR90STAT,Triggered DMA from FIFO reaching 90 percent full" "0,1"
|
|
bitfld.long 0x4 0. "DTHRSTAT,Triggered DMA from FIFO reaching threshold" "0,1"
|
|
line.long 0x8 "DMACFG,DMA Configuration"
|
|
bitfld.long 0x8 10. "DPWROFF,Power Off the ADC System upon DMACPL." "0,1"
|
|
bitfld.long 0x8 9. "DAUTOHIP,Raise priority to high on fifo full and DMAPRI set to low" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
|
|
bitfld.long 0x8 2. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction. THe PDM..,1: Memory to Peripheral transaction. Not available.."
|
|
newline
|
|
bitfld.long 0x8 0. "DMAEN,DMA Enable" "0: Disable DMA Function,1: Enable DMA Function"
|
|
group.long 0x154++0x7
|
|
line.long 0x0 "DMATARGADDR,DMA Target Address"
|
|
hexmask.long.byte 0x0 28.--31. 1. "UTARGADDR,SRAM Target"
|
|
hexmask.long 0x0 0.--27. 1. "LTARGADDR,DMA Target Address. This register is not updated with the current address of the DMA but will remain static with the original address during the DMA transfer."
|
|
line.long 0x4 "DMASTAT,DMA Status"
|
|
bitfld.long 0x4 2. "DMAERR,DMA Error" "0,1"
|
|
bitfld.long 0x4 1. "DMACPL,DMA Transfer Complete" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DMATIP,DMA Transfer In Progress" "0,1"
|
|
group.long 0x250++0x3
|
|
line.long 0x0 "DMATOTCOUNT,DMA Total Transfer Count"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "TOTCOUNT,Total Transfer Count. The transfer count must be a multiple of the THR setting to avoid DMA overruns."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMA4B2KP")||cpuis("AMAP42KK")||cpuis("AMAP42KP"))
|
|
tree "PDM2"
|
|
base ad:0x40203000
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "CTRL,PDM Control"
|
|
bitfld.long 0x0 6. "EN,PDM enable register" "0: Disable PDM.,1: Enable PDM."
|
|
bitfld.long 0x0 5. "PCMPACK,Enable PCM packing. Only 24-bit unpacked mode supported." "0: Disable PCM packing.,1: Enable PCM packing."
|
|
newline
|
|
bitfld.long 0x0 4. "RSTB,Reset IP core. 0 puts the core in reset; 1 takes the core out of reset." "0: Put the core in reset.,1: Core not in reset."
|
|
bitfld.long 0x0 1.--2. "CLKSEL,PDM Master Clock select (24.576MHz)." "0: HFRC2_192MHz div8 with HFAdj2,1: XTAL_HS Byapss,2: HFRC_96MHz div4,?"
|
|
newline
|
|
bitfld.long 0x0 0. "CLKEN,PDM Clock enable." "0: Disable serial clock,1: Enable serial clock"
|
|
line.long 0x4 "CORECFG0,PDM to PCM Core Configuration"
|
|
hexmask.long.byte 0x4 26.--30. 1. "PGAR,Right Channel PGA Gain:"
|
|
hexmask.long.byte 0x4 21.--25. 1. "PGAL,Left Channel PGA Gain:"
|
|
newline
|
|
hexmask.long.byte 0x4 14.--20. 1. "SINCRATE,Sinc decimation rate."
|
|
hexmask.long.byte 0x4 10.--13. 1. "MCLKDIV,PDMA_CKO frequency divisor."
|
|
newline
|
|
bitfld.long 0x4 9. "ADCHPD,Disable high pass filter when = 1" "0: Disable high pass filter.,1: Enable high pass filter."
|
|
hexmask.long.byte 0x4 5.--8. 1. "HPGAIN,Adjust High Pass filter coefficients"
|
|
newline
|
|
bitfld.long 0x4 2.--4. "SCYCLES,Set number of PDMA_CKO cycles during gain setting changes or soft mute" "0: Zero PDMA_CK0 clock cycles during gain setting..,1: One PDMA_CK0 clock cycle during gain setting..,2: Two PDMA_CK0 clock cycles during gain setting..,3: Three PDMA_CK0 clock cycles during gain setting..,4: Four PDMA_CK0 clock cycles during gain setting..,5: Five PDMA_CK0 clock cycles during gain setting..,6: Six PDMA_CK0 clock cycles during gain setting..,7: Seven PDMA_CK0 clock cycles during gain setting.."
|
|
bitfld.long 0x4 1. "SOFTMUTE,Soft mute enable when = 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "LRSWAP,Left/Right channel swap when = 1" "0: Disable left/right channel swapping.,1: Enable left/right channel swapping."
|
|
line.long 0x8 "CORECFG1,PDM to PCM Extra Configuration"
|
|
bitfld.long 0x8 7. "SELSTEP,Fine grain step size for smooth PGA or Softmute attenuation transition" "0: 0.13dB fine grain step size.,1: 0.26dB fine grain step size."
|
|
bitfld.long 0x8 4.--6. "CKODLY,PDMA_CKO clock phase delay in terms of PDMCLK period to internal sampler" "0: No extra PDMCLK cycle delays.,1: One xtra PDMCLK cycle delay.,2: Two extra PDMCLK cycle delays.,3: Three extra PDMCLK cycle delays.,4: Four extra PDMCLK cycle delays.,5: Five extra PDMCLK cycle delays.,6: Six extra PDMCLK cycle delays.,7: Seven extra PDMCLK cycle delays."
|
|
newline
|
|
bitfld.long 0x8 2.--3. "DIVMCLKQ,Divide down ratio for generating internal master MCLKQ." "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "PCMCHSET,PCM output chanel 0xsetting" "0: Channel Disabled,1: MONO Left,2: MONO right,3: Stereo"
|
|
line.long 0xC "CORECTRL,PDM to PCM Control"
|
|
hexmask.long 0xC 0.--31. 1. "CORECTRL,Overall control of PDM core. Internal use only"
|
|
line.long 0x10 "FIFOCNT,FIFO count"
|
|
hexmask.long.byte 0x10 0.--5. 1. "FIFOCNT,Valid 32-bit entries currently in the FIFO."
|
|
line.long 0x14 "FIFOREAD,FIFO Read"
|
|
hexmask.long 0x14 0.--31. 1. "FIFOREAD,FIFO read data."
|
|
line.long 0x18 "FIFOFLUSH,FIFO Flush"
|
|
bitfld.long 0x18 0. "FIFOFLUSH,FIFO FLUSH." "0,1"
|
|
line.long 0x1C "FIFOTHR,FIFO Threshold"
|
|
hexmask.long.byte 0x1C 0.--4. 1. "FIFOTHR,FIFO Threshold value. When the FIFO count is equal to or larger than this value (in words) a THR interrupt is generated (if enabled). If used for DMA purposes then only supported values are 0x4 0x8 0xc 0x10 0x14 0x18 and 0x1C."
|
|
group.long 0x100++0xF
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 4. "DERR,DMA Error receieved" "0,1"
|
|
bitfld.long 0x0 3. "DCMP,DMA completed a transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "UNDFL,This is the FIFO underflow interrupt." "0,1"
|
|
bitfld.long 0x0 1. "OVF,This is the FIFO overflow interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "THR,This is the FIFO threshold interrupt." "0,1"
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 4. "DERR,DMA Error receieved" "0,1"
|
|
bitfld.long 0x4 3. "DCMP,DMA completed a transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "UNDFL,This is the FIFO underflow interrupt." "0,1"
|
|
bitfld.long 0x4 1. "OVF,This is the FIFO overflow interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "THR,This is the FIFO threshold interrupt." "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 4. "DERR,DMA Error receieved" "0,1"
|
|
bitfld.long 0x8 3. "DCMP,DMA completed a transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "UNDFL,This is the FIFO underflow interrupt." "0,1"
|
|
bitfld.long 0x8 1. "OVF,This is the FIFO overflow interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "THR,This is the FIFO threshold interrupt." "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 4. "DERR,DMA Error receieved" "0,1"
|
|
bitfld.long 0xC 3. "DCMP,DMA completed a transfer" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "UNDFL,This is the FIFO underflow interrupt." "0,1"
|
|
bitfld.long 0xC 1. "OVF,This is the FIFO overflow interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "THR,This is the FIFO threshold interrupt." "0,1"
|
|
group.long 0x140++0xB
|
|
line.long 0x0 "DMATRIGEN,DMA Trigger Enable"
|
|
bitfld.long 0x0 1. "DTHR90,Trigger DMA at FIFO 90 percent full. This signal is also used internally for AUTOHIP function" "0,1"
|
|
bitfld.long 0x0 0. "DTHR,Trigger DMA upon when FIFO iss filled to level indicated by the FIFO THRESHOLD at granularity of 16 bytes only" "0,1"
|
|
line.long 0x4 "DMATRIGSTAT,DMA Trigger Status"
|
|
bitfld.long 0x4 1. "DTHR90STAT,Triggered DMA from FIFO reaching 90 percent full" "0,1"
|
|
bitfld.long 0x4 0. "DTHRSTAT,Triggered DMA from FIFO reaching threshold" "0,1"
|
|
line.long 0x8 "DMACFG,DMA Configuration"
|
|
bitfld.long 0x8 10. "DPWROFF,Power Off the ADC System upon DMACPL." "0,1"
|
|
bitfld.long 0x8 9. "DAUTOHIP,Raise priority to high on fifo full and DMAPRI set to low" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
|
|
bitfld.long 0x8 2. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction. THe PDM..,1: Memory to Peripheral transaction. Not available.."
|
|
newline
|
|
bitfld.long 0x8 0. "DMAEN,DMA Enable" "0: Disable DMA Function,1: Enable DMA Function"
|
|
group.long 0x154++0x7
|
|
line.long 0x0 "DMATARGADDR,DMA Target Address"
|
|
hexmask.long.byte 0x0 28.--31. 1. "UTARGADDR,SRAM Target"
|
|
hexmask.long 0x0 0.--27. 1. "LTARGADDR,DMA Target Address. This register is not updated with the current address of the DMA but will remain static with the original address during the DMA transfer."
|
|
line.long 0x4 "DMASTAT,DMA Status"
|
|
bitfld.long 0x4 2. "DMAERR,DMA Error" "0,1"
|
|
bitfld.long 0x4 1. "DMACPL,DMA Transfer Complete" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DMATIP,DMA Transfer In Progress" "0,1"
|
|
group.long 0x250++0x3
|
|
line.long 0x0 "DMATOTCOUNT,DMA Total Transfer Count"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "TOTCOUNT,Total Transfer Count. The transfer count must be a multiple of the THR setting to avoid DMA overruns."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMA4B2KP")||cpuis("AMAP42KK")||cpuis("AMAP42KP"))
|
|
tree "PDM3"
|
|
base ad:0x40204000
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "CTRL,PDM Control"
|
|
bitfld.long 0x0 6. "EN,PDM enable register" "0: Disable PDM.,1: Enable PDM."
|
|
bitfld.long 0x0 5. "PCMPACK,Enable PCM packing. Only 24-bit unpacked mode supported." "0: Disable PCM packing.,1: Enable PCM packing."
|
|
newline
|
|
bitfld.long 0x0 4. "RSTB,Reset IP core. 0 puts the core in reset; 1 takes the core out of reset." "0: Put the core in reset.,1: Core not in reset."
|
|
bitfld.long 0x0 1.--2. "CLKSEL,PDM Master Clock select (24.576MHz)." "0: HFRC2_192MHz div8 with HFAdj2,1: XTAL_HS Byapss,2: HFRC_96MHz div4,?"
|
|
newline
|
|
bitfld.long 0x0 0. "CLKEN,PDM Clock enable." "0: Disable serial clock,1: Enable serial clock"
|
|
line.long 0x4 "CORECFG0,PDM to PCM Core Configuration"
|
|
hexmask.long.byte 0x4 26.--30. 1. "PGAR,Right Channel PGA Gain:"
|
|
hexmask.long.byte 0x4 21.--25. 1. "PGAL,Left Channel PGA Gain:"
|
|
newline
|
|
hexmask.long.byte 0x4 14.--20. 1. "SINCRATE,Sinc decimation rate."
|
|
hexmask.long.byte 0x4 10.--13. 1. "MCLKDIV,PDMA_CKO frequency divisor."
|
|
newline
|
|
bitfld.long 0x4 9. "ADCHPD,Disable high pass filter when = 1" "0: Disable high pass filter.,1: Enable high pass filter."
|
|
hexmask.long.byte 0x4 5.--8. 1. "HPGAIN,Adjust High Pass filter coefficients"
|
|
newline
|
|
bitfld.long 0x4 2.--4. "SCYCLES,Set number of PDMA_CKO cycles during gain setting changes or soft mute" "0: Zero PDMA_CK0 clock cycles during gain setting..,1: One PDMA_CK0 clock cycle during gain setting..,2: Two PDMA_CK0 clock cycles during gain setting..,3: Three PDMA_CK0 clock cycles during gain setting..,4: Four PDMA_CK0 clock cycles during gain setting..,5: Five PDMA_CK0 clock cycles during gain setting..,6: Six PDMA_CK0 clock cycles during gain setting..,7: Seven PDMA_CK0 clock cycles during gain setting.."
|
|
bitfld.long 0x4 1. "SOFTMUTE,Soft mute enable when = 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "LRSWAP,Left/Right channel swap when = 1" "0: Disable left/right channel swapping.,1: Enable left/right channel swapping."
|
|
line.long 0x8 "CORECFG1,PDM to PCM Extra Configuration"
|
|
bitfld.long 0x8 7. "SELSTEP,Fine grain step size for smooth PGA or Softmute attenuation transition" "0: 0.13dB fine grain step size.,1: 0.26dB fine grain step size."
|
|
bitfld.long 0x8 4.--6. "CKODLY,PDMA_CKO clock phase delay in terms of PDMCLK period to internal sampler" "0: No extra PDMCLK cycle delays.,1: One xtra PDMCLK cycle delay.,2: Two extra PDMCLK cycle delays.,3: Three extra PDMCLK cycle delays.,4: Four extra PDMCLK cycle delays.,5: Five extra PDMCLK cycle delays.,6: Six extra PDMCLK cycle delays.,7: Seven extra PDMCLK cycle delays."
|
|
newline
|
|
bitfld.long 0x8 2.--3. "DIVMCLKQ,Divide down ratio for generating internal master MCLKQ." "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "PCMCHSET,PCM output chanel 0xsetting" "0: Channel Disabled,1: MONO Left,2: MONO right,3: Stereo"
|
|
line.long 0xC "CORECTRL,PDM to PCM Control"
|
|
hexmask.long 0xC 0.--31. 1. "CORECTRL,Overall control of PDM core. Internal use only"
|
|
line.long 0x10 "FIFOCNT,FIFO count"
|
|
hexmask.long.byte 0x10 0.--5. 1. "FIFOCNT,Valid 32-bit entries currently in the FIFO."
|
|
line.long 0x14 "FIFOREAD,FIFO Read"
|
|
hexmask.long 0x14 0.--31. 1. "FIFOREAD,FIFO read data."
|
|
line.long 0x18 "FIFOFLUSH,FIFO Flush"
|
|
bitfld.long 0x18 0. "FIFOFLUSH,FIFO FLUSH." "0,1"
|
|
line.long 0x1C "FIFOTHR,FIFO Threshold"
|
|
hexmask.long.byte 0x1C 0.--4. 1. "FIFOTHR,FIFO Threshold value. When the FIFO count is equal to or larger than this value (in words) a THR interrupt is generated (if enabled). If used for DMA purposes then only supported values are 0x4 0x8 0xc 0x10 0x14 0x18 and 0x1C."
|
|
group.long 0x100++0xF
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 4. "DERR,DMA Error receieved" "0,1"
|
|
bitfld.long 0x0 3. "DCMP,DMA completed a transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "UNDFL,This is the FIFO underflow interrupt." "0,1"
|
|
bitfld.long 0x0 1. "OVF,This is the FIFO overflow interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "THR,This is the FIFO threshold interrupt." "0,1"
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 4. "DERR,DMA Error receieved" "0,1"
|
|
bitfld.long 0x4 3. "DCMP,DMA completed a transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "UNDFL,This is the FIFO underflow interrupt." "0,1"
|
|
bitfld.long 0x4 1. "OVF,This is the FIFO overflow interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "THR,This is the FIFO threshold interrupt." "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 4. "DERR,DMA Error receieved" "0,1"
|
|
bitfld.long 0x8 3. "DCMP,DMA completed a transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "UNDFL,This is the FIFO underflow interrupt." "0,1"
|
|
bitfld.long 0x8 1. "OVF,This is the FIFO overflow interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "THR,This is the FIFO threshold interrupt." "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 4. "DERR,DMA Error receieved" "0,1"
|
|
bitfld.long 0xC 3. "DCMP,DMA completed a transfer" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "UNDFL,This is the FIFO underflow interrupt." "0,1"
|
|
bitfld.long 0xC 1. "OVF,This is the FIFO overflow interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "THR,This is the FIFO threshold interrupt." "0,1"
|
|
group.long 0x140++0xB
|
|
line.long 0x0 "DMATRIGEN,DMA Trigger Enable"
|
|
bitfld.long 0x0 1. "DTHR90,Trigger DMA at FIFO 90 percent full. This signal is also used internally for AUTOHIP function" "0,1"
|
|
bitfld.long 0x0 0. "DTHR,Trigger DMA upon when FIFO iss filled to level indicated by the FIFO THRESHOLD at granularity of 16 bytes only" "0,1"
|
|
line.long 0x4 "DMATRIGSTAT,DMA Trigger Status"
|
|
bitfld.long 0x4 1. "DTHR90STAT,Triggered DMA from FIFO reaching 90 percent full" "0,1"
|
|
bitfld.long 0x4 0. "DTHRSTAT,Triggered DMA from FIFO reaching threshold" "0,1"
|
|
line.long 0x8 "DMACFG,DMA Configuration"
|
|
bitfld.long 0x8 10. "DPWROFF,Power Off the ADC System upon DMACPL." "0,1"
|
|
bitfld.long 0x8 9. "DAUTOHIP,Raise priority to high on fifo full and DMAPRI set to low" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
|
|
bitfld.long 0x8 2. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction. THe PDM..,1: Memory to Peripheral transaction. Not available.."
|
|
newline
|
|
bitfld.long 0x8 0. "DMAEN,DMA Enable" "0: Disable DMA Function,1: Enable DMA Function"
|
|
group.long 0x154++0x7
|
|
line.long 0x0 "DMATARGADDR,DMA Target Address"
|
|
hexmask.long.byte 0x0 28.--31. 1. "UTARGADDR,SRAM Target"
|
|
hexmask.long 0x0 0.--27. 1. "LTARGADDR,DMA Target Address. This register is not updated with the current address of the DMA but will remain static with the original address during the DMA transfer."
|
|
line.long 0x4 "DMASTAT,DMA Status"
|
|
bitfld.long 0x4 2. "DMAERR,DMA Error" "0,1"
|
|
bitfld.long 0x4 1. "DMACPL,DMA Transfer Complete" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DMATIP,DMA Transfer In Progress" "0,1"
|
|
group.long 0x250++0x3
|
|
line.long 0x0 "DMATOTCOUNT,DMA Total Transfer Count"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "TOTCOUNT,Total Transfer Count. The transfer count must be a multiple of the THR setting to avoid DMA overruns."
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "PWRCTRL (PWR Controller Register Bank)"
|
|
base ad:0x40021000
|
|
group.long 0x0++0x37
|
|
line.long 0x0 "MCUPERFREQ,This register provides the performance mode knobs for MCU. S/w should write the *PERFREQ field to desired mode and wait for the *PERFACK and check for the *PERFSTATUS. Some times system may not allow certain modes but *PERFACK should always.."
|
|
bitfld.long 0x0 3.--4. "MCUPERFSTATUS,MCU Performance mode request" "0: MCU is in ULP mode (freq=24MHz),1: MCU is in LP mode (freq=96MHz),2: MCU is in HP mode (freq=192MHz),?"
|
|
newline
|
|
bitfld.long 0x0 2. "MCUPERFACK,Indicates the MCU performance status indicated in STATUS register is valid." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "MCUPERFREQ,MCU Performance mode request" "0: MCU to be run in ULP mode (freq=24MHz),1: MCU to be run in LP mode (freq=96MHz),2: MCU to be run in HP mode (freq=192MHz),?"
|
|
line.long 0x4 "DEVPWREN,This enables various peripherals power domains."
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 26. "PWRENI3C1,Powerup I3C1 power domain" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 26. "PWRENI3C1,Powerup I3C1 power domain" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 25. "PWRENI3C0,Powerup I3C0 power domain" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 25. "PWRENI3C0,Powerup I3C0 power domain" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
bitfld.long 0x4 24. "PWRENDBG,Powerup DBG power domain" "0: Disable,1: Enable"
|
|
newline
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMA4B2KP")||cpuis("AMAP42KK")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 23. "PWRENUSBPHY,Power up USB PHY" "0: Power down USB PHY,1: Power up USB PHY"
|
|
newline
|
|
bitfld.long 0x4 22. "PWRENUSB,Power up USB controller" "0: Power down USB,1: Power up USB"
|
|
newline
|
|
bitfld.long 0x4 19. "PWRENDISPPHY,Power up DISP PHY" "0: Power down DISP PHY,1: Power up DISP PHY"
|
|
newline
|
|
bitfld.long 0x4 18. "PWRENDISP,Power up DISP controller" "0: Power down DISP,1: Power up DISP"
|
|
newline
|
|
endif
|
|
bitfld.long 0x4 21. "PWRENSDIO,Power up SDIO controller" "0: Power down SDIO,1: Power up SDIO"
|
|
newline
|
|
bitfld.long 0x4 20. "PWRENCRYPTO,Power up CRYPTO module" "0: Power down CRYPTO,1: Power up CRYPTO"
|
|
newline
|
|
bitfld.long 0x4 17. "PWRENGFX,Power up GFX controller" "0: Power down GFX,1: Power up GFX"
|
|
newline
|
|
bitfld.long 0x4 16. "PWRENMSPI2,Power up MSPI Controller2" "0: Power down MSPI2,1: Power up MSPI2"
|
|
newline
|
|
bitfld.long 0x4 15. "PWRENMSPI1,Power up MSPI Controller1" "0: Power down MSPI1,1: Power up MSPI1"
|
|
newline
|
|
bitfld.long 0x4 14. "PWRENMSPI0,Power up MSPI Controller0" "0: Power down MSPI0,1: Power up MSPI0"
|
|
newline
|
|
bitfld.long 0x4 13. "PWRENADC,Power up ADC Digital Controller" "0: Power Down ADC,1: Power up ADC"
|
|
newline
|
|
bitfld.long 0x4 12. "PWRENUART3,Power up UART Controller 3" "0: Power down UART 3,1: Power up UART 3"
|
|
newline
|
|
bitfld.long 0x4 11. "PWRENUART2,Power up UART Controller 2" "0: Power down UART 2,1: Power up UART 2"
|
|
newline
|
|
bitfld.long 0x4 10. "PWRENUART1,Power up UART Controller 1" "0: Power down UART 1,1: Power up UART 1"
|
|
newline
|
|
bitfld.long 0x4 9. "PWRENUART0,Power up UART Controller 0" "0: Power down UART 0,1: Power up UART 0"
|
|
newline
|
|
bitfld.long 0x4 8. "PWRENIOM7,Power up IO Master 7" "0: Power down IO Master 7,1: Power up IO Master 7"
|
|
newline
|
|
bitfld.long 0x4 7. "PWRENIOM6,Power up IO Master 6" "0: Power down IO Master 6,1: Power up IO Master 6"
|
|
newline
|
|
bitfld.long 0x4 6. "PWRENIOM5,Power up IO Master 5" "0: Power down IO Master 5,1: Power up IO Master 5"
|
|
newline
|
|
bitfld.long 0x4 5. "PWRENIOM4,Power up IO Master 4" "0: Power down IO Master 4,1: Power up IO Master 4"
|
|
newline
|
|
bitfld.long 0x4 4. "PWRENIOM3,Power up IO Master 3" "0: Power down IO Master 3,1: Power up IO Master 3"
|
|
newline
|
|
bitfld.long 0x4 3. "PWRENIOM2,Power up IO Master 2" "0: Power down IO Master 2,1: Power up IO Master 2"
|
|
newline
|
|
bitfld.long 0x4 2. "PWRENIOM1,Power up IO Master 1" "0: Power down IO Master 1,1: Power up IO Master 1"
|
|
newline
|
|
bitfld.long 0x4 1. "PWRENIOM0,Power up IO Master 0" "0: Power down IO Master 0,1: Power up IO Master 0"
|
|
newline
|
|
bitfld.long 0x4 0. "PWRENIOS,Power up IO Slave" "0: Power down IO slave,1: Power up IO slave"
|
|
line.long 0x8 "DEVPWRSTATUS,This provides the power status for the peripheral device domains controlled through DEVPWREN register. Value of 1 means the device is powred up and ready to be used and 0 means its not powered up."
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 26. "PWRSTI3C1,Power Status I3C1" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 26. "PWRSTI3C1,Power Status I3C1" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 25. "PWRSTI3C0,Power Status I3C0" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 25. "PWRSTI3C0,Power Status I3C0" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
endif
|
|
bitfld.long 0x8 24. "PWRSTDBG,Power Status DBG subsystem" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMA4B2KP")||cpuis("AMAP42KK")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 23. "PWRSTUSBPHY,Power Status USB PHY" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
bitfld.long 0x8 22. "PWRSTUSB,Power Status USB controller" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
bitfld.long 0x8 19. "PWRSTDISPPHY,Power Status DISP PHY" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
bitfld.long 0x8 18. "PWRSTDISP,Power Status DISP controller" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
endif
|
|
bitfld.long 0x8 21. "PWRSTSDIO,Power Status SDIO controller" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
bitfld.long 0x8 20. "PWRSTCRYPTO,Power Status CRYPTO module" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
bitfld.long 0x8 17. "PWRSTGFX,Power Status GFX controller" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
bitfld.long 0x8 16. "PWRSTMSPI2,Power Status MSPI Controller2" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
bitfld.long 0x8 15. "PWRSTMSPI1,Power Status MSPI Controller1" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
bitfld.long 0x8 14. "PWRSTMSPI0,Power Status MSPI Controller0" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
bitfld.long 0x8 13. "PWRSTADC,Power Status ADC Digital Controller" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
bitfld.long 0x8 12. "PWRSTUART3,Power Status UART Controller 3" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
bitfld.long 0x8 11. "PWRSTUART2,Power Status UART Controller 2" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
bitfld.long 0x8 10. "PWRSTUART1,Power Status UART Controller 1" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
bitfld.long 0x8 9. "PWRSTUART0,Power Status UART Controller 0" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
bitfld.long 0x8 8. "PWRSTIOM7,Power Status IO Master 7" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
bitfld.long 0x8 7. "PWRSTIOM6,Power Status IO Master 6" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
bitfld.long 0x8 6. "PWRSTIOM5,Power Status IO Master 5" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
bitfld.long 0x8 5. "PWRSTIOM4,Power status IO Master 4" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
bitfld.long 0x8 4. "PWRSTIOM3,Power status IO Master 3" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
bitfld.long 0x8 3. "PWRSTIOM2,Power status IO Master 2" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
bitfld.long 0x8 2. "PWRSTIOM1,Power status IO Master 1" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
bitfld.long 0x8 1. "PWRSTIOM0,Power status IO Master 0" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
bitfld.long 0x8 0. "PWRSTIOS,Power status IO Slave" "0: Domain powered off,1: Domain powered on"
|
|
line.long 0xC "AUDSSPWREN,This enables various power domains in audio subsystem."
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMA4B2KP")||cpuis("AMAP42KK")||cpuis("AMAP42KP"))
|
|
bitfld.long 0xC 11. "PWRENDSPA,Enable one or more DSP subsystems" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0xC 10. "PWRENAUDADC,Power up audio subsystem ADC domain" "0: Power down AUDADC,1: Power up AUDADC"
|
|
newline
|
|
bitfld.long 0xC 5. "PWRENPDM3,Power up audio subsystem PDM3 domain" "0: Power down PDM3,1: Power up PDM3"
|
|
newline
|
|
bitfld.long 0xC 4. "PWRENPDM2,Power up audio subsystem PDM2 domain" "0: Power down PDM2,1: Power up PDM2"
|
|
newline
|
|
bitfld.long 0xC 3. "PWRENPDM1,Power up audio subsystem PDM1 domain" "0: Power down PDM1,1: Power up PDM1"
|
|
newline
|
|
endif
|
|
bitfld.long 0xC 7. "PWRENI2S1,Power up audio subsystem I2S1 domain" "0: Power down I2S1,1: Power up I2S1"
|
|
newline
|
|
bitfld.long 0xC 6. "PWRENI2S0,Power up audio subsystem I2S0 domain" "0: Power down I2S0,1: Power up I2S0"
|
|
newline
|
|
bitfld.long 0xC 2. "PWRENPDM0,Power up audio subsystem PDM0 domain" "0: Power down PDM0,1: Power up PDM0"
|
|
newline
|
|
bitfld.long 0xC 1. "PWRENAUDPB,Power up Audio Playback" "0: Power down AUDPB,1: Power up AUDPB"
|
|
newline
|
|
bitfld.long 0xC 0. "PWRENAUDREC,Power up Audio Record" "0: Power down AUDREC,1: Power up AUDREC"
|
|
line.long 0x10 "AUDSSPWRSTATUS,This provides the power status for the peripheral domains controlled through AUDSSPWREN register. Value of 1 means the device is powred up and ready to be used and 0 means its not powered up."
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMA4B2KP")||cpuis("AMAP42KK")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x10 11. "PWRSTDSPA,Power Status DSPA subsystem" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
bitfld.long 0x10 10. "PWRSTAUDADC,Power Status audio subsystem ADC domain" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
bitfld.long 0x10 5. "PWRSTPDM3,Power Status audio subsystem PDM3 domain" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
bitfld.long 0x10 4. "PWRSTPDM2,Power Status audio subsystem PDM2 domain" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
bitfld.long 0x10 3. "PWRSTPDM1,Power Status audio subsystem PDM1 domain" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
endif
|
|
bitfld.long 0x10 7. "PWRSTI2S1,Power Status audio subsystem I2S1 domain" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
bitfld.long 0x10 6. "PWRSTI2S0,Power Status audio subsystem I2S0 domain" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
bitfld.long 0x10 2. "PWRSTPDM0,Power Status audio subsystem PDM0 domain" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
bitfld.long 0x10 1. "PWRSTAUDPB,Power Status Audio Playback block" "0: Domain powered off,1: Domain powered on"
|
|
newline
|
|
bitfld.long 0x10 0. "PWRSTAUDREC,Power Status Audio Record block" "0: Domain powered off,1: Domain powered on"
|
|
line.long 0x14 "MEMPWREN,This register enables the individual banks for the memories. When set. power will be enabled to the banks. This register works in conjunction with the MEMRETCFG register. If this register is not set. then power will always be disabled to the.."
|
|
bitfld.long 0x14 5. "PWRENCACHEB2,Power up Cache Bank 2. This works in conjunction with Cache enable from flash_cache module. To power up cache bank2 cache has to be enabled and this bit has to be set." "0: Power down Cache Bank 2,1: Power up Cache Bank 2"
|
|
newline
|
|
bitfld.long 0x14 4. "PWRENCACHEB0,Power up Cache Bank 0. This works in conjunction with Cache enable from flash_cache module. To power up cache bank0 cache has to be enabled and this bit has to be set." "0: Power down Cache Bank 0,1: Power up Cache Bank 0"
|
|
newline
|
|
bitfld.long 0x14 3. "PWRENNVM0,Power up NVM0" "0: Power down NVM0,1: Power up NVM0"
|
|
newline
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x14 0.--2. "PWRENDTCM,Power up DTCM" "0: Do not enable power to any DTCMs,1: Power ON only lower 32k,?,3: Power ON only lower 128k,?,?,?,7: Power ON 384k"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMA4B2KP")||cpuis("AMAP42KK")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x14 0.--2. "PWRENDTCM,Power up DTCM" "0: Do not enable power to any DTCMs,1: Power ON only lower 8k,?,3: Power ON only lower 128k,?,?,?,7: Power ON 384k"
|
|
endif
|
|
line.long 0x18 "MEMPWRSTATUS,It provides the power status for all the memory banks including- caches. nvm (0 and 1) and all the SRAM groups. The status here should reflect the enable provided by the MEMPWREN register. There may be a lag time between setting the bits in.."
|
|
bitfld.long 0x18 5. "PWRSTCACHEB2,This bit is 1 if power is supplied to Cache Bank 2" "0,1"
|
|
newline
|
|
bitfld.long 0x18 4. "PWRSTCACHEB0,This bit is 1 if power is supplied to Cache Bank 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 3. "PWRSTNVM0,This bit is 1 if power is supplied to NVM 0" "0,1"
|
|
newline
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x18 0.--2. "PWRSTDTCM,Power status for DTCM. Each bit corresponds to one of the TCMs. bit0=DTCM0_0 bit1=DTCM0_1 bit2=DTCM1." "0: DTCM0_0,1: DTCM0_1,2: DTCM1,3: Only lower 128k is powered up,?,?,?,7: All 384k is powered up"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMA4B2KP")||cpuis("AMAP42KK")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x18 0.--2. "PWRSTDTCM,Power status for DTCM. Each bit corresponds to one of the TCMs. bit0=DTCM0_0 bit1=DTCM0_1 bit2=DTCM1." "0: DTCM0_0,1: DTCM0_1,2: DTCM1,3: Only lower 128k is powered up,?,?,?,7: All 384k is powered up"
|
|
endif
|
|
line.long 0x1C "MEMRETCFG,This controls the power down of the SRAM banks in deep sleep mode. If this is set. then the power for that SRAM bank will be gated when the core goes into deep sleep. Upon wake. the data within the SRAMs will be erased. If this is not set..."
|
|
bitfld.long 0x1C 4. "CACHEPWDSLP,power down cache in deep sleep" "0: Retain cache in deep sleep,1: Power down cache in deep sleep"
|
|
newline
|
|
bitfld.long 0x1C 3. "NVM0PWDSLP,Powerdown NVM0 in deep sleep" "0: NVM0 is kept powered on during deepsleep,1: NVM0 is powered down during deepsleep"
|
|
newline
|
|
bitfld.long 0x1C 0.--2. "DTCMPWDSLP,power down DTCM in deep sleep" "0: All DTCM retained,1: Group0_DTCM0 powered down in deep sleep (0KB-8KB),2: Group0_DTCM1 powered down in deep sleep..,3: Both DTCMs in group0 are powered down in deep..,4: Group1 DTCM powered down in deep sleep..,?,6: Group1 and Group0_DTCM1 are powered down in deep..,7: All DTCMs powered down in deep sleep (0KB-384KB)"
|
|
line.long 0x20 "SYSPWRSTATUS,Power ON Status for domains that are not part of devpwrstatus or mempwrstatus"
|
|
bitfld.long 0x20 31. "SYSDEEPSLEEP,Indicates all device domains powered down and MCU entered DEEPSLEEP state since it was last cleared. Write 1 to to clear it." "0,1"
|
|
newline
|
|
bitfld.long 0x20 30. "COREDEEPSLEEP,Indicates MCU entered DEEPSLEEP state since it was last cleared. Write 1 to to clear it." "0,1"
|
|
newline
|
|
bitfld.long 0x20 29. "CORESLEEP,Indicates MCU entered SLEEP state since it was last cleared. Write 1 to to clear it." "0,1"
|
|
newline
|
|
bitfld.long 0x20 3. "PWRSTDSP1H,Power Domain status for DSP1H" "0,1"
|
|
newline
|
|
bitfld.long 0x20 2. "PWRSTDSP0H,Power Domain status for DSP0H" "0,1"
|
|
newline
|
|
bitfld.long 0x20 1. "PWRSTMCUH,Power Domain status for MCUH" "0,1"
|
|
newline
|
|
bitfld.long 0x20 0. "PWRSTMCUL,Power Domain status for MCUL" "0,1"
|
|
line.long 0x24 "SSRAMPWREN,This register enables the individual banks for the memories. When set. power will be enabled to the banks. This register works in conjunction with the SSRAMRETCFG register. If this register is not set. then power will always be disabled to the.."
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
bitfld.long 0x24 0.--1. "PWRENSSRAM,Power up SRAM groups" "0: Do not power ON any of the SRAM banks,1: Power ON only SRAM group0 (512k),?,3: All shared SRAM banks (1M) powered ON"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x24 0.--1. "PWRENSSRAM,Power up SRAM groups" "0: Do not power ON any of the SRAM banks,1: Power ON only SRAM0 group (lower 1M),2: Power ON only SRAM1 group (upper 1M),3: All shared SRAM banks (SSRAM0 1M + SSRAM1 1M).."
|
|
endif
|
|
line.long 0x28 "SSRAMPWRST,It provides the power status for shared sram banks. The status here should reflect the enable provided by the SSRAMPWREN register."
|
|
bitfld.long 0x28 0.--1. "SSRAMPWRST,Each bit corresponds to 512K SSRAM groups. Power Status- 1:ON 0:OFF" "0: OFF,1: ON,?,?"
|
|
line.long 0x2C "SSRAMRETCFG,This controls the power down of the Shared SRAM banks in deep sleep mode. If this is set. then the power for that SRAM bank will be gated when the core goes into deep sleep. Upon wake. the data within the SRAMs will be erased. If this is not.."
|
|
bitfld.long 0x2C 8.--9. "SSRAMACTDISP,Keep the memory domain active based on DISP state. Each bit corresponds to a domain. 1: Keep SRAM active 0: Powerup on demand (i.e. when DISP is powered up)" "0: Powerup on demand,1: Keep SRAM active,?,?"
|
|
newline
|
|
bitfld.long 0x2C 6.--7. "SSRAMACTGFX,Keep the memory domain active based on GFX state. Each bit corresponds to a domain. 1: Keep SRAM active 0: Powerup on demand (i.e. when GFX is powered up)" "0: Powerup on demand,1: Keep SRAM active,?,?"
|
|
newline
|
|
bitfld.long 0x2C 4.--5. "SSRAMACTDSP,Keep the memory domain active based on DSP state. Each bit corresponds to a domain. 1: Keep SRAM active 0: Powerup on demand (i.e. when DSP is powered up)" "0: Powerup on demand,1: Keep SRAM active,?,?"
|
|
newline
|
|
bitfld.long 0x2C 2.--3. "SSRAMACTMCU,Keep the memory domain active based on MCU state. Each bit corresponds to a domain. 1: Keep SRAM active 0: Wakeup on demand (i.e. when MCU is powered up)" "0: Wakeup on demand,1: Keep SRAM active,?,?"
|
|
newline
|
|
bitfld.long 0x2C 0.--1. "SSRAMPWDSLP,Selects which shared SRAM banks are powered down in deep sleep mode causing the contents of the bank to be lost." "0: All banks retained,1: Power down only SRAM group0,2: Power down only SRAM group1,3: All shared SRAM banks powered down"
|
|
line.long 0x30 "DEVPWREVENTEN,This register controls which feature trigger will result in an event to the CPU. It includes all the power on status for the core domains. If any bits are set. then if the domain is turned on. it will result in an event to the ARM core."
|
|
bitfld.long 0x30 7. "AUDEVEN,Control AUD power-on status event" "0: Disable AUD power-on status event,1: Enable AUD power-on status event"
|
|
newline
|
|
bitfld.long 0x30 6. "MSPIEVEN,Control MSPI power-on status event" "0: Disable MSPI power-on status event,1: Enable MSPI power-on status event"
|
|
newline
|
|
bitfld.long 0x30 5. "ADCEVEN,Control ADC power-on status event" "0: Disable ADC power-on status event,1: Enable ADC power-on status event"
|
|
newline
|
|
bitfld.long 0x30 4. "HCPCEVEN,Control HCPC power-on status event" "0: Disable HCPC power-on status event,1: Enable HCPC power-on status event"
|
|
newline
|
|
bitfld.long 0x30 3. "HCPBEVEN,Control HCPB power-on status event" "0: Disable HCPB power-on status event,1: Enable HCPB power-on status event"
|
|
newline
|
|
bitfld.long 0x30 2. "HCPAEVEN,Control HCPA power-on status event" "0: Disable HCPA power-on status event,1: Enable HCPA power-on status event"
|
|
newline
|
|
bitfld.long 0x30 1. "MCUHEVEN,Control MCUH power-on status event" "0: Disable MCUH power-on status event,1: Enable MCHU power-on status event"
|
|
newline
|
|
bitfld.long 0x30 0. "MCULEVEN,Control MCUL power-on status event" "0: Disable MCUL power-on status event,1: Enable MCUL power-on status event"
|
|
line.long 0x34 "MEMPWREVENTEN,This register controls which power enable for the memories will result in an event to the CPU. It includes all the power on status for the memory domains. If any bits are set. then if the domain is turned on. it will result in an event to.."
|
|
bitfld.long 0x34 5. "CACHEB2EN,Control CACHEB2 power-on status event" "0: Disable CACHE BANK 2 status event,1: Enable CACHE BANK 2 status event"
|
|
newline
|
|
bitfld.long 0x34 4. "CACHEB0EN,Control CACHE BANK 0 power-on status event" "0: Disable CACHE BANK 0 status event,1: Enable CACHE BANK 0 status event"
|
|
newline
|
|
bitfld.long 0x34 3. "NVM0EN,Control NVM power-on status event" "0: Disables NVM status event,1: Enable NVM status event"
|
|
newline
|
|
bitfld.long 0x34 0.--2. "DTCMEN,Enable DTCM power-on status event" "0: Do not enable DTCM power-on status event,1: Enable GROUP0_DTCM0 power on status event,2: Enable GROUP0_DTCM1 power on status event,3: Enable DTCMs in group0 power on status event,4: Enable DTCMs in group1 power on status event,?,?,7: Enable all DTCM power on status event"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "MMSOVERRIDE,Power domain behavior overrides related to MMS ( Multimedia System )."
|
|
bitfld.long 0x0 10.--11. "MMSOVRSSRAMRETGFX,If set retention equation doesn't consider GFX. Each bit corresponds to a domain." "0: When PD_GFX is off retention is okay based on..,1: When PD_GFX is off retention is always okay for..,?,?"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "MMSOVRSSRAMRETDISP,If set retention equation doesn't consider DISP. Each bit corresponds to a domain." "0: When PD_DISP is off retention is okay based on..,1: When PD_DISP is off retention is always okay for..,?,?"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MMSOVRDSPRAMRETGFX,If set retention equation doesn't consider GFX. Each bit corresponds to a domain." "0: When PD_GFX is off retention is okay based on..,1: When PD_GFX is off retention is always okay for..,?,?"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "MMSOVRDSPRAMRETDISP,If set retention equation doesn't consider DISP. Each bit corresponds to a domain." "0: When PD_DISP is off retention is okay based on..,1: When PD_DISP is off retention is always okay for..,?,?"
|
|
newline
|
|
bitfld.long 0x0 3. "MMSOVRSSRAMGFX,MMS override for SSRAM power state by PD_GFX power setting." "0: SSRAM power state set by SSRAMPWREN_PWRENSSRAM..,1: SSRAM power state is not affected by PD_GFX.."
|
|
newline
|
|
bitfld.long 0x0 2. "MMSOVRSSRAMDISP,MMS override for SSRAM power state by PD_DISP power setting." "0: SSRAM power state set by SSRAMPWREN_PWRENSSRAM..,1: SSRAM power state is not affected by PD_DISP.."
|
|
newline
|
|
bitfld.long 0x0 1. "MMSOVRMCULGFX,MMS override for MCUL on by PD_GFX setting." "0: When PD_GFX is on MCUL is on.,1: When PD_GFX is on MCUL is still off."
|
|
newline
|
|
bitfld.long 0x0 0. "MMSOVRMCULDISP,MMS override for MCUL on by PD_DISP setting." "0: When PD_DISP is on MCUL is on.,1: When PD_DISP is on MCUL is still off."
|
|
group.long 0x50++0x13
|
|
line.long 0x0 "DSP0PWRCTRL,Power and RST controls for DSP0"
|
|
bitfld.long 0x0 4. "DSP0PCMRSTOR,PCM Reset override. If this is disabled then h/w will handle the de-assertion of pcm reset." "0: Remove DSP0 PCM Reset override,1: Keep DSP0 PCM in Reset"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DSP0PCMRSTDLY,PCM Reset delay in number of 24MHz clocks."
|
|
line.long 0x4 "DSP0PERFREQ,This register provides the performance mode knobs for DSP0. S/w should write the *PERFREQ field to desired mode and wait for the *PERFACK and check for the *PERFSTATUS. Some times system may not allow certain modes but *PERFACK should always.."
|
|
bitfld.long 0x4 3.--4. "DSP0PERFSTATUS,DSP0 Performance mode request" "0: DSP0 is in ULP mode (freq=48MHz),1: DSP0 is in LP mode (freq=192MHz),2: DSP0 is in HP mode (freq=384MHz),?"
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|
newline
|
|
bitfld.long 0x4 2. "DSP0PERFACK,Indicates the DSP0 performance status indicated in STATUS register is valid." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--1. "DSP0PERFREQ,DSP0 Performance mode request" "0: DSP0 to be run in ULP mode (freq=48MHz),1: DSP0 to be run in LP mode (freq=192MHz),2: DSP0 to be run in HP mode (freq=384MHz),?"
|
|
line.long 0x8 "DSP0MEMPWREN,This register enables the individual banks for the memories. When set. power will be enabled to the banks. This register works in conjunction with the DSP0MEMRETCFG register when DSP0 is OFF."
|
|
bitfld.long 0x8 1. "PWRENDSP0ICACHE,Power up DSP0 ICACHE banks" "0: Do not power up ICACHE,1: Power up ICACHE"
|
|
newline
|
|
bitfld.long 0x8 0. "PWRENDSP0RAM,Power up DSP0 IRAM and DRAM" "0: Do not power ON any of the IRAM/DRAM,1: Power up all IRAM (128K) and DRAM (256K)"
|
|
line.long 0xC "DSP0MEMPWRST,It provides the power status for all the memories of DSP0 subsystem"
|
|
bitfld.long 0xC 1. "PWRSTDSP0ICACHE,Power Status- 1:ON 0:OFF" "0: OFF,1: ON"
|
|
newline
|
|
bitfld.long 0xC 0. "PWRSTDSP0RAM,Status- 1:ON 0:OFF" "0: OFF,1: ON"
|
|
line.long 0x10 "DSP0MEMRETCFG,This controls the power down of the DRAM/IRAM/CACHE banks when DSP0 is powered off. If this is set. then the power for that corresponding SRAM bank will be gated when the DSP0 is powered off and data is erased. If this is not set. retention.."
|
|
bitfld.long 0x10 4. "DSP0RAMACTGFX,Keep the memory domain active based on GFX state." "0: Wakeup on demand,1: Keep RAMs active irrespective of GFX state"
|
|
newline
|
|
bitfld.long 0x10 3. "DSP0RAMACTDISP,Keep the memory domain active based on DISP state." "0: Wakeup on demand,1: Keep RAMs active irrespective of DISP state"
|
|
newline
|
|
bitfld.long 0x10 2. "ICACHEPWDDSP0OFF,ICACHE is powered down when DSP0 is switched off causing the contents of the bank to be lost." "0: ICACHE retained,1: Power down ICACHE"
|
|
newline
|
|
bitfld.long 0x10 1. "DSP0RAMACTMCU,Keep the memory domain active based on MCU state." "0: Wakeup on demand,1: Keep RAMs active irrespective of MCU state"
|
|
newline
|
|
bitfld.long 0x10 0. "RAMPWDDSP0OFF,IRAM/DRAM banks are powered down when DSP0 is switched off causing the contents of the bank to be lost." "0: IRAM and DRAM retained,1: Power down all IRAM and DRAM"
|
|
group.long 0x70++0x13
|
|
line.long 0x0 "DSP1PWRCTRL,Power and RST controls for DSP1"
|
|
bitfld.long 0x0 4. "DSP1PCMRSTOR,PCM Reset override. If this is disabled then h/w will handle the de-assertion of pcm reset." "0: Remove DSP1 PCM Reset override,1: Keep DSP1 PCM in Reset"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DSP1PCMRSTDLY,PCM Reset delay in number of 24MHz clocks."
|
|
line.long 0x4 "DSP1PERFREQ,This register provides the performance mode knobs for DSP1. S/w should write the *PERFREQ field to desired mode and wait for the *PERFACK and check for the *PERFSTATUS. Some times system may not allow certain modes but *PERFACK should always.."
|
|
bitfld.long 0x4 3.--4. "DSP1PERFSTATUS,DSP1 Performance mode request" "0: DSP1 is in ULP mode (freq=48MHz),1: DSP1 is in LP mode (freq=192MHz),2: DSP1 is in HP mode (freq=384MHz),?"
|
|
newline
|
|
bitfld.long 0x4 2. "DSP1PERFACK,Indicates the DSP1 performance status indicated in STATUS register is valid." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--1. "DSP1PERFREQ,DSP1 Performance mode request" "0: DSP1 to be run in ULP mode (freq=48MHz),1: DSP1 to be run in LP mode (freq=192MHz),2: DSP1 to be run in HP mode (freq=384MHz),?"
|
|
line.long 0x8 "DSP1MEMPWREN,This register enables the individual banks for the memories. When set. power will be enabled to the banks. This register works in conjunction with the DSP1MEMRETCFG register when DSP1 is OFF."
|
|
bitfld.long 0x8 1. "PWRENDSP1ICACHE,Power up DSP1 ICACHE banks" "0: Do not power up ICACHE,1: Power up ICACHE"
|
|
newline
|
|
bitfld.long 0x8 0. "PWRENDSP1RAM,Power up DSP1 IRAM and DRAM" "0: Do not power ON any of the IRAM/DRAM,1: Power up all IRAM (32K) and DRAM (64K)"
|
|
line.long 0xC "DSP1MEMPWRST,It provides the power status for all the memories of DSP1 subsystem"
|
|
bitfld.long 0xC 1. "PWRSTDSP1ICACHE,Power Status- 1:ON 0:OFF" "0: OFF,1: ON"
|
|
newline
|
|
bitfld.long 0xC 0. "PWRSTDSP1RAM,Status- 1:ON 0:OFF" "0: OFF,1: ON"
|
|
line.long 0x10 "DSP1MEMRETCFG,This controls the power down of the DRAM/IRAM/CACHE banks when DSP1 is powered off. If this is set. then the power for that corresponding SRAM bank will be gated when the DSP1 is powered off and data is erased. If this is not set. retention.."
|
|
bitfld.long 0x10 4. "DSP1RAMACTGFX,Keep the memory domain active based on GFX state." "0: Wakeup on demand,1: Keep RAMs active irrespective of GFX state"
|
|
newline
|
|
bitfld.long 0x10 3. "DSP1RAMACTDISP,Keep the memory domain active based on DISP state." "0: Wakeup on demand,1: Keep RAMs active irrespective of DISP state"
|
|
newline
|
|
bitfld.long 0x10 2. "ICACHEPWDDSP1OFF,ICACHE is powered down when DSP1 is switched off causing the contents of the bank to be lost." "0: ICACHE retained,1: Power down ICACHE"
|
|
newline
|
|
bitfld.long 0x10 1. "DSP1RAMACTMCU,Keep the memory domain active based on MCU state." "0: Wakeup on demand,1: Keep RAMs active irrespective of MCU state"
|
|
newline
|
|
bitfld.long 0x10 0. "RAMPWDDSP1OFF,IRAM/DRAM banks are powered down when DSP1 is switched off causing the contents of the bank to be lost." "0: IRAM and DRAM retained,1: Power down all IRAM and DRAM"
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
group.long 0x84++0x7
|
|
line.long 0x0 "PWRACKOVR,This register contains override bit fields for various power domain power switch acknowledge notification. As a part of power up sequnce. Power controller will look for power switch ack to advance power up sequence. It is possible for power.."
|
|
bitfld.long 0x0 17. "PWRACKOVERRIDEDSPA,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
bitfld.long 0x0 16. "PWRACKOVERRIDEUSBPHY,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
newline
|
|
bitfld.long 0x0 15. "PWRACKOVERRIDEUSB,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
bitfld.long 0x0 14. "PWRACKOVERRIDESDIO,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
newline
|
|
bitfld.long 0x0 13. "PWRACKOVERRIDEMSPI,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
bitfld.long 0x0 12. "PWRACKOVERRIDEMCUL,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
newline
|
|
bitfld.long 0x0 11. "PWRACKOVERRIDEIOS,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
bitfld.long 0x0 10. "PWRACKOVERRIDEHCPC,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
newline
|
|
bitfld.long 0x0 9. "PWRACKOVERRIDEHCPB,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
bitfld.long 0x0 8. "PWRACKOVERRIDEHCPA,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
newline
|
|
bitfld.long 0x0 7. "PWRACKOVERRIDEGFX,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
bitfld.long 0x0 6. "PWRACKOVERRIDEDISPPHY,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
newline
|
|
bitfld.long 0x0 5. "PWRACKOVERRIDEDISP,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
bitfld.long 0x0 4. "PWRACKOVERRIDEDBG,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
newline
|
|
bitfld.long 0x0 3. "PWRACKOVERRIDECRYPTO,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
bitfld.long 0x0 2. "PWRACKOVERRIDEAUDADC,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
newline
|
|
bitfld.long 0x0 1. "PWRACKOVERRIDEAUD,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
bitfld.long 0x0 0. "PWRACKOVERRIDEADC,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
line.long 0x4 "PWRCNTDEFVAL,This register contains programmble dealy values for various state michines. Fields contain dev st machine default value. SIMOBUCK state machine wait delay counter etc."
|
|
hexmask.long.word 0x4 6.--15. 1. "PWRACKWAITDELSIMOSTMC,Default counter max for buck ST MC"
|
|
hexmask.long.byte 0x4 0.--5. 1. "PWRDEFVALDEVSTMC,Default count max value for dev ST MC"
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
group.long 0x84++0x7
|
|
line.long 0x0 "PWRACKOVR,This register contains override bit fields for various power domain power switch acknowledge notification. As a part of power up sequnce. Power controller will look for power switch ack to advance power up sequence. It is possible for power.."
|
|
bitfld.long 0x0 17. "PWRACKOVERRIDEDSPA,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
bitfld.long 0x0 16. "PWRACKOVERRIDEUSBPHY,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
newline
|
|
bitfld.long 0x0 15. "PWRACKOVERRIDEUSB,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
bitfld.long 0x0 14. "PWRACKOVERRIDESDIO,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
newline
|
|
bitfld.long 0x0 13. "PWRACKOVERRIDEMSPI,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
bitfld.long 0x0 12. "PWRACKOVERRIDEMCUL,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
newline
|
|
bitfld.long 0x0 11. "PWRACKOVERRIDEIOS,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
bitfld.long 0x0 10. "PWRACKOVERRIDEHCPC,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
newline
|
|
bitfld.long 0x0 9. "PWRACKOVERRIDEHCPB,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
bitfld.long 0x0 8. "PWRACKOVERRIDEHCPA,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
newline
|
|
bitfld.long 0x0 7. "PWRACKOVERRIDEGFX,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
bitfld.long 0x0 6. "PWRACKOVERRIDEDISPPHY,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
newline
|
|
bitfld.long 0x0 5. "PWRACKOVERRIDEDISP,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
bitfld.long 0x0 4. "PWRACKOVERRIDEDBG,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
newline
|
|
bitfld.long 0x0 3. "PWRACKOVERRIDECRYPTO,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
bitfld.long 0x0 2. "PWRACKOVERRIDEAUDADC,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
newline
|
|
bitfld.long 0x0 1. "PWRACKOVERRIDEAUD,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
bitfld.long 0x0 0. "PWRACKOVERRIDEADC,Power switch acknowledgement override from Power switch to power control ST MC" "0: Hardware generates Power switch ack,1: Software override or defeaure mode. Will bypass.."
|
|
line.long 0x4 "PWRCNTDEFVAL,This register contains programmble delay values for various state michines. Fields contain dev st machine default value. SIMOBUCK state machine wait delay counter etc."
|
|
hexmask.long.word 0x4 6.--15. 1. "PWRACKWAITDELSIMOSTMC,Default counter max for buck ST MC"
|
|
hexmask.long.byte 0x4 0.--5. 1. "PWRDEFVALDEVSTMC,Default count max value for dev ST MC"
|
|
endif
|
|
group.long 0x100++0xB
|
|
line.long 0x0 "VRCTRL,This register includes additional debug control bits. This is an internal Ambiq-only register. Customers should not attempt to change this or else functionality cannot be guaranteed."
|
|
bitfld.long 0x0 0. "SIMOBUCKEN,Enables and Selects the SIMO Buck as the supply for the low-voltage power domains. It takes the initial value from the bit set in Customer INFO space." "0: Disable the SIMO Buck,1: Enable the SIMO Buck"
|
|
line.long 0x4 "LEGACYVRLPOVR,When an override is set for a power domain. VR logic will ignore that power domain state in making a decision to go into lp state."
|
|
bitfld.long 0x4 18. "IGNOREDBG,Ignore DBG" "0,1"
|
|
newline
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMA4B2KP")||cpuis("AMAP42KK")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 17. "IGNOREDSP1H,Ignore DSP1H" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "IGNOREDSP0H,Ignore DSP0H" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "IGNOREDSPA,Ignore DSPA" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "IGNOREUSBPHY,Ignore USB PHY" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "IGNOREUSB,Ignore USB Control" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "IGNOREDISPPHY,Ignore DISP PHY" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "IGNOREDISP,Ignore DISP Control" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x4 14. "IGNOREAUD,Ignore AUD" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "IGNORESDIO,Ignore SDIO" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "IGNORECRYPTO,Ignore CRYPTO" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "IGNOREGFX,Ignore GFX" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "IGNOREMSPI,Ignore MSPI" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "IGNOREHCPE,Ignore HCPE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "IGNOREHCPD,Ignore HCPD" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "IGNOREHCPC,Ignore HCPC" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "IGNOREHCPB,Ignore HCPB" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "IGNOREHCPA,Ignore HCPA" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IGNOREIOS,Ignore IOS" "0,1"
|
|
line.long 0x8 "VRSTATUS,Provides BUCK and LDOs status."
|
|
bitfld.long 0x8 4.--5. "SIMOBUCKST,Indicates SIMO BUCK status. bit[1] indicates ON/OFF and bit[0] indicates ACT/LP" "0: Indicates the the SIMO BUCK is OFF.,?,2: Indicates the the SIMO BUCK is ON and in LP mode.,3: Indicates the the SIMO BUCK is ON and in ACT mode."
|
|
newline
|
|
bitfld.long 0x8 2.--3. "MEMLDOST,Indicates MEMLDO status. bit[1] indicates ON/OFF and bit[0] indicates ACT/LP." "?,1: Indicates the the MEMLDO is OFF.,2: Indicates the the MEMLDO is ON and in LP mode.,3: Indicates the the MEMLDO is ON and in ACT mode."
|
|
newline
|
|
bitfld.long 0x8 0.--1. "CORELDOST,Indicates CORELDO status. bit[1] indicates ON/OFF and bit[0] indicates ACT/LP." "?,1: Indicates the the CORELDO is OFF.,2: Indicates the the CORELDO is ON and in LP mode.,3: Indicates the the CORELDO is ON and in ACT mode."
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMA4B2KP")||cpuis("AMAP42KK")||cpuis("AMAP42KP"))
|
|
group.long 0x140++0x4F
|
|
line.long 0x0 "PWRWEIGHTULP0,Weights specified in this register are applied to each of the masters active requests. The aggregate of all the masters is compared against the allowed value to change the buck from active to inactive mode."
|
|
hexmask.long.byte 0x0 28.--31. 1. "WTULPUART3,Weight used for ULP mode UART3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "WTULPUART2,Weight used for ULP mode UART2"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "WTULPUART1,Weight used for ULP mode UART1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "WTULPUART0,Weight used for ULP mode UART0"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "WTULPIOS,Weight used for ULP mode IOS"
|
|
hexmask.long.byte 0x0 8.--11. 1. "WTULPDSP1,Weight used for ULP mode DSP1"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "WTULPDSP0,Weight used for ULP mode DSP0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "WTULPMCU,Weight used for ULP mode MCU"
|
|
line.long 0x4 "PWRWEIGHTULP1,Weights specified in this register are applied to each of the masters active requests. The aggregate of all the masters is compared against the allowed value to change the buck from active to inactive mode."
|
|
hexmask.long.byte 0x4 28.--31. 1. "WTULPIOM7,Weight used for ULP mode IOM7"
|
|
hexmask.long.byte 0x4 24.--27. 1. "WTULPIOM6,Weight used for ULP mode IOM6"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--23. 1. "WTULPIOM5,Weight used for ULP mode IOM5"
|
|
hexmask.long.byte 0x4 16.--19. 1. "WTULPIOM4,Weight used for ULP mode IOM4"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "WTULPIOM3,Weight used for ULP mode IOM3"
|
|
hexmask.long.byte 0x4 8.--11. 1. "WTULPIOM2,Weight used for ULP mode IOM2"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "WTULPIOM1,Weight used for ULP mode IOM1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "WTULPIOM0,Weight used for ULP mode IOM0"
|
|
line.long 0x8 "PWRWEIGHTULP2,Weights specified in this register are applied to each of the masters active requests. The aggregate of all the masters is compared against the allowed value to change the buck from active to inactive mode."
|
|
hexmask.long.byte 0x8 28.--31. 1. "WTULPUSB,Weight used for ULP mode USB"
|
|
hexmask.long.byte 0x8 24.--27. 1. "WTULPSDIO,Weight used for ULP mode SDIO"
|
|
newline
|
|
hexmask.long.byte 0x8 20.--23. 1. "WTULPCRYPTO,Weight used for ULP mode CRYPTO"
|
|
hexmask.long.byte 0x8 16.--19. 1. "WTULPDISP,Weight used for ULP mode DISP"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--15. 1. "WTULPGFX,Weight used for ULP mode GFX"
|
|
hexmask.long.byte 0x8 8.--11. 1. "WTULPMSPI1,Weight used for ULP mode MSPI1"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "WTULPMSPI0,Weight used for ULP mode MSPI0"
|
|
hexmask.long.byte 0x8 0.--3. 1. "WTULPADC,Weight used for ULP mode ADC"
|
|
line.long 0xC "PWRWEIGHTULP3,Weights specified in this register are applied to each of the masters active requests. The aggregate of all the masters is compared against the allowed value to change the buck from active to inactive mode."
|
|
hexmask.long.byte 0xC 28.--31. 1. "WTULPMSPI2,Weight used for ULP mode MSPI2"
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0xC 24.--27. 1. "WTULPI3C1,Weight used for ULP mode I3C1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0xC 20.--23. 1. "WTULPI3C0,Weight used for ULP mode I3C0"
|
|
endif
|
|
hexmask.long.byte 0xC 16.--19. 1. "WTULPAUDADC,Weight used for ULP mode AUDADC"
|
|
newline
|
|
hexmask.long.byte 0xC 12.--15. 1. "WTULPAUDPB,Weight used for ULP mode AUDPB"
|
|
hexmask.long.byte 0xC 8.--11. 1. "WTULPAUDREC,Weight used for ULP mode AUDREC"
|
|
newline
|
|
hexmask.long.byte 0xC 4.--7. 1. "WTULPDBG,Weight used for ULP mode DBG"
|
|
hexmask.long.byte 0xC 0.--3. 1. "WTULPDSPA,Weight used for ULP mode DSPA"
|
|
line.long 0x10 "PWRWEIGHTULP4,Weights specified in this register are applied to each of the masters active requests. The aggregate of all the masters is compared against the allowed value to change the buck from active to inactive mode."
|
|
hexmask.long.byte 0x10 28.--31. 1. "WTULPPDM3,Weight used for ULP mode PDM3"
|
|
hexmask.long.byte 0x10 24.--27. 1. "WTULPPDM2,Weight used for ULP mode PDM2"
|
|
newline
|
|
hexmask.long.byte 0x10 20.--23. 1. "WTULPPDM1,Weight used for ULP mode PDM1"
|
|
hexmask.long.byte 0x10 16.--19. 1. "WTULPPDM0,Weight used for ULP mode PDM0"
|
|
newline
|
|
hexmask.long.byte 0x10 4.--7. 1. "WTULPI2S1,Weight used for ULP mode I2S1"
|
|
hexmask.long.byte 0x10 0.--3. 1. "WTULPI2S0,Weight used for ULP mode I2S0"
|
|
line.long 0x14 "PWRWEIGHTULP5,Weights specified in this register are applied to each of the masters active requests. The aggregate of all the masters is compared against the allowed value to change the buck from active to inactive mode."
|
|
hexmask.long.byte 0x14 4.--7. 1. "WTULPUSBPHY,Weight used for ULP mode USB PHY"
|
|
hexmask.long.byte 0x14 0.--3. 1. "WTULPDISPPHY,Weight used for ULP mode DISP PHY"
|
|
line.long 0x18 "PWRWEIGHTLP0,Weights specified in this register are applied to each of the masters active requests. The aggregate of all the masters is compared against the allowed value to change the buck from active to inactive mode."
|
|
hexmask.long.byte 0x18 28.--31. 1. "WTLPUART3,Weight used for LP mode UART3"
|
|
hexmask.long.byte 0x18 24.--27. 1. "WTLPUART2,Weight used for LP mode UART2"
|
|
newline
|
|
hexmask.long.byte 0x18 20.--23. 1. "WTLPUART1,Weight used for LP mode UART1"
|
|
hexmask.long.byte 0x18 16.--19. 1. "WTLPUART0,Weight used for LP mode UART0"
|
|
newline
|
|
hexmask.long.byte 0x18 12.--15. 1. "WTLPIOS,Weight used for LP mode IOS"
|
|
hexmask.long.byte 0x18 8.--11. 1. "WTLPDSP1,Weight used for LP mode DSP1"
|
|
newline
|
|
hexmask.long.byte 0x18 4.--7. 1. "WTLPDSP0,Weight used for LP mode DSP0"
|
|
hexmask.long.byte 0x18 0.--3. 1. "WTLPMCU,Weight used for LP mode MCU"
|
|
line.long 0x1C "PWRWEIGHTLP1,Weights specified in this register are applied to each of the masters active requests. The aggregate of all the masters is compared against the allowed value to change the buck from active to inactive mode."
|
|
hexmask.long.byte 0x1C 28.--31. 1. "WTLPIOM7,Weight used for LP mode IOM7"
|
|
hexmask.long.byte 0x1C 24.--27. 1. "WTLPIOM6,Weight used for LP mode IOM6"
|
|
newline
|
|
hexmask.long.byte 0x1C 20.--23. 1. "WTLPIOM5,Weight used for LP mode IOM5"
|
|
hexmask.long.byte 0x1C 16.--19. 1. "WTLPIOM4,Weight used for LP mode IOM4"
|
|
newline
|
|
hexmask.long.byte 0x1C 12.--15. 1. "WTLPIOM3,Weight used for LP mode IOM3"
|
|
hexmask.long.byte 0x1C 8.--11. 1. "WTLPIOM2,Weight used for LP mode IOM2"
|
|
newline
|
|
hexmask.long.byte 0x1C 4.--7. 1. "WTLPIOM1,Weight used for LP mode IOM1"
|
|
hexmask.long.byte 0x1C 0.--3. 1. "WTLPIOM0,Weight used for LP mode IOM0"
|
|
line.long 0x20 "PWRWEIGHTLP2,Weights specified in this register are applied to each of the masters active requests. The aggregate of all the masters is compared against the allowed value to change the buck from active to inactive mode."
|
|
hexmask.long.byte 0x20 28.--31. 1. "WTLPUSB,Weight used for LP mode USB"
|
|
hexmask.long.byte 0x20 24.--27. 1. "WTLPSDIO,Weight used for LP mode SDIO"
|
|
newline
|
|
hexmask.long.byte 0x20 20.--23. 1. "WTLPCRYPTO,Weight used for LP mode CRYPTO"
|
|
hexmask.long.byte 0x20 16.--19. 1. "WTLPDISP,Weight used for LP mode DISP"
|
|
newline
|
|
hexmask.long.byte 0x20 12.--15. 1. "WTLPGFX,Weight used for LP mode GFX"
|
|
hexmask.long.byte 0x20 8.--11. 1. "WTLPMSPI1,Weight used for LP mode MSPI1"
|
|
newline
|
|
hexmask.long.byte 0x20 4.--7. 1. "WTLPMSPI0,Weight used for LP mode MSPI0"
|
|
hexmask.long.byte 0x20 0.--3. 1. "WTLPADC,Weight used for LP mode ADC"
|
|
line.long 0x24 "PWRWEIGHTLP3,Weights specified in this register are applied to each of the masters active requests. The aggregate of all the masters is compared against the allowed value to change the buck from active to inactive mode."
|
|
hexmask.long.byte 0x24 28.--31. 1. "WTLPMSPI2,Weight used for LP mode MSPI2"
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x24 24.--27. 1. "WTLPI3C1,Weight used for LP mode I3C1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x24 20.--23. 1. "WTLPI3C0,Weight used for LP mode I3C0"
|
|
endif
|
|
hexmask.long.byte 0x24 16.--19. 1. "WTLPAUDADC,Weight used for LP mode AUDADC"
|
|
newline
|
|
hexmask.long.byte 0x24 12.--15. 1. "WTLPAUDPB,Weight used for LP mode AUDPB"
|
|
hexmask.long.byte 0x24 8.--11. 1. "WTLPAUDREC,Weight used for LP mode AUDREC"
|
|
newline
|
|
hexmask.long.byte 0x24 4.--7. 1. "WTLPDBG,Weight used for LP mode DBG"
|
|
hexmask.long.byte 0x24 0.--3. 1. "WTLPDSPA,Weight used for LP mode DSPA"
|
|
line.long 0x28 "PWRWEIGHTLP4,Weights specified in this register are applied to each of the masters active requests. The aggregate of all the masters is compared against the allowed value to change the buck from active to inactive mode."
|
|
hexmask.long.byte 0x28 28.--31. 1. "WTLPPDM3,Weight used for LP mode PDM3"
|
|
hexmask.long.byte 0x28 24.--27. 1. "WTLPPDM2,Weight used for LP mode PDM2"
|
|
newline
|
|
hexmask.long.byte 0x28 20.--23. 1. "WTLPPDM1,Weight used for LP mode PDM1"
|
|
hexmask.long.byte 0x28 16.--19. 1. "WTLPPDM0,Weight used for LP mode PDM0"
|
|
newline
|
|
hexmask.long.byte 0x28 4.--7. 1. "WTLPI2S1,Weight used for LP mode I2S1"
|
|
hexmask.long.byte 0x28 0.--3. 1. "WTLPI2S0,Weight used for LP mode I2S0"
|
|
line.long 0x2C "PWRWEIGHTLP5,Weights specified in this register are applied to each of the masters active requests. The aggregate of all the masters is compared against the allowed value to change the buck from active to inactive mode."
|
|
hexmask.long.byte 0x2C 4.--7. 1. "WTLPUSBPHY,Weight used for LP mode USB PHY"
|
|
hexmask.long.byte 0x2C 0.--3. 1. "WTLPDISPPHY,Weight used for LP mode DISP PHY"
|
|
line.long 0x30 "PWRWEIGHTHP0,Weights specified in this register are applied to each of the masters active requests. The aggregate of all the masters is compared against the allowed value to change the buck from active to inactive mode."
|
|
hexmask.long.byte 0x30 28.--31. 1. "WTHPUART3,Weight used for HP mode UART3"
|
|
hexmask.long.byte 0x30 24.--27. 1. "WTHPUART2,Weight used for HP mode UART2"
|
|
newline
|
|
hexmask.long.byte 0x30 20.--23. 1. "WTHPUART1,Weight used for HP mode UART1"
|
|
hexmask.long.byte 0x30 16.--19. 1. "WTHPUART0,Weight used for HP mode UART0"
|
|
newline
|
|
hexmask.long.byte 0x30 12.--15. 1. "WTHPIOS,Weight used for HP mode IOS"
|
|
hexmask.long.byte 0x30 8.--11. 1. "WTHPDSP1,Weight used for HP mode DSP1"
|
|
newline
|
|
hexmask.long.byte 0x30 4.--7. 1. "WTHPDSP0,Weight used for HP mode DSP0"
|
|
hexmask.long.byte 0x30 0.--3. 1. "WTHPMCU,Weight used for HP mode MCU"
|
|
line.long 0x34 "PWRWEIGHTHP1,Weights specified in this register are applied to each of the masters active requests. The aggregate of all the masters is compared against the allowed value to change the buck from active to inactive mode."
|
|
hexmask.long.byte 0x34 28.--31. 1. "WTHPIOM7,Weight used for HP mode IOM7"
|
|
hexmask.long.byte 0x34 24.--27. 1. "WTHPIOM6,Weight used for HP mode IOM6"
|
|
newline
|
|
hexmask.long.byte 0x34 20.--23. 1. "WTHPIOM5,Weight used for HP mode IOM5"
|
|
hexmask.long.byte 0x34 16.--19. 1. "WTHPIOM4,Weight used for HP mode IOM4"
|
|
newline
|
|
hexmask.long.byte 0x34 12.--15. 1. "WTHPIOM3,Weight used for HP mode IOM3"
|
|
hexmask.long.byte 0x34 8.--11. 1. "WTHPIOM2,Weight used for HP mode IOM2"
|
|
newline
|
|
hexmask.long.byte 0x34 4.--7. 1. "WTHPIOM1,Weight used for HP mode IOM1"
|
|
hexmask.long.byte 0x34 0.--3. 1. "WTHPIOM0,Weight used for HP mode IOM0"
|
|
line.long 0x38 "PWRWEIGHTHP2,Weights specified in this register are applied to each of the masters active requests. The aggregate of all the masters is compared against the allowed value to change the buck from active to inactive mode."
|
|
hexmask.long.byte 0x38 28.--31. 1. "WTHPUSB,Weight used for HP mode USB"
|
|
hexmask.long.byte 0x38 24.--27. 1. "WTHPSDIO,Weight used for HP mode SDIO"
|
|
newline
|
|
hexmask.long.byte 0x38 20.--23. 1. "WTHPCRYPTO,Weight used for HP mode CRYPTO"
|
|
hexmask.long.byte 0x38 16.--19. 1. "WTHPDISP,Weight used for HP mode DISP"
|
|
newline
|
|
hexmask.long.byte 0x38 12.--15. 1. "WTHPGFX,Weight used for HP mode GFX"
|
|
hexmask.long.byte 0x38 8.--11. 1. "WTHPMSPI1,Weight used for HP mode MSPI1"
|
|
newline
|
|
hexmask.long.byte 0x38 4.--7. 1. "WTHPMSPI0,Weight used for HP mode MSPI0"
|
|
hexmask.long.byte 0x38 0.--3. 1. "WTHPADC,Weight used for HP mode ADC"
|
|
line.long 0x3C "PWRWEIGHTHP3,Weights specified in this register are applied to each of the masters active requests. The aggregate of all the masters is compared against the allowed value to change the buck from active to inactive mode."
|
|
hexmask.long.byte 0x3C 28.--31. 1. "WTHPMSPI2,Weight used for HP mode MSPI2"
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x3C 24.--27. 1. "WTHPI3C1,Weight used for HP mode I3C1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x3C 20.--23. 1. "WTHPI3C0,Weight used for HP mode I3C0"
|
|
endif
|
|
hexmask.long.byte 0x3C 16.--19. 1. "WTHPAUDADC,Weight used for HP mode AUDADC"
|
|
newline
|
|
hexmask.long.byte 0x3C 12.--15. 1. "WTHPAUDPB,Weight used for HP mode AUDPB"
|
|
hexmask.long.byte 0x3C 8.--11. 1. "WTHPAUDREC,Weight used for HP mode AUDREC"
|
|
newline
|
|
hexmask.long.byte 0x3C 4.--7. 1. "WTHPDBG,Weight used for HP mode DBG"
|
|
hexmask.long.byte 0x3C 0.--3. 1. "WTHPDSPA,Weight used for HP mode DSPA"
|
|
line.long 0x40 "PWRWEIGHTHP4,Weights specified in this register are applied to each of the masters active requests. The aggregate of all the masters is compared against the allowed value to change the buck from active to inactive mode."
|
|
hexmask.long.byte 0x40 28.--31. 1. "WTHPPDM3,Weight used for HP mode PDM3"
|
|
hexmask.long.byte 0x40 24.--27. 1. "WTHPPDM2,Weight used for HP mode PDM2"
|
|
newline
|
|
hexmask.long.byte 0x40 20.--23. 1. "WTHPPDM1,Weight used for HP mode PDM1"
|
|
hexmask.long.byte 0x40 16.--19. 1. "WTHPPDM0,Weight used for HP mode PDM0"
|
|
newline
|
|
hexmask.long.byte 0x40 4.--7. 1. "WTHPI2S1,Weight used for HP mode I2S1"
|
|
hexmask.long.byte 0x40 0.--3. 1. "WTHPI2S0,Weight used for HP mode I2S0"
|
|
line.long 0x44 "PWRWEIGHTHP5,Weights specified in this register are applied to each of the masters active requests. The aggregate of all the masters is compared against the allowed value to change the buck from active to inactive mode."
|
|
hexmask.long.byte 0x44 4.--7. 1. "WTHPUSBPHY,Weight used for HP mode USB PHY"
|
|
hexmask.long.byte 0x44 0.--3. 1. "WTHPDISPPHY,Weight used for HP mode DISP PHY"
|
|
line.long 0x48 "PWRWEIGHTSLP,Weights specified in this register are applied to each of the masters active requests. The aggregate of all the masters is compared against the allowed value to change the buck from active to inactive mode."
|
|
hexmask.long.byte 0x48 0.--3. 1. "WTDSMCU,Weight used for Deep Sleep mode MCU"
|
|
line.long 0x4C "VRDEMOTIONTHR,Weights specified in PWRWEIGHT* registers are applied to each of the masters active requests. The aggregate of all the masters is compared against the this threshold value to change the buck from active to inactive mode."
|
|
hexmask.long 0x4C 0.--31. 1. "VRDEMOTIONTHR,VR Demotion Threshold"
|
|
endif
|
|
group.long 0x190++0xB
|
|
line.long 0x0 "SRAMCTRL,This register provides additional fine-tune power management controls for the SRAMs and the SRAM controller. This includes enabling light sleep for the SRAM and TCM banks. and clock gating for reduced dynamic power."
|
|
hexmask.long.word 0x0 8.--19. 1. "SRAMLIGHTSLEEP,Light Sleep enable for each TCM/SRAM bank. When 1 corresponding bank will be put into light sleep. For optimal power banks should be put into light sleep while the system is active but the bank has minimal or no accesses."
|
|
newline
|
|
bitfld.long 0x0 2. "SRAMMASTERCLKGATE,This bit is 1 when the master clock gate is enabled (top-level clock gate for entire SRAM block)" "0: Disables Master SRAM Clock Gating,1: Enable Master SRAM Clock Gate"
|
|
newline
|
|
bitfld.long 0x0 1. "SRAMCLKGATE,This bit is 1 if clock gating is allowed for individual system SRAMs" "0: Disables Individual SRAM Clock Gating,1: Enable Individual SRAM Clock Gating"
|
|
line.long 0x4 "ADCSTATUS,This provides the power status for various blocks within the ADC. These status comes directly from the ADC module and is captured through this interface."
|
|
bitfld.long 0x4 5. "REFBUFPWD,This bit indicates that the ADC REFBUF is powered down" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "REFKEEPPWD,This bit indicates that the ADC REFKEEP is powered down" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "VBATPWD,This bit indicates that the ADC VBAT resistor divider is powered down" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "VPTATPWD,This bit indicates that the ADC temperature sensor input buffer is powered down" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "BGTPWD,This bit indicates that the ADC Band Gap is powered down" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "ADCPWD,This bit indicates that the ADC is powered down" "0,1"
|
|
line.long 0x8 "AUDADCSTATUS,This provides the power status for various blocks within the audio ADC. These status comes directly from the audio ADC module and is captured through this interface."
|
|
bitfld.long 0x8 5. "AUDREFBUFPWD,This bit indicates that the ADC REFBUF is powered down" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "AUDREFKEEPPWD,This bit indicates that the ADC REFKEEP is powered down" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "AUDVBATPWD,This bit indicates that the ADC VBAT resistor divider is powered down" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "AUDVPTATPWD,This bit indicates that the ADC temperature sensor input buffer is powered down" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "AUDBGTPWD,This bit indicates that the ADC Band Gap is powered down" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "AUDADCPWD,This bit indicates that the ADC is powered down" "0,1"
|
|
group.long 0x200++0x23
|
|
line.long 0x0 "EMONCTRL,Controls each of the energy monitor conuters"
|
|
hexmask.long.byte 0x0 8.--15. 1. "CLEAR,Clear the counter. Each bit corresponds to a counter. 0: Let the counter run run on its input clk. 1: Clear the counter"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "FREEZE,Freeze the counter. Each bit corresponds to a counter. 0: Let the counter run. 1: Stop the counter."
|
|
line.long 0x4 "EMONCFG0,The counter increments when the counter is enabled and the mode selected here matches the power mode."
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x4 0.--7. 1. "EMONSEL0,Power modes for incrementing the counter"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x4 0.--7. 1. "EMONSEL0,Power modes for incrementing the counter"
|
|
endif
|
|
line.long 0x8 "EMONCFG1,The counter increments when the counter is enabled and the mode selected here matches the power mode."
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x8 0.--7. 1. "EMONSEL1,Power modes for incrementing the counter"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x8 0.--7. 1. "EMONSEL1,Power modes for incrementing the counter"
|
|
endif
|
|
line.long 0xC "EMONCFG2,The counter increments when the counter is enabled and the mode selected here matches the power mode."
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0xC 0.--7. 1. "EMONSEL2,Power modes for incrementing the counter"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0xC 0.--7. 1. "EMONSEL2,Power modes for incrementing the counter"
|
|
endif
|
|
line.long 0x10 "EMONCFG3,The counter increments when the counter is enabled and the mode selected here matches the power mode."
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x10 0.--7. 1. "EMONSEL3,Power modes for incrementing the counter"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x10 0.--7. 1. "EMONSEL3,Power modes for incrementing the counter"
|
|
endif
|
|
line.long 0x14 "EMONCFG4,The counter increments when the counter is enabled and the mode selected here matches the power mode."
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x14 0.--7. 1. "EMONSEL4,Power modes for incrementing the counter"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x14 0.--7. 1. "EMONSEL4,Power modes for incrementing the counter"
|
|
endif
|
|
line.long 0x18 "EMONCFG5,The counter increments when the counter is enabled and the mode selected here matches the power mode."
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x18 0.--7. 1. "EMONSEL5,Power modes for incrementing the counter"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x18 0.--7. 1. "EMONSEL5,Power modes for incrementing the counter"
|
|
endif
|
|
line.long 0x1C "EMONCFG6,The counter increments when the counter is enabled and the mode selected here matches the power mode."
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x1C 0.--7. 1. "EMONSEL6,Power modes for incrementing the counter"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x1C 0.--7. 1. "EMONSEL6,Power modes for incrementing the counter"
|
|
endif
|
|
line.long 0x20 "EMONCFG7,The counter increments when the counter is enabled and the mode selected here matches the power mode."
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x20 0.--7. 1. "EMONSEL7,Power modes for incrementing the counter"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x20 0.--7. 1. "EMONSEL7,Power modes for incrementing the counter"
|
|
endif
|
|
group.long 0x228++0x1F
|
|
line.long 0x0 "EMONCOUNT0,Energy Monitor count value for counter 0"
|
|
hexmask.long 0x0 0.--31. 1. "EMONCOUNT0,Energy Monitor count value counter 0"
|
|
line.long 0x4 "EMONCOUNT1,Energy Monitor count value for counter 1"
|
|
hexmask.long 0x4 0.--31. 1. "EMONCOUNT1,Energy Monitor count value counter 1"
|
|
line.long 0x8 "EMONCOUNT2,Energy Monitor count value for counter 2"
|
|
hexmask.long 0x8 0.--31. 1. "EMONCOUNT2,Energy Monitor count value counter 2"
|
|
line.long 0xC "EMONCOUNT3,Energy Monitor count value for counter 3"
|
|
hexmask.long 0xC 0.--31. 1. "EMONCOUNT3,Energy Monitor count value counter 3"
|
|
line.long 0x10 "EMONCOUNT4,Energy Monitor count value for counter 4"
|
|
hexmask.long 0x10 0.--31. 1. "EMONCOUNT4,Energy Monitor count value counter 4"
|
|
line.long 0x14 "EMONCOUNT5,Energy Monitor count value for counter 5"
|
|
hexmask.long 0x14 0.--31. 1. "EMONCOUNT5,Energy Monitor count value counter 5"
|
|
line.long 0x18 "EMONCOUNT6,Energy Monitor count value for counter 6"
|
|
hexmask.long 0x18 0.--31. 1. "EMONCOUNT6,Energy Monitor count value counter 6"
|
|
line.long 0x1C "EMONCOUNT7,Energy Monitor count value for counter 7"
|
|
hexmask.long 0x1C 0.--31. 1. "EMONCOUNT7,Energy Monitor count value counter 7"
|
|
group.long 0x24C++0x3
|
|
line.long 0x0 "EMONSTATUS,Energy Monitor status"
|
|
bitfld.long 0x0 7. "EMONOVERFLOW7,Energy Monitor counter7 overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "EMONOVERFLOW6,Energy Monitor counter6 overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EMONOVERFLOW5,Energy Monitor counter5 overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMONOVERFLOW4,Energy Monitor counter4 overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EMONOVERFLOW3,Energy Monitor counter3 overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EMONOVERFLOW2,Energy Monitor counter2 overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EMONOVERFLOW1,Energy Monitor counter1 overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EMONOVERFLOW0,Energy Monitor counter0 overflow" "0,1"
|
|
tree.end
|
|
tree "RSTGEN (MCU Reset Generator)"
|
|
base ad:0x40000000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CFG,Reset configuration register. This controls the reset enables for brownout condition. choice of brownout method and for the expiration of the watch dog timer."
|
|
bitfld.long 0x0 1. "WDREN,Watchdog Timer Reset Enable. NOTE: The WDT module must also be configured for WDT reset. This includes enabling the RESEN bit in WDTCFG register in Watch dog timer block." "0,1"
|
|
bitfld.long 0x0 0. "BODHREN,Brown out high (2.1v) reset enable. Note - Enabling this bit for Apollo4 which operates at 1.8v/1.9v will cause a continual reset loop." "0,1"
|
|
line.long 0x4 "SWPOI,This is the software POI reset. writing the key value to this register will trigger a POI to the system. This will cause a reset to all blocks except for registers in clock gen. RTC and the stimer."
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x4 0.--7. 1. "SWPOIKEY,0x1B generates a software POI reset. This is a write-only register. Reading from this register will yield only all 0s."
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x4 0.--7. 1. "SWPOIKEY,0x1B generates a software POI reset. This is a write-only register. Reading from this register will yield only all 0s."
|
|
endif
|
|
line.long 0x8 "SWPOR,This is the software POR reset. Writing the key value to this register will trigger a POR to the system. This will cause a reset to all blocks except for registers in clock gen. RTC. power management unit. the stimer. and the power management unit."
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x8 0.--7. 1. "SWPORKEY,0xD4 generates a software POR reset."
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x8 0.--7. 1. "SWPORKEY,0xD4 generates a software POR reset."
|
|
endif
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "SIMOBODM,This register unmasks the individual digital detection brownout bits into the interrupt block"
|
|
bitfld.long 0x0 3. "DIGBOECLV,Enable the gate into the interrupt block for the digital brownout detection on VDDC_LV. Note: The interrupt block must also be unmasked for ISR and interrupt status to be set" "0: Mask the VDDC_LV digital brownout detection into..,1: Enable brown VDDC_LV digital brownout detection.."
|
|
bitfld.long 0x0 2. "DIGBOES,Enable the gate into the interrupt block for the digital brownout detection on VDDS. Note: The interrupt block must also be unmasked for ISR and interrupt status to be set" "0: Mask the VDDS digital brownout detection into..,1: Enable the VDDS digital brownout detection into.."
|
|
newline
|
|
bitfld.long 0x0 1. "DIGBOEF,Enable the gate into the interrupt block for the digital brownout detection on VDDF. Note: The interrupt block must also be unmasked for ISR and interrupt status to be set" "0: Mask the VDDF digital brownout detection into..,1: Enable the VDDF digital brownout detection into.."
|
|
bitfld.long 0x0 0. "DIGBOEC,Enable the gate into the interrupt block for the digital brownout detection on VDDC. Note: The interrupt block must also be unmasked for ISR and interrupt status to be set" "0: Enable brown out detection for VDDF using the..,1: Enable brown out detection for VDDF using the.."
|
|
group.long 0x200++0xF
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 4. "BODDIGCLV,Enables an interrupt that triggers when simobuck digital detects inactivity on VDDC_LV" "0,1"
|
|
bitfld.long 0x0 3. "BODDIGS,Enables an interrupt that triggers when simobuck digital detects inactivity on VDDS" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "BODDIGF,Enables an interrupt that triggers when simobuck digital detects inactivity on VDDF" "0,1"
|
|
bitfld.long 0x0 1. "BODDIGC,Enables an interrupt that triggers when simobuck digital detects inactivity on VDDC" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BODH,Enables an interrupt that triggers when VCC is below BODH level." "0,1"
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 4. "BODDIGCLV,Enables an interrupt that triggers when simobuck digital detects inactivity on VDDC_LV" "0,1"
|
|
bitfld.long 0x4 3. "BODDIGS,Enables an interrupt that triggers when simobuck digital detects inactivity on VDDS" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "BODDIGF,Enables an interrupt that triggers when simobuck digital detects inactivity on VDDF" "0,1"
|
|
bitfld.long 0x4 1. "BODDIGC,Enables an interrupt that triggers when simobuck digital detects inactivity on VDDC" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "BODH,Enables an interrupt that triggers when VCC is below BODH level." "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 4. "BODDIGCLV,Enables an interrupt that triggers when simobuck digital detects inactivity on VDDC_LV" "0,1"
|
|
bitfld.long 0x8 3. "BODDIGS,Enables an interrupt that triggers when simobuck digital detects inactivity on VDDS" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "BODDIGF,Enables an interrupt that triggers when simobuck digital detects inactivity on VDDF" "0,1"
|
|
bitfld.long 0x8 1. "BODDIGC,Enables an interrupt that triggers when simobuck digital detects inactivity on VDDC" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "BODH,Enables an interrupt that triggers when VCC is below BODH level." "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 4. "BODDIGCLV,Enables an interrupt that triggers when simobuck digital detects inactivity on VDDC_LV" "0,1"
|
|
bitfld.long 0xC 3. "BODDIGS,Enables an interrupt that triggers when simobuck digital detects inactivity on VDDS" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "BODDIGF,Enables an interrupt that triggers when simobuck digital detects inactivity on VDDF" "0,1"
|
|
bitfld.long 0xC 1. "BODDIGC,Enables an interrupt that triggers when simobuck digital detects inactivity on VDDC" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "BODH,Enables an interrupt that triggers when VCC is below BODH level." "0,1"
|
|
group.long 0x885C++0x3
|
|
line.long 0x0 "STAT,This register contains the status for brownout events and the causes for resets.\n NOTE 1: All bits in this register. including reserved bits. are writable. Therefore care should be taken not to write this register.\n NOTE 2: This register is only.."
|
|
bitfld.long 0x0 10. "BOSSTAT,VDDS Analog Brownout Event occured." "0,1"
|
|
bitfld.long 0x0 9. "BOFSTAT,VDDF Analog Brownout Event occured." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "BOCSTAT,VDDC Analog Brownout Event occured." "0,1"
|
|
bitfld.long 0x0 7. "BOUSTAT,An Unregulated Supply Brownout Event occured." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "WDRSTAT,Reset was initiated by a Watchdog Timer Reset." "0,1"
|
|
bitfld.long 0x0 5. "DBGRSTAT,Reset was a initiated by Debugger Reset." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "POIRSTAT,Reset was a initiated by Software POI Reset." "0,1"
|
|
bitfld.long 0x0 3. "SWRSTAT,Reset was a initiated by SW POR or AIRCR Reset." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "BORSTAT,Reset was initiated by a Brown-Out Reset." "0,1"
|
|
bitfld.long 0x0 1. "PORSTAT,Reset was initiated by a Power-On Reset." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EXRSTAT,Reset was initiated by an External Reset." "0,1"
|
|
tree.end
|
|
tree "RTC (Real Time Clock)"
|
|
base ad:0x40004800
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "RTCCTL,This is the register control for the RTC module. It enables counter writes and sets the alarm repeat interval."
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 5. "HR1224,Hours Counter mode Only 24HR mode supported" "0: Hours in 24 hour mode,1: Disable the 24 hour mode"
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 5. "HR1224,Hours Counter mode Only 24HR mode supported" "0: Hours in 24 hour mode,1: Disable the 24 hour mode"
|
|
endif
|
|
bitfld.long 0x0 4. "RSTOP,RTC input clock control" "0: Allow the RTC input clock to run,1: Stop the RTC input clock"
|
|
newline
|
|
bitfld.long 0x0 1.--3. "RPT,Alarm repeat interval" "0: Alarm interrupt disabled,1: Interrupt every year,2: Interrupt every month,3: Interrupt every week,4: Interrupt every day,5: Interrupt every hour,6: Interrupt every minute,7: Interrupt every second/10th/100th"
|
|
bitfld.long 0x0 0. "WRTC,Counter write control" "0: Counter writes are disabled,1: Counter writes are enabled"
|
|
line.long 0x4 "RTCSTAT,This is the register status for the RTC module."
|
|
bitfld.long 0x4 0. "WRITEBUSY,Indicates that an RTC update (write) is still in progress. Writes are initiated by writing the CTTLOW register - CTRUP must be written before CTRLOW to be updated (otherwise it will retain its current value)" "0,1"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "CTRLOW,This counter contains the values for hour. minutes. seconds and 100ths of a second Counter."
|
|
hexmask.long.byte 0x0 24.--29. 1. "CTRHR,Hours Counter"
|
|
hexmask.long.byte 0x0 16.--22. 1. "CTRMIN,Minutes Counter"
|
|
hexmask.long.byte 0x0 8.--14. 1. "CTRSEC,Seconds Counter"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "CTR100,100ths of a second Counter"
|
|
line.long 0x4 "CTRUP,This register contains the day. month and year information. It contains which day in the week. and the century as well. The information of the century can also be derived from the year information. The 31st bit contains the error bit. See.."
|
|
bitfld.long 0x4 31. "CTERR,Counter read error status. Error is triggered when software reads the lower word of the counters and fails to read the upper counter within 1/100 second. This is because when the lower counter is read the upper counter is held off from.." "0: No read error occurred,1: Read error occurred"
|
|
bitfld.long 0x4 29. "CEB,Century enable" "0: Disable the Century bit from changing,1: Enable the Century bit to change"
|
|
bitfld.long 0x4 28. "CB,Century" "0: Century is 2000s,1: Century is 1900s/2100s"
|
|
newline
|
|
bitfld.long 0x4 24.--26. "CTRWKDY,Weekdays Counter" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 16.--23. 1. "CTRYR,Years Counter"
|
|
hexmask.long.byte 0x4 8.--12. 1. "CTRMO,Months Counter"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "CTRDATE,Date Counter"
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "ALMLOW,This register is the Alarm settings for hours. minutes. second and 1/100th seconds settings."
|
|
hexmask.long.byte 0x0 24.--29. 1. "ALMHR,Hours Alarm"
|
|
hexmask.long.byte 0x0 16.--22. 1. "ALMMIN,Minutes Alarm"
|
|
hexmask.long.byte 0x0 8.--14. 1. "ALMSEC,Seconds Alarm"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "ALM100,100ths of a second Alarm"
|
|
line.long 0x4 "ALMUP,This register is the alarm settings for week. month and day."
|
|
bitfld.long 0x4 16.--18. "ALMWKDY,Weekdays Alarm" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 8.--12. 1. "ALMMO,Months Alarm"
|
|
hexmask.long.byte 0x4 0.--5. 1. "ALMDATE,Date Alarm"
|
|
group.long 0x200++0xF
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 0. "ALM,RTC Alarm interrupt" "0,1"
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 0. "ALM,RTC Alarm interrupt" "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 0. "ALM,RTC Alarm interrupt" "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 0. "ALM,RTC Alarm interrupt" "0,1"
|
|
tree.end
|
|
tree "SDIO (Secure Digital Input Output)"
|
|
base ad:0x40070000
|
|
group.long 0x0++0x73
|
|
line.long 0x0 "SDMA,SDMA system address"
|
|
hexmask.long 0x0 0.--31. 1. "SDMASYSTEMADDRESS,This register contains the physical system memory address used for DMA transfers or the second argument for the Auto CMD23. (1) SDMA System Address This register contains the system memory address for a SDMA transfer. When the Host.."
|
|
line.long 0x4 "BLOCK,Block size"
|
|
hexmask.long.word 0x4 16.--31. 1. "BLKCNT,This register is enabled when Block Count Enable in the Transfer Mode register is set to 1 and is valid only for multiple block transfers. The HC decrements the block count after each block transfer and stops when the count reaches zero. It can be.."
|
|
newline
|
|
bitfld.long 0x4 12.--14. "HOSTSDMABUFSZ,To perform long DMA transfer System Address register shall be updated at every system boundary during DMA transfer. These bits specify the size of contiguous buffer in the system memory. The DMA transfer shall wait at the every boundary.." "0: 4KB(Detects A11 Carry out),1: 8KB(Detects A12 Carry out),2: 16KB(Detects A13 Carry out),3: 32KB(Detects A14 Carry out),4: 64KB(Detects A15 Carry out),5: 128KB(Detects A16 Carry out),6: 256KB(Detects A17 Carry out),7: 512KB(Detects A18 Carry out)"
|
|
newline
|
|
hexmask.long.word 0x4 0.--11. 1. "TRANSFERBLOCKSIZE,This register specifies the block size for block data transfers for CMD17 CMD18 CMD24 CMD25 and CMD53. It can be accessed only if no transaction is executing (i.e after a transaction has stopped). Read operations during transfer.."
|
|
line.long 0x8 "ARGUMENT1,Argument1"
|
|
hexmask.long 0x8 0.--31. 1. "CMDARG1,The SD Command Argument is specified as bit39-8 of Command-Format."
|
|
line.long 0xC "TRANSFER,Transfer mode"
|
|
hexmask.long.byte 0xC 24.--29. 1. "CMDIDX,This bit shall be set to the command number (CMD0-63 ACMD063)."
|
|
newline
|
|
bitfld.long 0xC 22.--23. "CMDTYPE,There are three types of special commands. Suspend Resume and Abort. These bits shall bet set to 00b for all other commands. Suspend Command If the Suspend command succeeds the HC shall assume the SD Bus has been released and that it is.." "0: Normal,1: Suspend,2: Resume,3: Abort"
|
|
newline
|
|
bitfld.long 0xC 21. "DATAPRSNTSEL,This bit is set to 1 to indicate that data is present and shall be transferred using the DAT line. If is set to 0 for the following: 1. Commands using only CMD line (ex. CMD52) 2. Commands with no data transfer but using busy signal on.." "0: No Data Present,1: Data Present"
|
|
newline
|
|
bitfld.long 0xC 20. "CMDIDXCHKEN,If this bit is set to 1 the HC shall check the index field in the response to see if it has the same value as the command index. If it is not it is reported as a Command Index Error. If this bit is set to 0 the Index field is not checked." "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0xC 19. "CMDCRCCHKEN,If this bit is set to 1 the HC shall check the CRC field in the response. If an error is detected it is reported as a Command CRC Error. If this bit is set to 0 the CRC field is not checked." "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0xC 16.--17. "RESPTYPESEL,Response Type Select" "0: No Response,1: Response length 136,2: Response length 48,3: Response length 48 check Busy after response"
|
|
newline
|
|
bitfld.long 0xC 5. "BLKSEL,This bit enables multiple block data transfers." "0: Single Block,1: Multiple Block"
|
|
newline
|
|
bitfld.long 0xC 4. "DXFERDIRSEL,Data Transfer Direction Select. This bit defines the direction of data transfers." "0: Write (Host to Card),1: Read (Card to Host)"
|
|
newline
|
|
bitfld.long 0xC 2.--3. "ACMDEN,This field determines use of auto command functions. There are two methods to stop Multiple-block read and write operation. (1) Auto CMD12 Enable Multiple-block read and write commands for memory require CMD12 to stop the operation. When this.." "0: Auto Command Disabled,1: Auto CMD12 Enable,2: Auto CMD23 Enable,?"
|
|
newline
|
|
bitfld.long 0xC 1. "BLKCNTEN,This bit is used to enable the Block count register which is only relevant for multiple block transfers. When this bit is 0 the Block Count register is disabled which is useful in executing an infinite transfer." "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0xC 0. "DMAEN,DMA can be enabled only if DMA Support bit in the Capabilities register is set. If this bit is set to 1 a DMA operation shall begin when the HD writes to the upper byte of Command register (00Fh)." "0: Disable,1: Enable"
|
|
line.long 0x10 "RESPONSE0,Response0"
|
|
hexmask.long 0x10 0.--31. 1. "CMDRESP0,R[] refers to a bit range within the response data as transmitted on the SD Bus REP[] refers to a bit range within the Response register."
|
|
line.long 0x14 "RESPONSE1,Response1"
|
|
hexmask.long 0x14 0.--31. 1. "CMDRESP1,R[] refers to a bit range within the response data as transmitted on the SD Bus REP[] refers to a bit range within the Response register."
|
|
line.long 0x18 "RESPONSE2,Response2"
|
|
hexmask.long 0x18 0.--31. 1. "CMDRESP2,R[] refers to a bit range within the response data as transmitted on the SD Bus REP[] refers to a bit range within the Response register."
|
|
line.long 0x1C "RESPONSE3,Response3"
|
|
hexmask.long 0x1C 0.--31. 1. "CMDRESP3,R[] refers to a bit range within the response data as transmitted on the SD Bus REP[] refers to a bit range within the Response register."
|
|
line.long 0x20 "BUFFER,Buffer data port"
|
|
hexmask.long 0x20 0.--31. 1. "BUFFERDATA,The Host Controller Buffer can be accessed through this 32-bit Data Port Register."
|
|
line.long 0x24 "PRESENT,Present state"
|
|
hexmask.long.byte 0x24 25.--28. 1. "DAT74LINE,This status is used to check DAT line level to recover from errors and for debugging."
|
|
newline
|
|
bitfld.long 0x24 24. "CMDLINE,This status is used to check CMD line level to recover from errors and for debugging." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x24 20.--23. 1. "DAT30LINE,This status is used to check DAT line level to recover from errors and for debugging. This is especially useful in detecting the busy signal level from DAT[0]."
|
|
newline
|
|
bitfld.long 0x24 19. "WRPROTSW,The Write Protect Switch is supported for memory and combo cards. This bit reflects the SDWP# pin." "0: Write protected (SDWP# = 0),1: Write enabled (SDWP# = 1)"
|
|
newline
|
|
bitfld.long 0x24 18. "CARDDET,This bit reflects the inverse value of the SDCD# pin." "0: No Card present (SDCD# = 1),1: Card present (SDCD# = 0)"
|
|
newline
|
|
bitfld.long 0x24 17. "CARDSTABLE,This bit is used for testing. If it is 0 the Card Detect Pin Level is not stable. If this bit is set to 1 it means the Card Detect Pin Level is stable. The Software Reset For All in the Software Reset Register shall not affect this bit." "0: Reset or Debouncing or No Card,1: Card Inserted"
|
|
newline
|
|
bitfld.long 0x24 16. "CARDINSERTED,This bit indicates whether a card has been inserted. Changing from 0 to 1 generates a Card Insertion interrupt in the Normal Interrupt Status register and changing from 1 to 0 generates a Card Removal Interrupt in the Normal Interrupt Status.." "0: Reset or Debouncing or No Card,1: Card Inserted"
|
|
newline
|
|
bitfld.long 0x24 11. "BUFRDEN,This status is used for non-DMA read transfers. This read only flag indicates that valid data exists in the host side buffer status. If this bit is 1 readable data exists in the buffer. A change of this bit from 1 to 0 occurs when all the block.." "0: Read Disable,1: Read Enable."
|
|
newline
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bitfld.long 0x24 10. "BUFWREN,This status is used for non-DMA write transfers. This read only flag indicates if space is available for write data. If this bit is 1 data can be written to the buffer. A change of this bit from 1 to 0 occurs when all the block data is written.." "0: Write Disable,1: Write Enable."
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bitfld.long 0x24 9. "RDXFERACT,This status is used for detecting completion of a read transfer. This bit is set to 1 for either of the following conditions: After the end bit of the read command When writing a 1 to continue Request in the Block Gap Control register to.." "0: No valid data,1: Transferring data"
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bitfld.long 0x24 8. "WRXFERACT,This status indicates a write transfer is active. If this bit is 0 it means no valid write data exists in the HC. This bit is set in either of the following cases: After the end bit of the write command. When writing a 1 to Continue Request in.." "0: No valid data,1: transferring data"
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bitfld.long 0x24 3. "RETUNINGREQUEST,Re-Tuning Request Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive correct.." "0: Fixed or well tuned sampling clock,1: Sampling clock needs re-tuning"
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bitfld.long 0x24 2. "DLINEACT,This bit indicates whether one of the DAT line on SD bus is in use." "0: DAT line inactive,1: DAT line active"
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bitfld.long 0x24 1. "CMDINHDAT,This status bit is generated if either the DAT Line Active or the Read transfer Active is set to 1. If this bit is 0 it indicates the HC can issue the next SD command. Commands with busy signal belong to Command Inhibit (DAT) (ex. R1b R5b.." "0: Can issue command which uses the DAT line,1: cannot issue command which uses the DAT line"
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bitfld.long 0x24 0. "CMDINHCMD,If this bit is 0 it indicates the CMD line is not in use and the HC can issue a SD command using the CMD line. This bit is set immediately after the Command register (00Fh) is written. This bit is cleared when the command response is received." "0: Indicates that the CMD line is not in use and..,1: CMD line is in use"
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line.long 0x28 "HOSTCTRL1,Host control 1"
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bitfld.long 0x28 26. "WUENCARDREMOVL,This bit enables wakeup event via Card Removal assertion in the Normal Interrupt Status register. FN_WUS (Wake up Support) in CIS does not affect this bit." "0: Disable,1: Enable"
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bitfld.long 0x28 25. "WUENCARDINSERT,This bit enables wakeup event via Card Insertion assertion in the Normal Interrupt Status register. FN_WUS (Wake up Support) in CIS does not affect this bit." "0: Disable,1: Enable"
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bitfld.long 0x28 24. "WUENCARDINT,This bit enables wakeup event via Card Interrupt assertion in the Normal Interrupt Status register. This bit can be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1." "0: Disable,1: Enable"
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bitfld.long 0x28 23. "BOOTACKCHK,To check for the boot acknowledge in boot operation." "0: Will not wait for boot ack from eMMC card,1: wait for boot ack from eMMC card"
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bitfld.long 0x28 22. "ALTBOOTEN,To start boot code access in alternative mode." "0: To stop alternate boot mode access,1: To start alternate boot mode access"
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bitfld.long 0x28 21. "BOOTEN,To start boot code access" "0: To stop boot code access,1: To start boot code access"
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bitfld.long 0x28 20. "SPIMODE,SPI mode enable bit." "0: SD mode,1: SPI mode"
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bitfld.long 0x28 19. "GAP,This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the interrupt cycle. Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. If the SD card cannot signal an interrupt during a.." "0,1"
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bitfld.long 0x28 18. "READWAITCTRL,The read wait function is optional for SDIO cards. If the card supports read wait set this bit to enable use of the read wait protocol to stop read data using DAT[2] line. Otherwise the HC has to stop the SD clock to hold read data which.." "0: Disable Read Wait Control,1: Enable Read Wait Control"
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bitfld.long 0x28 17. "CONTREQ,This bit is used to restart a transaction which was stopped using the Stop At Block Gap Request. To cancel stop at the block gap set Stop At block Gap Request to 0 and set this bit to restart the transfer. The HC automatically clears this bit in.." "0: Ignored,1: Restart"
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bitfld.long 0x28 16. "STOPATBLOCKGAPREQUEST,This bit is used to stop executing a transaction at the next block gap for non- DMA SDMA and ADMA transfers. Until the transfer complete is set to 1 indicating a transfer completion the HD shall leave this bit set to 1. Clearing.." "0: Transfer,1: Stop"
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bitfld.long 0x28 12. "HWRESET,Hardware reset signal is generated for eMMC card when this bit is set" "0: Deassert the hardware reset pin,1: Drives the hardware reset pin as ZERO (Active.."
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bitfld.long 0x28 9.--11. "VOLTSELECT,By setting these bits the HD selects the voltage level for the SD card. Before setting this register the HD shall check the voltage support bits in the capabilities register. If an unsupported voltage is selected the Host System shall not.." "?,?,?,?,?,5: 1.8 V(Typ.),6: 3.0 V(Typ.),7: 3.3 V(Typ.)"
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bitfld.long 0x28 8. "SDBUSPOWER,Before setting this bit the SD host driver shall set SD Bus Voltage Select. If the HC detects the No Card State this bit shall be cleared." "0: Power off,1: Power on"
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bitfld.long 0x28 7. "CARDSRC,This bit selects source for card detection." "0: SDCD is selected (for normal use),1: The card detect test level is selected"
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bitfld.long 0x28 6. "TESTLEVEL,This bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates card inserted or not. Generates (card ins or card removal) interrupt when the normal int sts enable bit is set." "0: No Card,1: Card Inserted"
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bitfld.long 0x28 5. "XFERWIDTH,This bit controls 8-bit bus width mode for embedded device. Support of this function is indicated in 8-bit Support for Embedded Device in the Capabilities register. If a device supports 8-bit bus mode this bit may be set to 1. If this bit is.." "0: Bus Width is selected by Data Transfer Width,1: 8-bit Bus Width"
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bitfld.long 0x28 3.--4. "DMASELECT,One of supported DMA modes can be selected. The host driver shall check support of DMA modes by referring the Capabilities register." "0: SDMA is selected,1: 32-bit Address ADMA1 is selected,2: 32-bit Address ADMA2 is selected,3: 64-bit Address ADMA2 is selected"
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bitfld.long 0x28 2. "HISPEEDEN,This bit is optional. Before setting this bit the HD shall check the High Speed Support in the capabilities register. If this bit is set to 0 (default) the HC outputs CMD line and DAT lines at the falling edge of the SD clock (up to 25 MHz/.." "0: Normal Speed Mode,1: High Speed Mode"
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bitfld.long 0x28 1. "DATATRANSFERWIDTH,(SD1 or SD4) This bit selects the data width of the HC. The HD shall select it to match the data width of the SD card." "0: 1 bit mode,1: 4 bit mode"
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bitfld.long 0x28 0. "LEDCONTROL,This bit is used to caution the user not to remove the card while the SD card is being accessed. If the software is going to issue multiple SD commands this bit can be set during all transactions. It is not necessary to change for each.." "0: LED off,1: LED on"
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line.long 0x2C "CLOCKCTRL,Clock control"
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bitfld.long 0x2C 26. "SWRSTDAT,Only part of data circuit is reset. The following registers and bits are cleared by this bit: Buffer Data Port Register Buffer is cleared and Initialized. Present State register Buffer read Enable Buffer write Enable Read Transfer Active Write.." "0: Work,1: Reset"
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bitfld.long 0x2C 25. "SWRSTCMD,Only part of command circuit is reset. The following registers and bits are cleared by this bit: Present State register Command Inhibit (CMD) Normal Interrupt Status register Command Complete" "0: Work,1: Reset"
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bitfld.long 0x2C 24. "SWRSTALL,This reset affects the entire HC except for the card detection circuit. Register bits of type ROC RW RW1C RWAC are cleared to 0. During its initialization the HD shall set this bit to 1 to reset the HC. The HC shall reset this bit to 0 when.." "0: Work,1: Reset"
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hexmask.long.byte 0x2C 16.--19. 1. "TIMEOUTCNT,This value determines the interval by which DAT line time-outs are detected. Refer to the Data Time-out Error in the Error Interrupt Status register for information on factors that dictate time-out generation. Time-out clock frequency will be.."
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hexmask.long.byte 0x2C 8.--15. 1. "FREQSEL,This register is used to select the frequency of the SDCLK pin. The frequency is not programmed directly; rather this register holds the divisor of the Base Clock Frequency For SD clock in the capabilities register. Only the following settings.."
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bitfld.long 0x2C 6.--7. "UPRCLKDIV,Bit 07-06 is assigned to bit 09-08 of clock divider in SDCLK Frequency Select" "0,1,2,3"
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bitfld.long 0x2C 5. "CLKGENSEL,This bit is used to select the clock generator mode in SDCLK Frequency Select. If the Programmable Clock Mode is supported (non-zero value is set to Clock Multiplier in the Capabilities register) this bit attribute is RW and if not supported .." "0: Divided Clock Mode,1: Programmable Clock Mode"
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bitfld.long 0x2C 2. "SDCLKEN,The HC shall stop SDCLK when writing this bit to 0. SDCLK frequency Select can be changed when this bit is 0. Then the HC shall maintain the same clock frequency until SDCLK is stopped (Stop at SDCLK = 0). If the HC detects the No Card state .." "0: Disable,1: Enable"
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bitfld.long 0x2C 1. "CLKSTABLE,This bit is set to 1 when SD clock is stable after writing to Internal Clock Enable in this register to 1. The SD Host Driver shall wait to set SD Clock Enable until this bit is set to 1. Note: This is useful when using PLL for a clock.." "0: Not Ready,1: Ready"
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bitfld.long 0x2C 0. "CLKEN,This bit is set to 0 when the HD is not using the HC or the HC awaits a wakeup event. The HC should stop its internal clock to go very low power state. Still registers shall be able to be read and written. Clock starts to oscillate when this bit.." "0: Stop,1: Oscillate"
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line.long 0x30 "INTSTAT,Interrupt enable"
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bitfld.long 0x30 29.--31. "VNDERRSTAT,Vendor specific error status." "0: Not Ready,1: Ready,?,?,?,?,?,?"
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bitfld.long 0x30 28. "TGTRESPERR,Occurs when detecting error in aximst_bresp or aximst_rresp" "0: no error,1: error"
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bitfld.long 0x30 25. "ADMAERROR,This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the ADMA Error Status Register." "0: No error,1: Error"
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bitfld.long 0x30 24. "AUTOCMDERROR,Auto CMD12 and Auto CMD23 use this error status. This bit is set when detecting that one of the bits D00-D04 in Auto CMD Error Status register has changed from 0 to 1. In case of Auto CMD12 this bit is set to 1 not only when the errors in.." "0: D04 in Auto CMD Error Status register has..,1: Error"
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bitfld.long 0x30 23. "CURRENTLIMITERROR,By setting the SD Bus Power bit in the Power Control Register the HC is requested to supply power for the SD Bus. If the HC supports the Current Limit Function it can be protected from an Illegal card by stopping power supply to the.." "0: No Error,1: Power Fail"
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bitfld.long 0x30 22. "DATAENDBITERROR,Occurs when detecting 0 at the end bit position of read data which uses the DAT line or the end bit position of the CRC status." "0: No Error,1: Error"
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bitfld.long 0x30 21. "DATACRCERROR,Occurs when detecting CRC error when transferring read data which uses the DAT line or when detecting the Write CRC Status having a value of other than 0." "0: No Error,1: Error"
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bitfld.long 0x30 20. "DATATIMEOUTERROR,Occurs when detecting one of following timeout conditions. 1. Busy Timeout for R1b R5b type. 2. Busy Timeout after Write CRC status 3. Write CRC status Timeout 4. Read Data Timeout" "0: No Error,1: Timeout"
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bitfld.long 0x30 19. "COMMANDINDEXERROR,Occurs if a Command Index error occurs in the Command Response." "0: No Error,1: Error"
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bitfld.long 0x30 18. "COMMANDENDBITERROR,Occurs only if the no response is returned within 64 SDCLK cycles from the end bit of the command. If the HC detects a CMD line conflict in which case Command CRC Error shall also be set. This bit shall be set without waiting for 64.." "0: No Error,1: Timeout"
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bitfld.long 0x30 17. "COMMANDCRCERROR,Occurs when detecting that the end bit of a command response is 0." "0: No Error,1: End Bit Error Generated"
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bitfld.long 0x30 16. "COMMANDTIMEOUTERROR,Command CRC Error is generated in two cases. 1. If a response is returned and the Command Time-out Error is set to 0 this bit is set to 1 when detecting a CRT error in the command response 2. The HC detects a CMD line conflict by.." "0: No Error,1: CRC Error Generated"
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bitfld.long 0x30 15. "ERRORINTERRUPT,If any of the bits in the Error Interrupt Status Register are set then this bit is set. Therefore the HD can test for an error by checking this bit first." "0: No Error.,1: Error."
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bitfld.long 0x30 14. "BOOTTERMINATE,Interrupt This status is set if the boot operation get terminated" "0: Boot operation is not terminated.,1: Boot operation is terminated"
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bitfld.long 0x30 13. "BOOTACKRCV,This status is set if the boot acknowledge is received from device." "0: Boot ack is not received.,1: Boot ack is received."
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bitfld.long 0x30 12. "RETUNINGEVENT,This status is set if Re-Tuning Request in the Present State register changes from 0 to 1. Host Controller requests Host Driver to perform re-tuning for next data transfer. Current data transfer (not large block count) can be completed.." "0: ReTuning is not required,1: ReTuning should be performed"
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bitfld.long 0x30 11. "INTC,This status is set if INT_C is enabled and INT_C# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_C interrupt factor" "0,1"
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bitfld.long 0x30 10. "INTB,This status is set if INT_B is enabled and INT_B# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_B interrupt factor" "0,1"
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bitfld.long 0x30 9. "INTA,This status is set if INT_A is enabled and INT_A# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_A interrupt factor" "0,1"
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bitfld.long 0x30 8. "CARDINTERRUPT,Writing this bit to 1 does not clear this bit. It is cleared by resetting the SD card interrupt factor. In 1-bit mode the HC shall detect the Card Interrupt without SD Clock to support wakeup. In 4-bit mode the card interrupt signal is.." "0: No Card Interrupt,1: bit mode"
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bitfld.long 0x30 7. "CARDREMOVAL,This status is set if the Card Inserted in the Present State register changes from 1 to 0. When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed. Because the.." "0: Card State Stable or Debouncing,1: Card Removed"
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bitfld.long 0x30 6. "CARDINSERTION,This status is set if the Card Inserted in the Present State register changes from 0 to 1. When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed. Because the.." "0: Card State Stable or Debouncing,1: Card Inserted"
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bitfld.long 0x30 5. "BUFFERREADREADY,This status is set if the Buffer Read Enable changes from 0 to 1. Buffer Read Ready is set to 1 for every CMD19 execution in tuning procedure." "0: Not Ready to read Buffer.,1: Ready to read Buffer."
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bitfld.long 0x30 4. "BUFFERWRITEREADY,This status is set if the Buffer Write Enable changes from 0 to 1." "0: Not Ready to Write Buffer.,1: Ready to Write Buffer."
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bitfld.long 0x30 3. "DMAINTERRUPT,This status is set if the HC detects the Host DMA Buffer Boundary in the Block Size regiser." "0: No DMA Interrupt,1: DMA Interrupt is Generated"
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bitfld.long 0x30 2. "BLOCKGAPEVENT,If the Stop At Block Gap Request in the Block Gap Control Register is set this bit is set. Read Transaction: This bit is set at the falling edge of the DAT Line Active Status (When the transaction is stopped at SD Bus timing. The Read Wait.." "0: No Block Gap Event,1: Transaction stopped at Block Gap"
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bitfld.long 0x30 1. "TRANSFERCOMPLETE,This bit is set when a read / write transaction is completed. Read Transaction: This bit is set at the falling edge of Read Transfer Active Status. There are two cases in which the Interrupt is generated. The first is when a data.." "0: No Data Transfer Complete,1: Data Transfer Complete"
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bitfld.long 0x30 0. "COMMANDCOMPLETE,This bit is set when we get the end bit of the command response (Except Auto CMD12 and Auto CMD23) Note: Command Time-out Error has higher priority than Command Complete. If both are set to 1 it can be considered that the response was.." "0: No Command Complete,1: Command Complete"
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line.long 0x34 "INTENABLE,Normal interrupt status enable"
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bitfld.long 0x34 29.--31. "VENDORSPECIFICERRORSTATUSENABLE,Vendor-specific error status enable." "0,1,2,3,4,5,6,7"
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bitfld.long 0x34 28. "TGTRESPERRHOSTERRSTATEN,Desc" "0,1"
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bitfld.long 0x34 26. "TUNINGERRORSTATUS,enable" "0,1"
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bitfld.long 0x34 25. "ADMAERRORSTATUSENABLE,Desc" "0,1"
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bitfld.long 0x34 24. "AUTOCMD12ERRORSTATUSENABLE,Desc" "0,1"
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bitfld.long 0x34 23. "CURRENTLIMITERRORSTATUSENABLE,Desc" "0,1"
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bitfld.long 0x34 22. "DATAENDBITERRORSTATUSENABLE,Desc" "0,1"
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bitfld.long 0x34 21. "DATACRCERRORSTATUSENABLE,Desc" "0,1"
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bitfld.long 0x34 20. "DATATIMEOUTERRORSTATUSENABLE,Desc" "0,1"
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bitfld.long 0x34 19. "COMMANDINDEXERRORSTATUSENABLE,Desc" "0,1"
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bitfld.long 0x34 18. "COMMANDENDBITERRORSTATUSENABLE,Desc" "0,1"
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bitfld.long 0x34 17. "COMMANDCRCERRORSTATUSENABLE,Desc" "0,1"
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bitfld.long 0x34 16. "COMMANDTIMEOUTERRORSTATUSENABLE,Desc" "0,1"
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bitfld.long 0x34 15. "FIXEDTO0,The HC shall control error Interrupts using the Error Interrupt Status Enable register." "0,1"
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bitfld.long 0x34 14. "BOOTTERMINATE,Boot is terminated?" "0,1"
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bitfld.long 0x34 13. "BOOTACKRCVENABLE,Interrupt" "0,1"
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bitfld.long 0x34 12. "RETUNINGEVENTSTATUSENABLE,Interrupt" "0,1"
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bitfld.long 0x34 11. "INTCSTATUSENABLE,If this bit is set to 0 the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_C and may set this bit again after all interrupt requests to INT_C pin are cleared.." "0,1"
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bitfld.long 0x34 10. "INTBSTATUSENABLE,If this bit is set to 0 the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_B and may set this bit again after all interrupt requests to INT_B pin are cleared.." "0,1"
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bitfld.long 0x34 9. "INTASTATUSENABLE,If this bit is set to 0 the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_A and may set this bit again after all interrupt requests to INT_A pin are cleared.." "0,1"
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bitfld.long 0x34 8. "CARDINTERRUPTSTATUSENABLE,If this bit is set to 0 the HC shall clear Interrupt request to the System. The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. The HD may clear the Card Interrupt Status.." "0,1"
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bitfld.long 0x34 7. "CARDREMOVALSTATUSENABLE,Description" "0,1"
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bitfld.long 0x34 6. "CARDINSERTIONSTATUSENABLE,Description" "0,1"
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bitfld.long 0x34 5. "BUFFERREADREADYSTATUSENABLE,Description" "0,1"
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bitfld.long 0x34 4. "BUFFERWRITEREADYSTATUSENABLE,Description" "0,1"
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bitfld.long 0x34 3. "DMAINTERRUPTSTATUSENABLE,Description" "0,1"
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bitfld.long 0x34 2. "BLOCKGAPEVENTSTATUSENABLE,Description" "0,1"
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bitfld.long 0x34 1. "TRANSFERCOMPLETESTATUSENABLE,Description" "0,1"
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bitfld.long 0x34 0. "COMMANDCOMPLETESTATUSENABLE,Description" "0,1"
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line.long 0x38 "INTSIG,Normal interrupt signal enable"
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bitfld.long 0x38 29.--31. "VNDERREN,VNDERREN field description needed here." "0,1,2,3,4,5,6,7"
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bitfld.long 0x38 28. "TGTRESPEN,Interrupt" "0: Masked,1: Enabled"
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bitfld.long 0x38 26. "TUNINGERREN,Desc" "0: Masked,1: Enabled"
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bitfld.long 0x38 25. "ADMAERREN,Desc" "0: Masked,1: Enabled"
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bitfld.long 0x38 24. "AUTOCMD12ERREN,Desc" "0: Masked,1: Enabled"
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bitfld.long 0x38 23. "CURRLMTERREN,Desc" "0: Masked,1: Enabled"
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bitfld.long 0x38 22. "DATAENDERREN,Desc" "0: Masked,1: Enabled"
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bitfld.long 0x38 21. "DATACRCERREN,Desc" "0: Masked,1: Enabled"
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bitfld.long 0x38 20. "DATATOERROREN,Desc" "0: Masked,1: Enabled"
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bitfld.long 0x38 19. "CMDIDXERREN,Desc" "0: Masked,1: Enabled"
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bitfld.long 0x38 18. "CMDENDBITERREN,Desc" "0: Masked,1: Enabled"
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bitfld.long 0x38 17. "CMDCRCERREN,Desc" "0: Masked,1: Enabled"
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bitfld.long 0x38 16. "CMDTOERREN,Desc" "0: Masked,1: Enabled"
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bitfld.long 0x38 15. "FIXED0,Fixed to 0. The HD shall control error Interrupts using the Error Interrupt Signal Enable register." "0: Masked,1: Enabled"
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bitfld.long 0x38 14. "BOOTTERM,Boot terminate interrupt signal enable" "0: Masked,1: Enabled"
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bitfld.long 0x38 13. "BOOTACKEN,Interrupt" "0: Masked,1: Enabled"
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bitfld.long 0x38 12. "RETUNEEVENTEN,Interrupt signal enable" "0: Masked,1: Enabled"
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bitfld.long 0x38 11. "INTCEN,Interrupt" "0: Masked,1: Enabled"
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bitfld.long 0x38 10. "INTBEN,Interrupt" "0: Masked,1: Enabled"
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bitfld.long 0x38 9. "INTAEN,Interrupt" "0: Masked,1: Enabled"
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bitfld.long 0x38 8. "CARDINTEN,Interrupt" "0: Masked,1: Enabled"
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bitfld.long 0x38 7. "CARDREMOVALEN,Interrupt" "0: Masked,1: Enabled"
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bitfld.long 0x38 6. "CARDINSERTEN,Interrupt" "0: Masked,1: Enabled"
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bitfld.long 0x38 5. "BUFFERRDEN,Interrupt" "0: Masked,1: Enabled"
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bitfld.long 0x38 4. "BUFFERWREN,Interrupt" "0: Masked,1: Enabled"
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bitfld.long 0x38 3. "DMAINTEN,Interrupt" "0: Masked,1: Enabled"
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bitfld.long 0x38 2. "BLOCKGAPEN,Interrupt" "0: Masked,1: Enabled"
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bitfld.long 0x38 1. "XFERCMPEN,Interrupt" "0: Masked,1: Enabled"
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bitfld.long 0x38 0. "CMDCMPEN,Interrupt" "0: Masked,1: Enabled"
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line.long 0x3C "AUTO,Auto CMD error status"
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bitfld.long 0x3C 31. "PRESETEN,Host Controller Version 3.00 supports this bit. As the operating SDCLK frequency and I/O driver strength depend on the Host System implementation it is difficult to determine these parameters in the Standard Host Driver. When Preset Value.." "0: SDCLK and Driver Strength are controlled by Host..,1: Automatic Selection by Preset Value are Enabled"
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bitfld.long 0x3C 30. "ASYNCINTEN,This bit can be set to 1 if a card support asynchronous interrupt and Asynchronous Interrupt Support is set to 1 in the Capabilities register. Asynchronous interrupt is effective when DAT[1] interrupt is used in 4-bit SD mode (and zero is set.." "0: Disabled,1: Enabled"
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bitfld.long 0x3C 23. "SAMPLCLKSEL,This bit is set by tuning procedure when Execute Tuning is cleared. Writing 1 to this bit is meaningless and ignored. Setting 1 means that tuning is completed successfully and setting 0 means that tuning is failed. Host Controller uses this.." "0: Fixed clock is used to sample data,1: Tuned clock is used to sample data"
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bitfld.long 0x3C 22. "STARTTUNING,This bit is set to 1 to start tuning procedure and automatically cleared when tuning procedure is completed. The result of tuning is indicated to Sampling Clock Select. Tuning procedure is aborted by writing 0 for more detail about tuning.." "0: Not Tuned or Tuning Completed,1: Execute Tuning"
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bitfld.long 0x3C 20.--21. "DRVRSTRSEL,Host Controller output driver in 1.8V signaling is selected by this bit. In 3.3V signaling this field is not effective. This field can be set depends on Driver Type A C and D support bits in the Capabilities register. This bit depends on.." "0: Driver Type B is Selected (Default),1: Driver Type A is Selected,2: Driver Type C is Selected,3: Driver Type D is Selected"
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bitfld.long 0x3C 19. "SIGNALVOLT,This bit controls voltage regulator for I/O cell. 3.3V is supplied to the card regardless of signaling voltage. Setting this bit from 0 to 1 starts changing signal voltage from 3.3V to 1.8V. 1.8V regulator output shall be stable within 5ms." "0: 3.3V Signaling,1: SDR50"
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bitfld.long 0x3C 16.--18. "UHSMODESEL,This field is used to select one of UHS-I modes and effective when 1.8V Signaling Enable is set to 1. If Preset Value Enable in the Host Control 2 register is set to 1 Host Controller sets SDCLK Frequency Select Clock Generator Select in the.." "0: UHS-I mode SDR12,1: UHS-I mode SDR25,2: UHS-I mode SDR50,3: UHS-I mode SDR104,4: UHS-I mode DDR50,?,?,?"
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bitfld.long 0x3C 7. "NOTAUTOCMD12ERR,Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 error (D04 - D01) in this register. This bit is set to 0 when Auto CMD Error is generated by Auto CMD23" "0: No Error,1: Not Issued"
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bitfld.long 0x3C 4. "CMDIDXERR,Occurs if the Command Index error occurs in response to a command." "0: No Error,1: Error"
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bitfld.long 0x3C 3. "CMDENDERR,Occurs when detecting that the end bit of command response is 0." "0: No Error,1: End Bit Error Generated"
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bitfld.long 0x3C 2. "CMDCRCERR,Occurs when detecting a CRC error in the command response." "0: No Error,1: CRC Error Generated"
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bitfld.long 0x3C 1. "CMDTOERR,Occurs if the no response is returned within 64 SDCLK cycles from the end bit of the command. If this bit is set to 1 the other error status bits (D04 - D02) are meaningless." "0: No Error,1: Timeout"
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bitfld.long 0x3C 0. "CMD12NOTEXEC,If memory multiple block data transfer is not started due to command error this bit is not set because it is not necessary to issue Auto CMD12. Setting this bit to 1 means the HC cannot issue Auto CMD12 to stop memory multiple block.." "0: Executed,1: Not Executed"
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line.long 0x40 "CAPABILITIES0,Capabilities"
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bitfld.long 0x40 30.--31. "SLOTTYPE,This field indicates usage of a slot by a specific Host System. (A host controller register set is defined per slot.) Embedded slot for one device (01b) means that only one non-removable device is connected to a SD bus slot. Shared Bus Slot.." "0: Removable card slot,1: Embedded Slot for One Device,2: Shared Bus Slot,?"
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bitfld.long 0x40 29. "ASYNCINT,Refer to SDIO Specification Version 3.00 about asynchronous interrupt." "0: Asynchronous Interrupt Not Supported,1: Asynchronous Interrupt Supported"
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bitfld.long 0x40 28. "SYSBUS64,Desc" "0: Does not support 64 bit system address,1: Supports 64 bit system address"
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bitfld.long 0x40 26. "VOLT18V,Voltage support 1.8v" "0: 1.8 V Not Supported,1: 1.8 V Supported"
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bitfld.long 0x40 25. "VOLT30V,Voltage support 3.0v" "0: 3.0 V Not Supported,1: 3.0 V Supported"
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bitfld.long 0x40 24. "VOLT33V,Desc" "0: 3.3 V Not Supported,1: 3.3 V Supported"
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bitfld.long 0x40 23. "SUSPRES,This bit indicates whether the HC supports Suspend / Resume functionality. If this bit is 0 the Suspend and Resume mechanism are not supported and the HD shall not issue either Suspend / Resume commands." "0: Suspend / Resume Not Supported,1: Suspend / Resume Supported"
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bitfld.long 0x40 22. "SDMA,This bit indicates whether the HC is capable of using DMA to transfer data between system memory and the HC directly." "0: SDMA Not Supported,1: SDMA Supported."
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bitfld.long 0x40 21. "HIGHSPEED,This bit indicates whether the HC and the Host System support High Speed mode and they can supply SD Clock frequency from 25Mhz to 50 Mhz (for SD)/ 20MHz to 52MHz (for MMC)." "0: High Speed Not Supported,1: High Speed Supported"
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bitfld.long 0x40 19. "ADMA2,Desc" "0: ADMA2 not support,1: ADMA2 support."
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bitfld.long 0x40 18. "EXTMEDIA,This bit indicates whether the Host Controller is capable of using 8-bit bus width mode. This bit is not effective when Slot Type is set to 10b. In this case refer to Bus Width Preset in the Shared Bus resister. Supported" "0: Extended Media Bus not supported,1: Extended Media Bus Supported"
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bitfld.long 0x40 16.--17. "MAXBLKLEN,This value indicates the maximum block size that the HD can read and write to the buffer in the HC. The buffer shall transfer this block size without wait cycles. Three sizes can be defined as indicated below." "0: 512 byte,1: 1024 byte,2: 2048 byte,3: 4096 byte"
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hexmask.long.byte 0x40 8.--15. 1. "SDCLKFREQ,6-bit Base Clock Frequency This mode is supported by the Host Controller Version 1.00 and 2.00. Upper 2-bit is not effective and always 0. Unit values are 1MHz. The supported clock range is 10MHz to 63MHz. 11xx xxxxb Not supported 0011 1111b.."
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bitfld.long 0x40 7. "TOCLKUNIT,This bit shows the unit of base clock frequency used to detect Data Timeout Error." "0: Khz,1: Mhz"
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hexmask.long.byte 0x40 0.--5. 1. "TOCLKFREQ,This bit shows the base clock frequency used to detect Data Timeout Error. Not 0 - 1Khz to 63Khz or 1Mhz to 63Mhz Note: The Host System shall support at least one of these voltages above. The HD sets the SD Bus Voltage Select in Power Control.."
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line.long 0x44 "CAPABILITIES1,Capabilities"
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bitfld.long 0x44 25. "SPIBLOCKMODE,Spi block mode" "0: Not Supported,1: Supported"
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bitfld.long 0x44 24. "SPIMODE,Spi mode" "0: Not Supported,1: Supported"
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hexmask.long.byte 0x44 16.--23. 1. "CLKMULT,This field indicates clock multiplier value of programmable clock generator. Refer to Clock Control register. Setting 00h means that Host Controller does not support programmable clock generator. The multiplier is (CLKMULT+1)."
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bitfld.long 0x44 14.--15. "RETUNINGMODES,This field defines the re-tuning capability of a Host Controller and how to manage the data transfer length and a Re-Tuning Timer by the Host Driver There are two re-tuning timings: Re-Tuning Request and expiration of a Re-Tuning Timer. By.." "0: Mode1,1: Mode2,2: Mode3,3: Clock Multiplier is not supported."
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bitfld.long 0x44 13. "TUNINGSDR50,If this bit is set to 1 this Host Controller requires tuning to operate SDR50. (Tuning is always required to operate SDR104.)" "0: SDR50 does not require tuning,1: SDR50 requires tuning"
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hexmask.long.byte 0x44 8.--11. 1. "RETUNINGTMRCNT,This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3. 0h - Get information via other source."
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bitfld.long 0x44 6. "TYPED,Reserved This bit indicates support of Driver Type D for 1.8 Signaling." "0: Driver Type D is Not Supported,1: Driver Type D is Supported"
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bitfld.long 0x44 5. "TYPEC,This bit indicates support of Driver Type C for 1.8 Signaling." "0: Driver Type C is Not Supported,1: Driver Type C is Supported"
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bitfld.long 0x44 4. "TYPEA,This bit indicates support of Driver Type A for 1.8 Signaling." "0: Driver Type A is Not Supported,1: Driver Type A is Supported"
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bitfld.long 0x44 2. "DDR50,DDR50 field description needed here." "0: DDR50 is Not Supported,1: DDR50 is Supported"
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bitfld.long 0x44 1. "SDR104,1- SDR104 is Supported" "0: SDR104 is Not Supported,1: SDR104 is Supported"
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bitfld.long 0x44 0. "SDR50,1- SDR50 is Supported" "0: SDR50 is Not Supported,1: SDR50 is Supported"
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line.long 0x48 "MAXIMUM0,Maximum current capabilities"
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hexmask.long 0x48 0.--31. 1. "ALLBITSRSVD,The entire 32-bits of this register are reserved do not read or write."
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line.long 0x4C "MAXIMUM1,Maximum current capabilities"
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hexmask.long.byte 0x4C 16.--23. 1. "MAXCURR18V,Maximum Current for 1.8V. The current value is specified as MAXCURR18V * 4mA. Some example enums follow:"
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hexmask.long.byte 0x4C 8.--15. 1. "MAXCURR30V,Maximum Current for 3.0V. The current value is specified as MAXCURR18V * 4mA. Some example enums follow:"
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hexmask.long.byte 0x4C 0.--7. 1. "MAXCURR33V,Maximum Current for 3.3V. The current value is specified as MAXCURR18V * 4mA. Some example enums follow:"
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line.long 0x50 "FORCE,Force event register for error interrupt status"
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bitfld.long 0x50 25. "FORCEADMAERR,Force event for ADMA error" "0: No interrupt,1: Interrupt is generated"
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bitfld.long 0x50 24. "FORCEACMDERR,Force Event for Auto CMD Error" "0: No interrupt,1: Interrupt is generated"
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bitfld.long 0x50 23. "FORCECURRLIMITERR,Force Event for Current Limit Error" "0: No interrupt,1: Interrupt is generated"
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bitfld.long 0x50 22. "FORCEDATAENDERR,Force Event for Data End Bit Error" "0: No interrupt,1: Interrupt is generated"
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bitfld.long 0x50 21. "FORCEDATACRCERR,Force Event for Data CRC Error" "0: No interrupt,1: Interrupt is generated"
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bitfld.long 0x50 20. "FORCEDATATOERR,Force Event for Data Timeout Error" "0: No interrupt,1: Interrupt is generated"
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bitfld.long 0x50 19. "FORCECMDIDXERR,Force Event for Command Index Error" "0: No interrupt,1: Interrupt is generated"
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bitfld.long 0x50 18. "FORCECMDENDERR,Force Event for Command End Bit Error" "0: No interrupt,1: Interrupt is generated"
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bitfld.long 0x50 17. "FORCECMDCRCERR,Force Event for Command CRC Error" "0: No interrupt,1: Interrupt is generated"
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bitfld.long 0x50 16. "FORCECMDTOERR,Force Event for Command Timeout Error" "0: No interrupt,1: Interrupt is generated"
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bitfld.long 0x50 7. "FORCEACMDISSUEDERR,1 - Interrupt is generated" "0: no interrupt,1: Interrupt is generated"
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bitfld.long 0x50 4. "FORCEACMDIDXERR,Desc" "0: no interrupt,1: Interrupt is generated"
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bitfld.long 0x50 3. "FORCEACMDENDERR,Description" "0: no interrupt,1: Interrupt is generated"
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bitfld.long 0x50 2. "FORCEACMDCRCERR,Description" "0: no interrupt,1: Interrupt is generated"
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bitfld.long 0x50 1. "FORCEACMDTOERR,Description" "0: no interrupt,1: Interrupt is generated"
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bitfld.long 0x50 0. "FORCEACMD12NOT,Description" "0: no interrupt,1: Interrupt is generated"
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line.long 0x54 "ADMA,ADMA error status"
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bitfld.long 0x54 2. "ADMALENMISMATCHERR,This error occurs in the following 2 cases. While Block Count Enable being set the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length. Total data length can not be.." "0: No error,1: Error"
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bitfld.long 0x54 0.--1. "ADMAERRORSTATE,This field indicates the state of ADMA when error is occurred during ADMA data transfer. This field never indicates 10 because ADMA never stops in this state. D01 - D00 : ADMA Error State when error occurred Contents of SYS_SDR register" "0: ST_STOP (Stop DMA) Points to next of the error..,1: D00 : ADMA Error State when error occurred..,2: Never set this state (Not used),3: ST_TFR (Transfer Data) Points to the next of the.."
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line.long 0x58 "ADMALOWD,ADMA system address [31:0]"
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hexmask.long 0x58 0.--31. 1. "LOWD,This register holds byte address of executing command of the Descriptor table. 32-bit Address Descriptor uses lower 32bit of this register. At the start of ADMA the Host Driver shall set start address of the Descriptor table. The ADMA increments.."
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line.long 0x5C "ADMAHIWD,ADMA system address [63:0]"
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hexmask.long 0x5C 0.--31. 1. "HIWD,This register holds byte address of executing command of the Descriptor table. 32-bit Address Descriptor uses lower 32bit of this register. At the start of ADMA the Host Driver shall set start address of the Descriptor table. The ADMA increments.."
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line.long 0x60 "PRESET0,Preset Value initialization and default speed"
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bitfld.long 0x60 30.--31. "DEFSPDRVRSTRSEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0: Driver Type B is Selected,1: Driver Type A is Selected,2: Driver Type C is Selected,3: Driver Type D is Selected"
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bitfld.long 0x60 26. "DEFSPCLKGENSEL,This bit is effective when Host Controller supports programmable clock generator." "0: Host Controller Ver2.00 Compatible Clock Generator,1: Programmable Clock Generator"
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hexmask.long.word 0x60 16.--25. 1. "DEFSPSDCLKFREQSEL,10 bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system. When Host Controller supports shared bus a set of Preset Value registers for each device required and the registers location.."
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bitfld.long 0x60 14.--15. "HISPDRVRSTRSEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0: Driver Type B is Selected,1: Driver Type A is Selected,2: Driver Type C is Selected,3: Driver Type D is Selected"
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bitfld.long 0x60 10. "HISPCLKGENSEL,This bit is effective when Host Controller supports programmable clock generator." "0: Host Controller Ver2.00 Compatible Clock Generator,1: Programmable Clock Generator"
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hexmask.long.word 0x60 0.--9. 1. "HISPSDCLKFREQSEL,10 bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system. When Host Controller supports shared bus a set of Preset Value registers for each device required and the registers location.."
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line.long 0x64 "PRESET1,Preset Value for high speed and SDR12"
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bitfld.long 0x64 30.--31. "SDR12DRVRSTRSEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0: Driver Type B is Selected,1: Driver Type A is Selected,2: Driver Type C is Selected,3: Driver Type D is Selected"
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bitfld.long 0x64 26. "SDR12CLKGENSEL,This bit is effective when Host Controller supports programmable clock generator." "0: Host Controller Ver2.00 Compatible Clock Generator,1: Programmable Clock Generator"
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hexmask.long.word 0x64 16.--25. 1. "SDR12SDCLKFREQSEL,10 bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system. When Host Controller supports shared bus a set of Preset Value registers for each device required and the registers location.."
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bitfld.long 0x64 14.--15. "HSDRVRSTRSEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0: Driver Type B is Selected,1: Driver Type A is Selected,2: Driver Type C is Selected,3: Driver Type D is Selected"
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bitfld.long 0x64 10. "HSCLKGENSEL,This bit is effective when Host Controller supports programmable clock generator." "0: Host Controller Ver2.00 Compatible Clock Generator,1: Programmable Clock Generator"
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hexmask.long.word 0x64 0.--9. 1. "HSSDCLKFREQSEL,10 bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system. When Host Controller supports shared bus a set of Preset Value registers for each device required and the registers location.."
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line.long 0x68 "PRESET2,Preset Value for SDR25 and SDR50"
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bitfld.long 0x68 30.--31. "SDR50DRVRSTRSEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0: Driver Type B is Selected,1: Driver Type A is Selected,2: Driver Type C is Selected,3: Driver Type D is Selected"
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bitfld.long 0x68 26. "SDR50CLKGENSEL,This bit is effective when Host Controller supports programmable clock generator." "0: Host Controller Ver2.00 Compatible Clock Generator,1: Programmable Clock Generator"
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hexmask.long.word 0x68 16.--25. 1. "SDR50SDCLKFREQSEL,10 bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system. When Host Controller supports shared bus a set of Preset Value registers for each device required and the registers location.."
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bitfld.long 0x68 14.--15. "SDR25DRVRSTRSEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0: Driver Type B is Selected,1: Driver Type A is Selected,2: Driver Type C is Selected,3: Driver Type D is Selected"
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bitfld.long 0x68 10. "SDR25CLKGENSEL,This bit is effective when Host Controller supports programmable clock generator." "0: Host Controller Ver2.00 Compatible Clock Generator,1: Programmable Clock Generator"
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hexmask.long.word 0x68 0.--9. 1. "SDR25SDCLKFREQSEL,10 bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system. When Host Controller supports shared bus a set of Preset Value registers for each device required and the registers location.."
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line.long 0x6C "PRESET3,Preset Value for SDR104 and DDR50"
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bitfld.long 0x6C 30.--31. "DDR50DRVRSTRSEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0: Driver Type B is Selected,1: Driver Type A is Selected,2: Driver Type C is Selected,3: Driver Type D is Selected"
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bitfld.long 0x6C 26. "DDR50CLKGENSEL,This bit is effective when Host Controller supports programmable clock generator." "0: Host Controller Ver2.00 Compatible Clock Generator,1: Programmable Clock Generator"
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hexmask.long.word 0x6C 16.--25. 1. "DDR50SDCLKFREQSEL,10 bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system. When Host Controller supports shared bus a set of Preset Value registers for each device required and the registers location.."
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bitfld.long 0x6C 14.--15. "SDR104DRVRSTRSEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0: Driver Type B is Selected,1: Driver Type A is Selected,2: Driver Type C is Selected,3: Driver Type D is Selected"
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bitfld.long 0x6C 10. "SDR104CLKGENSEL,This bit is effective when Host Controller supports programmable clock generator." "0: Host Controller Ver2.00 Compatible Clock Generator,1: Programmable Clock Generator"
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hexmask.long.word 0x6C 0.--9. 1. "SDR104SDCLKFREQSEL,10 bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system. When Host Controller supports shared bus a set of Preset Value registers for each device required and the registers.."
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line.long 0x70 "BOOTTOCTRL,Boot Data Timeout control"
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hexmask.long 0x70 0.--31. 1. "BOOTDATATO,This value determines the interval by which DAT line time-outs are detected during boot operation for eMMC card. The value is in number of sd clock."
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group.long 0x78++0x3
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line.long 0x0 "VENDOR,Vendor"
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bitfld.long 0x0 1. "DLYDIS,Enable/disable the hardware delay added to the sampling of cmd_in and data_in." "0: Enable the hardware delay for sampling of cmd_in..,1: Disable the hardware delay for sampling of.."
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bitfld.long 0x0 0. "GATESDCLKEN,If this bit is 0 SD_CLK to card will not be gated automatically when there is no transfer. If this bit set to 1 SD_CLK to card will be gated automatically when there is no transfer." "0: SD_CLK to card will NOT be gated automatically..,1: SD_CLK to card will be gated automatically when.."
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group.long 0xFC++0x3
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line.long 0x0 "SLOTSTAT,Slot interrupt status"
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hexmask.long.byte 0x0 24.--31. 1. "VENDORVER,The Vendor Version Number is set to 0x10 (1.0)"
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hexmask.long.byte 0x0 16.--23. 1. "SPECVER,The Host Controller Version Number is set to 0x02 (SD Host Specification Version 3.00)."
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|
|
bitfld.long 0x0 0. "INTSLOT0,This status bit indicates the OR of Interrupt signal and Wakeup signal for slot" "0,1"
|
|
tree.end
|
|
tree "SECURITY (Security Interfaces)"
|
|
base ad:0x40030000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Control"
|
|
bitfld.long 0x0 31. "CRCERROR,CRC Error Status - Set to 1 if an error occurs during a CRC operation. Cleared when CTRL register is written (with any value). Usually indicates an invalid address range." "0,1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "FUNCTION,Function Select"
|
|
bitfld.long 0x0 0. "ENABLE,Function Enable. Software should set the ENABLE bit to initiate a CRC operation. Hardware will clear the ENABLE bit upon completion." "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "SRCADDR,Source Addresss"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Source Buffer Address. Address may be byte aligned but the length must be a multiple of 4 bits."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "LEN,Length"
|
|
hexmask.long.tbyte 0x0 2.--23. 1. "LEN,Buffer size (bottom two bits assumed to be zero to ensure a multiple of 4 bytes)"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "RESULT,CRC Seed/Result"
|
|
hexmask.long 0x0 0.--31. 1. "CRC,CRC Seed/Result. Software must seed the CRC with 0xFFFFFFFF before starting a CRC operation (unless the CRC is continued from a previous operation)."
|
|
group.long 0x78++0x17
|
|
line.long 0x0 "LOCKCTRL,LOCK Control"
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x0 0.--7. 1. "SELECT,LOCK Function Select register."
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 0.--7. 1. "SELECT,LOCK Function Select register."
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 0.--7. 1. "SELECT,LOCK Function Select register."
|
|
endif
|
|
line.long 0x4 "LOCKSTAT,LOCK Status"
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long 0x4 0.--31. 1. "STATUS,LOCK Status register. This register is a bitmask for which resources are currently unlocked. These bits are one-hot per resource."
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long 0x4 0.--31. 1. "STATUS,Lock status. Bit is high to signify it is enabled. 0: LOCK01 1: LOCK02 4: LOCK11 5: LOCK12 30: LOCK9D 31: LOCK9E"
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long 0x4 0.--31. 1. "STATUS,Lock status. Bit is high to signify it is enabled. 0: LOCK01 1: LOCK02 4: LOCK11 5: LOCK12 30: LOCK9D 31: LOCK9E"
|
|
endif
|
|
line.long 0x8 "KEY0,Key0"
|
|
hexmask.long 0x8 0.--31. 1. "KEY0,Bits [31:0] of the 128-bit key should be written to this register. To protect key values the register always returns 0x00000000."
|
|
line.long 0xC "KEY1,Key1"
|
|
hexmask.long 0xC 0.--31. 1. "KEY1,Bits [63:32] of the 128-bit key should be written to this register. To protect key values the register always returns 0x00000000."
|
|
line.long 0x10 "KEY2,Key2"
|
|
hexmask.long 0x10 0.--31. 1. "KEY2,Bits [95:64] of the 128-bit key should be written to this register. To protect key values the register always returns 0x00000000."
|
|
line.long 0x14 "KEY3,Key3"
|
|
hexmask.long 0x14 0.--31. 1. "KEY3,Bits [127:96] of the 128-bit key should be written to this register. To protect key values the register always returns 0x00000000."
|
|
tree.end
|
|
tree "STIMER (System Timer)"
|
|
base ad:0x40008800
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "STCFG,The STIMER Configuration Register contains the software control for selecting the clock divider and source feeding the system timer."
|
|
bitfld.long 0x0 31. "FREEZE,Set this bit to one to freeze the clock input to the COUNTER register. Once frozen the value can be safely written from the MCU. Unfreeze to resume." "0: Let the COUNTER register run on its input clock.,1: Stop the COUNTER register for loading."
|
|
bitfld.long 0x0 30. "CLEAR,Set this bit to one to clear the System Timer register. If this bit is set to '1' the system timer register will stay cleared. It needs to be set to '0' for the system timer to start running." "0: Let the COUNTER register run on its input clock.,1: Stop the COUNTER register for loading."
|
|
newline
|
|
bitfld.long 0x0 15. "COMPAREHEN,Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled the interrupt status is set once the comparision is met." "0: Compare H disabled.,1: Compare H enabled."
|
|
bitfld.long 0x0 14. "COMPAREGEN,Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled the interrupt status is set once the comparision is met." "0: Compare G disabled.,1: Compare G enabled."
|
|
newline
|
|
bitfld.long 0x0 13. "COMPAREFEN,Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled the interrupt status is set once the comparision is met." "0: Compare F disabled.,1: Compare F enabled."
|
|
bitfld.long 0x0 12. "COMPAREEEN,Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled the interrupt status is set once the comparision is met." "0: Compare E disabled.,1: Compare E enabled."
|
|
newline
|
|
bitfld.long 0x0 11. "COMPAREDEN,Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled the interrupt status is set once the comparision is met." "0: Compare D disabled.,1: Compare D enabled."
|
|
bitfld.long 0x0 10. "COMPARECEN,Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled the interrupt status is set once the comparision is met." "0: Compare C disabled.,1: Compare C enabled."
|
|
newline
|
|
bitfld.long 0x0 9. "COMPAREBEN,Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled the interrupt status is set once the comparision is met." "0: Compare B disabled.,1: Compare B enabled."
|
|
bitfld.long 0x0 8. "COMPAREAEN,Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled the interrupt status is set once the comparision is met." "0: Compare A disabled.,1: Compare A enabled."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "CLKSEL,Selects an appropriate clock source and divider to use for the System Timer clock."
|
|
line.long 0x4 "STTMR,The COUNTER Register contains the running count of time as maintained by incrementing for every rising clock edge of the clock source selected in the configuration register. It is this counter value that captured in the capture registers and it is.."
|
|
hexmask.long 0x4 0.--31. 1. "STTMR,Value of the 32-bit counter as it ticks over."
|
|
group.long 0x10++0x4B
|
|
line.long 0x0 "SCAPCTRL0,The STIMER Capture Control Register controls each of the 4 capture registers. It selects their GPIO pin number for a trigger source. enables a capture operation and sets the input polarity for the capture. NOTE: 8-bit writes can control.."
|
|
bitfld.long 0x0 9. "CAPTURE0,Selects whether capture 0 is enabled for the specified capture register." "0: Capture function disabled.,1: Capture function enabled."
|
|
bitfld.long 0x0 8. "STPOL0,STIMER Capture 0 Polarity." "0: Capture on low to high GPIO transition,1: Capture on high to low GPIO transition"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "STSEL0,STIMER Capture 0 Select."
|
|
line.long 0x4 "SCAPCTRL1,The STIMER Capture Control Register controls each of the 4 capture registers. It selects their GPIO pin number for a trigger source. enables a capture operation and sets the input polarity for the capture. NOTE: 8-bit writes can control.."
|
|
bitfld.long 0x4 9. "CAPTURE1,Selects whether capture 1 is enabled for the specified capture register." "0: Capture function disabled.,1: Capture function enabled."
|
|
bitfld.long 0x4 8. "STPOL1,STIMER Capture 1 Polarity." "0: Capture on low to high GPIO transition,1: Capture on high to low GPIO transition"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "STSEL1,STIMER Capture 1 Select."
|
|
line.long 0x8 "SCAPCTRL2,The STIMER Capture Control Register controls each of the 4 capture registers. It selects their GPIO pin number for a trigger source. enables a capture operation and sets the input polarity for the capture. NOTE: 8-bit writes can control.."
|
|
bitfld.long 0x8 9. "CAPTURE2,Selects whether capture 2 is enabled for the specified capture register." "0: Capture function disabled.,1: Capture function enabled."
|
|
bitfld.long 0x8 8. "STPOL2,STIMER Capture 2 Polarity." "0: Capture on low to high GPIO transition,1: Capture on high to low GPIO transition"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--6. 1. "STSEL2,STIMER Capture 2 Select."
|
|
line.long 0xC "SCAPCTRL3,The STIMER Capture Control Register controls each of the 4 capture registers. It selects their GPIO pin number for a trigger source. enables a capture operation and sets the input polarity for the capture. NOTE: 8-bit writes can control.."
|
|
bitfld.long 0xC 9. "CAPTURE3,Selects whether capture 3 is enabled for the specified capture register." "0: Capture function disabled.,1: Capture function enabled."
|
|
bitfld.long 0xC 8. "STPOL3,STIMER Capture 3 Polarity." "0: Capture on low to high GPIO transition,1: Capture on high to low GPIO transition"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--6. 1. "STSEL3,STIMER Capture 3 Select."
|
|
line.long 0x10 "SCMPR0,The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal.."
|
|
hexmask.long 0x10 0.--31. 1. "SCMPR0,Compare this value to the value in the COUNTER register according to the match criterion as selected in the COMPARE_A_EN bit in the REG_CTIMER_STCFG register."
|
|
line.long 0x14 "SCMPR1,The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal.."
|
|
hexmask.long 0x14 0.--31. 1. "SCMPR1,Compare this value to the value in the COUNTER register according to the match criterion as selected in the COMPARE_A_EN bit in the REG_CTIMER_STCFG register."
|
|
line.long 0x18 "SCMPR2,The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal.."
|
|
hexmask.long 0x18 0.--31. 1. "SCMPR2,Compare this value to the value in the COUNTER register according to the match criterion as selected in the COMPARE_A_EN bit in the REG_CTIMER_STCFG register."
|
|
line.long 0x1C "SCMPR3,The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal.."
|
|
hexmask.long 0x1C 0.--31. 1. "SCMPR3,Compare this value to the value in the COUNTER register according to the match criterion as selected in the COMPARE_A_EN bit in the REG_CTIMER_STCFG register."
|
|
line.long 0x20 "SCMPR4,The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal.."
|
|
hexmask.long 0x20 0.--31. 1. "SCMPR4,Compare this value to the value in the COUNTER register according to the match criterion as selected in the COMPARE_A_EN bit in the REG_CTIMER_STCFG register."
|
|
line.long 0x24 "SCMPR5,The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal.."
|
|
hexmask.long 0x24 0.--31. 1. "SCMPR5,Compare this value to the value in the COUNTER register according to the match criterion as selected in the COMPARE_A_EN bit in the REG_CTIMER_STCFG register."
|
|
line.long 0x28 "SCMPR6,The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal.."
|
|
hexmask.long 0x28 0.--31. 1. "SCMPR6,Compare this value to the value in the COUNTER register according to the match criterion as selected in the COMPARE_A_EN bit in the REG_CTIMER_STCFG register."
|
|
line.long 0x2C "SCMPR7,The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal.."
|
|
hexmask.long 0x2C 0.--31. 1. "SCMPR7,Compare this value to the value in the COUNTER register according to the match criterion as selected in the COMPARE_A_EN bit in the REG_CTIMER_STCFG register."
|
|
line.long 0x30 "SCAPT0,The STIMER capture Register 0 captures the VALUE in the COUNTER register whenever capture condition (event) occurs. This register holds a time stamp for the event."
|
|
hexmask.long 0x30 0.--31. 1. "SCAPT0,Whenever the event is detected the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set."
|
|
line.long 0x34 "SCAPT1,The STIMER capture Register 1 captures the VALUE in the COUNTER register whenever capture condition (event) occurs. This register holds a time stamp for the event."
|
|
hexmask.long 0x34 0.--31. 1. "SCAPT1,Whenever the event is detected the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set."
|
|
line.long 0x38 "SCAPT2,The STIMER capture Register 2 captures the VALUE in the COUNTER register whenever capture condition (event) occurs. This register holds a time stamp for the event."
|
|
hexmask.long 0x38 0.--31. 1. "SCAPT2,Whenever the event is detected the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set."
|
|
line.long 0x3C "SCAPT3,The STIMER capture Register 3 captures the VALUE in the COUNTER register whenever capture condition (event) occurs. This register holds a time stamp for the event."
|
|
hexmask.long 0x3C 0.--31. 1. "SCAPT3,Whenever the event is detected the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set."
|
|
line.long 0x40 "SNVR0,The SNVR0 Register contains a portion of the stored epoch offset associated with the time in the COUNTER register. This register is only reset by POI not by HRESETn. Its contents are intended to survive all reset level except POI and full power.."
|
|
hexmask.long 0x40 0.--31. 1. "SNVR0,Value of the 32-bit counter as it ticks over."
|
|
line.long 0x44 "SNVR1,The SNVR1 Register contains a portion of the stored epoch offset associated with the time in the COUNTER register. This register is only reset by POI not by HRESETn. Its contents are intended to survive all reset level except POI and full power.."
|
|
hexmask.long 0x44 0.--31. 1. "SNVR1,Value of the 32-bit counter as it ticks over."
|
|
line.long 0x48 "SNVR2,The SNVR2 Register contains a portion of the stored epoch offset associated with the time in the COUNTER register. This register is only reset by POI not by HRESETn. Its contents are intended to survive all reset level except POI and full power.."
|
|
hexmask.long 0x48 0.--31. 1. "SNVR2,Value of the 32-bit counter as it ticks over."
|
|
group.long 0x100++0xF
|
|
line.long 0x0 "STMINTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
bitfld.long 0x0 12. "CAPTURED,CAPTURE register D has grabbed the value in the counter" "?,1: Capture D interrupt status bit was set."
|
|
bitfld.long 0x0 11. "CAPTUREC,CAPTURE register C has grabbed the value in the counter" "?,1: CAPTURE C interrupt status bit was set."
|
|
newline
|
|
bitfld.long 0x0 10. "CAPTUREB,CAPTURE register B has grabbed the value in the counter" "?,1: CAPTURE B interrupt status bit was set."
|
|
bitfld.long 0x0 9. "CAPTUREA,CAPTURE register A has grabbed the value in the counter" "?,1: CAPTURE A interrupt status bit was set."
|
|
newline
|
|
bitfld.long 0x0 8. "OVERFLOW,COUNTER over flowed from 0xFFFFFFFF back to 0x00000000." "?,1: Overflow interrupt status bit was set."
|
|
bitfld.long 0x0 7. "COMPAREH,COUNTER is greater than or equal to COMPARE register H." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
bitfld.long 0x0 6. "COMPAREG,COUNTER is greater than or equal to COMPARE register G." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
bitfld.long 0x0 5. "COMPAREF,COUNTER is greater than or equal to COMPARE register F." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
bitfld.long 0x0 4. "COMPAREE,COUNTER is greater than or equal to COMPARE register E." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
bitfld.long 0x0 3. "COMPARED,COUNTER is greater than or equal to COMPARE register D." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
bitfld.long 0x0 2. "COMPAREC,COUNTER is greater than or equal to COMPARE register C." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
bitfld.long 0x0 1. "COMPAREB,COUNTER is greater than or equal to COMPARE register B." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
bitfld.long 0x0 0. "COMPAREA,COUNTER is greater than or equal to COMPARE register A." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 12. "CAPTURED,CAPTURE register D has grabbed the value in the counter" "0: Capture D interrupt status default/not set.,1: Capture D interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 11. "CAPTUREC,CAPTURE register C has grabbed the value in the counter" "0: CAPTURE C interrupt status default/not set.,1: CAPTURE C interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 11. "CAPTUREC,CAPTURE register C has grabbed the value in the counter" "0: CAPTURE C interrupt status default/not set.,1: CAPTURE C interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 10. "CAPTUREB,CAPTURE register B has grabbed the value in the counter" "0: CAPTURE B interrupt status default/not set.,1: CAPTURE B interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 10. "CAPTUREB,CAPTURE register B has grabbed the value in the counter" "0: CAPTURE B interrupt status default/not set.,1: CAPTURE B interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 9. "CAPTUREA,CAPTURE register A has grabbed the value in the counter" "0: CAPTURE A interrupt status default/not set.,1: CAPTURE A interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 9. "CAPTUREA,CAPTURE register A has grabbed the value in the counter" "0: CAPTURE A interrupt status default/not set.,1: CAPTURE A interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 8. "OVERFLOW,COUNTER over flowed from 0xFFFFFFFF back to 0x00000000." "0: Overflow interrupt status bit default/not set.,1: Overflow interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 8. "OVERFLOW,COUNTER over flowed from 0xFFFFFFFF back to 0x00000000." "0: Overflow interrupt status bit default/not set.,1: Overflow interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 7. "COMPAREH,COUNTER is greater than or equal to COMPARE register H." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 7. "COMPAREH,COUNTER is greater than or equal to COMPARE register H." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 6. "COMPAREG,COUNTER is greater than or equal to COMPARE register G." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 6. "COMPAREG,COUNTER is greater than or equal to COMPARE register G." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 5. "COMPAREF,COUNTER is greater than or equal to COMPARE register F." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 5. "COMPAREF,COUNTER is greater than or equal to COMPARE register F." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 4. "COMPAREE,COUNTER is greater than or equal to COMPARE register E." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 4. "COMPAREE,COUNTER is greater than or equal to COMPARE register E." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 3. "COMPARED,COUNTER is greater than or equal to COMPARE register D." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 3. "COMPARED,COUNTER is greater than or equal to COMPARE register D." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 2. "COMPAREC,COUNTER is greater than or equal to COMPARE register C." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 2. "COMPAREC,COUNTER is greater than or equal to COMPARE register C." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 1. "COMPAREB,COUNTER is greater than or equal to COMPARE register B." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 1. "COMPAREB,COUNTER is greater than or equal to COMPARE register B." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 0. "COMPAREA,COUNTER is greater than or equal to COMPARE register A." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 0. "COMPAREA,COUNTER is greater than or equal to COMPARE register A." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
endif
|
|
line.long 0x4 "STMINTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
bitfld.long 0x4 12. "CAPTURED,CAPTURE register D has grabbed the value in the counter" "?,1: Capture D interrupt status bit was set."
|
|
bitfld.long 0x4 11. "CAPTUREC,CAPTURE register C has grabbed the value in the counter" "?,1: CAPTURE C interrupt status bit was set."
|
|
newline
|
|
bitfld.long 0x4 10. "CAPTUREB,CAPTURE register B has grabbed the value in the counter" "?,1: CAPTURE B interrupt status bit was set."
|
|
bitfld.long 0x4 9. "CAPTUREA,CAPTURE register A has grabbed the value in the counter" "?,1: CAPTURE A interrupt status bit was set."
|
|
newline
|
|
bitfld.long 0x4 8. "OVERFLOW,COUNTER over flowed from 0xFFFFFFFF back to 0x00000000." "?,1: Overflow interrupt status bit was set."
|
|
bitfld.long 0x4 7. "COMPAREH,COUNTER is greater than or equal to COMPARE register H." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
bitfld.long 0x4 6. "COMPAREG,COUNTER is greater than or equal to COMPARE register G." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
bitfld.long 0x4 5. "COMPAREF,COUNTER is greater than or equal to COMPARE register F." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
bitfld.long 0x4 4. "COMPAREE,COUNTER is greater than or equal to COMPARE register E." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
bitfld.long 0x4 3. "COMPARED,COUNTER is greater than or equal to COMPARE register D." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
bitfld.long 0x4 2. "COMPAREC,COUNTER is greater than or equal to COMPARE register C." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
bitfld.long 0x4 1. "COMPAREB,COUNTER is greater than or equal to COMPARE register B." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
bitfld.long 0x4 0. "COMPAREA,COUNTER is greater than or equal to COMPARE register A." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 12. "CAPTURED,CAPTURE register D has grabbed the value in the counter" "0: Capture D interrupt status default/not set.,1: Capture D interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 11. "CAPTUREC,CAPTURE register C has grabbed the value in the counter" "0: CAPTURE C interrupt status default/not set.,1: CAPTURE C interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 11. "CAPTUREC,CAPTURE register C has grabbed the value in the counter" "0: CAPTURE C interrupt status default/not set.,1: CAPTURE C interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 10. "CAPTUREB,CAPTURE register B has grabbed the value in the counter" "0: CAPTURE B interrupt status default/not set.,1: CAPTURE B interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 10. "CAPTUREB,CAPTURE register B has grabbed the value in the counter" "0: CAPTURE B interrupt status default/not set.,1: CAPTURE B interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 9. "CAPTUREA,CAPTURE register A has grabbed the value in the counter" "0: CAPTURE A interrupt status default/not set.,1: CAPTURE A interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 9. "CAPTUREA,CAPTURE register A has grabbed the value in the counter" "0: CAPTURE A interrupt status default/not set.,1: CAPTURE A interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 8. "OVERFLOW,COUNTER over flowed from 0xFFFFFFFF back to 0x00000000." "0: Overflow interrupt status bit default/not set.,1: Overflow interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 8. "OVERFLOW,COUNTER over flowed from 0xFFFFFFFF back to 0x00000000." "0: Overflow interrupt status bit default/not set.,1: Overflow interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 7. "COMPAREH,COUNTER is greater than or equal to COMPARE register H." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 7. "COMPAREH,COUNTER is greater than or equal to COMPARE register H." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 6. "COMPAREG,COUNTER is greater than or equal to COMPARE register G." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 6. "COMPAREG,COUNTER is greater than or equal to COMPARE register G." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 5. "COMPAREF,COUNTER is greater than or equal to COMPARE register F." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 5. "COMPAREF,COUNTER is greater than or equal to COMPARE register F." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 4. "COMPAREE,COUNTER is greater than or equal to COMPARE register E." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 4. "COMPAREE,COUNTER is greater than or equal to COMPARE register E." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 3. "COMPARED,COUNTER is greater than or equal to COMPARE register D." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 3. "COMPARED,COUNTER is greater than or equal to COMPARE register D." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 2. "COMPAREC,COUNTER is greater than or equal to COMPARE register C." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 2. "COMPAREC,COUNTER is greater than or equal to COMPARE register C." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 1. "COMPAREB,COUNTER is greater than or equal to COMPARE register B." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 1. "COMPAREB,COUNTER is greater than or equal to COMPARE register B." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 0. "COMPAREA,COUNTER is greater than or equal to COMPARE register A." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 0. "COMPAREA,COUNTER is greater than or equal to COMPARE register A." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
endif
|
|
line.long 0x8 "STMINTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
bitfld.long 0x8 12. "CAPTURED,CAPTURE register D has grabbed the value in the counter" "?,1: Capture D interrupt status bit was set."
|
|
bitfld.long 0x8 11. "CAPTUREC,CAPTURE register C has grabbed the value in the counter" "?,1: CAPTURE C interrupt status bit was set."
|
|
newline
|
|
bitfld.long 0x8 10. "CAPTUREB,CAPTURE register B has grabbed the value in the counter" "?,1: CAPTURE B interrupt status bit was set."
|
|
bitfld.long 0x8 9. "CAPTUREA,CAPTURE register A has grabbed the value in the counter" "?,1: CAPTURE A interrupt status bit was set."
|
|
newline
|
|
bitfld.long 0x8 8. "OVERFLOW,COUNTER over flowed from 0xFFFFFFFF back to 0x00000000." "?,1: Overflow interrupt status bit was set."
|
|
bitfld.long 0x8 7. "COMPAREH,COUNTER is greater than or equal to COMPARE register H." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
bitfld.long 0x8 6. "COMPAREG,COUNTER is greater than or equal to COMPARE register G." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
bitfld.long 0x8 5. "COMPAREF,COUNTER is greater than or equal to COMPARE register F." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
bitfld.long 0x8 4. "COMPAREE,COUNTER is greater than or equal to COMPARE register E." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
bitfld.long 0x8 3. "COMPARED,COUNTER is greater than or equal to COMPARE register D." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
bitfld.long 0x8 2. "COMPAREC,COUNTER is greater than or equal to COMPARE register C." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
bitfld.long 0x8 1. "COMPAREB,COUNTER is greater than or equal to COMPARE register B." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
bitfld.long 0x8 0. "COMPAREA,COUNTER is greater than or equal to COMPARE register A." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 12. "CAPTURED,CAPTURE register D has grabbed the value in the counter" "0: Capture D interrupt status default/not set.,1: Capture D interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 11. "CAPTUREC,CAPTURE register C has grabbed the value in the counter" "0: CAPTURE C interrupt status default/not set.,1: CAPTURE C interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 11. "CAPTUREC,CAPTURE register C has grabbed the value in the counter" "0: CAPTURE C interrupt status default/not set.,1: CAPTURE C interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 10. "CAPTUREB,CAPTURE register B has grabbed the value in the counter" "0: CAPTURE B interrupt status default/not set.,1: CAPTURE B interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 10. "CAPTUREB,CAPTURE register B has grabbed the value in the counter" "0: CAPTURE B interrupt status default/not set.,1: CAPTURE B interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 9. "CAPTUREA,CAPTURE register A has grabbed the value in the counter" "0: CAPTURE A interrupt status default/not set.,1: CAPTURE A interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 9. "CAPTUREA,CAPTURE register A has grabbed the value in the counter" "0: CAPTURE A interrupt status default/not set.,1: CAPTURE A interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 8. "OVERFLOW,COUNTER over flowed from 0xFFFFFFFF back to 0x00000000." "0: Overflow interrupt status bit default/not set.,1: Overflow interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 8. "OVERFLOW,COUNTER over flowed from 0xFFFFFFFF back to 0x00000000." "0: Overflow interrupt status bit default/not set.,1: Overflow interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 7. "COMPAREH,COUNTER is greater than or equal to COMPARE register H." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 7. "COMPAREH,COUNTER is greater than or equal to COMPARE register H." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 6. "COMPAREG,COUNTER is greater than or equal to COMPARE register G." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 6. "COMPAREG,COUNTER is greater than or equal to COMPARE register G." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 5. "COMPAREF,COUNTER is greater than or equal to COMPARE register F." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 5. "COMPAREF,COUNTER is greater than or equal to COMPARE register F." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 4. "COMPAREE,COUNTER is greater than or equal to COMPARE register E." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 4. "COMPAREE,COUNTER is greater than or equal to COMPARE register E." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 3. "COMPARED,COUNTER is greater than or equal to COMPARE register D." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 3. "COMPARED,COUNTER is greater than or equal to COMPARE register D." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 2. "COMPAREC,COUNTER is greater than or equal to COMPARE register C." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 2. "COMPAREC,COUNTER is greater than or equal to COMPARE register C." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 1. "COMPAREB,COUNTER is greater than or equal to COMPARE register B." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 1. "COMPAREB,COUNTER is greater than or equal to COMPARE register B." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 0. "COMPAREA,COUNTER is greater than or equal to COMPARE register A." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x8 0. "COMPAREA,COUNTER is greater than or equal to COMPARE register A." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
endif
|
|
line.long 0xC "STMINTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
bitfld.long 0xC 12. "CAPTURED,CAPTURE register D has grabbed the value in the counter" "?,1: Capture D interrupt status bit was set."
|
|
bitfld.long 0xC 11. "CAPTUREC,CAPTURE register C has grabbed the value in the counter" "?,1: CAPTURE C interrupt status bit was set."
|
|
newline
|
|
bitfld.long 0xC 10. "CAPTUREB,CAPTURE register B has grabbed the value in the counter" "?,1: CAPTURE B interrupt status bit was set."
|
|
bitfld.long 0xC 9. "CAPTUREA,CAPTURE register A has grabbed the value in the counter" "?,1: CAPTURE A interrupt status bit was set."
|
|
newline
|
|
bitfld.long 0xC 8. "OVERFLOW,COUNTER over flowed from 0xFFFFFFFF back to 0x00000000." "?,1: Overflow interrupt status bit was set."
|
|
bitfld.long 0xC 7. "COMPAREH,COUNTER is greater than or equal to COMPARE register H." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
bitfld.long 0xC 6. "COMPAREG,COUNTER is greater than or equal to COMPARE register G." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
bitfld.long 0xC 5. "COMPAREF,COUNTER is greater than or equal to COMPARE register F." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
bitfld.long 0xC 4. "COMPAREE,COUNTER is greater than or equal to COMPARE register E." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
bitfld.long 0xC 3. "COMPARED,COUNTER is greater than or equal to COMPARE register D." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
bitfld.long 0xC 2. "COMPAREC,COUNTER is greater than or equal to COMPARE register C." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
bitfld.long 0xC 1. "COMPAREB,COUNTER is greater than or equal to COMPARE register B." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
bitfld.long 0xC 0. "COMPAREA,COUNTER is greater than or equal to COMPARE register A." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0xC 12. "CAPTURED,CAPTURE register D has grabbed the value in the counter" "0: Capture D interrupt status default/not set.,1: Capture D interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0xC 11. "CAPTUREC,CAPTURE register C has grabbed the value in the counter" "0: CAPTURE C interrupt status default/not set.,1: CAPTURE C interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0xC 11. "CAPTUREC,CAPTURE register C has grabbed the value in the counter" "0: CAPTURE C interrupt status default/not set.,1: CAPTURE C interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0xC 10. "CAPTUREB,CAPTURE register B has grabbed the value in the counter" "0: CAPTURE B interrupt status default/not set.,1: CAPTURE B interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0xC 10. "CAPTUREB,CAPTURE register B has grabbed the value in the counter" "0: CAPTURE B interrupt status default/not set.,1: CAPTURE B interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0xC 9. "CAPTUREA,CAPTURE register A has grabbed the value in the counter" "0: CAPTURE A interrupt status default/not set.,1: CAPTURE A interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0xC 9. "CAPTUREA,CAPTURE register A has grabbed the value in the counter" "0: CAPTURE A interrupt status default/not set.,1: CAPTURE A interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0xC 8. "OVERFLOW,COUNTER over flowed from 0xFFFFFFFF back to 0x00000000." "0: Overflow interrupt status bit default/not set.,1: Overflow interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0xC 8. "OVERFLOW,COUNTER over flowed from 0xFFFFFFFF back to 0x00000000." "0: Overflow interrupt status bit default/not set.,1: Overflow interrupt status bit was set."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0xC 7. "COMPAREH,COUNTER is greater than or equal to COMPARE register H." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0xC 7. "COMPAREH,COUNTER is greater than or equal to COMPARE register H." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0xC 6. "COMPAREG,COUNTER is greater than or equal to COMPARE register G." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0xC 6. "COMPAREG,COUNTER is greater than or equal to COMPARE register G." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0xC 5. "COMPAREF,COUNTER is greater than or equal to COMPARE register F." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0xC 5. "COMPAREF,COUNTER is greater than or equal to COMPARE register F." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0xC 4. "COMPAREE,COUNTER is greater than or equal to COMPARE register E." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0xC 4. "COMPAREE,COUNTER is greater than or equal to COMPARE register E." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0xC 3. "COMPARED,COUNTER is greater than or equal to COMPARE register D." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0xC 3. "COMPARED,COUNTER is greater than or equal to COMPARE register D." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0xC 2. "COMPAREC,COUNTER is greater than or equal to COMPARE register C." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0xC 2. "COMPAREC,COUNTER is greater than or equal to COMPARE register C." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0xC 1. "COMPAREB,COUNTER is greater than or equal to COMPARE register B." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0xC 1. "COMPAREB,COUNTER is greater than or equal to COMPARE register B." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0xC 0. "COMPAREA,COUNTER is greater than or equal to COMPARE register A." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0xC 0. "COMPAREA,COUNTER is greater than or equal to COMPARE register A." "0: COUNTER less than COMPARE register.,1: COUNTER greater than or equal to COMPARE register."
|
|
endif
|
|
tree.end
|
|
tree "TIMER (Counter/Timer)"
|
|
base ad:0x40008000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CTRL,General Timer Controls"
|
|
bitfld.long 0x0 31. "RESET,Write to 1 to reset all timers (self-clearing)" "0,1"
|
|
line.long 0x4 "STATUS,General Timer status"
|
|
hexmask.long.byte 0x4 16.--20. 1. "NTIMERS,Indicates the number of timer blocks present in the design"
|
|
hexmask.long.word 0x4 0.--15. 1. "ACTIVE,Indicates which timers are currnetly active (enabled)"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "GLOBEN,Alternate enables for all TIMERs."
|
|
bitfld.long 0x0 31. "ADCEN,ADC controls enable for timer 7" "0: Disable TIMER .,1: Timer Enabled. TMREN enable is used."
|
|
bitfld.long 0x0 30. "AUDADCEN,Audio ADC controls enable for timer 6" "0: Disable TIMER .,1: Timer Enabled. TMREN enable is used."
|
|
newline
|
|
bitfld.long 0x0 29. "ENABLEALLINPUTS,Override to enable all GPIO inputs" "0: Normal mode where inputs from GPIO are enabled..,1: Override to enable all inputs from GPIO"
|
|
bitfld.long 0x0 15. "ENB15,Alternate enable for timer 15" "0: Disable TIMER 15.,1: Timer Enabled. TMR15EN enable is used."
|
|
newline
|
|
bitfld.long 0x0 14. "ENB14,Alternate enable for timer 14" "0: Disable TIMER 14.,1: Timer Enabled. TMR14EN enable is used."
|
|
bitfld.long 0x0 13. "ENB13,Alternate enable for timer 13" "0: Disable TIMER 13.,1: Timer Enabled. TMR13EN enable is used."
|
|
newline
|
|
bitfld.long 0x0 12. "ENB12,Alternate enable for timer 12" "0: Disable TIMER 12.,1: Timer Enabled. TMR12EN enable is used."
|
|
bitfld.long 0x0 11. "ENB11,Alternate enable for timer 11" "0: Disable TIMER 11.,1: Timer Enabled. TMR11EN enable is used."
|
|
newline
|
|
bitfld.long 0x0 10. "ENB10,Alternate enable for timer 10" "0: Disable TIMER 10.,1: Timer Enabled. TMR10EN enable is used."
|
|
bitfld.long 0x0 9. "ENB9,Alternate enable for timer 9" "0: Disable TIMER 9.,1: Timer Enabled. TMR9EN enable is used."
|
|
newline
|
|
bitfld.long 0x0 8. "ENB8,Alternate enable for timer 8" "0: Disable TIMER 8.,1: Timer Enabled. TMR8EN enable is used."
|
|
bitfld.long 0x0 7. "ENB7,Alternate enable for timer 7" "0: Disable TIMER 7.,1: Timer Enabled. TMR7EN enable is used."
|
|
newline
|
|
bitfld.long 0x0 6. "ENB6,Alternate enable for timer 6" "0: Disable TIMER 6.,1: Timer Enabled. TMR6EN enable is used."
|
|
bitfld.long 0x0 5. "ENB5,Alternate enable for timer 5" "0: Disable TIMER 5.,1: Timer Enabled. TMR5EN enable is used."
|
|
newline
|
|
bitfld.long 0x0 4. "ENB4,Alternate enable for timer 4" "0: Disable TIMER 4.,1: Timer Enabled. TMR4EN enable is used."
|
|
bitfld.long 0x0 3. "ENB3,Alternate enable for timer 3" "0: Disable TIMER 3.,1: Timer Enabled. TMR3EN enable is used."
|
|
newline
|
|
bitfld.long 0x0 2. "ENB2,Alternate enable for timer 2" "0: Disable TIMER 2.,1: Timer Enabled. TMR2EN enable is used."
|
|
bitfld.long 0x0 1. "ENB1,Alternate enable for timer 1" "0: Disable TIMER 1.,1: Timer Enabled. TMR1EN enable is used."
|
|
newline
|
|
bitfld.long 0x0 0. "ENB0,Alternate enable for timer 0" "0: Disable TIMER 0.,1: Timer Enabled. TMR0EN enable is used."
|
|
group.long 0x60++0xF
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 31. "TMR151INT,Counter/Timer 15 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x0 30. "TMR150INT,Counter/Timer 15 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "TMR141INT,Counter/Timer 14 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x0 28. "TMR140INT,Counter/Timer 14 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "TMR131INT,Counter/Timer 13 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x0 26. "TMR130INT,Counter/Timer 13 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TMR121INT,Counter/Timer 12 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x0 24. "TMR120INT,Counter/Timer 12 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TMR111INT,Counter/Timer 11 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x0 22. "TMR110INT,Counter/Timer 11 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TMR101INT,Counter/Timer 10 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x0 20. "TMR100INT,Counter/Timer 10 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TMR91INT,Counter/Timer 9 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x0 18. "TMR90INT,Counter/Timer 9 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "TMR81INT,Counter/Timer 8 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x0 16. "TMR80INT,Counter/Timer 8 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TMR71INT,Counter/Timer 7 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x0 14. "TMR70INT,Counter/Timer 7 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TMR61INT,Counter/Timer 6 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x0 12. "TMR60INT,Counter/Timer 6 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TMR51INT,Counter/Timer 5 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x0 10. "TMR50INT,Counter/Timer 5 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TMR41INT,Counter/Timer 4 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x0 8. "TMR40INT,Counter/Timer 4 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TMR31INT,Counter/Timer 3 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x0 6. "TMR30INT,Counter/Timer 3 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TMR21INT,Counter/Timer 2 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x0 4. "TMR20INT,Counter/Timer 2 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TMR11INT,Counter/Timer 1 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x0 2. "TMR10INT,Counter/Timer 1 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TMR01INT,Counter/Timer 0 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x0 0. "TMR00INT,Counter/Timer 0 interrupt based on CMP0." "0,1"
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 31. "TMR151INT,Counter/Timer 15 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x4 30. "TMR150INT,Counter/Timer 15 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "TMR141INT,Counter/Timer 14 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x4 28. "TMR140INT,Counter/Timer 14 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "TMR131INT,Counter/Timer 13 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x4 26. "TMR130INT,Counter/Timer 13 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "TMR121INT,Counter/Timer 12 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x4 24. "TMR120INT,Counter/Timer 12 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "TMR111INT,Counter/Timer 11 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x4 22. "TMR110INT,Counter/Timer 11 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "TMR101INT,Counter/Timer 10 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x4 20. "TMR100INT,Counter/Timer 10 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "TMR91INT,Counter/Timer 9 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x4 18. "TMR90INT,Counter/Timer 9 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "TMR81INT,Counter/Timer 8 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x4 16. "TMR80INT,Counter/Timer 8 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TMR71INT,Counter/Timer 7 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x4 14. "TMR70INT,Counter/Timer 7 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "TMR61INT,Counter/Timer 6 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x4 12. "TMR60INT,Counter/Timer 6 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TMR51INT,Counter/Timer 5 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x4 10. "TMR50INT,Counter/Timer 5 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TMR41INT,Counter/Timer 4 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x4 8. "TMR40INT,Counter/Timer 4 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "TMR31INT,Counter/Timer 3 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x4 6. "TMR30INT,Counter/Timer 3 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "TMR21INT,Counter/Timer 2 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x4 4. "TMR20INT,Counter/Timer 2 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "TMR11INT,Counter/Timer 1 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x4 2. "TMR10INT,Counter/Timer 1 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TMR01INT,Counter/Timer 0 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x4 0. "TMR00INT,Counter/Timer 0 interrupt based on CMP0." "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 31. "TMR151INT,Counter/Timer 15 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x8 30. "TMR150INT,Counter/Timer 15 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "TMR141INT,Counter/Timer 14 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x8 28. "TMR140INT,Counter/Timer 14 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "TMR131INT,Counter/Timer 13 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x8 26. "TMR130INT,Counter/Timer 13 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "TMR121INT,Counter/Timer 12 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x8 24. "TMR120INT,Counter/Timer 12 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "TMR111INT,Counter/Timer 11 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x8 22. "TMR110INT,Counter/Timer 11 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "TMR101INT,Counter/Timer 10 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x8 20. "TMR100INT,Counter/Timer 10 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "TMR91INT,Counter/Timer 9 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x8 18. "TMR90INT,Counter/Timer 9 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "TMR81INT,Counter/Timer 8 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x8 16. "TMR80INT,Counter/Timer 8 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "TMR71INT,Counter/Timer 7 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x8 14. "TMR70INT,Counter/Timer 7 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "TMR61INT,Counter/Timer 6 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x8 12. "TMR60INT,Counter/Timer 6 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "TMR51INT,Counter/Timer 5 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x8 10. "TMR50INT,Counter/Timer 5 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "TMR41INT,Counter/Timer 4 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x8 8. "TMR40INT,Counter/Timer 4 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "TMR31INT,Counter/Timer 3 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x8 6. "TMR30INT,Counter/Timer 3 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "TMR21INT,Counter/Timer 2 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x8 4. "TMR20INT,Counter/Timer 2 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "TMR11INT,Counter/Timer 1 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x8 2. "TMR10INT,Counter/Timer 1 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "TMR01INT,Counter/Timer 0 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0x8 0. "TMR00INT,Counter/Timer 0 interrupt based on CMP0." "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 31. "TMR151INT,Counter/Timer 15 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0xC 30. "TMR150INT,Counter/Timer 15 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "TMR141INT,Counter/Timer 14 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0xC 28. "TMR140INT,Counter/Timer 14 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "TMR131INT,Counter/Timer 13 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0xC 26. "TMR130INT,Counter/Timer 13 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "TMR121INT,Counter/Timer 12 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0xC 24. "TMR120INT,Counter/Timer 12 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "TMR111INT,Counter/Timer 11 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0xC 22. "TMR110INT,Counter/Timer 11 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "TMR101INT,Counter/Timer 10 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0xC 20. "TMR100INT,Counter/Timer 10 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "TMR91INT,Counter/Timer 9 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0xC 18. "TMR90INT,Counter/Timer 9 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "TMR81INT,Counter/Timer 8 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0xC 16. "TMR80INT,Counter/Timer 8 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "TMR71INT,Counter/Timer 7 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0xC 14. "TMR70INT,Counter/Timer 7 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "TMR61INT,Counter/Timer 6 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0xC 12. "TMR60INT,Counter/Timer 6 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "TMR51INT,Counter/Timer 5 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0xC 10. "TMR50INT,Counter/Timer 5 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "TMR41INT,Counter/Timer 4 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0xC 8. "TMR40INT,Counter/Timer 4 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "TMR31INT,Counter/Timer 3 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0xC 6. "TMR30INT,Counter/Timer 3 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "TMR21INT,Counter/Timer 2 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0xC 4. "TMR20INT,Counter/Timer 2 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "TMR11INT,Counter/Timer 1 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0xC 2. "TMR10INT,Counter/Timer 1 interrupt based on CMP0." "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "TMR01INT,Counter/Timer 0 interrupt based on CMP1." "0,1"
|
|
bitfld.long 0xC 0. "TMR00INT,Counter/Timer 0 interrupt based on CMP0." "0,1"
|
|
group.long 0x80++0x7F
|
|
line.long 0x0 "OUTCFG0,Pad output configuration 0."
|
|
hexmask.long.byte 0x0 24.--29. 1. "OUTCFG3,Pad output 3 configuration"
|
|
hexmask.long.byte 0x0 16.--21. 1. "OUTCFG2,Pad output 2 configuration"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "OUTCFG1,Pad output 1 configuration"
|
|
hexmask.long.byte 0x0 0.--5. 1. "OUTCFG0,Pad output 0 configuration"
|
|
line.long 0x4 "OUTCFG1,Pad output configuration 0."
|
|
hexmask.long.byte 0x4 24.--29. 1. "OUTCFG7,Pad output 7 configuration"
|
|
hexmask.long.byte 0x4 16.--21. 1. "OUTCFG6,Pad output 6 configuration"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--13. 1. "OUTCFG5,Pad output 5 configuration"
|
|
hexmask.long.byte 0x4 0.--5. 1. "OUTCFG4,Pad output 4 configuration"
|
|
line.long 0x8 "OUTCFG2,Pad output configuration 0."
|
|
hexmask.long.byte 0x8 24.--29. 1. "OUTCFG11,Pad output 11 configuration"
|
|
hexmask.long.byte 0x8 16.--21. 1. "OUTCFG10,Pad output 10 configuration"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--13. 1. "OUTCFG9,Pad output 9 configuration"
|
|
hexmask.long.byte 0x8 0.--5. 1. "OUTCFG8,Pad output 8 configuration"
|
|
line.long 0xC "OUTCFG3,Pad output configuration 0."
|
|
hexmask.long.byte 0xC 24.--29. 1. "OUTCFG15,Pad output 15 configuration"
|
|
hexmask.long.byte 0xC 16.--21. 1. "OUTCFG14,Pad output 14 configuration"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--13. 1. "OUTCFG13,Pad output 13 configuration"
|
|
hexmask.long.byte 0xC 0.--5. 1. "OUTCFG12,Pad output 12 configuration"
|
|
line.long 0x10 "OUTCFG4,Pad output configuration 0."
|
|
hexmask.long.byte 0x10 24.--29. 1. "OUTCFG19,Pad output 19 configuration"
|
|
hexmask.long.byte 0x10 16.--21. 1. "OUTCFG18,Pad output 18 configuration"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--13. 1. "OUTCFG17,Pad output 17 configuration"
|
|
hexmask.long.byte 0x10 0.--5. 1. "OUTCFG16,Pad output 16 configuration"
|
|
line.long 0x14 "OUTCFG5,Pad output configuration 0."
|
|
hexmask.long.byte 0x14 24.--29. 1. "OUTCFG23,Pad output 23 configuration"
|
|
hexmask.long.byte 0x14 16.--21. 1. "OUTCFG22,Pad output 22 configuration"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--13. 1. "OUTCFG21,Pad output 21 configuration"
|
|
hexmask.long.byte 0x14 0.--5. 1. "OUTCFG20,Pad output 20 configuration"
|
|
line.long 0x18 "OUTCFG6,Pad output configuration 0."
|
|
hexmask.long.byte 0x18 24.--29. 1. "OUTCFG27,Pad output 27 configuration"
|
|
hexmask.long.byte 0x18 16.--21. 1. "OUTCFG26,Pad output 26 configuration"
|
|
newline
|
|
hexmask.long.byte 0x18 8.--13. 1. "OUTCFG25,Pad output 25 configuration"
|
|
hexmask.long.byte 0x18 0.--5. 1. "OUTCFG24,Pad output 24 configuration"
|
|
line.long 0x1C "OUTCFG7,Pad output configuration 0."
|
|
hexmask.long.byte 0x1C 24.--29. 1. "OUTCFG31,Pad output 31 configuration"
|
|
hexmask.long.byte 0x1C 16.--21. 1. "OUTCFG30,Pad output 30 configuration"
|
|
newline
|
|
hexmask.long.byte 0x1C 8.--13. 1. "OUTCFG29,Pad output 29 configuration"
|
|
hexmask.long.byte 0x1C 0.--5. 1. "OUTCFG28,Pad output 28 configuration"
|
|
line.long 0x20 "OUTCFG8,Pad output configuration 0."
|
|
hexmask.long.byte 0x20 24.--29. 1. "OUTCFG35,Pad output 35 configuration"
|
|
hexmask.long.byte 0x20 16.--21. 1. "OUTCFG34,Pad output 34 configuration"
|
|
newline
|
|
hexmask.long.byte 0x20 8.--13. 1. "OUTCFG33,Pad output 33 configuration"
|
|
hexmask.long.byte 0x20 0.--5. 1. "OUTCFG32,Pad output 32 configuration"
|
|
line.long 0x24 "OUTCFG9,Pad output configuration 0."
|
|
hexmask.long.byte 0x24 24.--29. 1. "OUTCFG39,Pad output 39 configuration"
|
|
hexmask.long.byte 0x24 16.--21. 1. "OUTCFG38,Pad output 38 configuration"
|
|
newline
|
|
hexmask.long.byte 0x24 8.--13. 1. "OUTCFG37,Pad output 37 configuration"
|
|
hexmask.long.byte 0x24 0.--5. 1. "OUTCFG36,Pad output 36 configuration"
|
|
line.long 0x28 "OUTCFG10,Pad output configuration 0."
|
|
hexmask.long.byte 0x28 24.--29. 1. "OUTCFG43,Pad output 43 configuration"
|
|
hexmask.long.byte 0x28 16.--21. 1. "OUTCFG42,Pad output 42 configuration"
|
|
newline
|
|
hexmask.long.byte 0x28 8.--13. 1. "OUTCFG41,Pad output 41 configuration"
|
|
hexmask.long.byte 0x28 0.--5. 1. "OUTCFG40,Pad output 40 configuration"
|
|
line.long 0x2C "OUTCFG11,Pad output configuration 0."
|
|
hexmask.long.byte 0x2C 24.--29. 1. "OUTCFG47,Pad output 47 configuration"
|
|
hexmask.long.byte 0x2C 16.--21. 1. "OUTCFG46,Pad output 46 configuration"
|
|
newline
|
|
hexmask.long.byte 0x2C 8.--13. 1. "OUTCFG45,Pad output 45 configuration"
|
|
hexmask.long.byte 0x2C 0.--5. 1. "OUTCFG44,Pad output 44 configuration"
|
|
line.long 0x30 "OUTCFG12,Pad output configuration 0."
|
|
hexmask.long.byte 0x30 24.--29. 1. "OUTCFG51,Pad output 51 configuration"
|
|
hexmask.long.byte 0x30 16.--21. 1. "OUTCFG50,Pad output 50 configuration"
|
|
newline
|
|
hexmask.long.byte 0x30 8.--13. 1. "OUTCFG49,Pad output 49 configuration"
|
|
hexmask.long.byte 0x30 0.--5. 1. "OUTCFG48,Pad output 48 configuration"
|
|
line.long 0x34 "OUTCFG13,Pad output configuration 0."
|
|
hexmask.long.byte 0x34 24.--29. 1. "OUTCFG55,Pad output 55 configuration"
|
|
hexmask.long.byte 0x34 16.--21. 1. "OUTCFG54,Pad output 54 configuration"
|
|
newline
|
|
hexmask.long.byte 0x34 8.--13. 1. "OUTCFG53,Pad output 53 configuration"
|
|
hexmask.long.byte 0x34 0.--5. 1. "OUTCFG52,Pad output 52 configuration"
|
|
line.long 0x38 "OUTCFG14,Pad output configuration 0."
|
|
hexmask.long.byte 0x38 24.--29. 1. "OUTCFG59,Pad output 59 configuration"
|
|
hexmask.long.byte 0x38 16.--21. 1. "OUTCFG58,Pad output 58 configuration"
|
|
newline
|
|
hexmask.long.byte 0x38 8.--13. 1. "OUTCFG57,Pad output 57 configuration"
|
|
hexmask.long.byte 0x38 0.--5. 1. "OUTCFG56,Pad output 56 configuration"
|
|
line.long 0x3C "OUTCFG15,Pad output configuration 0."
|
|
hexmask.long.byte 0x3C 24.--29. 1. "OUTCFG63,Pad output 63 configuration"
|
|
hexmask.long.byte 0x3C 16.--21. 1. "OUTCFG62,Pad output 62 configuration"
|
|
newline
|
|
hexmask.long.byte 0x3C 8.--13. 1. "OUTCFG61,Pad output 61 configuration"
|
|
hexmask.long.byte 0x3C 0.--5. 1. "OUTCFG60,Pad output 60 configuration"
|
|
line.long 0x40 "OUTCFG16,Pad output configuration 0."
|
|
hexmask.long.byte 0x40 24.--29. 1. "OUTCFG67,Pad output 67 configuration"
|
|
hexmask.long.byte 0x40 16.--21. 1. "OUTCFG66,Pad output 66 configuration"
|
|
newline
|
|
hexmask.long.byte 0x40 8.--13. 1. "OUTCFG65,Pad output 65 configuration"
|
|
hexmask.long.byte 0x40 0.--5. 1. "OUTCFG64,Pad output 64 configuration"
|
|
line.long 0x44 "OUTCFG17,Pad output configuration 0."
|
|
hexmask.long.byte 0x44 24.--29. 1. "OUTCFG71,Pad output 71 configuration"
|
|
hexmask.long.byte 0x44 16.--21. 1. "OUTCFG70,Pad output 70 configuration"
|
|
newline
|
|
hexmask.long.byte 0x44 8.--13. 1. "OUTCFG69,Pad output 69 configuration"
|
|
hexmask.long.byte 0x44 0.--5. 1. "OUTCFG68,Pad output 68 configuration"
|
|
line.long 0x48 "OUTCFG18,Pad output configuration 0."
|
|
hexmask.long.byte 0x48 24.--29. 1. "OUTCFG75,Pad output 75 configuration"
|
|
hexmask.long.byte 0x48 16.--21. 1. "OUTCFG74,Pad output 74 configuration"
|
|
newline
|
|
hexmask.long.byte 0x48 8.--13. 1. "OUTCFG73,Pad output 73 configuration"
|
|
hexmask.long.byte 0x48 0.--5. 1. "OUTCFG72,Pad output 72 configuration"
|
|
line.long 0x4C "OUTCFG19,Pad output configuration 0."
|
|
hexmask.long.byte 0x4C 24.--29. 1. "OUTCFG79,Pad output 79 configuration"
|
|
hexmask.long.byte 0x4C 16.--21. 1. "OUTCFG78,Pad output 78 configuration"
|
|
newline
|
|
hexmask.long.byte 0x4C 8.--13. 1. "OUTCFG77,Pad output 77 configuration"
|
|
hexmask.long.byte 0x4C 0.--5. 1. "OUTCFG76,Pad output 76 configuration"
|
|
line.long 0x50 "OUTCFG20,Pad output configuration 0."
|
|
hexmask.long.byte 0x50 24.--29. 1. "OUTCFG83,Pad output 83 configuration"
|
|
hexmask.long.byte 0x50 16.--21. 1. "OUTCFG82,Pad output 82 configuration"
|
|
newline
|
|
hexmask.long.byte 0x50 8.--13. 1. "OUTCFG81,Pad output 81 configuration"
|
|
hexmask.long.byte 0x50 0.--5. 1. "OUTCFG80,Pad output 80 configuration"
|
|
line.long 0x54 "OUTCFG21,Pad output configuration 0."
|
|
hexmask.long.byte 0x54 24.--29. 1. "OUTCFG87,Pad output 87 configuration"
|
|
hexmask.long.byte 0x54 16.--21. 1. "OUTCFG86,Pad output 86 configuration"
|
|
newline
|
|
hexmask.long.byte 0x54 8.--13. 1. "OUTCFG85,Pad output 85 configuration"
|
|
hexmask.long.byte 0x54 0.--5. 1. "OUTCFG84,Pad output 84 configuration"
|
|
line.long 0x58 "OUTCFG22,Pad output configuration 0."
|
|
hexmask.long.byte 0x58 24.--29. 1. "OUTCFG91,Pad output 91 configuration"
|
|
hexmask.long.byte 0x58 16.--21. 1. "OUTCFG90,Pad output 90 configuration"
|
|
newline
|
|
hexmask.long.byte 0x58 8.--13. 1. "OUTCFG89,Pad output 89 configuration"
|
|
hexmask.long.byte 0x58 0.--5. 1. "OUTCFG88,Pad output 88 configuration"
|
|
line.long 0x5C "OUTCFG23,Pad output configuration 0."
|
|
hexmask.long.byte 0x5C 24.--29. 1. "OUTCFG95,Pad output 95 configuration"
|
|
hexmask.long.byte 0x5C 16.--21. 1. "OUTCFG94,Pad output 94 configuration"
|
|
newline
|
|
hexmask.long.byte 0x5C 8.--13. 1. "OUTCFG93,Pad output 93 configuration"
|
|
hexmask.long.byte 0x5C 0.--5. 1. "OUTCFG92,Pad output 92 configuration"
|
|
line.long 0x60 "OUTCFG24,Pad output configuration 0."
|
|
hexmask.long.byte 0x60 24.--29. 1. "OUTCFG99,Pad output 99 configuration"
|
|
hexmask.long.byte 0x60 16.--21. 1. "OUTCFG98,Pad output 98 configuration"
|
|
newline
|
|
hexmask.long.byte 0x60 8.--13. 1. "OUTCFG97,Pad output 97 configuration"
|
|
hexmask.long.byte 0x60 0.--5. 1. "OUTCFG96,Pad output 96 configuration"
|
|
line.long 0x64 "OUTCFG25,Pad output configuration 0."
|
|
hexmask.long.byte 0x64 24.--29. 1. "OUTCFG103,Pad output 103 configuration"
|
|
hexmask.long.byte 0x64 16.--21. 1. "OUTCFG102,Pad output 102 configuration"
|
|
newline
|
|
hexmask.long.byte 0x64 8.--13. 1. "OUTCFG101,Pad output 101 configuration"
|
|
hexmask.long.byte 0x64 0.--5. 1. "OUTCFG100,Pad output 100 configuration"
|
|
line.long 0x68 "OUTCFG26,Pad output configuration 0."
|
|
hexmask.long.byte 0x68 24.--29. 1. "OUTCFG107,Pad output 107 configuration"
|
|
hexmask.long.byte 0x68 16.--21. 1. "OUTCFG106,Pad output 106 configuration"
|
|
newline
|
|
hexmask.long.byte 0x68 8.--13. 1. "OUTCFG105,Pad output 105 configuration"
|
|
hexmask.long.byte 0x68 0.--5. 1. "OUTCFG104,Pad output 104 configuration"
|
|
line.long 0x6C "OUTCFG27,Pad output configuration 0."
|
|
hexmask.long.byte 0x6C 24.--29. 1. "OUTCFG111,Pad output 111 configuration"
|
|
hexmask.long.byte 0x6C 16.--21. 1. "OUTCFG110,Pad output 110 configuration"
|
|
newline
|
|
hexmask.long.byte 0x6C 8.--13. 1. "OUTCFG109,Pad output 109 configuration"
|
|
hexmask.long.byte 0x6C 0.--5. 1. "OUTCFG108,Pad output 108 configuration"
|
|
line.long 0x70 "OUTCFG28,Pad output configuration 0."
|
|
hexmask.long.byte 0x70 24.--29. 1. "OUTCFG115,Pad output 115 configuration"
|
|
hexmask.long.byte 0x70 16.--21. 1. "OUTCFG114,Pad output 114 configuration"
|
|
newline
|
|
hexmask.long.byte 0x70 8.--13. 1. "OUTCFG113,Pad output 113 configuration"
|
|
hexmask.long.byte 0x70 0.--5. 1. "OUTCFG112,Pad output 112 configuration"
|
|
line.long 0x74 "OUTCFG29,Pad output configuration 0."
|
|
hexmask.long.byte 0x74 24.--29. 1. "OUTCFG119,Pad output 119 configuration"
|
|
hexmask.long.byte 0x74 16.--21. 1. "OUTCFG118,Pad output 118 configuration"
|
|
newline
|
|
hexmask.long.byte 0x74 8.--13. 1. "OUTCFG117,Pad output 117 configuration"
|
|
hexmask.long.byte 0x74 0.--5. 1. "OUTCFG116,Pad output 116 configuration"
|
|
line.long 0x78 "OUTCFG30,Pad output configuration 0."
|
|
hexmask.long.byte 0x78 24.--29. 1. "OUTCFG123,Pad output 123 configuration"
|
|
hexmask.long.byte 0x78 16.--21. 1. "OUTCFG122,Pad output 122 configuration"
|
|
newline
|
|
hexmask.long.byte 0x78 8.--13. 1. "OUTCFG121,Pad output 121 configuration"
|
|
hexmask.long.byte 0x78 0.--5. 1. "OUTCFG120,Pad output 120 configuration"
|
|
line.long 0x7C "OUTCFG31,Pad output configuration 0."
|
|
hexmask.long.byte 0x7C 24.--29. 1. "OUTCFG127,Pad output 127 configuration"
|
|
hexmask.long.byte 0x7C 16.--21. 1. "OUTCFG126,Pad output 126 configuration"
|
|
newline
|
|
hexmask.long.byte 0x7C 8.--13. 1. "OUTCFG125,Pad output 125 configuration"
|
|
hexmask.long.byte 0x7C 0.--5. 1. "OUTCFG124,Pad output 124 configuration"
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
group.long 0x104++0x3
|
|
line.long 0x0 "AUXEN,Pattern Address"
|
|
bitfld.long 0x0 16. "STMREN,Rev B1 STIMER auxiliary enable." "0: Disable STIMER.,1: Enable STIMER."
|
|
bitfld.long 0x0 15. "TMR15EN,Rev B1 TIMER15 auxiliary enable." "0: Disable TIMER15.,1: Enable TIMER15."
|
|
newline
|
|
bitfld.long 0x0 14. "TMR14EN,Rev B1 TIMER14 auxiliary enable." "0: Disable TIMER14.,1: Enable TIMER14."
|
|
bitfld.long 0x0 13. "TMR13EN,Rev B1 TIMER13 auxiliary enable." "0: Disable TIMER13.,1: Enable TIMER13."
|
|
newline
|
|
bitfld.long 0x0 12. "TMR12EN,Rev B1 TIMER12 auxiliary enable." "0: Disable TIMER12.,1: Enable TIMER12."
|
|
bitfld.long 0x0 11. "TMR11EN,Rev B1 TIMER11 auxiliary enable." "0: Disable TIMER11.,1: Enable TIMER11."
|
|
newline
|
|
bitfld.long 0x0 10. "TMR10EN,Rev B1 TIMER10 auxiliary enable." "0: Disable TIMER10.,1: Enable TIMER10."
|
|
bitfld.long 0x0 9. "TMR09EN,Rev B1 TIMER09 auxiliary enable." "0: Disable TIMER09.,1: Enable TIMER09."
|
|
newline
|
|
bitfld.long 0x0 8. "TMR08EN,Rev B1 TIMER08 auxiliary enable." "0: Disable TIMER08.,1: Enable TIMER08."
|
|
bitfld.long 0x0 7. "TMR07EN,Rev B1 TIMER07 auxiliary enable." "0: Disable TIMER07.,1: Enable TIMER07."
|
|
newline
|
|
bitfld.long 0x0 6. "TMR06EN,Rev B1 TIMER06 auxiliary enable." "0: Disable TIMER06.,1: Enable TIMER06."
|
|
bitfld.long 0x0 5. "TMR05EN,Rev B1 TIMER05 auxiliary enable." "0: Disable TIMER05.,1: Enable TIMER05."
|
|
newline
|
|
bitfld.long 0x0 4. "TMR04EN,Rev B1 TIMER04 auxiliary enable." "0: Disable TIMER04.,1: Enable TIMER04."
|
|
bitfld.long 0x0 3. "TMR03EN,Rev B1 TIMER03 auxiliary enable." "0: Disable TIMER03.,1: Enable TIMER03."
|
|
newline
|
|
bitfld.long 0x0 2. "TMR02EN,Rev B1 TIMER02 auxiliary enable." "0: Disable TIMER02.,1: Enable TIMER02."
|
|
bitfld.long 0x0 1. "TMR01EN,Rev B1 TIMER01 auxiliary enable." "0: Disable TIMER01.,1: Enable TIMER01."
|
|
newline
|
|
bitfld.long 0x0 0. "TMR00EN,Rev B1 TIMER00 auxiliary enable." "0: Disable TIMER00.,1: Enable TIMER00."
|
|
endif
|
|
group.long 0x200++0x13
|
|
line.long 0x0 "CTRL0,This includes the Control bit fields for timer 0."
|
|
hexmask.long.byte 0x0 24.--31. 1. "TMR0LMT,Counter/Timer 0 Pattern Limit Count."
|
|
bitfld.long 0x0 16.--17. "TMR0TMODE,Counter/Timer 0 Trigger Mode" "0: Trigger not enabled,1: Trigger on rising edge of TRIGSEL source,2: Trigger on falling edge of TRIGSEL source,3: Trigger on either edge of TRIGSEL source"
|
|
newline
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR0CLK,Counter/Timer 0 Clock Select."
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR0CLK,Counter/Timer 0 Clock Select."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR0CLK,Counter/Timer 0 Clock Select."
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR0FN,Counter/Timer 0 Function Select."
|
|
newline
|
|
bitfld.long 0x0 1. "TMR0CLR,Counter/Timer Clear bit." "?,1: When written to a 1 the timer will automatically.."
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR0FN,Counter/Timer 0 Function Select. For all Functions CMP0 marks the end of timer cycle and thus restarts the timer."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR0FN,Counter/Timer 0 Function Select. For all Functions CMP0 marks the end of timer cycle and thus restarts the timer."
|
|
endif
|
|
bitfld.long 0x0 3. "TMR0POL1,Counter/Timer 0 output 1 polarity." "0: The polarity of the TMR0OUT1 pin is the same as..,1: The polarity of the TMR0OUT1 pin is the inverse.."
|
|
newline
|
|
bitfld.long 0x0 2. "TMR0POL0,Counter/Timer 0 output 0 polarity." "0: The polarity of the TMR0OUT0 pin is the same as..,1: The polarity of the TMR0OUT0 pin is the inverse.."
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 1. "TMR0CLR,Counter/Timer Clear bit." "0: Default value set to 0. Timer works normally.,1: When written to a 1 the timer will automatically.."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 1. "TMR0CLR,Counter/Timer Clear bit." "0: Default value set to 0. Timer works normally.,1: When written to a 1 the timer will automatically.."
|
|
endif
|
|
bitfld.long 0x0 0. "TMR0EN,Counter/Timer 0 Enable bit." "0: Counter/Timer 0 Disable.,1: Counter/Timer 0 Enable."
|
|
line.long 0x4 "TIMER0,This register holds the running time or event count for timer 0."
|
|
hexmask.long 0x4 0.--31. 1. "TIMER0,Counter/Timer 0"
|
|
line.long 0x8 "TMR0CMP0,This contains the Compare limits for timer 0. This is the primary comparator that can be used to mark the END of a timer cycle (and thus restart the timer for repeat modes)"
|
|
hexmask.long 0x8 0.--31. 1. "TMR0CMP0,Counter/Timer 0 End Compare Register. For MEASURE mode indicates the high phase sample count."
|
|
line.long 0xC "TMR0CMP1,This comparator is used as a secondary compare count for modes that generate pulses. For MEASURE mode indicates the low phase sample count."
|
|
hexmask.long 0xC 0.--31. 1. "TMR0CMP1,Holds the secondary comparator that can be used to generate a PWM or generate secondary pulses. CMP0 should ALWAYS be used first."
|
|
line.long 0x10 "MODE0,The mode register contains optional mode controls for the timer"
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x10 8.--15. 1. "TMR0TRIGSEL,Counter/Timer 0 Trigger Source Selection"
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x10 8.--15. 1. "TMR0TRIGSEL,Counter/Timer 0 Trigger Source Selection"
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
group.long 0x214++0x3
|
|
line.long 0x0 "TMR0LMTVAL,This is an internal counter in the hardware that counts down from TMR_LMT to 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TMR0LMTVAL,Counter/Timer 0 Limit Readback"
|
|
group.long 0x234++0x3
|
|
line.long 0x0 "TMR1LMTVAL,This is an internal counter in the hardware that counts down from TMR_LMT to 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TMR1LMTVAL,Counter/Timer 1 Limit Readback"
|
|
group.long 0x254++0x3
|
|
line.long 0x0 "TMR2LMTVAL,This is an internal counter in the hardware that counts down from TMR_LMT to 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TMR2LMTVAL,Counter/Timer 2 Limit Readback"
|
|
group.long 0x274++0x3
|
|
line.long 0x0 "TMR3LMTVAL,This is an internal counter in the hardware that counts down from TMR_LMT to 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TMR3LMTVAL,Counter/Timer 3 Limit Readback"
|
|
group.long 0x294++0x3
|
|
line.long 0x0 "TMR4LMTVAL,This is an internal counter in the hardware that counts down from TMR_LMT to 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TMR4LMTVAL,Counter/Timer 4 Limit Readback"
|
|
group.long 0x2B4++0x3
|
|
line.long 0x0 "TMR5LMTVAL,This is an internal counter in the hardware that counts down from TMR_LMT to 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TMR5LMTVAL,Counter/Timer 5 Limit Readback"
|
|
group.long 0x2D4++0x3
|
|
line.long 0x0 "TMR6LMTVAL,This is an internal counter in the hardware that counts down from TMR_LMT to 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TMR6LMTVAL,Counter/Timer 6 Limit Readback"
|
|
group.long 0x2F4++0x3
|
|
line.long 0x0 "TMR7LMTVAL,This is an internal counter in the hardware that counts down from TMR_LMT to 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TMR7LMTVAL,Counter/Timer 7 Limit Readback"
|
|
group.long 0x314++0x3
|
|
line.long 0x0 "TMR8LMTVAL,This is an internal counter in the hardware that counts down from TMR_LMT to 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TMR8LMTVAL,Counter/Timer 8 Limit Readback"
|
|
group.long 0x334++0x3
|
|
line.long 0x0 "TMR9LMTVAL,This is an internal counter in the hardware that counts down from TMR_LMT to 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TMR9LMTVAL,Counter/Timer 9 Limit Readback"
|
|
group.long 0x354++0x3
|
|
line.long 0x0 "TMR10LMTVAL,This is an internal counter in the hardware that counts down from TMR_LMT to 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TMR10LMTVAL,Counter/Timer 10 Limit Readback"
|
|
group.long 0x374++0x3
|
|
line.long 0x0 "TMR11LMTVAL,This is an internal counter in the hardware that counts down from TMR_LMT to 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TMR11LMTVAL,Counter/Timer 11 Limit Readback"
|
|
group.long 0x394++0x3
|
|
line.long 0x0 "TMR12LMTVAL,This is an internal counter in the hardware that counts down from TMR_LMT to 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TMR12LMTVAL,Counter/Timer 12 Limit Readback"
|
|
group.long 0x3B4++0x3
|
|
line.long 0x0 "TMR13LMTVAL,This is an internal counter in the hardware that counts down from TMR_LMT to 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TMR13LMTVAL,Counter/Timer 13 Limit Readback"
|
|
group.long 0x3D4++0x3
|
|
line.long 0x0 "TMR14LMTVAL,This is an internal counter in the hardware that counts down from TMR_LMT to 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TMR14LMTVAL,Counter/Timer 14 Limit Readback"
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
group.long 0x214++0x3
|
|
line.long 0x0 "TMR0LMTVAL,This is an internal counter in the hardware that counts down from TMR_LMT to 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TMR0LMTVAL,Counter/Timer 0 Limit Readback"
|
|
group.long 0x234++0x3
|
|
line.long 0x0 "TMR1LMTVAL,This is an internal counter in the hardware that counts down from TMR_LMT to 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TMR1LMTVAL,Counter/Timer 1 Limit Readback"
|
|
group.long 0x254++0x3
|
|
line.long 0x0 "TMR2LMTVAL,This is an internal counter in the hardware that counts down from TMR_LMT to 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TMR2LMTVAL,Counter/Timer 2 Limit Readback"
|
|
group.long 0x274++0x3
|
|
line.long 0x0 "TMR3LMTVAL,This is an internal counter in the hardware that counts down from TMR_LMT to 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TMR3LMTVAL,Counter/Timer 3 Limit Readback"
|
|
group.long 0x294++0x3
|
|
line.long 0x0 "TMR4LMTVAL,This is an internal counter in the hardware that counts down from TMR_LMT to 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TMR4LMTVAL,Counter/Timer 4 Limit Readback"
|
|
group.long 0x2B4++0x3
|
|
line.long 0x0 "TMR5LMTVAL,This is an internal counter in the hardware that counts down from TMR_LMT to 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TMR5LMTVAL,Counter/Timer 5 Limit Readback"
|
|
group.long 0x2D4++0x3
|
|
line.long 0x0 "TMR6LMTVAL,This is an internal counter in the hardware that counts down from TMR_LMT to 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TMR6LMTVAL,Counter/Timer 6 Limit Readback"
|
|
group.long 0x2F4++0x3
|
|
line.long 0x0 "TMR7LMTVAL,This is an internal counter in the hardware that counts down from TMR_LMT to 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TMR7LMTVAL,Counter/Timer 7 Limit Readback"
|
|
group.long 0x314++0x3
|
|
line.long 0x0 "TMR8LMTVAL,This is an internal counter in the hardware that counts down from TMR_LMT to 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TMR8LMTVAL,Counter/Timer 8 Limit Readback"
|
|
group.long 0x334++0x3
|
|
line.long 0x0 "TMR9LMTVAL,This is an internal counter in the hardware that counts down from TMR_LMT to 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TMR9LMTVAL,Counter/Timer 9 Limit Readback"
|
|
group.long 0x354++0x3
|
|
line.long 0x0 "TMR10LMTVAL,This is an internal counter in the hardware that counts down from TMR_LMT to 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TMR10LMTVAL,Counter/Timer 10 Limit Readback"
|
|
group.long 0x374++0x3
|
|
line.long 0x0 "TMR11LMTVAL,This is an internal counter in the hardware that counts down from TMR_LMT to 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TMR11LMTVAL,Counter/Timer 11 Limit Readback"
|
|
group.long 0x394++0x3
|
|
line.long 0x0 "TMR12LMTVAL,This is an internal counter in the hardware that counts down from TMR_LMT to 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TMR12LMTVAL,Counter/Timer 12 Limit Readback"
|
|
group.long 0x3B4++0x3
|
|
line.long 0x0 "TMR13LMTVAL,This is an internal counter in the hardware that counts down from TMR_LMT to 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TMR13LMTVAL,Counter/Timer 13 Limit Readback"
|
|
group.long 0x3D4++0x3
|
|
line.long 0x0 "TMR14LMTVAL,This is an internal counter in the hardware that counts down from TMR_LMT to 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TMR14LMTVAL,Counter/Timer 14 Limit Readback"
|
|
group.long 0x3F4++0x3
|
|
line.long 0x0 "TMR15LMTVAL,This is an internal counter in the hardware that counts down from TMR_LMT to 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TMR15LMTVAL,Counter/Timer 15 Limit Readback"
|
|
endif
|
|
group.long 0x220++0x13
|
|
line.long 0x0 "CTRL1,This includes the Control bit fields for timer 1."
|
|
hexmask.long.byte 0x0 24.--31. 1. "TMR1LMT,Counter/Timer 1 Pattern Limit Count."
|
|
bitfld.long 0x0 16.--17. "TMR1TMODE,Counter/Timer 1 Trigger Mode" "0: Trigger not enabled,1: Trigger on rising edge of TRIGSEL source,2: Trigger on falling edge of TRIGSEL source,3: Trigger on either edge of TRIGSEL source"
|
|
newline
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR1CLK,Counter/Timer 1 Clock Select."
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR1CLK,Counter/Timer 1 Clock Select."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR1CLK,Counter/Timer 1 Clock Select."
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR1FN,Counter/Timer 1 Function Select."
|
|
newline
|
|
bitfld.long 0x0 1. "TMR1CLR,Counter/Timer Clear bit." "?,1: When written to a 1 the timer will automatically.."
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR1FN,Counter/Timer 1 Function Select. For all Functions CMP0 marks the end of timer cycle and thus restarts the timer."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR1FN,Counter/Timer 1 Function Select. For all Functions CMP0 marks the end of timer cycle and thus restarts the timer."
|
|
endif
|
|
bitfld.long 0x0 3. "TMR1POL1,Counter/Timer 1 output 1 polarity." "0: The polarity of the TMR1OUT1 pin is the same as..,1: The polarity of the TMR1OUT1 pin is the inverse.."
|
|
newline
|
|
bitfld.long 0x0 2. "TMR1POL0,Counter/Timer 1 output 0 polarity." "0: The polarity of the TMR1OUT0 pin is the same as..,1: The polarity of the TMR1OUT0 pin is the inverse.."
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 1. "TMR1CLR,Counter/Timer Clear bit." "0: Default value set to 0. Timer works normally.,1: When written to a 1 the timer will automatically.."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 1. "TMR1CLR,Counter/Timer Clear bit." "0: Default value set to 0. Timer works normally.,1: When written to a 1 the timer will automatically.."
|
|
endif
|
|
bitfld.long 0x0 0. "TMR1EN,Counter/Timer 1 Enable bit." "0: Counter/Timer 1 Disable.,1: Counter/Timer 1 Enable."
|
|
line.long 0x4 "TIMER1,This register holds the running time or event count for timer 1."
|
|
hexmask.long 0x4 0.--31. 1. "TIMER1,Counter/Timer 1"
|
|
line.long 0x8 "TMR1CMP0,This contains the Compare limits for timer 1. This is the primary comparator that can be used to mark the END of a timer cycle (and thus restart the timer for repeat modes)"
|
|
hexmask.long 0x8 0.--31. 1. "TMR1CMP0,Counter/Timer 1 End Compare Register. For MEASURE mode indicates the high phase sample count."
|
|
line.long 0xC "TMR1CMP1,This comparator is used as a secondary compare count for modes that generate pulses. For MEASURE mode indicates the low phase sample count."
|
|
hexmask.long 0xC 0.--31. 1. "TMR1CMP1,Holds the secondary comparator that can be used to generate a PWM or generate secondary pulses. CMP0 should ALWAYS be used first."
|
|
line.long 0x10 "MODE1,The mode register contains optional mode controls for the timer"
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x10 8.--15. 1. "TMR1TRIGSEL,Counter/Timer 1 Trigger Source Selection"
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x10 8.--15. 1. "TMR1TRIGSEL,Counter/Timer 1 Trigger Source Selection"
|
|
endif
|
|
group.long 0x240++0x13
|
|
line.long 0x0 "CTRL2,This includes the Control bit fields for timer 2."
|
|
hexmask.long.byte 0x0 24.--31. 1. "TMR2LMT,Counter/Timer 2 Pattern Limit Count."
|
|
bitfld.long 0x0 16.--17. "TMR2TMODE,Counter/Timer 2 Trigger Mode" "0: Trigger not enabled,1: Trigger on rising edge of TRIGSEL source,2: Trigger on falling edge of TRIGSEL source,3: Trigger on either edge of TRIGSEL source"
|
|
newline
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR2CLK,Counter/Timer 2 Clock Select."
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR2CLK,Counter/Timer 2 Clock Select."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR2CLK,Counter/Timer 2 Clock Select."
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR2FN,Counter/Timer 2 Function Select."
|
|
newline
|
|
bitfld.long 0x0 1. "TMR2CLR,Counter/Timer Clear bit." "?,1: When written to a 1 the timer will automatically.."
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR2FN,Counter/Timer 2 Function Select. For all Functions CMP0 marks the end of timer cycle and thus restarts the timer."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR2FN,Counter/Timer 2 Function Select. For all Functions CMP0 marks the end of timer cycle and thus restarts the timer."
|
|
endif
|
|
bitfld.long 0x0 3. "TMR2POL1,Counter/Timer 2 output 1 polarity." "0: The polarity of the TMR2OUT1 pin is the same as..,1: The polarity of the TMR2OUT1 pin is the inverse.."
|
|
newline
|
|
bitfld.long 0x0 2. "TMR2POL0,Counter/Timer 2 output 0 polarity." "0: The polarity of the TMR2OUT0 pin is the same as..,1: The polarity of the TMR2OUT0 pin is the inverse.."
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 1. "TMR2CLR,Counter/Timer Clear bit." "0: Default value set to 0. Timer works normally.,1: When written to a 1 the timer will automatically.."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 1. "TMR2CLR,Counter/Timer Clear bit." "0: Default value set to 0. Timer works normally.,1: When written to a 1 the timer will automatically.."
|
|
endif
|
|
bitfld.long 0x0 0. "TMR2EN,Counter/Timer 2 Enable bit." "0: Counter/Timer 2 Disable.,1: Counter/Timer 2 Enable."
|
|
line.long 0x4 "TIMER2,This register holds the running time or event count for timer 2."
|
|
hexmask.long 0x4 0.--31. 1. "TIMER2,Counter/Timer 2"
|
|
line.long 0x8 "TMR2CMP0,This contains the Compare limits for timer 2. This is the primary comparator that can be used to mark the END of a timer cycle (and thus restart the timer for repeat modes)"
|
|
hexmask.long 0x8 0.--31. 1. "TMR2CMP0,Counter/Timer 2 End Compare Register. For MEASURE mode indicates the high phase sample count."
|
|
line.long 0xC "TMR2CMP1,This comparator is used as a secondary compare count for modes that generate pulses. For MEASURE mode indicates the low phase sample count."
|
|
hexmask.long 0xC 0.--31. 1. "TMR2CMP1,Holds the secondary comparator that can be used to generate a PWM or generate secondary pulses. CMP0 should ALWAYS be used first."
|
|
line.long 0x10 "MODE2,The mode register contains optional mode controls for the timer"
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x10 8.--15. 1. "TMR2TRIGSEL,Counter/Timer 2 Trigger Source Selection"
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x10 8.--15. 1. "TMR2TRIGSEL,Counter/Timer 2 Trigger Source Selection"
|
|
endif
|
|
group.long 0x260++0x13
|
|
line.long 0x0 "CTRL3,This includes the Control bit fields for timer 3."
|
|
hexmask.long.byte 0x0 24.--31. 1. "TMR3LMT,Counter/Timer 3 Pattern Limit Count."
|
|
bitfld.long 0x0 16.--17. "TMR3TMODE,Counter/Timer 3 Trigger Mode" "0: Trigger not enabled,1: Trigger on rising edge of TRIGSEL source,2: Trigger on falling edge of TRIGSEL source,3: Trigger on either edge of TRIGSEL source"
|
|
newline
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR3CLK,Counter/Timer 3 Clock Select."
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR3CLK,Counter/Timer 3 Clock Select."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR3CLK,Counter/Timer 3 Clock Select."
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR3FN,Counter/Timer 3 Function Select."
|
|
newline
|
|
bitfld.long 0x0 1. "TMR3CLR,Counter/Timer Clear bit." "?,1: When written to a 1 the timer will automatically.."
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR3FN,Counter/Timer 3 Function Select. For all Functions CMP0 marks the end of timer cycle and thus restarts the timer."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR3FN,Counter/Timer 3 Function Select. For all Functions CMP0 marks the end of timer cycle and thus restarts the timer."
|
|
endif
|
|
bitfld.long 0x0 3. "TMR3POL1,Counter/Timer 3 output 1 polarity." "0: The polarity of the TMR3OUT1 pin is the same as..,1: The polarity of the TMR3OUT1 pin is the inverse.."
|
|
newline
|
|
bitfld.long 0x0 2. "TMR3POL0,Counter/Timer 3 output 0 polarity." "0: The polarity of the TMR3OUT0 pin is the same as..,1: The polarity of the TMR3OUT0 pin is the inverse.."
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 1. "TMR3CLR,Counter/Timer Clear bit." "0: Default value set to 0. Timer works normally.,1: When written to a 1 the timer will automatically.."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 1. "TMR3CLR,Counter/Timer Clear bit." "0: Default value set to 0. Timer works normally.,1: When written to a 1 the timer will automatically.."
|
|
endif
|
|
bitfld.long 0x0 0. "TMR3EN,Counter/Timer 3 Enable bit." "0: Counter/Timer 3 Disable.,1: Counter/Timer 3 Enable."
|
|
line.long 0x4 "TIMER3,This register holds the running time or event count for timer 3."
|
|
hexmask.long 0x4 0.--31. 1. "TIMER3,Counter/Timer 3"
|
|
line.long 0x8 "TMR3CMP0,This contains the Compare limits for timer 3. This is the primary comparator that can be used to mark the END of a timer cycle (and thus restart the timer for repeat modes)"
|
|
hexmask.long 0x8 0.--31. 1. "TMR3CMP0,Counter/Timer 3 End Compare Register. For MEASURE mode indicates the high phase sample count."
|
|
line.long 0xC "TMR3CMP1,This comparator is used as a secondary compare count for modes that generate pulses. For MEASURE mode indicates the low phase sample count."
|
|
hexmask.long 0xC 0.--31. 1. "TMR3CMP1,Holds the secondary comparator that can be used to generate a PWM or generate secondary pulses. CMP0 should ALWAYS be used first."
|
|
line.long 0x10 "MODE3,The mode register contains optional mode controls for the timer"
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x10 8.--15. 1. "TMR3TRIGSEL,Counter/Timer 3 Trigger Source Selection"
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x10 8.--15. 1. "TMR3TRIGSEL,Counter/Timer 3 Trigger Source Selection"
|
|
endif
|
|
group.long 0x280++0x13
|
|
line.long 0x0 "CTRL4,This includes the Control bit fields for timer 4."
|
|
hexmask.long.byte 0x0 24.--31. 1. "TMR4LMT,Counter/Timer 4 Pattern Limit Count."
|
|
bitfld.long 0x0 16.--17. "TMR4TMODE,Counter/Timer 4 Trigger Mode" "0: Trigger not enabled,1: Trigger on rising edge of TRIGSEL source,2: Trigger on falling edge of TRIGSEL source,3: Trigger on either edge of TRIGSEL source"
|
|
newline
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR4CLK,Counter/Timer 4 Clock Select."
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR4CLK,Counter/Timer 4 Clock Select."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR4CLK,Counter/Timer 4 Clock Select."
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR4FN,Counter/Timer 4 Function Select."
|
|
newline
|
|
bitfld.long 0x0 1. "TMR4CLR,Counter/Timer Clear bit." "?,1: When written to a 1 the timer will automatically.."
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR4FN,Counter/Timer 4 Function Select. For all Functions CMP0 marks the end of timer cycle and thus restarts the timer."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR4FN,Counter/Timer 4 Function Select. For all Functions CMP0 marks the end of timer cycle and thus restarts the timer."
|
|
endif
|
|
bitfld.long 0x0 3. "TMR4POL1,Counter/Timer 4 output 1 polarity." "0: The polarity of the TMR4OUT1 pin is the same as..,1: The polarity of the TMR4OUT1 pin is the inverse.."
|
|
newline
|
|
bitfld.long 0x0 2. "TMR4POL0,Counter/Timer 4 output 0 polarity." "0: The polarity of the TMR4OUT0 pin is the same as..,1: The polarity of the TMR4OUT0 pin is the inverse.."
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 1. "TMR4CLR,Counter/Timer Clear bit." "0: Default value set to 0. Timer works normally.,1: When written to a 1 the timer will automatically.."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 1. "TMR4CLR,Counter/Timer Clear bit." "0: Default value set to 0. Timer works normally.,1: When written to a 1 the timer will automatically.."
|
|
endif
|
|
bitfld.long 0x0 0. "TMR4EN,Counter/Timer 4 Enable bit." "0: Counter/Timer 4 Disable.,1: Counter/Timer 4 Enable."
|
|
line.long 0x4 "TIMER4,This register holds the running time or event count for timer 4."
|
|
hexmask.long 0x4 0.--31. 1. "TIMER4,Counter/Timer 4"
|
|
line.long 0x8 "TMR4CMP0,This contains the Compare limits for timer 4. This is the primary comparator that can be used to mark the END of a timer cycle (and thus restart the timer for repeat modes)"
|
|
hexmask.long 0x8 0.--31. 1. "TMR4CMP0,Counter/Timer 4 End Compare Register. For MEASURE mode indicates the high phase sample count."
|
|
line.long 0xC "TMR4CMP1,This comparator is used as a secondary compare count for modes that generate pulses. For MEASURE mode indicates the low phase sample count."
|
|
hexmask.long 0xC 0.--31. 1. "TMR4CMP1,Holds the secondary comparator that can be used to generate a PWM or generate secondary pulses. CMP0 should ALWAYS be used first."
|
|
line.long 0x10 "MODE4,The mode register contains optional mode controls for the timer"
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x10 8.--15. 1. "TMR4TRIGSEL,Counter/Timer 4 Trigger Source Selection"
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x10 8.--15. 1. "TMR4TRIGSEL,Counter/Timer 4 Trigger Source Selection"
|
|
endif
|
|
group.long 0x2A0++0x13
|
|
line.long 0x0 "CTRL5,This includes the Control bit fields for timer 5."
|
|
hexmask.long.byte 0x0 24.--31. 1. "TMR5LMT,Counter/Timer 5 Pattern Limit Count."
|
|
bitfld.long 0x0 16.--17. "TMR5TMODE,Counter/Timer 5 Trigger Mode" "0: Trigger not enabled,1: Trigger on rising edge of TRIGSEL source,2: Trigger on falling edge of TRIGSEL source,3: Trigger on either edge of TRIGSEL source"
|
|
newline
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR5CLK,Counter/Timer 5 Clock Select."
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR5CLK,Counter/Timer 5 Clock Select."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR5CLK,Counter/Timer 5 Clock Select."
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR5FN,Counter/Timer 5 Function Select."
|
|
newline
|
|
bitfld.long 0x0 1. "TMR5CLR,Counter/Timer Clear bit." "?,1: When written to a 1 the timer will automatically.."
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR5FN,Counter/Timer 5 Function Select. For all Functions CMP0 marks the end of timer cycle and thus restarts the timer."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR5FN,Counter/Timer 5 Function Select. For all Functions CMP0 marks the end of timer cycle and thus restarts the timer."
|
|
endif
|
|
bitfld.long 0x0 3. "TMR5POL1,Counter/Timer 5 output 1 polarity." "0: The polarity of the TMR5OUT1 pin is the same as..,1: The polarity of the TMR5OUT1 pin is the inverse.."
|
|
newline
|
|
bitfld.long 0x0 2. "TMR5POL0,Counter/Timer 5 output 0 polarity." "0: The polarity of the TMR5OUT0 pin is the same as..,1: The polarity of the TMR5OUT0 pin is the inverse.."
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 1. "TMR5CLR,Counter/Timer Clear bit." "0: Default value set to 0. Timer works normally.,1: When written to a 1 the timer will automatically.."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 1. "TMR5CLR,Counter/Timer Clear bit." "0: Default value set to 0. Timer works normally.,1: When written to a 1 the timer will automatically.."
|
|
endif
|
|
bitfld.long 0x0 0. "TMR5EN,Counter/Timer 5 Enable bit." "0: Counter/Timer 5 Disable.,1: Counter/Timer 5 Enable."
|
|
line.long 0x4 "TIMER5,This register holds the running time or event count for timer 5."
|
|
hexmask.long 0x4 0.--31. 1. "TIMER5,Counter/Timer 5"
|
|
line.long 0x8 "TMR5CMP0,This contains the Compare limits for timer 5. This is the primary comparator that can be used to mark the END of a timer cycle (and thus restart the timer for repeat modes)"
|
|
hexmask.long 0x8 0.--31. 1. "TMR5CMP0,Counter/Timer 5 End Compare Register. For MEASURE mode indicates the high phase sample count."
|
|
line.long 0xC "TMR5CMP1,This comparator is used as a secondary compare count for modes that generate pulses. For MEASURE mode indicates the low phase sample count."
|
|
hexmask.long 0xC 0.--31. 1. "TMR5CMP1,Holds the secondary comparator that can be used to generate a PWM or generate secondary pulses. CMP0 should ALWAYS be used first."
|
|
line.long 0x10 "MODE5,The mode register contains optional mode controls for the timer"
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x10 8.--15. 1. "TMR5TRIGSEL,Counter/Timer 5 Trigger Source Selection"
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x10 8.--15. 1. "TMR5TRIGSEL,Counter/Timer 5 Trigger Source Selection"
|
|
endif
|
|
group.long 0x2C0++0x13
|
|
line.long 0x0 "CTRL6,This includes the Control bit fields for timer 6."
|
|
hexmask.long.byte 0x0 24.--31. 1. "TMR6LMT,Counter/Timer 6 Pattern Limit Count."
|
|
bitfld.long 0x0 16.--17. "TMR6TMODE,Counter/Timer 6 Trigger Mode" "0: Trigger not enabled,1: Trigger on rising edge of TRIGSEL source,2: Trigger on falling edge of TRIGSEL source,3: Trigger on either edge of TRIGSEL source"
|
|
newline
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR6CLK,Counter/Timer 6 Clock Select."
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR6CLK,Counter/Timer 6 Clock Select."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR6CLK,Counter/Timer 6 Clock Select."
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR6FN,Counter/Timer 6 Function Select."
|
|
newline
|
|
bitfld.long 0x0 1. "TMR6CLR,Counter/Timer Clear bit." "?,1: When written to a 1 the timer will automatically.."
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR6FN,Counter/Timer 6 Function Select. For all Functions CMP0 marks the end of timer cycle and thus restarts the timer."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR6FN,Counter/Timer 6 Function Select. For all Functions CMP0 marks the end of timer cycle and thus restarts the timer."
|
|
endif
|
|
bitfld.long 0x0 3. "TMR6POL1,Counter/Timer 6 output 1 polarity." "0: The polarity of the TMR6OUT1 pin is the same as..,1: The polarity of the TMR6OUT1 pin is the inverse.."
|
|
newline
|
|
bitfld.long 0x0 2. "TMR6POL0,Counter/Timer 6 output 0 polarity." "0: The polarity of the TMR6OUT0 pin is the same as..,1: The polarity of the TMR6OUT0 pin is the inverse.."
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 1. "TMR6CLR,Counter/Timer Clear bit." "0: Default value set to 0. Timer works normally.,1: When written to a 1 the timer will automatically.."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 1. "TMR6CLR,Counter/Timer Clear bit." "0: Default value set to 0. Timer works normally.,1: When written to a 1 the timer will automatically.."
|
|
endif
|
|
bitfld.long 0x0 0. "TMR6EN,Counter/Timer 6 Enable bit." "0: Counter/Timer 6 Disable.,1: Counter/Timer 6 Enable."
|
|
line.long 0x4 "TIMER6,This register holds the running time or event count for timer 6."
|
|
hexmask.long 0x4 0.--31. 1. "TIMER6,Counter/Timer 6"
|
|
line.long 0x8 "TMR6CMP0,This contains the Compare limits for timer 6. This is the primary comparator that can be used to mark the END of a timer cycle (and thus restart the timer for repeat modes)"
|
|
hexmask.long 0x8 0.--31. 1. "TMR6CMP0,Counter/Timer 6 End Compare Register. For MEASURE mode indicates the high phase sample count."
|
|
line.long 0xC "TMR6CMP1,This comparator is used as a secondary compare count for modes that generate pulses. For MEASURE mode indicates the low phase sample count."
|
|
hexmask.long 0xC 0.--31. 1. "TMR6CMP1,Holds the secondary comparator that can be used to generate a PWM or generate secondary pulses. CMP0 should ALWAYS be used first."
|
|
line.long 0x10 "MODE6,The mode register contains optional mode controls for the timer"
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x10 8.--15. 1. "TMR6TRIGSEL,Counter/Timer 6 Trigger Source Selection"
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x10 8.--15. 1. "TMR6TRIGSEL,Counter/Timer 6 Trigger Source Selection"
|
|
endif
|
|
group.long 0x2E0++0x13
|
|
line.long 0x0 "CTRL7,This includes the Control bit fields for timer 7."
|
|
hexmask.long.byte 0x0 24.--31. 1. "TMR7LMT,Counter/Timer 7 Pattern Limit Count."
|
|
bitfld.long 0x0 16.--17. "TMR7TMODE,Counter/Timer 7 Trigger Mode" "0: Trigger not enabled,1: Trigger on rising edge of TRIGSEL source,2: Trigger on falling edge of TRIGSEL source,3: Trigger on either edge of TRIGSEL source"
|
|
newline
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR7CLK,Counter/Timer 7 Clock Select."
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR7CLK,Counter/Timer 7 Clock Select."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR7CLK,Counter/Timer 7 Clock Select."
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR7FN,Counter/Timer 7 Function Select."
|
|
newline
|
|
bitfld.long 0x0 1. "TMR7CLR,Counter/Timer Clear bit." "?,1: When written to a 1 the timer will automatically.."
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR7FN,Counter/Timer 7 Function Select. For all Functions CMP0 marks the end of timer cycle and thus restarts the timer."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR7FN,Counter/Timer 7 Function Select. For all Functions CMP0 marks the end of timer cycle and thus restarts the timer."
|
|
endif
|
|
bitfld.long 0x0 3. "TMR7POL1,Counter/Timer 7 output 1 polarity." "0: The polarity of the TMR7OUT1 pin is the same as..,1: The polarity of the TMR7OUT1 pin is the inverse.."
|
|
newline
|
|
bitfld.long 0x0 2. "TMR7POL0,Counter/Timer 7 output 0 polarity." "0: The polarity of the TMR7OUT0 pin is the same as..,1: The polarity of the TMR7OUT0 pin is the inverse.."
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 1. "TMR7CLR,Counter/Timer Clear bit." "0: Default value set to 0. Timer works normally.,1: When written to a 1 the timer will automatically.."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 1. "TMR7CLR,Counter/Timer Clear bit." "0: Default value set to 0. Timer works normally.,1: When written to a 1 the timer will automatically.."
|
|
endif
|
|
bitfld.long 0x0 0. "TMR7EN,Counter/Timer 7 Enable bit." "0: Counter/Timer 7 Disable.,1: Counter/Timer 7 Enable."
|
|
line.long 0x4 "TIMER7,This register holds the running time or event count for timer 7."
|
|
hexmask.long 0x4 0.--31. 1. "TIMER7,Counter/Timer 7"
|
|
line.long 0x8 "TMR7CMP0,This contains the Compare limits for timer 7. This is the primary comparator that can be used to mark the END of a timer cycle (and thus restart the timer for repeat modes)"
|
|
hexmask.long 0x8 0.--31. 1. "TMR7CMP0,Counter/Timer 7 End Compare Register. For MEASURE mode indicates the high phase sample count."
|
|
line.long 0xC "TMR7CMP1,This comparator is used as a secondary compare count for modes that generate pulses. For MEASURE mode indicates the low phase sample count."
|
|
hexmask.long 0xC 0.--31. 1. "TMR7CMP1,Holds the secondary comparator that can be used to generate a PWM or generate secondary pulses. CMP0 should ALWAYS be used first."
|
|
line.long 0x10 "MODE7,The mode register contains optional mode controls for the timer"
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x10 8.--15. 1. "TMR7TRIGSEL,Counter/Timer 7 Trigger Source Selection"
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x10 8.--15. 1. "TMR7TRIGSEL,Counter/Timer 7 Trigger Source Selection"
|
|
endif
|
|
group.long 0x300++0x13
|
|
line.long 0x0 "CTRL8,This includes the Control bit fields for timer 8."
|
|
hexmask.long.byte 0x0 24.--31. 1. "TMR8LMT,Counter/Timer 8 Pattern Limit Count."
|
|
bitfld.long 0x0 16.--17. "TMR8TMODE,Counter/Timer 8 Trigger Mode" "0: Trigger not enabled,1: Trigger on rising edge of TRIGSEL source,2: Trigger on falling edge of TRIGSEL source,3: Trigger on either edge of TRIGSEL source"
|
|
newline
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR8CLK,Counter/Timer 8 Clock Select."
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR8CLK,Counter/Timer 8 Clock Select."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR8CLK,Counter/Timer 8 Clock Select."
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR8FN,Counter/Timer 8 Function Select."
|
|
newline
|
|
bitfld.long 0x0 1. "TMR8CLR,Counter/Timer Clear bit." "?,1: When written to a 1 the timer will automatically.."
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR8FN,Counter/Timer 8 Function Select. For all Functions CMP0 marks the end of timer cycle and thus restarts the timer."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR8FN,Counter/Timer 8 Function Select. For all Functions CMP0 marks the end of timer cycle and thus restarts the timer."
|
|
endif
|
|
bitfld.long 0x0 3. "TMR8POL1,Counter/Timer 8 output 1 polarity." "0: The polarity of the TMR8OUT1 pin is the same as..,1: The polarity of the TMR8OUT1 pin is the inverse.."
|
|
newline
|
|
bitfld.long 0x0 2. "TMR8POL0,Counter/Timer 8 output 0 polarity." "0: The polarity of the TMR8OUT0 pin is the same as..,1: The polarity of the TMR8OUT0 pin is the inverse.."
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 1. "TMR8CLR,Counter/Timer Clear bit." "0: Default value set to 0. Timer works normally.,1: When written to a 1 the timer will automatically.."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 1. "TMR8CLR,Counter/Timer Clear bit." "0: Default value set to 0. Timer works normally.,1: When written to a 1 the timer will automatically.."
|
|
endif
|
|
bitfld.long 0x0 0. "TMR8EN,Counter/Timer 8 Enable bit." "0: Counter/Timer 8 Disable.,1: Counter/Timer 8 Enable."
|
|
line.long 0x4 "TIMER8,This register holds the running time or event count for timer 8."
|
|
hexmask.long 0x4 0.--31. 1. "TIMER8,Counter/Timer 8"
|
|
line.long 0x8 "TMR8CMP0,This contains the Compare limits for timer 8. This is the primary comparator that can be used to mark the END of a timer cycle (and thus restart the timer for repeat modes)"
|
|
hexmask.long 0x8 0.--31. 1. "TMR8CMP0,Counter/Timer 8 End Compare Register. For MEASURE mode indicates the high phase sample count."
|
|
line.long 0xC "TMR8CMP1,This comparator is used as a secondary compare count for modes that generate pulses. For MEASURE mode indicates the low phase sample count."
|
|
hexmask.long 0xC 0.--31. 1. "TMR8CMP1,Holds the secondary comparator that can be used to generate a PWM or generate secondary pulses. CMP0 should ALWAYS be used first."
|
|
line.long 0x10 "MODE8,The mode register contains optional mode controls for the timer"
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x10 8.--15. 1. "TMR8TRIGSEL,Counter/Timer 8 Trigger Source Selection"
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x10 8.--15. 1. "TMR8TRIGSEL,Counter/Timer 8 Trigger Source Selection"
|
|
endif
|
|
group.long 0x320++0x13
|
|
line.long 0x0 "CTRL9,This includes the Control bit fields for timer 9."
|
|
hexmask.long.byte 0x0 24.--31. 1. "TMR9LMT,Counter/Timer 9 Pattern Limit Count."
|
|
bitfld.long 0x0 16.--17. "TMR9TMODE,Counter/Timer 9 Trigger Mode" "0: Trigger not enabled,1: Trigger on rising edge of TRIGSEL source,2: Trigger on falling edge of TRIGSEL source,3: Trigger on either edge of TRIGSEL source"
|
|
newline
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR9CLK,Counter/Timer 9 Clock Select."
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR9CLK,Counter/Timer 9 Clock Select."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR9CLK,Counter/Timer 9 Clock Select."
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR9FN,Counter/Timer 9 Function Select."
|
|
newline
|
|
bitfld.long 0x0 1. "TMR9CLR,Counter/Timer Clear bit." "?,1: When written to a 1 the timer will automatically.."
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR9FN,Counter/Timer 9 Function Select. For all Functions CMP0 marks the end of timer cycle and thus restarts the timer."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR9FN,Counter/Timer 9 Function Select. For all Functions CMP0 marks the end of timer cycle and thus restarts the timer."
|
|
endif
|
|
bitfld.long 0x0 3. "TMR9POL1,Counter/Timer 9 output 1 polarity." "0: The polarity of the TMR9OUT1 pin is the same as..,1: The polarity of the TMR9OUT1 pin is the inverse.."
|
|
newline
|
|
bitfld.long 0x0 2. "TMR9POL0,Counter/Timer 9 output 0 polarity." "0: The polarity of the TMR9OUT0 pin is the same as..,1: The polarity of the TMR9OUT0 pin is the inverse.."
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 1. "TMR9CLR,Counter/Timer Clear bit." "0: Default value set to 0. Timer works normally.,1: When written to a 1 the timer will automatically.."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 1. "TMR9CLR,Counter/Timer Clear bit." "0: Default value set to 0. Timer works normally.,1: When written to a 1 the timer will automatically.."
|
|
endif
|
|
bitfld.long 0x0 0. "TMR9EN,Counter/Timer 9 Enable bit." "0: Counter/Timer 9 Disable.,1: Counter/Timer 9 Enable."
|
|
line.long 0x4 "TIMER9,This register holds the running time or event count for timer 9."
|
|
hexmask.long 0x4 0.--31. 1. "TIMER9,Counter/Timer 9"
|
|
line.long 0x8 "TMR9CMP0,This contains the Compare limits for timer 9. This is the primary comparator that can be used to mark the END of a timer cycle (and thus restart the timer for repeat modes)"
|
|
hexmask.long 0x8 0.--31. 1. "TMR9CMP0,Counter/Timer 9 End Compare Register. For MEASURE mode indicates the high phase sample count."
|
|
line.long 0xC "TMR9CMP1,This comparator is used as a secondary compare count for modes that generate pulses. For MEASURE mode indicates the low phase sample count."
|
|
hexmask.long 0xC 0.--31. 1. "TMR9CMP1,Holds the secondary comparator that can be used to generate a PWM or generate secondary pulses. CMP0 should ALWAYS be used first."
|
|
line.long 0x10 "MODE9,The mode register contains optional mode controls for the timer"
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x10 8.--15. 1. "TMR9TRIGSEL,Counter/Timer 9 Trigger Source Selection"
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x10 8.--15. 1. "TMR9TRIGSEL,Counter/Timer 9 Trigger Source Selection"
|
|
endif
|
|
group.long 0x340++0x13
|
|
line.long 0x0 "CTRL10,This includes the Control bit fields for timer 10."
|
|
hexmask.long.byte 0x0 24.--31. 1. "TMR10LMT,Counter/Timer 10 Pattern Limit Count."
|
|
bitfld.long 0x0 16.--17. "TMR10TMODE,Counter/Timer 10 Trigger Mode" "0: Trigger not enabled,1: Trigger on rising edge of TRIGSEL source,2: Trigger on falling edge of TRIGSEL source,3: Trigger on either edge of TRIGSEL source"
|
|
newline
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR10CLK,Counter/Timer 10 Clock Select."
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR10CLK,Counter/Timer 10 Clock Select."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR10CLK,Counter/Timer 10 Clock Select."
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR10FN,Counter/Timer 10 Function Select."
|
|
newline
|
|
bitfld.long 0x0 1. "TMR10CLR,Counter/Timer Clear bit." "?,1: When written to a 1 the timer will automatically.."
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR10FN,Counter/Timer 10 Function Select. For all Functions CMP0 marks the end of timer cycle and thus restarts the timer."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR10FN,Counter/Timer 10 Function Select. For all Functions CMP0 marks the end of timer cycle and thus restarts the timer."
|
|
endif
|
|
bitfld.long 0x0 3. "TMR10POL1,Counter/Timer 10 output 1 polarity." "0: The polarity of the TMR10OUT1 pin is the same as..,1: The polarity of the TMR10OUT1 pin is the inverse.."
|
|
newline
|
|
bitfld.long 0x0 2. "TMR10POL0,Counter/Timer 10 output 0 polarity." "0: The polarity of the TMR10OUT0 pin is the same as..,1: The polarity of the TMR10OUT0 pin is the inverse.."
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 1. "TMR10CLR,Counter/Timer Clear bit." "0: Default value set to 0. Timer works normally.,1: When written to a 1 the timer will automatically.."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 1. "TMR10CLR,Counter/Timer Clear bit." "0: Default value set to 0. Timer works normally.,1: When written to a 1 the timer will automatically.."
|
|
endif
|
|
bitfld.long 0x0 0. "TMR10EN,Counter/Timer 10 Enable bit." "0: Counter/Timer 10 Disable.,1: Counter/Timer 10 Enable."
|
|
line.long 0x4 "TIMER10,This register holds the running time or event count for timer 10."
|
|
hexmask.long 0x4 0.--31. 1. "TIMER10,Counter/Timer 10"
|
|
line.long 0x8 "TMR10CMP0,This contains the Compare limits for timer 10. This is the primary comparator that can be used to mark the END of a timer cycle (and thus restart the timer for repeat modes)"
|
|
hexmask.long 0x8 0.--31. 1. "TMR10CMP0,Counter/Timer 10 End Compare Register. For MEASURE mode indicates the high phase sample count."
|
|
line.long 0xC "TMR10CMP1,This comparator is used as a secondary compare count for modes that generate pulses. For MEASURE mode indicates the low phase sample count."
|
|
hexmask.long 0xC 0.--31. 1. "TMR10CMP1,Holds the secondary comparator that can be used to generate a PWM or generate secondary pulses. CMP0 should ALWAYS be used first."
|
|
line.long 0x10 "MODE10,The mode register contains optional mode controls for the timer"
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x10 8.--15. 1. "TMR10TRIGSEL,Counter/Timer 10 Trigger Source Selection"
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x10 8.--15. 1. "TMR10TRIGSEL,Counter/Timer 10 Trigger Source Selection"
|
|
endif
|
|
group.long 0x360++0x13
|
|
line.long 0x0 "CTRL11,This includes the Control bit fields for timer 11."
|
|
hexmask.long.byte 0x0 24.--31. 1. "TMR11LMT,Counter/Timer 11 Pattern Limit Count."
|
|
bitfld.long 0x0 16.--17. "TMR11TMODE,Counter/Timer 11 Trigger Mode" "0: Trigger not enabled,1: Trigger on rising edge of TRIGSEL source,2: Trigger on falling edge of TRIGSEL source,3: Trigger on either edge of TRIGSEL source"
|
|
newline
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR11CLK,Counter/Timer 11 Clock Select."
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR11CLK,Counter/Timer 11 Clock Select."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR11CLK,Counter/Timer 11 Clock Select."
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR11FN,Counter/Timer 11 Function Select."
|
|
newline
|
|
bitfld.long 0x0 1. "TMR11CLR,Counter/Timer Clear bit." "?,1: When written to a 1 the timer will automatically.."
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR11FN,Counter/Timer 11 Function Select. For all Functions CMP0 marks the end of timer cycle and thus restarts the timer."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR11FN,Counter/Timer 11 Function Select. For all Functions CMP0 marks the end of timer cycle and thus restarts the timer."
|
|
endif
|
|
bitfld.long 0x0 3. "TMR11POL1,Counter/Timer 11 output 1 polarity." "0: The polarity of the TMR11OUT1 pin is the same as..,1: The polarity of the TMR11OUT1 pin is the inverse.."
|
|
newline
|
|
bitfld.long 0x0 2. "TMR11POL0,Counter/Timer 11 output 0 polarity." "0: The polarity of the TMR11OUT0 pin is the same as..,1: The polarity of the TMR11OUT0 pin is the inverse.."
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 1. "TMR11CLR,Counter/Timer Clear bit." "0: Default value set to 0. Timer works normally.,1: When written to a 1 the timer will automatically.."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 1. "TMR11CLR,Counter/Timer Clear bit." "0: Default value set to 0. Timer works normally.,1: When written to a 1 the timer will automatically.."
|
|
endif
|
|
bitfld.long 0x0 0. "TMR11EN,Counter/Timer 11 Enable bit." "0: Counter/Timer 11 Disable.,1: Counter/Timer 11 Enable."
|
|
line.long 0x4 "TIMER11,This register holds the running time or event count for timer 11."
|
|
hexmask.long 0x4 0.--31. 1. "TIMER11,Counter/Timer 11"
|
|
line.long 0x8 "TMR11CMP0,This contains the Compare limits for timer 11. This is the primary comparator that can be used to mark the END of a timer cycle (and thus restart the timer for repeat modes)"
|
|
hexmask.long 0x8 0.--31. 1. "TMR11CMP0,Counter/Timer 11 End Compare Register. For MEASURE mode indicates the high phase sample count."
|
|
line.long 0xC "TMR11CMP1,This comparator is used as a secondary compare count for modes that generate pulses. For MEASURE mode indicates the low phase sample count."
|
|
hexmask.long 0xC 0.--31. 1. "TMR11CMP1,Holds the secondary comparator that can be used to generate a PWM or generate secondary pulses. CMP0 should ALWAYS be used first."
|
|
line.long 0x10 "MODE11,The mode register contains optional mode controls for the timer"
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x10 8.--15. 1. "TMR11TRIGSEL,Counter/Timer 11 Trigger Source Selection"
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x10 8.--15. 1. "TMR11TRIGSEL,Counter/Timer 11 Trigger Source Selection"
|
|
endif
|
|
group.long 0x380++0x13
|
|
line.long 0x0 "CTRL12,This includes the Control bit fields for timer 12."
|
|
hexmask.long.byte 0x0 24.--31. 1. "TMR12LMT,Counter/Timer 12 Pattern Limit Count."
|
|
bitfld.long 0x0 16.--17. "TMR12TMODE,Counter/Timer 12 Trigger Mode" "0: Trigger not enabled,1: Trigger on rising edge of TRIGSEL source,2: Trigger on falling edge of TRIGSEL source,3: Trigger on either edge of TRIGSEL source"
|
|
newline
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR12CLK,Counter/Timer 12 Clock Select."
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR12CLK,Counter/Timer 12 Clock Select."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR12CLK,Counter/Timer 12 Clock Select."
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR12FN,Counter/Timer 12 Function Select."
|
|
newline
|
|
bitfld.long 0x0 1. "TMR12CLR,Counter/Timer Clear bit." "?,1: When written to a 1 the timer will automatically.."
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR12FN,Counter/Timer 12 Function Select. For all Functions CMP0 marks the end of timer cycle and thus restarts the timer."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR12FN,Counter/Timer 12 Function Select. For all Functions CMP0 marks the end of timer cycle and thus restarts the timer."
|
|
endif
|
|
bitfld.long 0x0 3. "TMR12POL1,Counter/Timer 12 output 1 polarity." "0: The polarity of the TMR12OUT1 pin is the same as..,1: The polarity of the TMR12OUT1 pin is the inverse.."
|
|
newline
|
|
bitfld.long 0x0 2. "TMR12POL0,Counter/Timer 12 output 0 polarity." "0: The polarity of the TMR12OUT0 pin is the same as..,1: The polarity of the TMR12OUT0 pin is the inverse.."
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 1. "TMR12CLR,Counter/Timer Clear bit." "0: Default value set to 0. Timer works normally.,1: When written to a 1 the timer will automatically.."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 1. "TMR12CLR,Counter/Timer Clear bit." "0: Default value set to 0. Timer works normally.,1: When written to a 1 the timer will automatically.."
|
|
endif
|
|
bitfld.long 0x0 0. "TMR12EN,Counter/Timer 12 Enable bit." "0: Counter/Timer 12 Disable.,1: Counter/Timer 12 Enable."
|
|
line.long 0x4 "TIMER12,This register holds the running time or event count for timer 12."
|
|
hexmask.long 0x4 0.--31. 1. "TIMER12,Counter/Timer 12"
|
|
line.long 0x8 "TMR12CMP0,This contains the Compare limits for timer 12. This is the primary comparator that can be used to mark the END of a timer cycle (and thus restart the timer for repeat modes)"
|
|
hexmask.long 0x8 0.--31. 1. "TMR12CMP0,Counter/Timer 12 End Compare Register. For MEASURE mode indicates the high phase sample count."
|
|
line.long 0xC "TMR12CMP1,This comparator is used as a secondary compare count for modes that generate pulses. For MEASURE mode indicates the low phase sample count."
|
|
hexmask.long 0xC 0.--31. 1. "TMR12CMP1,Holds the secondary comparator that can be used to generate a PWM or generate secondary pulses. CMP0 should ALWAYS be used first."
|
|
line.long 0x10 "MODE12,The mode register contains optional mode controls for the timer"
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x10 8.--15. 1. "TMR12TRIGSEL,Counter/Timer 12 Trigger Source Selection"
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x10 8.--15. 1. "TMR12TRIGSEL,Counter/Timer 12 Trigger Source Selection"
|
|
endif
|
|
group.long 0x3A0++0x13
|
|
line.long 0x0 "CTRL13,This includes the Control bit fields for timer 13."
|
|
hexmask.long.byte 0x0 24.--31. 1. "TMR13LMT,Counter/Timer 13 Pattern Limit Count."
|
|
bitfld.long 0x0 16.--17. "TMR13TMODE,Counter/Timer 13 Trigger Mode" "0: Trigger not enabled,1: Trigger on rising edge of TRIGSEL source,2: Trigger on falling edge of TRIGSEL source,3: Trigger on either edge of TRIGSEL source"
|
|
newline
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR13CLK,Counter/Timer 13 Clock Select."
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR13CLK,Counter/Timer 13 Clock Select."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR13CLK,Counter/Timer 13 Clock Select."
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR13FN,Counter/Timer 13 Function Select."
|
|
newline
|
|
bitfld.long 0x0 1. "TMR13CLR,Counter/Timer Clear bit." "?,1: When written to a 1 the timer will automatically.."
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR13FN,Counter/Timer 13 Function Select. For all Functions CMP0 marks the end of timer cycle and thus restarts the timer."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR13FN,Counter/Timer 13 Function Select. For all Functions CMP0 marks the end of timer cycle and thus restarts the timer."
|
|
endif
|
|
bitfld.long 0x0 3. "TMR13POL1,Counter/Timer 13 output 1 polarity." "0: The polarity of the TMR13OUT1 pin is the same as..,1: The polarity of the TMR13OUT1 pin is the inverse.."
|
|
newline
|
|
bitfld.long 0x0 2. "TMR13POL0,Counter/Timer 13 output 0 polarity." "0: The polarity of the TMR13OUT0 pin is the same as..,1: The polarity of the TMR13OUT0 pin is the inverse.."
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 1. "TMR13CLR,Counter/Timer Clear bit." "0: Default value set to 0. Timer works normally.,1: When written to a 1 the timer will automatically.."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 1. "TMR13CLR,Counter/Timer Clear bit." "0: Default value set to 0. Timer works normally.,1: When written to a 1 the timer will automatically.."
|
|
endif
|
|
bitfld.long 0x0 0. "TMR13EN,Counter/Timer 13 Enable bit." "0: Counter/Timer 13 Disable.,1: Counter/Timer 13 Enable."
|
|
line.long 0x4 "TIMER13,This register holds the running time or event count for timer 13."
|
|
hexmask.long 0x4 0.--31. 1. "TIMER13,Counter/Timer 13"
|
|
line.long 0x8 "TMR13CMP0,This contains the Compare limits for timer 13. This is the primary comparator that can be used to mark the END of a timer cycle (and thus restart the timer for repeat modes)"
|
|
hexmask.long 0x8 0.--31. 1. "TMR13CMP0,Counter/Timer 13 End Compare Register. For MEASURE mode indicates the high phase sample count."
|
|
line.long 0xC "TMR13CMP1,This comparator is used as a secondary compare count for modes that generate pulses. For MEASURE mode indicates the low phase sample count."
|
|
hexmask.long 0xC 0.--31. 1. "TMR13CMP1,Holds the secondary comparator that can be used to generate a PWM or generate secondary pulses. CMP0 should ALWAYS be used first."
|
|
line.long 0x10 "MODE13,The mode register contains optional mode controls for the timer"
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x10 8.--15. 1. "TMR13TRIGSEL,Counter/Timer 13 Trigger Source Selection"
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x10 8.--15. 1. "TMR13TRIGSEL,Counter/Timer 13 Trigger Source Selection"
|
|
endif
|
|
group.long 0x3C0++0x13
|
|
line.long 0x0 "CTRL14,This includes the Control bit fields for timer 14."
|
|
hexmask.long.byte 0x0 24.--31. 1. "TMR14LMT,Counter/Timer 14 Pattern Limit Count."
|
|
bitfld.long 0x0 16.--17. "TMR14TMODE,Counter/Timer 14 Trigger Mode" "0: Trigger not enabled,1: Trigger on rising edge of TRIGSEL source,2: Trigger on falling edge of TRIGSEL source,3: Trigger on either edge of TRIGSEL source"
|
|
newline
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR14CLK,Counter/Timer 14 Clock Select."
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR14CLK,Counter/Timer 14 Clock Select."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR14CLK,Counter/Timer 14 Clock Select."
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR14FN,Counter/Timer 14 Function Select."
|
|
newline
|
|
bitfld.long 0x0 1. "TMR14CLR,Counter/Timer Clear bit." "?,1: When written to a 1 the timer will automatically.."
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR14FN,Counter/Timer 14 Function Select. For all Functions CMP0 marks the end of timer cycle and thus restarts the timer."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR14FN,Counter/Timer 14 Function Select. For all Functions CMP0 marks the end of timer cycle and thus restarts the timer."
|
|
endif
|
|
bitfld.long 0x0 3. "TMR14POL1,Counter/Timer 14 output 1 polarity." "0: The polarity of the TMR14OUT1 pin is the same as..,1: The polarity of the TMR14OUT1 pin is the inverse.."
|
|
newline
|
|
bitfld.long 0x0 2. "TMR14POL0,Counter/Timer 14 output 0 polarity." "0: The polarity of the TMR14OUT0 pin is the same as..,1: The polarity of the TMR14OUT0 pin is the inverse.."
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 1. "TMR14CLR,Counter/Timer Clear bit." "0: Default value set to 0. Timer works normally.,1: When written to a 1 the timer will automatically.."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 1. "TMR14CLR,Counter/Timer Clear bit." "0: Default value set to 0. Timer works normally.,1: When written to a 1 the timer will automatically.."
|
|
endif
|
|
bitfld.long 0x0 0. "TMR14EN,Counter/Timer 14 Enable bit." "0: Counter/Timer 14 Disable.,1: Counter/Timer 14 Enable."
|
|
line.long 0x4 "TIMER14,This register holds the running time or event count for timer 14."
|
|
hexmask.long 0x4 0.--31. 1. "TIMER14,Counter/Timer 14"
|
|
line.long 0x8 "TMR14CMP0,This contains the Compare limits for timer 14. This is the primary comparator that can be used to mark the END of a timer cycle (and thus restart the timer for repeat modes)"
|
|
hexmask.long 0x8 0.--31. 1. "TMR14CMP0,Counter/Timer 14 End Compare Register. For MEASURE mode indicates the high phase sample count."
|
|
line.long 0xC "TMR14CMP1,This comparator is used as a secondary compare count for modes that generate pulses. For MEASURE mode indicates the low phase sample count."
|
|
hexmask.long 0xC 0.--31. 1. "TMR14CMP1,Holds the secondary comparator that can be used to generate a PWM or generate secondary pulses. CMP0 should ALWAYS be used first."
|
|
line.long 0x10 "MODE14,The mode register contains optional mode controls for the timer"
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x10 8.--15. 1. "TMR14TRIGSEL,Counter/Timer 14 Trigger Source Selection"
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x10 8.--15. 1. "TMR14TRIGSEL,Counter/Timer 14 Trigger Source Selection"
|
|
endif
|
|
group.long 0x3E0++0x13
|
|
line.long 0x0 "CTRL15,This includes the Control bit fields for timer 15."
|
|
hexmask.long.byte 0x0 24.--31. 1. "TMR15LMT,Counter/Timer 15 Pattern Limit Count."
|
|
bitfld.long 0x0 16.--17. "TMR15TMODE,Counter/Timer 15 Trigger Mode" "0: Trigger not enabled,1: Trigger on rising edge of TRIGSEL source,2: Trigger on falling edge of TRIGSEL source,3: Trigger on either edge of TRIGSEL source"
|
|
newline
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR15CLK,Counter/Timer 15 Clock Select."
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR15CLK,Counter/Timer 15 Clock Select."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMR15CLK,Counter/Timer 15 Clock Select."
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR15FN,Counter/Timer 15 Function Select."
|
|
newline
|
|
bitfld.long 0x0 1. "TMR15CLR,Counter/Timer Clear bit." "?,1: When written to a 1 the timer will automatically.."
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR15FN,Counter/Timer 15 Function Select. For all Functions CMP0 marks the end of timer cycle and thus restarts the timer."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "TMR15FN,Counter/Timer 15 Function Select. For all Functions CMP0 marks the end of timer cycle and thus restarts the timer."
|
|
endif
|
|
bitfld.long 0x0 3. "TMR15POL1,Counter/Timer 15 output 1 polarity." "0: The polarity of the TMR15OUT1 pin is the same as..,1: The polarity of the TMR15OUT1 pin is the inverse.."
|
|
newline
|
|
bitfld.long 0x0 2. "TMR15POL0,Counter/Timer 15 output 0 polarity." "0: The polarity of the TMR15OUT0 pin is the same as..,1: The polarity of the TMR15OUT0 pin is the inverse.."
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 1. "TMR15CLR,Counter/Timer Clear bit." "0: Default value set to 0. Timer works normally.,1: When written to a 1 the timer will automatically.."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x0 1. "TMR15CLR,Counter/Timer Clear bit." "0: Default value set to 0. Timer works normally.,1: When written to a 1 the timer will automatically.."
|
|
endif
|
|
bitfld.long 0x0 0. "TMR15EN,Counter/Timer 15 Enable bit." "0: Counter/Timer 15 Disable.,1: Counter/Timer 15 Enable."
|
|
line.long 0x4 "TIMER15,This register holds the running time or event count for timer 15."
|
|
hexmask.long 0x4 0.--31. 1. "TIMER15,Counter/Timer 15"
|
|
line.long 0x8 "TMR15CMP0,This contains the Compare limits for timer 15. This is the primary comparator that can be used to mark the END of a timer cycle (and thus restart the timer for repeat modes)"
|
|
hexmask.long 0x8 0.--31. 1. "TMR15CMP0,Counter/Timer 15 End Compare Register. For MEASURE mode indicates the high phase sample count."
|
|
line.long 0xC "TMR15CMP1,This comparator is used as a secondary compare count for modes that generate pulses. For MEASURE mode indicates the low phase sample count."
|
|
hexmask.long 0xC 0.--31. 1. "TMR15CMP1,Holds the secondary comparator that can be used to generate a PWM or generate secondary pulses. CMP0 should ALWAYS be used first."
|
|
line.long 0x10 "MODE15,The mode register contains optional mode controls for the timer"
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
hexmask.long.byte 0x10 8.--15. 1. "TMR15TRIGSEL,Counter/Timer 15 Trigger Source Selection"
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
hexmask.long.byte 0x10 8.--15. 1. "TMR15TRIGSEL,Counter/Timer 15 Trigger Source Selection"
|
|
endif
|
|
sif (cpuis("AMA4B2KP")||cpuis("AMAP42KP"))
|
|
group.long 0x3F4++0x7
|
|
line.long 0x0 "TMR15LMTVAL,This is an internal counter in the hardware that counts down from TMR_LMT to 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TMR15LMTVAL,Counter/Timer 15 Limit Readback"
|
|
line.long 0x4 "TIMERSPARES,Timer Spare Regs"
|
|
hexmask.long 0x4 0.--31. 1. "TMRSPARES,Placeholer spare registes that can be used as needed for future use"
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
group.long 0x3F8++0x3
|
|
line.long 0x0 "TIMERSPARES,Timer Spare Regs"
|
|
hexmask.long 0x0 0.--31. 1. "TMRSPARES,Placeholer spare registes that can be used as needed for future use"
|
|
endif
|
|
tree.end
|
|
tree "UART (Universal Asynchronous Receiver/Transmitter)"
|
|
base ad:0x0
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
tree "UART0"
|
|
base ad:0x4001C000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "DR,UART Data"
|
|
bitfld.long 0x0 11. "OEDATA,Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it." "0: No error on UART OEDATA overrun error indicator.,1: Error on UART OEDATA overrun error indicator."
|
|
bitfld.long 0x0 10. "BEDATA,Break error. This bit is set to 1 if a break condition was detected indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start data parity and stop bits). In FIFO mode this error is.." "0: No error on UART BEDATA break error indicator.,1: Error on UART BEDATA break error indicator."
|
|
newline
|
|
bitfld.long 0x0 9. "PEDATA,Parity error. When set to 1 it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register UARTLCRH select. In FIFO mode this error is associated with the character.." "0: No error on UART PEDATA parity error indicator.,1: Error on UART PEDATA parity error indicator."
|
|
bitfld.long 0x0 8. "FEDATA,Framing error. When set to 1 it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode this error is associated with the character at the top of the FIFO." "0: No error on UART FEDATA framing error indicator.,1: Error on UART FEDATA framing error indicator."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,Receive (read) data character. Transmit (write) data character."
|
|
line.long 0x4 "RSR,UART Status"
|
|
bitfld.long 0x4 3. "OESTAT,Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full only the contents of the.." "0: No error on UART OESTAT overrun error indicator.,1: Error on UART OESTAT overrun error indicator."
|
|
bitfld.long 0x4 2. "BESTAT,Break error. This bit is set to 1 if a break condition was detected indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start data parity and stop bits). This bit is cleared to 0 after.." "0: No error on UART BESTAT break error indicator.,1: Error on UART BESTAT break error indicator."
|
|
newline
|
|
bitfld.long 0x4 1. "PESTAT,Parity error. When set to 1 it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register UARTLCRH select. This bit is cleared to 0 by a write to UARTECR. In FIFO.." "0: No error on UART PESTAT parity error indicator.,1: Error on UART PESTAT parity error indicator."
|
|
bitfld.long 0x4 0. "FESTAT,Framing error. When set to 1 it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode this error is associated with the character at the top of.." "0: No error on UART FESTAT framing error indicator.,1: Error on UART FESTAT framing error indicator."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "FR,Flags"
|
|
bitfld.long 0x0 8. "TXBUSY,This bit holds the transmit BUSY indicator." "0,1"
|
|
bitfld.long 0x0 7. "TXFE,Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register UARTLCRH. If the FIFO is disabled this bit is set when the transmit holding register is empty. If the FIFO is enabled the TXFE bit is.." "?,1: Transmit fifo is empty."
|
|
newline
|
|
bitfld.long 0x0 6. "RXFF,Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCRH Register. If the FIFO is disabled this bit is set when the receive holding register is full. If the FIFO is enabled the RXFF bit is set when the receive.." "?,1: Receive fifo is full."
|
|
bitfld.long 0x0 5. "TXFF,Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCRH Register. If the FIFO is disabled this bit is set when the transmit holding register is full. If the FIFO is enabled the TXFF bit is set when the.." "?,1: Transmit fifo is full."
|
|
newline
|
|
bitfld.long 0x0 4. "RXFE,Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCRH Register. If the FIFO is disabled this bit is set when the receive holding register is empty. If the FIFO is enabled the RXFE bit is set when the.." "?,1: Receive fifo is empty."
|
|
bitfld.long 0x0 3. "BUSY,UART busy. If this bit is set to 1 the UART is busy transmitting data. This bit remains set until the complete byte including all the stop bits has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty .." "?,1: UART busy indicator."
|
|
newline
|
|
bitfld.long 0x0 2. "DCD,Data carrier detect. This bit is the complement of the UART data carrier detect nUARTDCD modem status input. That is the bit is 1 when nUARTDCD is LOW." "?,1: Data carrier detect detected."
|
|
bitfld.long 0x0 1. "DSR,Data set ready. This bit is the complement of the UART data set ready nUARTDSR modem status input. That is the bit is 1 when nUARTDSR is LOW." "?,1: Data set ready."
|
|
newline
|
|
bitfld.long 0x0 0. "CTS,Clear to send. This bit is the complement of the UART clear to send nUARTCTS modem status input. That is the bit is 1 when nUARTCTS is LOW." "?,1: Clear to send is indicated."
|
|
group.long 0x20++0x27
|
|
line.long 0x0 "ILPR,IrDA Counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ILPDVSR,8-bit low-power divisor value. These bits are cleared to 0 at reset. Programming a zero value results in no IrLPBaud16 pulses being generated."
|
|
line.long 0x4 "IBRD,Integer Baud Rate Divisor"
|
|
hexmask.long.word 0x4 0.--15. 1. "DIVINT,These bits hold the baud integer divisor. These bits are cleared to 0 on reset."
|
|
line.long 0x8 "FBRD,Fractional Baud Rate Divisor"
|
|
hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,These bits hold the baud fractional divisor. These bits are cleared to 0 on reset."
|
|
line.long 0xC "LCRH,Line Control High"
|
|
bitfld.long 0xC 7. "SPS,This bit holds the stick parity select. If the EPS bit is 0 then the parity bit is transmitted and checked as a 1. If the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity.." "0,1"
|
|
bitfld.long 0xC 5.--6. "WLEN,These bits hold the write length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 4. "FEN,This bit holds the FIFO enable. 0 = FIFOs are disabled (character mode) that is the FIFOs become 1-byte-deep holding registers. 1 = transmit and receive FIFO buffers are enabled (FIFO mode)." "0: FIFOs are disabled,1: transmit and receive FIFO buffers are enabled"
|
|
bitfld.long 0xC 3. "STP2,This bit holds the two stop bits select. If this bit is set to 1 two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received." "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "EPS,This bit holds the even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates.." "0: odd parity,1: even parity"
|
|
bitfld.long 0xC 1. "PEN,This bit holds the parity enable. 0 = parity is disabled and no parity bit added to the data frame. 1 = parity checking and generation is enabled." "0: parity is disabled and no parity bit added to..,1: parity checking and generation is enabled"
|
|
newline
|
|
bitfld.long 0xC 0. "BRK,This bit holds the break set. If this bit is set to 1 a low-level is continually output on the UARTTXD output after completing transmission of the current character. For the proper execution of the break command the software must set this bit for.." "0,1"
|
|
line.long 0x10 "CR,Control"
|
|
bitfld.long 0x10 15. "CTSEN,This bit enables CTS hardware flow control. If this bit is set to 1 CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted." "0,1"
|
|
bitfld.long 0x10 14. "RTSEN,This bit enables RTS hardware flow control. If this bit is set to 1 RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received." "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "OUT2,This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is when the bit is programmed to a 1 the output is 0. For DTE this can be used as Ring Indicator (RI)." "0,1"
|
|
bitfld.long 0x10 12. "OUT1,This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD)." "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "RTS,This bit enables request to send. This bit is the complement of the UART request to send nUARTRTS modem status output. That is when the bit is programmed to a 1 then nUARTRTS is LOW." "0,1"
|
|
bitfld.long 0x10 10. "DTR,This bit enables data transmit ready. This bit is the complement of the UART data transmit ready nUARTDTR modem status output. That is when the bit is programmed to a 1 then nUARTDTR is LOW." "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "RXE,This bit is the receive enable. If this bit is set to 1 the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of.." "0,1"
|
|
bitfld.long 0x10 8. "TXE,This bit is the transmit enable. If this bit is set to 1 the transmit section of the UART is enabled. Data transmission occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle.." "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "LBE,This bit is the loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register UARTTCR is set to 1 then the nSIROUT path is inverted and fed through to the SIRIN path. The SIRTEST bit in the.." "0,1"
|
|
bitfld.long 0x10 4.--6. "CLKSEL,This bitfield is the UART clock select." "0: No UART clock. This is the low power default.,1: 24 MHz clock.,2: 12 MHz clock.,3: 6 MHz clock.,4: 3 MHz clock.,5: Reserved.,?,?"
|
|
newline
|
|
bitfld.long 0x10 3. "CLKEN,This bit is the UART clock enable." "0,1"
|
|
bitfld.long 0x10 2. "SIRLP,This bit is the SIR low power select. This bit selects the IrDA encoding mode. If this bit is cleared to 0 low-level bits are transmitted as an active high pulse with a width of 3/16th of the bit period. If this bit is set to 1 low-level bits are.." "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "SIREN,This bit is the SIR ENDEC enable. If this bit is set to 1 the IrDA SIR ENDEC is enabled. This bit has no effect if the UART is not enabled by bit 0 being set to 1. When the IrDA SIR ENDEC is enabled data is transmitted and received on nSIROUT and.." "0,1"
|
|
bitfld.long 0x10 0. "UARTEN,This bit is the UART enable. 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either.." "0: UART is disabled,1: the UART is enabled"
|
|
line.long 0x14 "IFLS,FIFO Interrupt Level Select"
|
|
bitfld.long 0x14 3.--5. "RXIFLSEL,These bits hold the receive FIFO interrupt level." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 0.--2. "TXIFLSEL,These bits hold the transmit FIFO interrupt level." "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "IER,Interrupt Enable"
|
|
bitfld.long 0x18 10. "OEIM,This bit holds the overflow interrupt enable." "0,1"
|
|
bitfld.long 0x18 9. "BEIM,This bit holds the break error interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 8. "PEIM,This bit holds the parity error interrupt enable." "0,1"
|
|
bitfld.long 0x18 7. "FEIM,This bit holds the framing error interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 6. "RTIM,This bit holds the receive timeout interrupt enable." "0,1"
|
|
bitfld.long 0x18 5. "TXIM,This bit holds the transmit interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 4. "RXIM,This bit holds the receive interrupt enable." "0,1"
|
|
bitfld.long 0x18 3. "DSRMIM,This bit holds the modem DSR interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 2. "DCDMIM,This bit holds the modem DCD interrupt enable." "0,1"
|
|
bitfld.long 0x18 1. "CTSMIM,This bit holds the modem CTS interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXCMPMIM,This bit holds the modem TXCMP interrupt enable." "0,1"
|
|
line.long 0x1C "IES,Interrupt Status"
|
|
bitfld.long 0x1C 10. "OERIS,This bit holds the overrun interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt." "0,1"
|
|
bitfld.long 0x1C 9. "BERIS,This bit holds the break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 8. "PERIS,This bit holds the parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt." "0,1"
|
|
bitfld.long 0x1C 7. "FERIS,This bit holds the framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 6. "RTRIS,This bit holds the receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt." "0,1"
|
|
bitfld.long 0x1C 5. "TXRIS,This bit holds the transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 4. "RXRIS,This bit holds the receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt." "0,1"
|
|
bitfld.long 0x1C 3. "DSRMRIS,This bit holds the nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 2. "DCDMRIS,This bit holds the nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt." "0,1"
|
|
bitfld.long 0x1C 1. "CTSMRIS,This bit holds the nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "TXCMPMRIS,This bit holds the modem TXCMP interrupt status." "0,1"
|
|
line.long 0x20 "MIS,Masked Interrupt Status"
|
|
bitfld.long 0x20 10. "OEMIS,This bit holds the overrun interrupt status masked. Returns the masked interrupt state of the UARTOEINTR interrupt." "0,1"
|
|
bitfld.long 0x20 9. "BEMIS,This bit holds the break error interrupt status masked. Returns the masked interrupt state of the UARTBEINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x20 8. "PEMIS,This bit holds the parity error interrupt status masked. Returns the masked interrupt state of the UARTPEINTR interrupt." "0,1"
|
|
bitfld.long 0x20 7. "FEMIS,This bit holds the framing error interrupt status masked. Returns the masked interrupt state of the UARTFEINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x20 6. "RTMIS,This bit holds the receive timeout interrupt status masked. Returns the masked interrupt state of the UARTRTINTR interrupt." "0,1"
|
|
bitfld.long 0x20 5. "TXMIS,This bit holds the transmit interrupt status masked. Returns the masked interrupt state of the UARTTXINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x20 4. "RXMIS,This bit holds the receive interrupt status masked. Returns the masked interrupt state of the UARTRXINTR interrupt." "0,1"
|
|
bitfld.long 0x20 3. "DSRMMIS,This bit holds the nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x20 2. "DCDMMIS,This bit holds the nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt." "0,1"
|
|
bitfld.long 0x20 1. "CTSMMIS,This bit holds the nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x20 0. "TXCMPMMIS,This bit holds the modem TXCMP interrupt status masked." "0,1"
|
|
line.long 0x24 "IEC,Interrupt Clear"
|
|
bitfld.long 0x24 10. "OEIC,This bit holds the overrun interrupt clear. Clears the UARTOEINTR interrupt." "0,1"
|
|
bitfld.long 0x24 9. "BEIC,This bit holds the break error interrupt clear. Clears the UARTBEINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x24 8. "PEIC,This bit holds the parity error interrupt clear. Clears the UARTPEINTR interrupt." "0,1"
|
|
bitfld.long 0x24 7. "FEIC,This bit holds the framing error interrupt clear. Clears the UARTFEINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x24 6. "RTIC,This bit holds the receive timeout interrupt clear. Clears the UARTRTINTR interrupt." "0,1"
|
|
bitfld.long 0x24 5. "TXIC,This bit holds the transmit interrupt clear. Clears the UARTTXINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x24 4. "RXIC,This bit holds the receive interrupt clear. Clears the UARTRXINTR interrupt." "0,1"
|
|
bitfld.long 0x24 3. "DSRMIC,This bit holds the nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x24 2. "DCDMIC,This bit holds the nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt." "0,1"
|
|
bitfld.long 0x24 1. "CTSMIC,This bit holds the nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x24 0. "TXCMPMIC,This bit holds the modem TXCMP interrupt clear." "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
tree "UART1"
|
|
base ad:0x4001D000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "DR,UART Data"
|
|
bitfld.long 0x0 11. "OEDATA,Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it." "0: No error on UART OEDATA overrun error indicator.,1: Error on UART OEDATA overrun error indicator."
|
|
bitfld.long 0x0 10. "BEDATA,Break error. This bit is set to 1 if a break condition was detected indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start data parity and stop bits). In FIFO mode this error is.." "0: No error on UART BEDATA break error indicator.,1: Error on UART BEDATA break error indicator."
|
|
newline
|
|
bitfld.long 0x0 9. "PEDATA,Parity error. When set to 1 it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register UARTLCRH select. In FIFO mode this error is associated with the character.." "0: No error on UART PEDATA parity error indicator.,1: Error on UART PEDATA parity error indicator."
|
|
bitfld.long 0x0 8. "FEDATA,Framing error. When set to 1 it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode this error is associated with the character at the top of the FIFO." "0: No error on UART FEDATA framing error indicator.,1: Error on UART FEDATA framing error indicator."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,Receive (read) data character. Transmit (write) data character."
|
|
line.long 0x4 "RSR,UART Status"
|
|
bitfld.long 0x4 3. "OESTAT,Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full only the contents of the.." "0: No error on UART OESTAT overrun error indicator.,1: Error on UART OESTAT overrun error indicator."
|
|
bitfld.long 0x4 2. "BESTAT,Break error. This bit is set to 1 if a break condition was detected indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start data parity and stop bits). This bit is cleared to 0 after.." "0: No error on UART BESTAT break error indicator.,1: Error on UART BESTAT break error indicator."
|
|
newline
|
|
bitfld.long 0x4 1. "PESTAT,Parity error. When set to 1 it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register UARTLCRH select. This bit is cleared to 0 by a write to UARTECR. In FIFO.." "0: No error on UART PESTAT parity error indicator.,1: Error on UART PESTAT parity error indicator."
|
|
bitfld.long 0x4 0. "FESTAT,Framing error. When set to 1 it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode this error is associated with the character at the top of.." "0: No error on UART FESTAT framing error indicator.,1: Error on UART FESTAT framing error indicator."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "FR,Flags"
|
|
bitfld.long 0x0 8. "TXBUSY,This bit holds the transmit BUSY indicator." "0,1"
|
|
bitfld.long 0x0 7. "TXFE,Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register UARTLCRH. If the FIFO is disabled this bit is set when the transmit holding register is empty. If the FIFO is enabled the TXFE bit is.." "?,1: Transmit fifo is empty."
|
|
newline
|
|
bitfld.long 0x0 6. "RXFF,Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCRH Register. If the FIFO is disabled this bit is set when the receive holding register is full. If the FIFO is enabled the RXFF bit is set when the receive.." "?,1: Receive fifo is full."
|
|
bitfld.long 0x0 5. "TXFF,Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCRH Register. If the FIFO is disabled this bit is set when the transmit holding register is full. If the FIFO is enabled the TXFF bit is set when the.." "?,1: Transmit fifo is full."
|
|
newline
|
|
bitfld.long 0x0 4. "RXFE,Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCRH Register. If the FIFO is disabled this bit is set when the receive holding register is empty. If the FIFO is enabled the RXFE bit is set when the.." "?,1: Receive fifo is empty."
|
|
bitfld.long 0x0 3. "BUSY,UART busy. If this bit is set to 1 the UART is busy transmitting data. This bit remains set until the complete byte including all the stop bits has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty .." "?,1: UART busy indicator."
|
|
newline
|
|
bitfld.long 0x0 2. "DCD,Data carrier detect. This bit is the complement of the UART data carrier detect nUARTDCD modem status input. That is the bit is 1 when nUARTDCD is LOW." "?,1: Data carrier detect detected."
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|
bitfld.long 0x0 1. "DSR,Data set ready. This bit is the complement of the UART data set ready nUARTDSR modem status input. That is the bit is 1 when nUARTDSR is LOW." "?,1: Data set ready."
|
|
newline
|
|
bitfld.long 0x0 0. "CTS,Clear to send. This bit is the complement of the UART clear to send nUARTCTS modem status input. That is the bit is 1 when nUARTCTS is LOW." "?,1: Clear to send is indicated."
|
|
group.long 0x20++0x27
|
|
line.long 0x0 "ILPR,IrDA Counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ILPDVSR,8-bit low-power divisor value. These bits are cleared to 0 at reset. Programming a zero value results in no IrLPBaud16 pulses being generated."
|
|
line.long 0x4 "IBRD,Integer Baud Rate Divisor"
|
|
hexmask.long.word 0x4 0.--15. 1. "DIVINT,These bits hold the baud integer divisor. These bits are cleared to 0 on reset."
|
|
line.long 0x8 "FBRD,Fractional Baud Rate Divisor"
|
|
hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,These bits hold the baud fractional divisor. These bits are cleared to 0 on reset."
|
|
line.long 0xC "LCRH,Line Control High"
|
|
bitfld.long 0xC 7. "SPS,This bit holds the stick parity select. If the EPS bit is 0 then the parity bit is transmitted and checked as a 1. If the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity.." "0,1"
|
|
bitfld.long 0xC 5.--6. "WLEN,These bits hold the write length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 4. "FEN,This bit holds the FIFO enable. 0 = FIFOs are disabled (character mode) that is the FIFOs become 1-byte-deep holding registers. 1 = transmit and receive FIFO buffers are enabled (FIFO mode)." "0: FIFOs are disabled,1: transmit and receive FIFO buffers are enabled"
|
|
bitfld.long 0xC 3. "STP2,This bit holds the two stop bits select. If this bit is set to 1 two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received." "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "EPS,This bit holds the even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates.." "0: odd parity,1: even parity"
|
|
bitfld.long 0xC 1. "PEN,This bit holds the parity enable. 0 = parity is disabled and no parity bit added to the data frame. 1 = parity checking and generation is enabled." "0: parity is disabled and no parity bit added to..,1: parity checking and generation is enabled"
|
|
newline
|
|
bitfld.long 0xC 0. "BRK,This bit holds the break set. If this bit is set to 1 a low-level is continually output on the UARTTXD output after completing transmission of the current character. For the proper execution of the break command the software must set this bit for.." "0,1"
|
|
line.long 0x10 "CR,Control"
|
|
bitfld.long 0x10 15. "CTSEN,This bit enables CTS hardware flow control. If this bit is set to 1 CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted." "0,1"
|
|
bitfld.long 0x10 14. "RTSEN,This bit enables RTS hardware flow control. If this bit is set to 1 RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received." "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "OUT2,This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is when the bit is programmed to a 1 the output is 0. For DTE this can be used as Ring Indicator (RI)." "0,1"
|
|
bitfld.long 0x10 12. "OUT1,This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD)." "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "RTS,This bit enables request to send. This bit is the complement of the UART request to send nUARTRTS modem status output. That is when the bit is programmed to a 1 then nUARTRTS is LOW." "0,1"
|
|
bitfld.long 0x10 10. "DTR,This bit enables data transmit ready. This bit is the complement of the UART data transmit ready nUARTDTR modem status output. That is when the bit is programmed to a 1 then nUARTDTR is LOW." "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "RXE,This bit is the receive enable. If this bit is set to 1 the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of.." "0,1"
|
|
bitfld.long 0x10 8. "TXE,This bit is the transmit enable. If this bit is set to 1 the transmit section of the UART is enabled. Data transmission occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle.." "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "LBE,This bit is the loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register UARTTCR is set to 1 then the nSIROUT path is inverted and fed through to the SIRIN path. The SIRTEST bit in the.." "0,1"
|
|
bitfld.long 0x10 4.--6. "CLKSEL,This bitfield is the UART clock select." "0: No UART clock. This is the low power default.,1: 24 MHz clock.,2: 12 MHz clock.,3: 6 MHz clock.,4: 3 MHz clock.,5: Reserved.,?,?"
|
|
newline
|
|
bitfld.long 0x10 3. "CLKEN,This bit is the UART clock enable." "0,1"
|
|
bitfld.long 0x10 2. "SIRLP,This bit is the SIR low power select. This bit selects the IrDA encoding mode. If this bit is cleared to 0 low-level bits are transmitted as an active high pulse with a width of 3/16th of the bit period. If this bit is set to 1 low-level bits are.." "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "SIREN,This bit is the SIR ENDEC enable. If this bit is set to 1 the IrDA SIR ENDEC is enabled. This bit has no effect if the UART is not enabled by bit 0 being set to 1. When the IrDA SIR ENDEC is enabled data is transmitted and received on nSIROUT and.." "0,1"
|
|
bitfld.long 0x10 0. "UARTEN,This bit is the UART enable. 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either.." "0: UART is disabled,1: the UART is enabled"
|
|
line.long 0x14 "IFLS,FIFO Interrupt Level Select"
|
|
bitfld.long 0x14 3.--5. "RXIFLSEL,These bits hold the receive FIFO interrupt level." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 0.--2. "TXIFLSEL,These bits hold the transmit FIFO interrupt level." "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "IER,Interrupt Enable"
|
|
bitfld.long 0x18 10. "OEIM,This bit holds the overflow interrupt enable." "0,1"
|
|
bitfld.long 0x18 9. "BEIM,This bit holds the break error interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 8. "PEIM,This bit holds the parity error interrupt enable." "0,1"
|
|
bitfld.long 0x18 7. "FEIM,This bit holds the framing error interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 6. "RTIM,This bit holds the receive timeout interrupt enable." "0,1"
|
|
bitfld.long 0x18 5. "TXIM,This bit holds the transmit interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 4. "RXIM,This bit holds the receive interrupt enable." "0,1"
|
|
bitfld.long 0x18 3. "DSRMIM,This bit holds the modem DSR interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 2. "DCDMIM,This bit holds the modem DCD interrupt enable." "0,1"
|
|
bitfld.long 0x18 1. "CTSMIM,This bit holds the modem CTS interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXCMPMIM,This bit holds the modem TXCMP interrupt enable." "0,1"
|
|
line.long 0x1C "IES,Interrupt Status"
|
|
bitfld.long 0x1C 10. "OERIS,This bit holds the overrun interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt." "0,1"
|
|
bitfld.long 0x1C 9. "BERIS,This bit holds the break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 8. "PERIS,This bit holds the parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt." "0,1"
|
|
bitfld.long 0x1C 7. "FERIS,This bit holds the framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 6. "RTRIS,This bit holds the receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt." "0,1"
|
|
bitfld.long 0x1C 5. "TXRIS,This bit holds the transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 4. "RXRIS,This bit holds the receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt." "0,1"
|
|
bitfld.long 0x1C 3. "DSRMRIS,This bit holds the nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 2. "DCDMRIS,This bit holds the nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt." "0,1"
|
|
bitfld.long 0x1C 1. "CTSMRIS,This bit holds the nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "TXCMPMRIS,This bit holds the modem TXCMP interrupt status." "0,1"
|
|
line.long 0x20 "MIS,Masked Interrupt Status"
|
|
bitfld.long 0x20 10. "OEMIS,This bit holds the overrun interrupt status masked. Returns the masked interrupt state of the UARTOEINTR interrupt." "0,1"
|
|
bitfld.long 0x20 9. "BEMIS,This bit holds the break error interrupt status masked. Returns the masked interrupt state of the UARTBEINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x20 8. "PEMIS,This bit holds the parity error interrupt status masked. Returns the masked interrupt state of the UARTPEINTR interrupt." "0,1"
|
|
bitfld.long 0x20 7. "FEMIS,This bit holds the framing error interrupt status masked. Returns the masked interrupt state of the UARTFEINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x20 6. "RTMIS,This bit holds the receive timeout interrupt status masked. Returns the masked interrupt state of the UARTRTINTR interrupt." "0,1"
|
|
bitfld.long 0x20 5. "TXMIS,This bit holds the transmit interrupt status masked. Returns the masked interrupt state of the UARTTXINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x20 4. "RXMIS,This bit holds the receive interrupt status masked. Returns the masked interrupt state of the UARTRXINTR interrupt." "0,1"
|
|
bitfld.long 0x20 3. "DSRMMIS,This bit holds the nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x20 2. "DCDMMIS,This bit holds the nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt." "0,1"
|
|
bitfld.long 0x20 1. "CTSMMIS,This bit holds the nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x20 0. "TXCMPMMIS,This bit holds the modem TXCMP interrupt status masked." "0,1"
|
|
line.long 0x24 "IEC,Interrupt Clear"
|
|
bitfld.long 0x24 10. "OEIC,This bit holds the overrun interrupt clear. Clears the UARTOEINTR interrupt." "0,1"
|
|
bitfld.long 0x24 9. "BEIC,This bit holds the break error interrupt clear. Clears the UARTBEINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x24 8. "PEIC,This bit holds the parity error interrupt clear. Clears the UARTPEINTR interrupt." "0,1"
|
|
bitfld.long 0x24 7. "FEIC,This bit holds the framing error interrupt clear. Clears the UARTFEINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x24 6. "RTIC,This bit holds the receive timeout interrupt clear. Clears the UARTRTINTR interrupt." "0,1"
|
|
bitfld.long 0x24 5. "TXIC,This bit holds the transmit interrupt clear. Clears the UARTTXINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x24 4. "RXIC,This bit holds the receive interrupt clear. Clears the UARTRXINTR interrupt." "0,1"
|
|
bitfld.long 0x24 3. "DSRMIC,This bit holds the nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x24 2. "DCDMIC,This bit holds the nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt." "0,1"
|
|
bitfld.long 0x24 1. "CTSMIC,This bit holds the nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x24 0. "TXCMPMIC,This bit holds the modem TXCMP interrupt clear." "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
tree "UART2"
|
|
base ad:0x4001E000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "DR,UART Data"
|
|
bitfld.long 0x0 11. "OEDATA,Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it." "0: No error on UART OEDATA overrun error indicator.,1: Error on UART OEDATA overrun error indicator."
|
|
bitfld.long 0x0 10. "BEDATA,Break error. This bit is set to 1 if a break condition was detected indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start data parity and stop bits). In FIFO mode this error is.." "0: No error on UART BEDATA break error indicator.,1: Error on UART BEDATA break error indicator."
|
|
newline
|
|
bitfld.long 0x0 9. "PEDATA,Parity error. When set to 1 it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register UARTLCRH select. In FIFO mode this error is associated with the character.." "0: No error on UART PEDATA parity error indicator.,1: Error on UART PEDATA parity error indicator."
|
|
bitfld.long 0x0 8. "FEDATA,Framing error. When set to 1 it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode this error is associated with the character at the top of the FIFO." "0: No error on UART FEDATA framing error indicator.,1: Error on UART FEDATA framing error indicator."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,Receive (read) data character. Transmit (write) data character."
|
|
line.long 0x4 "RSR,UART Status"
|
|
bitfld.long 0x4 3. "OESTAT,Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full only the contents of the.." "0: No error on UART OESTAT overrun error indicator.,1: Error on UART OESTAT overrun error indicator."
|
|
bitfld.long 0x4 2. "BESTAT,Break error. This bit is set to 1 if a break condition was detected indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start data parity and stop bits). This bit is cleared to 0 after.." "0: No error on UART BESTAT break error indicator.,1: Error on UART BESTAT break error indicator."
|
|
newline
|
|
bitfld.long 0x4 1. "PESTAT,Parity error. When set to 1 it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register UARTLCRH select. This bit is cleared to 0 by a write to UARTECR. In FIFO.." "0: No error on UART PESTAT parity error indicator.,1: Error on UART PESTAT parity error indicator."
|
|
bitfld.long 0x4 0. "FESTAT,Framing error. When set to 1 it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode this error is associated with the character at the top of.." "0: No error on UART FESTAT framing error indicator.,1: Error on UART FESTAT framing error indicator."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "FR,Flags"
|
|
bitfld.long 0x0 8. "TXBUSY,This bit holds the transmit BUSY indicator." "0,1"
|
|
bitfld.long 0x0 7. "TXFE,Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register UARTLCRH. If the FIFO is disabled this bit is set when the transmit holding register is empty. If the FIFO is enabled the TXFE bit is.." "?,1: Transmit fifo is empty."
|
|
newline
|
|
bitfld.long 0x0 6. "RXFF,Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCRH Register. If the FIFO is disabled this bit is set when the receive holding register is full. If the FIFO is enabled the RXFF bit is set when the receive.." "?,1: Receive fifo is full."
|
|
bitfld.long 0x0 5. "TXFF,Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCRH Register. If the FIFO is disabled this bit is set when the transmit holding register is full. If the FIFO is enabled the TXFF bit is set when the.." "?,1: Transmit fifo is full."
|
|
newline
|
|
bitfld.long 0x0 4. "RXFE,Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCRH Register. If the FIFO is disabled this bit is set when the receive holding register is empty. If the FIFO is enabled the RXFE bit is set when the.." "?,1: Receive fifo is empty."
|
|
bitfld.long 0x0 3. "BUSY,UART busy. If this bit is set to 1 the UART is busy transmitting data. This bit remains set until the complete byte including all the stop bits has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty .." "?,1: UART busy indicator."
|
|
newline
|
|
bitfld.long 0x0 2. "DCD,Data carrier detect. This bit is the complement of the UART data carrier detect nUARTDCD modem status input. That is the bit is 1 when nUARTDCD is LOW." "?,1: Data carrier detect detected."
|
|
bitfld.long 0x0 1. "DSR,Data set ready. This bit is the complement of the UART data set ready nUARTDSR modem status input. That is the bit is 1 when nUARTDSR is LOW." "?,1: Data set ready."
|
|
newline
|
|
bitfld.long 0x0 0. "CTS,Clear to send. This bit is the complement of the UART clear to send nUARTCTS modem status input. That is the bit is 1 when nUARTCTS is LOW." "?,1: Clear to send is indicated."
|
|
group.long 0x20++0x27
|
|
line.long 0x0 "ILPR,IrDA Counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ILPDVSR,8-bit low-power divisor value. These bits are cleared to 0 at reset. Programming a zero value results in no IrLPBaud16 pulses being generated."
|
|
line.long 0x4 "IBRD,Integer Baud Rate Divisor"
|
|
hexmask.long.word 0x4 0.--15. 1. "DIVINT,These bits hold the baud integer divisor. These bits are cleared to 0 on reset."
|
|
line.long 0x8 "FBRD,Fractional Baud Rate Divisor"
|
|
hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,These bits hold the baud fractional divisor. These bits are cleared to 0 on reset."
|
|
line.long 0xC "LCRH,Line Control High"
|
|
bitfld.long 0xC 7. "SPS,This bit holds the stick parity select. If the EPS bit is 0 then the parity bit is transmitted and checked as a 1. If the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity.." "0,1"
|
|
bitfld.long 0xC 5.--6. "WLEN,These bits hold the write length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 4. "FEN,This bit holds the FIFO enable. 0 = FIFOs are disabled (character mode) that is the FIFOs become 1-byte-deep holding registers. 1 = transmit and receive FIFO buffers are enabled (FIFO mode)." "0: FIFOs are disabled,1: transmit and receive FIFO buffers are enabled"
|
|
bitfld.long 0xC 3. "STP2,This bit holds the two stop bits select. If this bit is set to 1 two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received." "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "EPS,This bit holds the even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates.." "0: odd parity,1: even parity"
|
|
bitfld.long 0xC 1. "PEN,This bit holds the parity enable. 0 = parity is disabled and no parity bit added to the data frame. 1 = parity checking and generation is enabled." "0: parity is disabled and no parity bit added to..,1: parity checking and generation is enabled"
|
|
newline
|
|
bitfld.long 0xC 0. "BRK,This bit holds the break set. If this bit is set to 1 a low-level is continually output on the UARTTXD output after completing transmission of the current character. For the proper execution of the break command the software must set this bit for.." "0,1"
|
|
line.long 0x10 "CR,Control"
|
|
bitfld.long 0x10 15. "CTSEN,This bit enables CTS hardware flow control. If this bit is set to 1 CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted." "0,1"
|
|
bitfld.long 0x10 14. "RTSEN,This bit enables RTS hardware flow control. If this bit is set to 1 RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received." "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "OUT2,This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is when the bit is programmed to a 1 the output is 0. For DTE this can be used as Ring Indicator (RI)." "0,1"
|
|
bitfld.long 0x10 12. "OUT1,This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD)." "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "RTS,This bit enables request to send. This bit is the complement of the UART request to send nUARTRTS modem status output. That is when the bit is programmed to a 1 then nUARTRTS is LOW." "0,1"
|
|
bitfld.long 0x10 10. "DTR,This bit enables data transmit ready. This bit is the complement of the UART data transmit ready nUARTDTR modem status output. That is when the bit is programmed to a 1 then nUARTDTR is LOW." "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "RXE,This bit is the receive enable. If this bit is set to 1 the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of.." "0,1"
|
|
bitfld.long 0x10 8. "TXE,This bit is the transmit enable. If this bit is set to 1 the transmit section of the UART is enabled. Data transmission occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle.." "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "LBE,This bit is the loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register UARTTCR is set to 1 then the nSIROUT path is inverted and fed through to the SIRIN path. The SIRTEST bit in the.." "0,1"
|
|
bitfld.long 0x10 4.--6. "CLKSEL,This bitfield is the UART clock select." "0: No UART clock. This is the low power default.,1: 24 MHz clock.,2: 12 MHz clock.,3: 6 MHz clock.,4: 3 MHz clock.,5: Reserved.,?,?"
|
|
newline
|
|
bitfld.long 0x10 3. "CLKEN,This bit is the UART clock enable." "0,1"
|
|
bitfld.long 0x10 2. "SIRLP,This bit is the SIR low power select. This bit selects the IrDA encoding mode. If this bit is cleared to 0 low-level bits are transmitted as an active high pulse with a width of 3/16th of the bit period. If this bit is set to 1 low-level bits are.." "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "SIREN,This bit is the SIR ENDEC enable. If this bit is set to 1 the IrDA SIR ENDEC is enabled. This bit has no effect if the UART is not enabled by bit 0 being set to 1. When the IrDA SIR ENDEC is enabled data is transmitted and received on nSIROUT and.." "0,1"
|
|
bitfld.long 0x10 0. "UARTEN,This bit is the UART enable. 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either.." "0: UART is disabled,1: the UART is enabled"
|
|
line.long 0x14 "IFLS,FIFO Interrupt Level Select"
|
|
bitfld.long 0x14 3.--5. "RXIFLSEL,These bits hold the receive FIFO interrupt level." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 0.--2. "TXIFLSEL,These bits hold the transmit FIFO interrupt level." "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "IER,Interrupt Enable"
|
|
bitfld.long 0x18 10. "OEIM,This bit holds the overflow interrupt enable." "0,1"
|
|
bitfld.long 0x18 9. "BEIM,This bit holds the break error interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 8. "PEIM,This bit holds the parity error interrupt enable." "0,1"
|
|
bitfld.long 0x18 7. "FEIM,This bit holds the framing error interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 6. "RTIM,This bit holds the receive timeout interrupt enable." "0,1"
|
|
bitfld.long 0x18 5. "TXIM,This bit holds the transmit interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 4. "RXIM,This bit holds the receive interrupt enable." "0,1"
|
|
bitfld.long 0x18 3. "DSRMIM,This bit holds the modem DSR interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 2. "DCDMIM,This bit holds the modem DCD interrupt enable." "0,1"
|
|
bitfld.long 0x18 1. "CTSMIM,This bit holds the modem CTS interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXCMPMIM,This bit holds the modem TXCMP interrupt enable." "0,1"
|
|
line.long 0x1C "IES,Interrupt Status"
|
|
bitfld.long 0x1C 10. "OERIS,This bit holds the overrun interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt." "0,1"
|
|
bitfld.long 0x1C 9. "BERIS,This bit holds the break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 8. "PERIS,This bit holds the parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt." "0,1"
|
|
bitfld.long 0x1C 7. "FERIS,This bit holds the framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 6. "RTRIS,This bit holds the receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt." "0,1"
|
|
bitfld.long 0x1C 5. "TXRIS,This bit holds the transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 4. "RXRIS,This bit holds the receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt." "0,1"
|
|
bitfld.long 0x1C 3. "DSRMRIS,This bit holds the nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 2. "DCDMRIS,This bit holds the nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt." "0,1"
|
|
bitfld.long 0x1C 1. "CTSMRIS,This bit holds the nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "TXCMPMRIS,This bit holds the modem TXCMP interrupt status." "0,1"
|
|
line.long 0x20 "MIS,Masked Interrupt Status"
|
|
bitfld.long 0x20 10. "OEMIS,This bit holds the overrun interrupt status masked. Returns the masked interrupt state of the UARTOEINTR interrupt." "0,1"
|
|
bitfld.long 0x20 9. "BEMIS,This bit holds the break error interrupt status masked. Returns the masked interrupt state of the UARTBEINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x20 8. "PEMIS,This bit holds the parity error interrupt status masked. Returns the masked interrupt state of the UARTPEINTR interrupt." "0,1"
|
|
bitfld.long 0x20 7. "FEMIS,This bit holds the framing error interrupt status masked. Returns the masked interrupt state of the UARTFEINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x20 6. "RTMIS,This bit holds the receive timeout interrupt status masked. Returns the masked interrupt state of the UARTRTINTR interrupt." "0,1"
|
|
bitfld.long 0x20 5. "TXMIS,This bit holds the transmit interrupt status masked. Returns the masked interrupt state of the UARTTXINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x20 4. "RXMIS,This bit holds the receive interrupt status masked. Returns the masked interrupt state of the UARTRXINTR interrupt." "0,1"
|
|
bitfld.long 0x20 3. "DSRMMIS,This bit holds the nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x20 2. "DCDMMIS,This bit holds the nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt." "0,1"
|
|
bitfld.long 0x20 1. "CTSMMIS,This bit holds the nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x20 0. "TXCMPMMIS,This bit holds the modem TXCMP interrupt status masked." "0,1"
|
|
line.long 0x24 "IEC,Interrupt Clear"
|
|
bitfld.long 0x24 10. "OEIC,This bit holds the overrun interrupt clear. Clears the UARTOEINTR interrupt." "0,1"
|
|
bitfld.long 0x24 9. "BEIC,This bit holds the break error interrupt clear. Clears the UARTBEINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x24 8. "PEIC,This bit holds the parity error interrupt clear. Clears the UARTPEINTR interrupt." "0,1"
|
|
bitfld.long 0x24 7. "FEIC,This bit holds the framing error interrupt clear. Clears the UARTFEINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x24 6. "RTIC,This bit holds the receive timeout interrupt clear. Clears the UARTRTINTR interrupt." "0,1"
|
|
bitfld.long 0x24 5. "TXIC,This bit holds the transmit interrupt clear. Clears the UARTTXINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x24 4. "RXIC,This bit holds the receive interrupt clear. Clears the UARTRXINTR interrupt." "0,1"
|
|
bitfld.long 0x24 3. "DSRMIC,This bit holds the nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x24 2. "DCDMIC,This bit holds the nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt." "0,1"
|
|
bitfld.long 0x24 1. "CTSMIC,This bit holds the nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x24 0. "TXCMPMIC,This bit holds the modem TXCMP interrupt clear." "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
tree "UART3"
|
|
base ad:0x4001F000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "DR,UART Data"
|
|
bitfld.long 0x0 11. "OEDATA,Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it." "0: No error on UART OEDATA overrun error indicator.,1: Error on UART OEDATA overrun error indicator."
|
|
bitfld.long 0x0 10. "BEDATA,Break error. This bit is set to 1 if a break condition was detected indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start data parity and stop bits). In FIFO mode this error is.." "0: No error on UART BEDATA break error indicator.,1: Error on UART BEDATA break error indicator."
|
|
newline
|
|
bitfld.long 0x0 9. "PEDATA,Parity error. When set to 1 it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register UARTLCRH select. In FIFO mode this error is associated with the character.." "0: No error on UART PEDATA parity error indicator.,1: Error on UART PEDATA parity error indicator."
|
|
bitfld.long 0x0 8. "FEDATA,Framing error. When set to 1 it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode this error is associated with the character at the top of the FIFO." "0: No error on UART FEDATA framing error indicator.,1: Error on UART FEDATA framing error indicator."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,Receive (read) data character. Transmit (write) data character."
|
|
line.long 0x4 "RSR,UART Status"
|
|
bitfld.long 0x4 3. "OESTAT,Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full only the contents of the.." "0: No error on UART OESTAT overrun error indicator.,1: Error on UART OESTAT overrun error indicator."
|
|
bitfld.long 0x4 2. "BESTAT,Break error. This bit is set to 1 if a break condition was detected indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start data parity and stop bits). This bit is cleared to 0 after.." "0: No error on UART BESTAT break error indicator.,1: Error on UART BESTAT break error indicator."
|
|
newline
|
|
bitfld.long 0x4 1. "PESTAT,Parity error. When set to 1 it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register UARTLCRH select. This bit is cleared to 0 by a write to UARTECR. In FIFO.." "0: No error on UART PESTAT parity error indicator.,1: Error on UART PESTAT parity error indicator."
|
|
bitfld.long 0x4 0. "FESTAT,Framing error. When set to 1 it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode this error is associated with the character at the top of.." "0: No error on UART FESTAT framing error indicator.,1: Error on UART FESTAT framing error indicator."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "FR,Flags"
|
|
bitfld.long 0x0 8. "TXBUSY,This bit holds the transmit BUSY indicator." "0,1"
|
|
bitfld.long 0x0 7. "TXFE,Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register UARTLCRH. If the FIFO is disabled this bit is set when the transmit holding register is empty. If the FIFO is enabled the TXFE bit is.." "?,1: Transmit fifo is empty."
|
|
newline
|
|
bitfld.long 0x0 6. "RXFF,Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCRH Register. If the FIFO is disabled this bit is set when the receive holding register is full. If the FIFO is enabled the RXFF bit is set when the receive.." "?,1: Receive fifo is full."
|
|
bitfld.long 0x0 5. "TXFF,Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCRH Register. If the FIFO is disabled this bit is set when the transmit holding register is full. If the FIFO is enabled the TXFF bit is set when the.." "?,1: Transmit fifo is full."
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newline
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bitfld.long 0x0 4. "RXFE,Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCRH Register. If the FIFO is disabled this bit is set when the receive holding register is empty. If the FIFO is enabled the RXFE bit is set when the.." "?,1: Receive fifo is empty."
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bitfld.long 0x0 3. "BUSY,UART busy. If this bit is set to 1 the UART is busy transmitting data. This bit remains set until the complete byte including all the stop bits has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty .." "?,1: UART busy indicator."
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newline
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bitfld.long 0x0 2. "DCD,Data carrier detect. This bit is the complement of the UART data carrier detect nUARTDCD modem status input. That is the bit is 1 when nUARTDCD is LOW." "?,1: Data carrier detect detected."
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bitfld.long 0x0 1. "DSR,Data set ready. This bit is the complement of the UART data set ready nUARTDSR modem status input. That is the bit is 1 when nUARTDSR is LOW." "?,1: Data set ready."
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newline
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bitfld.long 0x0 0. "CTS,Clear to send. This bit is the complement of the UART clear to send nUARTCTS modem status input. That is the bit is 1 when nUARTCTS is LOW." "?,1: Clear to send is indicated."
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group.long 0x20++0x27
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|
line.long 0x0 "ILPR,IrDA Counter"
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|
hexmask.long.byte 0x0 0.--7. 1. "ILPDVSR,8-bit low-power divisor value. These bits are cleared to 0 at reset. Programming a zero value results in no IrLPBaud16 pulses being generated."
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|
line.long 0x4 "IBRD,Integer Baud Rate Divisor"
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|
hexmask.long.word 0x4 0.--15. 1. "DIVINT,These bits hold the baud integer divisor. These bits are cleared to 0 on reset."
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|
line.long 0x8 "FBRD,Fractional Baud Rate Divisor"
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|
hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,These bits hold the baud fractional divisor. These bits are cleared to 0 on reset."
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|
line.long 0xC "LCRH,Line Control High"
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|
bitfld.long 0xC 7. "SPS,This bit holds the stick parity select. If the EPS bit is 0 then the parity bit is transmitted and checked as a 1. If the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity.." "0,1"
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bitfld.long 0xC 5.--6. "WLEN,These bits hold the write length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits." "0,1,2,3"
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newline
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bitfld.long 0xC 4. "FEN,This bit holds the FIFO enable. 0 = FIFOs are disabled (character mode) that is the FIFOs become 1-byte-deep holding registers. 1 = transmit and receive FIFO buffers are enabled (FIFO mode)." "0: FIFOs are disabled,1: transmit and receive FIFO buffers are enabled"
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bitfld.long 0xC 3. "STP2,This bit holds the two stop bits select. If this bit is set to 1 two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received." "0,1"
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newline
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bitfld.long 0xC 2. "EPS,This bit holds the even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates.." "0: odd parity,1: even parity"
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bitfld.long 0xC 1. "PEN,This bit holds the parity enable. 0 = parity is disabled and no parity bit added to the data frame. 1 = parity checking and generation is enabled." "0: parity is disabled and no parity bit added to..,1: parity checking and generation is enabled"
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newline
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bitfld.long 0xC 0. "BRK,This bit holds the break set. If this bit is set to 1 a low-level is continually output on the UARTTXD output after completing transmission of the current character. For the proper execution of the break command the software must set this bit for.." "0,1"
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line.long 0x10 "CR,Control"
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bitfld.long 0x10 15. "CTSEN,This bit enables CTS hardware flow control. If this bit is set to 1 CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted." "0,1"
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bitfld.long 0x10 14. "RTSEN,This bit enables RTS hardware flow control. If this bit is set to 1 RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received." "0,1"
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newline
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bitfld.long 0x10 13. "OUT2,This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is when the bit is programmed to a 1 the output is 0. For DTE this can be used as Ring Indicator (RI)." "0,1"
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bitfld.long 0x10 12. "OUT1,This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD)." "0,1"
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newline
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bitfld.long 0x10 11. "RTS,This bit enables request to send. This bit is the complement of the UART request to send nUARTRTS modem status output. That is when the bit is programmed to a 1 then nUARTRTS is LOW." "0,1"
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bitfld.long 0x10 10. "DTR,This bit enables data transmit ready. This bit is the complement of the UART data transmit ready nUARTDTR modem status output. That is when the bit is programmed to a 1 then nUARTDTR is LOW." "0,1"
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newline
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bitfld.long 0x10 9. "RXE,This bit is the receive enable. If this bit is set to 1 the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of.." "0,1"
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bitfld.long 0x10 8. "TXE,This bit is the transmit enable. If this bit is set to 1 the transmit section of the UART is enabled. Data transmission occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle.." "0,1"
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newline
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bitfld.long 0x10 7. "LBE,This bit is the loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register UARTTCR is set to 1 then the nSIROUT path is inverted and fed through to the SIRIN path. The SIRTEST bit in the.." "0,1"
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bitfld.long 0x10 4.--6. "CLKSEL,This bitfield is the UART clock select." "0: No UART clock. This is the low power default.,1: 24 MHz clock.,2: 12 MHz clock.,3: 6 MHz clock.,4: 3 MHz clock.,5: Reserved.,?,?"
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newline
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bitfld.long 0x10 3. "CLKEN,This bit is the UART clock enable." "0,1"
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bitfld.long 0x10 2. "SIRLP,This bit is the SIR low power select. This bit selects the IrDA encoding mode. If this bit is cleared to 0 low-level bits are transmitted as an active high pulse with a width of 3/16th of the bit period. If this bit is set to 1 low-level bits are.." "0,1"
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newline
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bitfld.long 0x10 1. "SIREN,This bit is the SIR ENDEC enable. If this bit is set to 1 the IrDA SIR ENDEC is enabled. This bit has no effect if the UART is not enabled by bit 0 being set to 1. When the IrDA SIR ENDEC is enabled data is transmitted and received on nSIROUT and.." "0,1"
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bitfld.long 0x10 0. "UARTEN,This bit is the UART enable. 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either.." "0: UART is disabled,1: the UART is enabled"
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line.long 0x14 "IFLS,FIFO Interrupt Level Select"
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bitfld.long 0x14 3.--5. "RXIFLSEL,These bits hold the receive FIFO interrupt level." "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 0.--2. "TXIFLSEL,These bits hold the transmit FIFO interrupt level." "0,1,2,3,4,5,6,7"
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line.long 0x18 "IER,Interrupt Enable"
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bitfld.long 0x18 10. "OEIM,This bit holds the overflow interrupt enable." "0,1"
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bitfld.long 0x18 9. "BEIM,This bit holds the break error interrupt enable." "0,1"
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newline
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bitfld.long 0x18 8. "PEIM,This bit holds the parity error interrupt enable." "0,1"
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bitfld.long 0x18 7. "FEIM,This bit holds the framing error interrupt enable." "0,1"
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newline
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bitfld.long 0x18 6. "RTIM,This bit holds the receive timeout interrupt enable." "0,1"
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bitfld.long 0x18 5. "TXIM,This bit holds the transmit interrupt enable." "0,1"
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newline
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bitfld.long 0x18 4. "RXIM,This bit holds the receive interrupt enable." "0,1"
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bitfld.long 0x18 3. "DSRMIM,This bit holds the modem DSR interrupt enable." "0,1"
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newline
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bitfld.long 0x18 2. "DCDMIM,This bit holds the modem DCD interrupt enable." "0,1"
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bitfld.long 0x18 1. "CTSMIM,This bit holds the modem CTS interrupt enable." "0,1"
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newline
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bitfld.long 0x18 0. "TXCMPMIM,This bit holds the modem TXCMP interrupt enable." "0,1"
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line.long 0x1C "IES,Interrupt Status"
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|
bitfld.long 0x1C 10. "OERIS,This bit holds the overrun interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt." "0,1"
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bitfld.long 0x1C 9. "BERIS,This bit holds the break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt." "0,1"
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newline
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bitfld.long 0x1C 8. "PERIS,This bit holds the parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt." "0,1"
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bitfld.long 0x1C 7. "FERIS,This bit holds the framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt." "0,1"
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newline
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bitfld.long 0x1C 6. "RTRIS,This bit holds the receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt." "0,1"
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bitfld.long 0x1C 5. "TXRIS,This bit holds the transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt." "0,1"
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newline
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bitfld.long 0x1C 4. "RXRIS,This bit holds the receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt." "0,1"
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bitfld.long 0x1C 3. "DSRMRIS,This bit holds the nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt." "0,1"
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newline
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bitfld.long 0x1C 2. "DCDMRIS,This bit holds the nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt." "0,1"
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bitfld.long 0x1C 1. "CTSMRIS,This bit holds the nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt." "0,1"
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newline
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bitfld.long 0x1C 0. "TXCMPMRIS,This bit holds the modem TXCMP interrupt status." "0,1"
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line.long 0x20 "MIS,Masked Interrupt Status"
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bitfld.long 0x20 10. "OEMIS,This bit holds the overrun interrupt status masked. Returns the masked interrupt state of the UARTOEINTR interrupt." "0,1"
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bitfld.long 0x20 9. "BEMIS,This bit holds the break error interrupt status masked. Returns the masked interrupt state of the UARTBEINTR interrupt." "0,1"
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newline
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bitfld.long 0x20 8. "PEMIS,This bit holds the parity error interrupt status masked. Returns the masked interrupt state of the UARTPEINTR interrupt." "0,1"
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bitfld.long 0x20 7. "FEMIS,This bit holds the framing error interrupt status masked. Returns the masked interrupt state of the UARTFEINTR interrupt." "0,1"
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newline
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bitfld.long 0x20 6. "RTMIS,This bit holds the receive timeout interrupt status masked. Returns the masked interrupt state of the UARTRTINTR interrupt." "0,1"
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bitfld.long 0x20 5. "TXMIS,This bit holds the transmit interrupt status masked. Returns the masked interrupt state of the UARTTXINTR interrupt." "0,1"
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newline
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bitfld.long 0x20 4. "RXMIS,This bit holds the receive interrupt status masked. Returns the masked interrupt state of the UARTRXINTR interrupt." "0,1"
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bitfld.long 0x20 3. "DSRMMIS,This bit holds the nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt." "0,1"
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newline
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bitfld.long 0x20 2. "DCDMMIS,This bit holds the nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt." "0,1"
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bitfld.long 0x20 1. "CTSMMIS,This bit holds the nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt." "0,1"
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newline
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bitfld.long 0x20 0. "TXCMPMMIS,This bit holds the modem TXCMP interrupt status masked." "0,1"
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line.long 0x24 "IEC,Interrupt Clear"
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bitfld.long 0x24 10. "OEIC,This bit holds the overrun interrupt clear. Clears the UARTOEINTR interrupt." "0,1"
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bitfld.long 0x24 9. "BEIC,This bit holds the break error interrupt clear. Clears the UARTBEINTR interrupt." "0,1"
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newline
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bitfld.long 0x24 8. "PEIC,This bit holds the parity error interrupt clear. Clears the UARTPEINTR interrupt." "0,1"
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bitfld.long 0x24 7. "FEIC,This bit holds the framing error interrupt clear. Clears the UARTFEINTR interrupt." "0,1"
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newline
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bitfld.long 0x24 6. "RTIC,This bit holds the receive timeout interrupt clear. Clears the UARTRTINTR interrupt." "0,1"
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bitfld.long 0x24 5. "TXIC,This bit holds the transmit interrupt clear. Clears the UARTTXINTR interrupt." "0,1"
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newline
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bitfld.long 0x24 4. "RXIC,This bit holds the receive interrupt clear. Clears the UARTRXINTR interrupt." "0,1"
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bitfld.long 0x24 3. "DSRMIC,This bit holds the nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt." "0,1"
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newline
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bitfld.long 0x24 2. "DCDMIC,This bit holds the nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt." "0,1"
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bitfld.long 0x24 1. "CTSMIC,This bit holds the nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt." "0,1"
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newline
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bitfld.long 0x24 0. "TXCMPMIC,This bit holds the modem TXCMP interrupt clear." "0,1"
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tree.end
|
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endif
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sif (cpuis("AMA4B2KL")||cpuis("AMA4B2KP")||cpuis("AMAP42KL")||cpuis("AMAP42KP"))
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tree "UART0"
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base ad:0x4001C000
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group.long 0x0++0x7
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line.long 0x0 "DR,UART Data"
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bitfld.long 0x0 11. "OEDATA,Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it." "0: No error on UART OEDATA overrun error indicator.,1: Error on UART OEDATA overrun error indicator."
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bitfld.long 0x0 10. "BEDATA,Break error. This bit is set to 1 if a break condition was detected indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start data parity and stop bits). In FIFO mode this error is.." "0: No error on UART BEDATA break error indicator.,1: Error on UART BEDATA break error indicator."
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newline
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bitfld.long 0x0 9. "PEDATA,Parity error. When set to 1 it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register UARTLCRH select. In FIFO mode this error is associated with the character.." "0: No error on UART PEDATA parity error indicator.,1: Error on UART PEDATA parity error indicator."
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bitfld.long 0x0 8. "FEDATA,Framing error. When set to 1 it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode this error is associated with the character at the top of the FIFO." "0: No error on UART FEDATA framing error indicator.,1: Error on UART FEDATA framing error indicator."
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newline
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hexmask.long.byte 0x0 0.--7. 1. "DATA,Receive (read) data character. Transmit (write) data character."
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line.long 0x4 "RSR,UART Status"
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bitfld.long 0x4 3. "OESTAT,Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full only the contents of the.." "0: No error on UART OESTAT overrun error indicator.,1: Error on UART OESTAT overrun error indicator."
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bitfld.long 0x4 2. "BESTAT,Break error. This bit is set to 1 if a break condition was detected indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start data parity and stop bits). This bit is cleared to 0 after.." "0: No error on UART BESTAT break error indicator.,1: Error on UART BESTAT break error indicator."
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newline
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bitfld.long 0x4 1. "PESTAT,Parity error. When set to 1 it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register UARTLCRH select. This bit is cleared to 0 by a write to UARTECR. In FIFO.." "0: No error on UART PESTAT parity error indicator.,1: Error on UART PESTAT parity error indicator."
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bitfld.long 0x4 0. "FESTAT,Framing error. When set to 1 it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode this error is associated with the character at the top of.." "0: No error on UART FESTAT framing error indicator.,1: Error on UART FESTAT framing error indicator."
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group.long 0x18++0x3
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line.long 0x0 "FR,Flags"
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bitfld.long 0x0 8. "TXBUSY,This bit holds the transmit BUSY indicator." "0,1"
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bitfld.long 0x0 7. "TXFE,Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register UARTLCRH. If the FIFO is disabled this bit is set when the transmit holding register is empty. If the FIFO is enabled the TXFE bit is.." "0: Transmit fifo is not empty.,1: Transmit fifo is empty."
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newline
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bitfld.long 0x0 6. "RXFF,Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCRH Register. If the FIFO is disabled this bit is set when the receive holding register is full. If the FIFO is enabled the RXFF bit is set when the receive.." "0: Receive fifo is not full.,1: Receive fifo is full."
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bitfld.long 0x0 5. "TXFF,Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCRH Register. If the FIFO is disabled this bit is set when the transmit holding register is full. If the FIFO is enabled the TXFF bit is set when the.." "0: Transmit fifo is not full.,1: Transmit fifo is full."
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newline
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bitfld.long 0x0 4. "RXFE,Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCRH Register. If the FIFO is disabled this bit is set when the receive holding register is empty. If the FIFO is enabled the RXFE bit is set when the.." "0: Receive fifo is not empty.,1: Receive fifo is empty."
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bitfld.long 0x0 3. "BUSY,UART busy. If this bit is set to 1 the UART is busy transmitting data. This bit remains set until the complete byte including all the stop bits has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty .." "0: UART not busy.,1: UART busy indicator."
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newline
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bitfld.long 0x0 2. "DCD,Data carrier detect. This bit is the complement of the UART data carrier detect nUARTDCD modem status input. That is the bit is 1 when nUARTDCD is LOW." "0: Data carrier detect not detected/default.,1: Data carrier detect detected."
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bitfld.long 0x0 1. "DSR,Data set ready. This bit is the complement of the UART data set ready nUARTDSR modem status input. That is the bit is 1 when nUARTDSR is LOW." "0: Data set not ready/default.,1: Data set ready."
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newline
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bitfld.long 0x0 0. "CTS,Clear to send. This bit is the complement of the UART clear to send nUARTCTS modem status input. That is the bit is 1 when nUARTCTS is LOW." "0: Clear to send default value.,1: Clear to send is indicated."
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group.long 0x20++0x27
|
|
line.long 0x0 "ILPR,IrDA Counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ILPDVSR,8-bit low-power divisor value. These bits are cleared to 0 at reset. Programming a zero value results in no IrLPBaud16 pulses being generated."
|
|
line.long 0x4 "IBRD,Integer Baud Rate Divisor"
|
|
hexmask.long.word 0x4 0.--15. 1. "DIVINT,These bits hold the baud integer divisor. These bits are cleared to 0 on reset."
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line.long 0x8 "FBRD,Fractional Baud Rate Divisor"
|
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hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,These bits hold the baud fractional divisor. These bits are cleared to 0 on reset."
|
|
line.long 0xC "LCRH,Line Control High"
|
|
bitfld.long 0xC 7. "SPS,This bit holds the stick parity select. If the EPS bit is 0 then the parity bit is transmitted and checked as a 1. If the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity.." "0,1"
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|
bitfld.long 0xC 5.--6. "WLEN,These bits hold the write length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits." "0,1,2,3"
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newline
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bitfld.long 0xC 4. "FEN,This bit holds the FIFO enable. 0 = FIFOs are disabled (character mode) that is the FIFOs become 1-byte-deep holding registers. 1 = transmit and receive FIFO buffers are enabled (FIFO mode)." "0: FIFOs are disabled,1: transmit and receive FIFO buffers are enabled"
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bitfld.long 0xC 3. "STP2,This bit holds the two stop bits select. If this bit is set to 1 two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received." "0,1"
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newline
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bitfld.long 0xC 2. "EPS,This bit holds the even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates.." "0: odd parity,1: even parity"
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bitfld.long 0xC 1. "PEN,This bit holds the parity enable. 0 = parity is disabled and no parity bit added to the data frame. 1 = parity checking and generation is enabled." "0: parity is disabled and no parity bit added to..,1: parity checking and generation is enabled"
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newline
|
|
bitfld.long 0xC 0. "BRK,This bit holds the break set. If this bit is set to 1 a low-level is continually output on the UARTTXD output after completing transmission of the current character. For the proper execution of the break command the software must set this bit for.." "0,1"
|
|
line.long 0x10 "CR,Control"
|
|
bitfld.long 0x10 15. "CTSEN,This bit enables CTS hardware flow control. If this bit is set to 1 CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted." "0,1"
|
|
bitfld.long 0x10 14. "RTSEN,This bit enables RTS hardware flow control. If this bit is set to 1 RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received." "0,1"
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|
newline
|
|
bitfld.long 0x10 13. "OUT2,This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is when the bit is programmed to a 1 the output is 0. For DTE this can be used as Ring Indicator (RI)." "0,1"
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bitfld.long 0x10 12. "OUT1,This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD)." "0,1"
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newline
|
|
bitfld.long 0x10 11. "RTS,This bit enables request to send. This bit is the complement of the UART request to send nUARTRTS modem status output. That is when the bit is programmed to a 1 then nUARTRTS is LOW." "0,1"
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|
bitfld.long 0x10 10. "DTR,This bit enables data transmit ready. This bit is the complement of the UART data transmit ready nUARTDTR modem status output. That is when the bit is programmed to a 1 then nUARTDTR is LOW." "0,1"
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|
newline
|
|
bitfld.long 0x10 9. "RXE,This bit is the receive enable. If this bit is set to 1 the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of.." "0,1"
|
|
bitfld.long 0x10 8. "TXE,This bit is the transmit enable. If this bit is set to 1 the transmit section of the UART is enabled. Data transmission occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle.." "0,1"
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|
newline
|
|
bitfld.long 0x10 7. "LBE,This bit is the loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register UARTTCR is set to 1 then the nSIROUT path is inverted and fed through to the SIRIN path. The SIRTEST bit in the.." "0,1"
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|
bitfld.long 0x10 4.--6. "CLKSEL,This bitfield is the UART clock select." "0: No UART clock. This is the low power default.,1: 24 MHz clock.,2: 12 MHz clock.,3: 6 MHz clock.,4: 3 MHz clock.,5: Reserved.,?,?"
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|
newline
|
|
bitfld.long 0x10 3. "CLKEN,This bit is the UART clock enable." "0,1"
|
|
bitfld.long 0x10 2. "SIRLP,This bit is the SIR low power select. This bit selects the IrDA encoding mode. If this bit is cleared to 0 low-level bits are transmitted as an active high pulse with a width of 3/16th of the bit period. If this bit is set to 1 low-level bits are.." "0,1"
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|
newline
|
|
bitfld.long 0x10 1. "SIREN,This bit is the SIR ENDEC enable. If this bit is set to 1 the IrDA SIR ENDEC is enabled. This bit has no effect if the UART is not enabled by bit 0 being set to 1. When the IrDA SIR ENDEC is enabled data is transmitted and received on nSIROUT and.." "0,1"
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|
bitfld.long 0x10 0. "UARTEN,This bit is the UART enable. 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either.." "0: UART is disabled,1: the UART is enabled"
|
|
line.long 0x14 "IFLS,FIFO Interrupt Level Select"
|
|
bitfld.long 0x14 3.--5. "RXIFLSEL,These bits hold the receive FIFO interrupt level." "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x14 0.--2. "TXIFLSEL,These bits hold the transmit FIFO interrupt level." "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "IER,Interrupt Enable"
|
|
bitfld.long 0x18 10. "OEIM,This bit holds the overflow interrupt enable." "0,1"
|
|
bitfld.long 0x18 9. "BEIM,This bit holds the break error interrupt enable." "0,1"
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|
newline
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|
bitfld.long 0x18 8. "PEIM,This bit holds the parity error interrupt enable." "0,1"
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|
bitfld.long 0x18 7. "FEIM,This bit holds the framing error interrupt enable." "0,1"
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|
newline
|
|
bitfld.long 0x18 6. "RTIM,This bit holds the receive timeout interrupt enable." "0,1"
|
|
bitfld.long 0x18 5. "TXIM,This bit holds the transmit interrupt enable." "0,1"
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|
newline
|
|
bitfld.long 0x18 4. "RXIM,This bit holds the receive interrupt enable." "0,1"
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|
bitfld.long 0x18 3. "DSRMIM,This bit holds the modem DSR interrupt enable." "0,1"
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|
newline
|
|
bitfld.long 0x18 2. "DCDMIM,This bit holds the modem DCD interrupt enable." "0,1"
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|
bitfld.long 0x18 1. "CTSMIM,This bit holds the modem CTS interrupt enable." "0,1"
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|
newline
|
|
bitfld.long 0x18 0. "TXCMPMIM,This bit holds the modem TXCMP interrupt enable." "0,1"
|
|
line.long 0x1C "IES,Interrupt Status"
|
|
bitfld.long 0x1C 10. "OERIS,This bit holds the overrun interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt." "0,1"
|
|
bitfld.long 0x1C 9. "BERIS,This bit holds the break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt." "0,1"
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|
newline
|
|
bitfld.long 0x1C 8. "PERIS,This bit holds the parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt." "0,1"
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|
bitfld.long 0x1C 7. "FERIS,This bit holds the framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt." "0,1"
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|
newline
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bitfld.long 0x1C 6. "RTRIS,This bit holds the receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt." "0,1"
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|
bitfld.long 0x1C 5. "TXRIS,This bit holds the transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt." "0,1"
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|
newline
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bitfld.long 0x1C 4. "RXRIS,This bit holds the receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt." "0,1"
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|
bitfld.long 0x1C 3. "DSRMRIS,This bit holds the nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt." "0,1"
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newline
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bitfld.long 0x1C 2. "DCDMRIS,This bit holds the nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt." "0,1"
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bitfld.long 0x1C 1. "CTSMRIS,This bit holds the nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt." "0,1"
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|
newline
|
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bitfld.long 0x1C 0. "TXCMPMRIS,This bit holds the modem TXCMP interrupt status." "0,1"
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|
line.long 0x20 "MIS,Masked Interrupt Status"
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|
bitfld.long 0x20 10. "OEMIS,This bit holds the overrun interrupt status masked. Returns the masked interrupt state of the UARTOEINTR interrupt." "0,1"
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|
bitfld.long 0x20 9. "BEMIS,This bit holds the break error interrupt status masked. Returns the masked interrupt state of the UARTBEINTR interrupt." "0,1"
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|
newline
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bitfld.long 0x20 8. "PEMIS,This bit holds the parity error interrupt status masked. Returns the masked interrupt state of the UARTPEINTR interrupt." "0,1"
|
|
bitfld.long 0x20 7. "FEMIS,This bit holds the framing error interrupt status masked. Returns the masked interrupt state of the UARTFEINTR interrupt." "0,1"
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newline
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bitfld.long 0x20 6. "RTMIS,This bit holds the receive timeout interrupt status masked. Returns the masked interrupt state of the UARTRTINTR interrupt." "0,1"
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|
bitfld.long 0x20 5. "TXMIS,This bit holds the transmit interrupt status masked. Returns the masked interrupt state of the UARTTXINTR interrupt." "0,1"
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newline
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bitfld.long 0x20 4. "RXMIS,This bit holds the receive interrupt status masked. Returns the masked interrupt state of the UARTRXINTR interrupt." "0,1"
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bitfld.long 0x20 3. "DSRMMIS,This bit holds the nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt." "0,1"
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newline
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bitfld.long 0x20 2. "DCDMMIS,This bit holds the nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt." "0,1"
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bitfld.long 0x20 1. "CTSMMIS,This bit holds the nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt." "0,1"
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newline
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bitfld.long 0x20 0. "TXCMPMMIS,This bit holds the modem TXCMP interrupt status masked." "0,1"
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|
line.long 0x24 "IEC,Interrupt Clear"
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bitfld.long 0x24 10. "OEIC,This bit holds the overrun interrupt clear. Clears the UARTOEINTR interrupt." "0,1"
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|
bitfld.long 0x24 9. "BEIC,This bit holds the break error interrupt clear. Clears the UARTBEINTR interrupt." "0,1"
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|
newline
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bitfld.long 0x24 8. "PEIC,This bit holds the parity error interrupt clear. Clears the UARTPEINTR interrupt." "0,1"
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|
bitfld.long 0x24 7. "FEIC,This bit holds the framing error interrupt clear. Clears the UARTFEINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x24 6. "RTIC,This bit holds the receive timeout interrupt clear. Clears the UARTRTINTR interrupt." "0,1"
|
|
bitfld.long 0x24 5. "TXIC,This bit holds the transmit interrupt clear. Clears the UARTTXINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x24 4. "RXIC,This bit holds the receive interrupt clear. Clears the UARTRXINTR interrupt." "0,1"
|
|
bitfld.long 0x24 3. "DSRMIC,This bit holds the nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt." "0,1"
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|
newline
|
|
bitfld.long 0x24 2. "DCDMIC,This bit holds the nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt." "0,1"
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|
bitfld.long 0x24 1. "CTSMIC,This bit holds the nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt." "0,1"
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newline
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bitfld.long 0x24 0. "TXCMPMIC,This bit holds the modem TXCMP interrupt clear." "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMA4B2KP")||cpuis("AMAP42KL")||cpuis("AMAP42KP"))
|
|
tree "UART1"
|
|
base ad:0x4001D000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "DR,UART Data"
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|
bitfld.long 0x0 11. "OEDATA,Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it." "0: No error on UART OEDATA overrun error indicator.,1: Error on UART OEDATA overrun error indicator."
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bitfld.long 0x0 10. "BEDATA,Break error. This bit is set to 1 if a break condition was detected indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start data parity and stop bits). In FIFO mode this error is.." "0: No error on UART BEDATA break error indicator.,1: Error on UART BEDATA break error indicator."
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newline
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bitfld.long 0x0 9. "PEDATA,Parity error. When set to 1 it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register UARTLCRH select. In FIFO mode this error is associated with the character.." "0: No error on UART PEDATA parity error indicator.,1: Error on UART PEDATA parity error indicator."
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bitfld.long 0x0 8. "FEDATA,Framing error. When set to 1 it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode this error is associated with the character at the top of the FIFO." "0: No error on UART FEDATA framing error indicator.,1: Error on UART FEDATA framing error indicator."
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newline
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hexmask.long.byte 0x0 0.--7. 1. "DATA,Receive (read) data character. Transmit (write) data character."
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line.long 0x4 "RSR,UART Status"
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bitfld.long 0x4 3. "OESTAT,Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full only the contents of the.." "0: No error on UART OESTAT overrun error indicator.,1: Error on UART OESTAT overrun error indicator."
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bitfld.long 0x4 2. "BESTAT,Break error. This bit is set to 1 if a break condition was detected indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start data parity and stop bits). This bit is cleared to 0 after.." "0: No error on UART BESTAT break error indicator.,1: Error on UART BESTAT break error indicator."
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newline
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bitfld.long 0x4 1. "PESTAT,Parity error. When set to 1 it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register UARTLCRH select. This bit is cleared to 0 by a write to UARTECR. In FIFO.." "0: No error on UART PESTAT parity error indicator.,1: Error on UART PESTAT parity error indicator."
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bitfld.long 0x4 0. "FESTAT,Framing error. When set to 1 it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode this error is associated with the character at the top of.." "0: No error on UART FESTAT framing error indicator.,1: Error on UART FESTAT framing error indicator."
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group.long 0x18++0x3
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line.long 0x0 "FR,Flags"
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bitfld.long 0x0 8. "TXBUSY,This bit holds the transmit BUSY indicator." "0,1"
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bitfld.long 0x0 7. "TXFE,Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register UARTLCRH. If the FIFO is disabled this bit is set when the transmit holding register is empty. If the FIFO is enabled the TXFE bit is.." "0: Transmit fifo is not empty.,1: Transmit fifo is empty."
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newline
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bitfld.long 0x0 6. "RXFF,Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCRH Register. If the FIFO is disabled this bit is set when the receive holding register is full. If the FIFO is enabled the RXFF bit is set when the receive.." "0: Receive fifo is not full.,1: Receive fifo is full."
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bitfld.long 0x0 5. "TXFF,Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCRH Register. If the FIFO is disabled this bit is set when the transmit holding register is full. If the FIFO is enabled the TXFF bit is set when the.." "0: Transmit fifo is not full.,1: Transmit fifo is full."
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newline
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bitfld.long 0x0 4. "RXFE,Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCRH Register. If the FIFO is disabled this bit is set when the receive holding register is empty. If the FIFO is enabled the RXFE bit is set when the.." "0: Receive fifo is not empty.,1: Receive fifo is empty."
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bitfld.long 0x0 3. "BUSY,UART busy. If this bit is set to 1 the UART is busy transmitting data. This bit remains set until the complete byte including all the stop bits has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty .." "0: UART not busy.,1: UART busy indicator."
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newline
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bitfld.long 0x0 2. "DCD,Data carrier detect. This bit is the complement of the UART data carrier detect nUARTDCD modem status input. That is the bit is 1 when nUARTDCD is LOW." "0: Data carrier detect not detected/default.,1: Data carrier detect detected."
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bitfld.long 0x0 1. "DSR,Data set ready. This bit is the complement of the UART data set ready nUARTDSR modem status input. That is the bit is 1 when nUARTDSR is LOW." "0: Data set not ready/default.,1: Data set ready."
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newline
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bitfld.long 0x0 0. "CTS,Clear to send. This bit is the complement of the UART clear to send nUARTCTS modem status input. That is the bit is 1 when nUARTCTS is LOW." "0: Clear to send default value.,1: Clear to send is indicated."
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group.long 0x20++0x27
|
|
line.long 0x0 "ILPR,IrDA Counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ILPDVSR,8-bit low-power divisor value. These bits are cleared to 0 at reset. Programming a zero value results in no IrLPBaud16 pulses being generated."
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|
line.long 0x4 "IBRD,Integer Baud Rate Divisor"
|
|
hexmask.long.word 0x4 0.--15. 1. "DIVINT,These bits hold the baud integer divisor. These bits are cleared to 0 on reset."
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|
line.long 0x8 "FBRD,Fractional Baud Rate Divisor"
|
|
hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,These bits hold the baud fractional divisor. These bits are cleared to 0 on reset."
|
|
line.long 0xC "LCRH,Line Control High"
|
|
bitfld.long 0xC 7. "SPS,This bit holds the stick parity select. If the EPS bit is 0 then the parity bit is transmitted and checked as a 1. If the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity.." "0,1"
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|
bitfld.long 0xC 5.--6. "WLEN,These bits hold the write length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits." "0,1,2,3"
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|
newline
|
|
bitfld.long 0xC 4. "FEN,This bit holds the FIFO enable. 0 = FIFOs are disabled (character mode) that is the FIFOs become 1-byte-deep holding registers. 1 = transmit and receive FIFO buffers are enabled (FIFO mode)." "0: FIFOs are disabled,1: transmit and receive FIFO buffers are enabled"
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|
bitfld.long 0xC 3. "STP2,This bit holds the two stop bits select. If this bit is set to 1 two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received." "0,1"
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newline
|
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bitfld.long 0xC 2. "EPS,This bit holds the even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates.." "0: odd parity,1: even parity"
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|
bitfld.long 0xC 1. "PEN,This bit holds the parity enable. 0 = parity is disabled and no parity bit added to the data frame. 1 = parity checking and generation is enabled." "0: parity is disabled and no parity bit added to..,1: parity checking and generation is enabled"
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|
newline
|
|
bitfld.long 0xC 0. "BRK,This bit holds the break set. If this bit is set to 1 a low-level is continually output on the UARTTXD output after completing transmission of the current character. For the proper execution of the break command the software must set this bit for.." "0,1"
|
|
line.long 0x10 "CR,Control"
|
|
bitfld.long 0x10 15. "CTSEN,This bit enables CTS hardware flow control. If this bit is set to 1 CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted." "0,1"
|
|
bitfld.long 0x10 14. "RTSEN,This bit enables RTS hardware flow control. If this bit is set to 1 RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received." "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "OUT2,This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is when the bit is programmed to a 1 the output is 0. For DTE this can be used as Ring Indicator (RI)." "0,1"
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|
bitfld.long 0x10 12. "OUT1,This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD)." "0,1"
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|
newline
|
|
bitfld.long 0x10 11. "RTS,This bit enables request to send. This bit is the complement of the UART request to send nUARTRTS modem status output. That is when the bit is programmed to a 1 then nUARTRTS is LOW." "0,1"
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|
bitfld.long 0x10 10. "DTR,This bit enables data transmit ready. This bit is the complement of the UART data transmit ready nUARTDTR modem status output. That is when the bit is programmed to a 1 then nUARTDTR is LOW." "0,1"
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|
newline
|
|
bitfld.long 0x10 9. "RXE,This bit is the receive enable. If this bit is set to 1 the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of.." "0,1"
|
|
bitfld.long 0x10 8. "TXE,This bit is the transmit enable. If this bit is set to 1 the transmit section of the UART is enabled. Data transmission occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle.." "0,1"
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|
newline
|
|
bitfld.long 0x10 7. "LBE,This bit is the loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register UARTTCR is set to 1 then the nSIROUT path is inverted and fed through to the SIRIN path. The SIRTEST bit in the.." "0,1"
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|
bitfld.long 0x10 4.--6. "CLKSEL,This bitfield is the UART clock select." "0: No UART clock. This is the low power default.,1: 24 MHz clock.,2: 12 MHz clock.,3: 6 MHz clock.,4: 3 MHz clock.,5: Reserved.,?,?"
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|
newline
|
|
bitfld.long 0x10 3. "CLKEN,This bit is the UART clock enable." "0,1"
|
|
bitfld.long 0x10 2. "SIRLP,This bit is the SIR low power select. This bit selects the IrDA encoding mode. If this bit is cleared to 0 low-level bits are transmitted as an active high pulse with a width of 3/16th of the bit period. If this bit is set to 1 low-level bits are.." "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "SIREN,This bit is the SIR ENDEC enable. If this bit is set to 1 the IrDA SIR ENDEC is enabled. This bit has no effect if the UART is not enabled by bit 0 being set to 1. When the IrDA SIR ENDEC is enabled data is transmitted and received on nSIROUT and.." "0,1"
|
|
bitfld.long 0x10 0. "UARTEN,This bit is the UART enable. 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either.." "0: UART is disabled,1: the UART is enabled"
|
|
line.long 0x14 "IFLS,FIFO Interrupt Level Select"
|
|
bitfld.long 0x14 3.--5. "RXIFLSEL,These bits hold the receive FIFO interrupt level." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 0.--2. "TXIFLSEL,These bits hold the transmit FIFO interrupt level." "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "IER,Interrupt Enable"
|
|
bitfld.long 0x18 10. "OEIM,This bit holds the overflow interrupt enable." "0,1"
|
|
bitfld.long 0x18 9. "BEIM,This bit holds the break error interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 8. "PEIM,This bit holds the parity error interrupt enable." "0,1"
|
|
bitfld.long 0x18 7. "FEIM,This bit holds the framing error interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 6. "RTIM,This bit holds the receive timeout interrupt enable." "0,1"
|
|
bitfld.long 0x18 5. "TXIM,This bit holds the transmit interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 4. "RXIM,This bit holds the receive interrupt enable." "0,1"
|
|
bitfld.long 0x18 3. "DSRMIM,This bit holds the modem DSR interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 2. "DCDMIM,This bit holds the modem DCD interrupt enable." "0,1"
|
|
bitfld.long 0x18 1. "CTSMIM,This bit holds the modem CTS interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXCMPMIM,This bit holds the modem TXCMP interrupt enable." "0,1"
|
|
line.long 0x1C "IES,Interrupt Status"
|
|
bitfld.long 0x1C 10. "OERIS,This bit holds the overrun interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt." "0,1"
|
|
bitfld.long 0x1C 9. "BERIS,This bit holds the break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 8. "PERIS,This bit holds the parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt." "0,1"
|
|
bitfld.long 0x1C 7. "FERIS,This bit holds the framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 6. "RTRIS,This bit holds the receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt." "0,1"
|
|
bitfld.long 0x1C 5. "TXRIS,This bit holds the transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 4. "RXRIS,This bit holds the receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt." "0,1"
|
|
bitfld.long 0x1C 3. "DSRMRIS,This bit holds the nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 2. "DCDMRIS,This bit holds the nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt." "0,1"
|
|
bitfld.long 0x1C 1. "CTSMRIS,This bit holds the nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "TXCMPMRIS,This bit holds the modem TXCMP interrupt status." "0,1"
|
|
line.long 0x20 "MIS,Masked Interrupt Status"
|
|
bitfld.long 0x20 10. "OEMIS,This bit holds the overrun interrupt status masked. Returns the masked interrupt state of the UARTOEINTR interrupt." "0,1"
|
|
bitfld.long 0x20 9. "BEMIS,This bit holds the break error interrupt status masked. Returns the masked interrupt state of the UARTBEINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x20 8. "PEMIS,This bit holds the parity error interrupt status masked. Returns the masked interrupt state of the UARTPEINTR interrupt." "0,1"
|
|
bitfld.long 0x20 7. "FEMIS,This bit holds the framing error interrupt status masked. Returns the masked interrupt state of the UARTFEINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x20 6. "RTMIS,This bit holds the receive timeout interrupt status masked. Returns the masked interrupt state of the UARTRTINTR interrupt." "0,1"
|
|
bitfld.long 0x20 5. "TXMIS,This bit holds the transmit interrupt status masked. Returns the masked interrupt state of the UARTTXINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x20 4. "RXMIS,This bit holds the receive interrupt status masked. Returns the masked interrupt state of the UARTRXINTR interrupt." "0,1"
|
|
bitfld.long 0x20 3. "DSRMMIS,This bit holds the nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x20 2. "DCDMMIS,This bit holds the nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt." "0,1"
|
|
bitfld.long 0x20 1. "CTSMMIS,This bit holds the nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x20 0. "TXCMPMMIS,This bit holds the modem TXCMP interrupt status masked." "0,1"
|
|
line.long 0x24 "IEC,Interrupt Clear"
|
|
bitfld.long 0x24 10. "OEIC,This bit holds the overrun interrupt clear. Clears the UARTOEINTR interrupt." "0,1"
|
|
bitfld.long 0x24 9. "BEIC,This bit holds the break error interrupt clear. Clears the UARTBEINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x24 8. "PEIC,This bit holds the parity error interrupt clear. Clears the UARTPEINTR interrupt." "0,1"
|
|
bitfld.long 0x24 7. "FEIC,This bit holds the framing error interrupt clear. Clears the UARTFEINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x24 6. "RTIC,This bit holds the receive timeout interrupt clear. Clears the UARTRTINTR interrupt." "0,1"
|
|
bitfld.long 0x24 5. "TXIC,This bit holds the transmit interrupt clear. Clears the UARTTXINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x24 4. "RXIC,This bit holds the receive interrupt clear. Clears the UARTRXINTR interrupt." "0,1"
|
|
bitfld.long 0x24 3. "DSRMIC,This bit holds the nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x24 2. "DCDMIC,This bit holds the nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt." "0,1"
|
|
bitfld.long 0x24 1. "CTSMIC,This bit holds the nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x24 0. "TXCMPMIC,This bit holds the modem TXCMP interrupt clear." "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMA4B2KP")||cpuis("AMAP42KL")||cpuis("AMAP42KP"))
|
|
tree "UART2"
|
|
base ad:0x4001E000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "DR,UART Data"
|
|
bitfld.long 0x0 11. "OEDATA,Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it." "0: No error on UART OEDATA overrun error indicator.,1: Error on UART OEDATA overrun error indicator."
|
|
bitfld.long 0x0 10. "BEDATA,Break error. This bit is set to 1 if a break condition was detected indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start data parity and stop bits). In FIFO mode this error is.." "0: No error on UART BEDATA break error indicator.,1: Error on UART BEDATA break error indicator."
|
|
newline
|
|
bitfld.long 0x0 9. "PEDATA,Parity error. When set to 1 it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register UARTLCRH select. In FIFO mode this error is associated with the character.." "0: No error on UART PEDATA parity error indicator.,1: Error on UART PEDATA parity error indicator."
|
|
bitfld.long 0x0 8. "FEDATA,Framing error. When set to 1 it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode this error is associated with the character at the top of the FIFO." "0: No error on UART FEDATA framing error indicator.,1: Error on UART FEDATA framing error indicator."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,Receive (read) data character. Transmit (write) data character."
|
|
line.long 0x4 "RSR,UART Status"
|
|
bitfld.long 0x4 3. "OESTAT,Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full only the contents of the.." "0: No error on UART OESTAT overrun error indicator.,1: Error on UART OESTAT overrun error indicator."
|
|
bitfld.long 0x4 2. "BESTAT,Break error. This bit is set to 1 if a break condition was detected indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start data parity and stop bits). This bit is cleared to 0 after.." "0: No error on UART BESTAT break error indicator.,1: Error on UART BESTAT break error indicator."
|
|
newline
|
|
bitfld.long 0x4 1. "PESTAT,Parity error. When set to 1 it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register UARTLCRH select. This bit is cleared to 0 by a write to UARTECR. In FIFO.." "0: No error on UART PESTAT parity error indicator.,1: Error on UART PESTAT parity error indicator."
|
|
bitfld.long 0x4 0. "FESTAT,Framing error. When set to 1 it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode this error is associated with the character at the top of.." "0: No error on UART FESTAT framing error indicator.,1: Error on UART FESTAT framing error indicator."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "FR,Flags"
|
|
bitfld.long 0x0 8. "TXBUSY,This bit holds the transmit BUSY indicator." "0,1"
|
|
bitfld.long 0x0 7. "TXFE,Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register UARTLCRH. If the FIFO is disabled this bit is set when the transmit holding register is empty. If the FIFO is enabled the TXFE bit is.." "0: Transmit fifo is not empty.,1: Transmit fifo is empty."
|
|
newline
|
|
bitfld.long 0x0 6. "RXFF,Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCRH Register. If the FIFO is disabled this bit is set when the receive holding register is full. If the FIFO is enabled the RXFF bit is set when the receive.." "0: Receive fifo is not full.,1: Receive fifo is full."
|
|
bitfld.long 0x0 5. "TXFF,Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCRH Register. If the FIFO is disabled this bit is set when the transmit holding register is full. If the FIFO is enabled the TXFF bit is set when the.." "0: Transmit fifo is not full.,1: Transmit fifo is full."
|
|
newline
|
|
bitfld.long 0x0 4. "RXFE,Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCRH Register. If the FIFO is disabled this bit is set when the receive holding register is empty. If the FIFO is enabled the RXFE bit is set when the.." "0: Receive fifo is not empty.,1: Receive fifo is empty."
|
|
bitfld.long 0x0 3. "BUSY,UART busy. If this bit is set to 1 the UART is busy transmitting data. This bit remains set until the complete byte including all the stop bits has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty .." "0: UART not busy.,1: UART busy indicator."
|
|
newline
|
|
bitfld.long 0x0 2. "DCD,Data carrier detect. This bit is the complement of the UART data carrier detect nUARTDCD modem status input. That is the bit is 1 when nUARTDCD is LOW." "0: Data carrier detect not detected/default.,1: Data carrier detect detected."
|
|
bitfld.long 0x0 1. "DSR,Data set ready. This bit is the complement of the UART data set ready nUARTDSR modem status input. That is the bit is 1 when nUARTDSR is LOW." "0: Data set not ready/default.,1: Data set ready."
|
|
newline
|
|
bitfld.long 0x0 0. "CTS,Clear to send. This bit is the complement of the UART clear to send nUARTCTS modem status input. That is the bit is 1 when nUARTCTS is LOW." "0: Clear to send default value.,1: Clear to send is indicated."
|
|
group.long 0x20++0x27
|
|
line.long 0x0 "ILPR,IrDA Counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ILPDVSR,8-bit low-power divisor value. These bits are cleared to 0 at reset. Programming a zero value results in no IrLPBaud16 pulses being generated."
|
|
line.long 0x4 "IBRD,Integer Baud Rate Divisor"
|
|
hexmask.long.word 0x4 0.--15. 1. "DIVINT,These bits hold the baud integer divisor. These bits are cleared to 0 on reset."
|
|
line.long 0x8 "FBRD,Fractional Baud Rate Divisor"
|
|
hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,These bits hold the baud fractional divisor. These bits are cleared to 0 on reset."
|
|
line.long 0xC "LCRH,Line Control High"
|
|
bitfld.long 0xC 7. "SPS,This bit holds the stick parity select. If the EPS bit is 0 then the parity bit is transmitted and checked as a 1. If the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity.." "0,1"
|
|
bitfld.long 0xC 5.--6. "WLEN,These bits hold the write length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 4. "FEN,This bit holds the FIFO enable. 0 = FIFOs are disabled (character mode) that is the FIFOs become 1-byte-deep holding registers. 1 = transmit and receive FIFO buffers are enabled (FIFO mode)." "0: FIFOs are disabled,1: transmit and receive FIFO buffers are enabled"
|
|
bitfld.long 0xC 3. "STP2,This bit holds the two stop bits select. If this bit is set to 1 two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received." "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "EPS,This bit holds the even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates.." "0: odd parity,1: even parity"
|
|
bitfld.long 0xC 1. "PEN,This bit holds the parity enable. 0 = parity is disabled and no parity bit added to the data frame. 1 = parity checking and generation is enabled." "0: parity is disabled and no parity bit added to..,1: parity checking and generation is enabled"
|
|
newline
|
|
bitfld.long 0xC 0. "BRK,This bit holds the break set. If this bit is set to 1 a low-level is continually output on the UARTTXD output after completing transmission of the current character. For the proper execution of the break command the software must set this bit for.." "0,1"
|
|
line.long 0x10 "CR,Control"
|
|
bitfld.long 0x10 15. "CTSEN,This bit enables CTS hardware flow control. If this bit is set to 1 CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted." "0,1"
|
|
bitfld.long 0x10 14. "RTSEN,This bit enables RTS hardware flow control. If this bit is set to 1 RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received." "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "OUT2,This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is when the bit is programmed to a 1 the output is 0. For DTE this can be used as Ring Indicator (RI)." "0,1"
|
|
bitfld.long 0x10 12. "OUT1,This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD)." "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "RTS,This bit enables request to send. This bit is the complement of the UART request to send nUARTRTS modem status output. That is when the bit is programmed to a 1 then nUARTRTS is LOW." "0,1"
|
|
bitfld.long 0x10 10. "DTR,This bit enables data transmit ready. This bit is the complement of the UART data transmit ready nUARTDTR modem status output. That is when the bit is programmed to a 1 then nUARTDTR is LOW." "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "RXE,This bit is the receive enable. If this bit is set to 1 the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of.." "0,1"
|
|
bitfld.long 0x10 8. "TXE,This bit is the transmit enable. If this bit is set to 1 the transmit section of the UART is enabled. Data transmission occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle.." "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "LBE,This bit is the loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register UARTTCR is set to 1 then the nSIROUT path is inverted and fed through to the SIRIN path. The SIRTEST bit in the.." "0,1"
|
|
bitfld.long 0x10 4.--6. "CLKSEL,This bitfield is the UART clock select." "0: No UART clock. This is the low power default.,1: 24 MHz clock.,2: 12 MHz clock.,3: 6 MHz clock.,4: 3 MHz clock.,5: Reserved.,?,?"
|
|
newline
|
|
bitfld.long 0x10 3. "CLKEN,This bit is the UART clock enable." "0,1"
|
|
bitfld.long 0x10 2. "SIRLP,This bit is the SIR low power select. This bit selects the IrDA encoding mode. If this bit is cleared to 0 low-level bits are transmitted as an active high pulse with a width of 3/16th of the bit period. If this bit is set to 1 low-level bits are.." "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "SIREN,This bit is the SIR ENDEC enable. If this bit is set to 1 the IrDA SIR ENDEC is enabled. This bit has no effect if the UART is not enabled by bit 0 being set to 1. When the IrDA SIR ENDEC is enabled data is transmitted and received on nSIROUT and.." "0,1"
|
|
bitfld.long 0x10 0. "UARTEN,This bit is the UART enable. 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either.." "0: UART is disabled,1: the UART is enabled"
|
|
line.long 0x14 "IFLS,FIFO Interrupt Level Select"
|
|
bitfld.long 0x14 3.--5. "RXIFLSEL,These bits hold the receive FIFO interrupt level." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 0.--2. "TXIFLSEL,These bits hold the transmit FIFO interrupt level." "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "IER,Interrupt Enable"
|
|
bitfld.long 0x18 10. "OEIM,This bit holds the overflow interrupt enable." "0,1"
|
|
bitfld.long 0x18 9. "BEIM,This bit holds the break error interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 8. "PEIM,This bit holds the parity error interrupt enable." "0,1"
|
|
bitfld.long 0x18 7. "FEIM,This bit holds the framing error interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 6. "RTIM,This bit holds the receive timeout interrupt enable." "0,1"
|
|
bitfld.long 0x18 5. "TXIM,This bit holds the transmit interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 4. "RXIM,This bit holds the receive interrupt enable." "0,1"
|
|
bitfld.long 0x18 3. "DSRMIM,This bit holds the modem DSR interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 2. "DCDMIM,This bit holds the modem DCD interrupt enable." "0,1"
|
|
bitfld.long 0x18 1. "CTSMIM,This bit holds the modem CTS interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXCMPMIM,This bit holds the modem TXCMP interrupt enable." "0,1"
|
|
line.long 0x1C "IES,Interrupt Status"
|
|
bitfld.long 0x1C 10. "OERIS,This bit holds the overrun interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt." "0,1"
|
|
bitfld.long 0x1C 9. "BERIS,This bit holds the break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 8. "PERIS,This bit holds the parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt." "0,1"
|
|
bitfld.long 0x1C 7. "FERIS,This bit holds the framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 6. "RTRIS,This bit holds the receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt." "0,1"
|
|
bitfld.long 0x1C 5. "TXRIS,This bit holds the transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 4. "RXRIS,This bit holds the receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt." "0,1"
|
|
bitfld.long 0x1C 3. "DSRMRIS,This bit holds the nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 2. "DCDMRIS,This bit holds the nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt." "0,1"
|
|
bitfld.long 0x1C 1. "CTSMRIS,This bit holds the nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "TXCMPMRIS,This bit holds the modem TXCMP interrupt status." "0,1"
|
|
line.long 0x20 "MIS,Masked Interrupt Status"
|
|
bitfld.long 0x20 10. "OEMIS,This bit holds the overrun interrupt status masked. Returns the masked interrupt state of the UARTOEINTR interrupt." "0,1"
|
|
bitfld.long 0x20 9. "BEMIS,This bit holds the break error interrupt status masked. Returns the masked interrupt state of the UARTBEINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x20 8. "PEMIS,This bit holds the parity error interrupt status masked. Returns the masked interrupt state of the UARTPEINTR interrupt." "0,1"
|
|
bitfld.long 0x20 7. "FEMIS,This bit holds the framing error interrupt status masked. Returns the masked interrupt state of the UARTFEINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x20 6. "RTMIS,This bit holds the receive timeout interrupt status masked. Returns the masked interrupt state of the UARTRTINTR interrupt." "0,1"
|
|
bitfld.long 0x20 5. "TXMIS,This bit holds the transmit interrupt status masked. Returns the masked interrupt state of the UARTTXINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x20 4. "RXMIS,This bit holds the receive interrupt status masked. Returns the masked interrupt state of the UARTRXINTR interrupt." "0,1"
|
|
bitfld.long 0x20 3. "DSRMMIS,This bit holds the nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x20 2. "DCDMMIS,This bit holds the nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt." "0,1"
|
|
bitfld.long 0x20 1. "CTSMMIS,This bit holds the nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x20 0. "TXCMPMMIS,This bit holds the modem TXCMP interrupt status masked." "0,1"
|
|
line.long 0x24 "IEC,Interrupt Clear"
|
|
bitfld.long 0x24 10. "OEIC,This bit holds the overrun interrupt clear. Clears the UARTOEINTR interrupt." "0,1"
|
|
bitfld.long 0x24 9. "BEIC,This bit holds the break error interrupt clear. Clears the UARTBEINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x24 8. "PEIC,This bit holds the parity error interrupt clear. Clears the UARTPEINTR interrupt." "0,1"
|
|
bitfld.long 0x24 7. "FEIC,This bit holds the framing error interrupt clear. Clears the UARTFEINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x24 6. "RTIC,This bit holds the receive timeout interrupt clear. Clears the UARTRTINTR interrupt." "0,1"
|
|
bitfld.long 0x24 5. "TXIC,This bit holds the transmit interrupt clear. Clears the UARTTXINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x24 4. "RXIC,This bit holds the receive interrupt clear. Clears the UARTRXINTR interrupt." "0,1"
|
|
bitfld.long 0x24 3. "DSRMIC,This bit holds the nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x24 2. "DCDMIC,This bit holds the nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt." "0,1"
|
|
bitfld.long 0x24 1. "CTSMIC,This bit holds the nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x24 0. "TXCMPMIC,This bit holds the modem TXCMP interrupt clear." "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMA4B2KP")||cpuis("AMAP42KL")||cpuis("AMAP42KP"))
|
|
tree "UART3"
|
|
base ad:0x4001F000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "DR,UART Data"
|
|
bitfld.long 0x0 11. "OEDATA,Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it." "0: No error on UART OEDATA overrun error indicator.,1: Error on UART OEDATA overrun error indicator."
|
|
bitfld.long 0x0 10. "BEDATA,Break error. This bit is set to 1 if a break condition was detected indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start data parity and stop bits). In FIFO mode this error is.." "0: No error on UART BEDATA break error indicator.,1: Error on UART BEDATA break error indicator."
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bitfld.long 0x0 9. "PEDATA,Parity error. When set to 1 it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register UARTLCRH select. In FIFO mode this error is associated with the character.." "0: No error on UART PEDATA parity error indicator.,1: Error on UART PEDATA parity error indicator."
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bitfld.long 0x0 8. "FEDATA,Framing error. When set to 1 it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode this error is associated with the character at the top of the FIFO." "0: No error on UART FEDATA framing error indicator.,1: Error on UART FEDATA framing error indicator."
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hexmask.long.byte 0x0 0.--7. 1. "DATA,Receive (read) data character. Transmit (write) data character."
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|
line.long 0x4 "RSR,UART Status"
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bitfld.long 0x4 3. "OESTAT,Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full only the contents of the.." "0: No error on UART OESTAT overrun error indicator.,1: Error on UART OESTAT overrun error indicator."
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bitfld.long 0x4 2. "BESTAT,Break error. This bit is set to 1 if a break condition was detected indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start data parity and stop bits). This bit is cleared to 0 after.." "0: No error on UART BESTAT break error indicator.,1: Error on UART BESTAT break error indicator."
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bitfld.long 0x4 1. "PESTAT,Parity error. When set to 1 it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register UARTLCRH select. This bit is cleared to 0 by a write to UARTECR. In FIFO.." "0: No error on UART PESTAT parity error indicator.,1: Error on UART PESTAT parity error indicator."
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bitfld.long 0x4 0. "FESTAT,Framing error. When set to 1 it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode this error is associated with the character at the top of.." "0: No error on UART FESTAT framing error indicator.,1: Error on UART FESTAT framing error indicator."
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group.long 0x18++0x3
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line.long 0x0 "FR,Flags"
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bitfld.long 0x0 8. "TXBUSY,This bit holds the transmit BUSY indicator." "0,1"
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bitfld.long 0x0 7. "TXFE,Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register UARTLCRH. If the FIFO is disabled this bit is set when the transmit holding register is empty. If the FIFO is enabled the TXFE bit is.." "0: Transmit fifo is not empty.,1: Transmit fifo is empty."
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bitfld.long 0x0 6. "RXFF,Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCRH Register. If the FIFO is disabled this bit is set when the receive holding register is full. If the FIFO is enabled the RXFF bit is set when the receive.." "0: Receive fifo is not full.,1: Receive fifo is full."
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bitfld.long 0x0 5. "TXFF,Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCRH Register. If the FIFO is disabled this bit is set when the transmit holding register is full. If the FIFO is enabled the TXFF bit is set when the.." "0: Transmit fifo is not full.,1: Transmit fifo is full."
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newline
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bitfld.long 0x0 4. "RXFE,Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCRH Register. If the FIFO is disabled this bit is set when the receive holding register is empty. If the FIFO is enabled the RXFE bit is set when the.." "0: Receive fifo is not empty.,1: Receive fifo is empty."
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bitfld.long 0x0 3. "BUSY,UART busy. If this bit is set to 1 the UART is busy transmitting data. This bit remains set until the complete byte including all the stop bits has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty .." "0: UART not busy.,1: UART busy indicator."
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bitfld.long 0x0 2. "DCD,Data carrier detect. This bit is the complement of the UART data carrier detect nUARTDCD modem status input. That is the bit is 1 when nUARTDCD is LOW." "0: Data carrier detect not detected/default.,1: Data carrier detect detected."
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bitfld.long 0x0 1. "DSR,Data set ready. This bit is the complement of the UART data set ready nUARTDSR modem status input. That is the bit is 1 when nUARTDSR is LOW." "0: Data set not ready/default.,1: Data set ready."
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newline
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bitfld.long 0x0 0. "CTS,Clear to send. This bit is the complement of the UART clear to send nUARTCTS modem status input. That is the bit is 1 when nUARTCTS is LOW." "0: Clear to send default value.,1: Clear to send is indicated."
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group.long 0x20++0x27
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line.long 0x0 "ILPR,IrDA Counter"
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hexmask.long.byte 0x0 0.--7. 1. "ILPDVSR,8-bit low-power divisor value. These bits are cleared to 0 at reset. Programming a zero value results in no IrLPBaud16 pulses being generated."
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line.long 0x4 "IBRD,Integer Baud Rate Divisor"
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hexmask.long.word 0x4 0.--15. 1. "DIVINT,These bits hold the baud integer divisor. These bits are cleared to 0 on reset."
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line.long 0x8 "FBRD,Fractional Baud Rate Divisor"
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hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,These bits hold the baud fractional divisor. These bits are cleared to 0 on reset."
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line.long 0xC "LCRH,Line Control High"
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bitfld.long 0xC 7. "SPS,This bit holds the stick parity select. If the EPS bit is 0 then the parity bit is transmitted and checked as a 1. If the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity.." "0,1"
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bitfld.long 0xC 5.--6. "WLEN,These bits hold the write length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits." "0,1,2,3"
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bitfld.long 0xC 4. "FEN,This bit holds the FIFO enable. 0 = FIFOs are disabled (character mode) that is the FIFOs become 1-byte-deep holding registers. 1 = transmit and receive FIFO buffers are enabled (FIFO mode)." "0: FIFOs are disabled,1: transmit and receive FIFO buffers are enabled"
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bitfld.long 0xC 3. "STP2,This bit holds the two stop bits select. If this bit is set to 1 two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received." "0,1"
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bitfld.long 0xC 2. "EPS,This bit holds the even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates.." "0: odd parity,1: even parity"
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bitfld.long 0xC 1. "PEN,This bit holds the parity enable. 0 = parity is disabled and no parity bit added to the data frame. 1 = parity checking and generation is enabled." "0: parity is disabled and no parity bit added to..,1: parity checking and generation is enabled"
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bitfld.long 0xC 0. "BRK,This bit holds the break set. If this bit is set to 1 a low-level is continually output on the UARTTXD output after completing transmission of the current character. For the proper execution of the break command the software must set this bit for.." "0,1"
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line.long 0x10 "CR,Control"
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bitfld.long 0x10 15. "CTSEN,This bit enables CTS hardware flow control. If this bit is set to 1 CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted." "0,1"
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bitfld.long 0x10 14. "RTSEN,This bit enables RTS hardware flow control. If this bit is set to 1 RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received." "0,1"
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bitfld.long 0x10 13. "OUT2,This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is when the bit is programmed to a 1 the output is 0. For DTE this can be used as Ring Indicator (RI)." "0,1"
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bitfld.long 0x10 12. "OUT1,This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD)." "0,1"
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bitfld.long 0x10 11. "RTS,This bit enables request to send. This bit is the complement of the UART request to send nUARTRTS modem status output. That is when the bit is programmed to a 1 then nUARTRTS is LOW." "0,1"
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bitfld.long 0x10 10. "DTR,This bit enables data transmit ready. This bit is the complement of the UART data transmit ready nUARTDTR modem status output. That is when the bit is programmed to a 1 then nUARTDTR is LOW." "0,1"
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newline
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bitfld.long 0x10 9. "RXE,This bit is the receive enable. If this bit is set to 1 the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of.." "0,1"
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bitfld.long 0x10 8. "TXE,This bit is the transmit enable. If this bit is set to 1 the transmit section of the UART is enabled. Data transmission occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle.." "0,1"
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newline
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bitfld.long 0x10 7. "LBE,This bit is the loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register UARTTCR is set to 1 then the nSIROUT path is inverted and fed through to the SIRIN path. The SIRTEST bit in the.." "0,1"
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bitfld.long 0x10 4.--6. "CLKSEL,This bitfield is the UART clock select." "0: No UART clock. This is the low power default.,1: 24 MHz clock.,2: 12 MHz clock.,3: 6 MHz clock.,4: 3 MHz clock.,5: Reserved.,?,?"
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newline
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bitfld.long 0x10 3. "CLKEN,This bit is the UART clock enable." "0,1"
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bitfld.long 0x10 2. "SIRLP,This bit is the SIR low power select. This bit selects the IrDA encoding mode. If this bit is cleared to 0 low-level bits are transmitted as an active high pulse with a width of 3/16th of the bit period. If this bit is set to 1 low-level bits are.." "0,1"
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newline
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bitfld.long 0x10 1. "SIREN,This bit is the SIR ENDEC enable. If this bit is set to 1 the IrDA SIR ENDEC is enabled. This bit has no effect if the UART is not enabled by bit 0 being set to 1. When the IrDA SIR ENDEC is enabled data is transmitted and received on nSIROUT and.." "0,1"
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bitfld.long 0x10 0. "UARTEN,This bit is the UART enable. 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either.." "0: UART is disabled,1: the UART is enabled"
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line.long 0x14 "IFLS,FIFO Interrupt Level Select"
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bitfld.long 0x14 3.--5. "RXIFLSEL,These bits hold the receive FIFO interrupt level." "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 0.--2. "TXIFLSEL,These bits hold the transmit FIFO interrupt level." "0,1,2,3,4,5,6,7"
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line.long 0x18 "IER,Interrupt Enable"
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bitfld.long 0x18 10. "OEIM,This bit holds the overflow interrupt enable." "0,1"
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bitfld.long 0x18 9. "BEIM,This bit holds the break error interrupt enable." "0,1"
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newline
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bitfld.long 0x18 8. "PEIM,This bit holds the parity error interrupt enable." "0,1"
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bitfld.long 0x18 7. "FEIM,This bit holds the framing error interrupt enable." "0,1"
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newline
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bitfld.long 0x18 6. "RTIM,This bit holds the receive timeout interrupt enable." "0,1"
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bitfld.long 0x18 5. "TXIM,This bit holds the transmit interrupt enable." "0,1"
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newline
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bitfld.long 0x18 4. "RXIM,This bit holds the receive interrupt enable." "0,1"
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bitfld.long 0x18 3. "DSRMIM,This bit holds the modem DSR interrupt enable." "0,1"
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newline
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bitfld.long 0x18 2. "DCDMIM,This bit holds the modem DCD interrupt enable." "0,1"
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bitfld.long 0x18 1. "CTSMIM,This bit holds the modem CTS interrupt enable." "0,1"
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newline
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bitfld.long 0x18 0. "TXCMPMIM,This bit holds the modem TXCMP interrupt enable." "0,1"
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line.long 0x1C "IES,Interrupt Status"
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bitfld.long 0x1C 10. "OERIS,This bit holds the overrun interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt." "0,1"
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bitfld.long 0x1C 9. "BERIS,This bit holds the break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt." "0,1"
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newline
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bitfld.long 0x1C 8. "PERIS,This bit holds the parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt." "0,1"
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bitfld.long 0x1C 7. "FERIS,This bit holds the framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt." "0,1"
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newline
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bitfld.long 0x1C 6. "RTRIS,This bit holds the receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt." "0,1"
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bitfld.long 0x1C 5. "TXRIS,This bit holds the transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt." "0,1"
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newline
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bitfld.long 0x1C 4. "RXRIS,This bit holds the receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt." "0,1"
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bitfld.long 0x1C 3. "DSRMRIS,This bit holds the nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt." "0,1"
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newline
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bitfld.long 0x1C 2. "DCDMRIS,This bit holds the nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt." "0,1"
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bitfld.long 0x1C 1. "CTSMRIS,This bit holds the nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt." "0,1"
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newline
|
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bitfld.long 0x1C 0. "TXCMPMRIS,This bit holds the modem TXCMP interrupt status." "0,1"
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line.long 0x20 "MIS,Masked Interrupt Status"
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bitfld.long 0x20 10. "OEMIS,This bit holds the overrun interrupt status masked. Returns the masked interrupt state of the UARTOEINTR interrupt." "0,1"
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bitfld.long 0x20 9. "BEMIS,This bit holds the break error interrupt status masked. Returns the masked interrupt state of the UARTBEINTR interrupt." "0,1"
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newline
|
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bitfld.long 0x20 8. "PEMIS,This bit holds the parity error interrupt status masked. Returns the masked interrupt state of the UARTPEINTR interrupt." "0,1"
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bitfld.long 0x20 7. "FEMIS,This bit holds the framing error interrupt status masked. Returns the masked interrupt state of the UARTFEINTR interrupt." "0,1"
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newline
|
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bitfld.long 0x20 6. "RTMIS,This bit holds the receive timeout interrupt status masked. Returns the masked interrupt state of the UARTRTINTR interrupt." "0,1"
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bitfld.long 0x20 5. "TXMIS,This bit holds the transmit interrupt status masked. Returns the masked interrupt state of the UARTTXINTR interrupt." "0,1"
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newline
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bitfld.long 0x20 4. "RXMIS,This bit holds the receive interrupt status masked. Returns the masked interrupt state of the UARTRXINTR interrupt." "0,1"
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bitfld.long 0x20 3. "DSRMMIS,This bit holds the nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt." "0,1"
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newline
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bitfld.long 0x20 2. "DCDMMIS,This bit holds the nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt." "0,1"
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bitfld.long 0x20 1. "CTSMMIS,This bit holds the nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt." "0,1"
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newline
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bitfld.long 0x20 0. "TXCMPMMIS,This bit holds the modem TXCMP interrupt status masked." "0,1"
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line.long 0x24 "IEC,Interrupt Clear"
|
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bitfld.long 0x24 10. "OEIC,This bit holds the overrun interrupt clear. Clears the UARTOEINTR interrupt." "0,1"
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bitfld.long 0x24 9. "BEIC,This bit holds the break error interrupt clear. Clears the UARTBEINTR interrupt." "0,1"
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newline
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bitfld.long 0x24 8. "PEIC,This bit holds the parity error interrupt clear. Clears the UARTPEINTR interrupt." "0,1"
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bitfld.long 0x24 7. "FEIC,This bit holds the framing error interrupt clear. Clears the UARTFEINTR interrupt." "0,1"
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newline
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bitfld.long 0x24 6. "RTIC,This bit holds the receive timeout interrupt clear. Clears the UARTRTINTR interrupt." "0,1"
|
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bitfld.long 0x24 5. "TXIC,This bit holds the transmit interrupt clear. Clears the UARTTXINTR interrupt." "0,1"
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newline
|
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bitfld.long 0x24 4. "RXIC,This bit holds the receive interrupt clear. Clears the UARTRXINTR interrupt." "0,1"
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bitfld.long 0x24 3. "DSRMIC,This bit holds the nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt." "0,1"
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newline
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bitfld.long 0x24 2. "DCDMIC,This bit holds the nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt." "0,1"
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bitfld.long 0x24 1. "CTSMIC,This bit holds the nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt." "0,1"
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newline
|
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bitfld.long 0x24 0. "TXCMPMIC,This bit holds the modem TXCMP interrupt clear." "0,1"
|
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tree.end
|
|
endif
|
|
tree.end
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMA4B2KP")||cpuis("AMAP42KK")||cpuis("AMAP42KP"))
|
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tree "USB (Universal Serial Bus)"
|
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base ad:0x400B0000
|
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group.long 0x0++0x37
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line.long 0x0 "CFG0,Function address. power management. interrupt status register for EP0 and IN Endpoints 1 to 5"
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bitfld.long 0x0 21. "EP5InIntStat,IN Endpoint 5 interrupt status. All interrupts are cleared when the register is read." "0: Interrupt inactive.,1: Interrupt active."
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newline
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bitfld.long 0x0 20. "EP4InIntStat,IN Endpoint 4 interrupt status. All interrupts are cleared when the register is read." "0: Interrupt inactive.,1: Interrupt active."
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newline
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bitfld.long 0x0 19. "EP3InIntStat,IN Endpoint 3 interrupt status. All interrupts are cleared when the register is read." "0: Interrupt inactive.,1: Interrupt active."
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newline
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bitfld.long 0x0 18. "EP2InIntStat,IN Endpoint 2 interrupt status. All interrupts are cleared when the register is read." "0: Interrupt inactive.,1: Interrupt active."
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newline
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bitfld.long 0x0 17. "EP1InIntStat,IN Endpoint 1 interrupt status. All interrupts are cleared when the register is read." "0: Interrupt inactive.,1: Interrupt active."
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newline
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bitfld.long 0x0 16. "EP0InIntStat,IN Endpoint 0 interrupt status. All interrupts are cleared when the register is read." "0: Interrupt inactive.,1: Interrupt active."
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newline
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bitfld.long 0x0 15. "ISOUpdate,Isochronous Transfer Update. When set by the CPU the USB Controller will wait for an SOF token from the time InPktRdy is set before sending the packet. If an IN token is received before an SOF token then a zero length data packet will be.." "0: Clear for USB Controller not to wait for SOF..,1: Set to have USB Controller wait for SOF token.."
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newline
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bitfld.long 0x0 14. "AMSPECIFIC,Software-enabled Connection (SoftConn). When set to 1 the PHY is placed in its normal mode and the D+/D- lines of the USB bus are enabled. When bit is cleared the PHY is put into non-driving mode and D+ and D- are tri-stated." "0: Clear to disable/disconnect USB lines.,1: Set to enable USB lines."
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newline
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bitfld.long 0x0 13. "HSEnab,High-speed Enable. When set by the CPU the USB Controller will negotiate for high-speed mode when the device is reset by the hub. If not set the device will only operate in Full-speed mode. The HSEnab bit can be used to disable high-speed.." "0: Clear to disable High-speed mode (Full-speed..,1: Set to enable High-speed mode."
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newline
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bitfld.long 0x0 12. "HSMode,This read-only bit is set when the USB Controller has successfully negotiated for High-speed mode. The HSMode bit can be used to determine whether the USB Controller is in High-speed mode or Full-speed mode. It will go high when the function has.." "0: Indicates USB Controller is in Full-speed mode..,1: Indicates USB Controller is in High-speed mode."
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newline
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bitfld.long 0x0 11. "Reset,Reset Status. Cleared when either HS negotiation has completed successfully or after 2.1 ms of reset signaling if HS negotiation fails. The Reset bit can be used to determine when reset signaling is present on the USB. Set when Reset signaling is.." "0: Indicates that HS negotiation has completed..,1: Indicates that Reset signaling is detected and.."
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newline
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bitfld.long 0x0 10. "Resume,Resume. Set should clear this bit after 10 ms (a maximum of 15 ms) to end Resume signaling. The Resume bit is used to force the USB Controller to generate Resume signaling on the USB to perform remote wake-up from Suspend mode. Once set high it.." "0: Cleared automatically 10-15 ms after being..,1: Set to force USB Controller to generate Resume.."
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newline
|
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bitfld.long 0x0 9. "Suspen,Suspend Status. This read-only bit is set when Suspend mode is entered. It is cleared when the CPU reads the interrupt register or sets the Resume bit of this register. The Suspen bit is set by the USB Controller when Suspend mode is entered. It.." "0: Indicates that Suspend Mode exited.,1: Indicates that Suspend Mode entered."
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newline
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bitfld.long 0x0 8. "Enabl,Set by the CPU to enable the SUSPENDM signal. The Enabl bit is set to enable the SUSPENDM signal to put the UTM (and any other hardware which uses the SUSPENDM signal) into Suspend mode. If this bit is not set Suspend mode will be detected as.." "0: Clear to disable SUSPENDM signal - UTM does not..,1: Set to enable the SUSPENDM signal to put the UTM.."
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|
newline
|
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bitfld.long 0x0 7. "Update,Function Address Update. Set when FuncAddr is written. Cleared when the new address takes effect (at the end of the current transfer)." "0: Indicates that the new address has taken effect.,1: Indicates that a new function address has been.."
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|
newline
|
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hexmask.long.byte 0x0 0.--6. 1. "FuncAddr,The function address. This field should be written with the address value contained in the SET_ADDRESS standard device request when it is received on Endpoint 0. The new address will not take effect immediately as the host will still be using.."
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|
line.long 0x4 "CFG1,Indicates which of the IN Endpoint 1 - 5 interrupts and the single Endpoint 0 interrupt are currently active. Also indicates which of the interrupts for OUT Endpoint 1 - 5 are currently active. All active interrupts are cleared when this register is.."
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bitfld.long 0x4 21. "EP5InIntEn,IN Endpoint 5 Interrupt Enable" "0: IN Endpoint interrupt disabled.,1: IN Endpoint interrupt enabled."
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newline
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bitfld.long 0x4 20. "EP4InIntEn,IN Endpoint 4 Interrupt Enable" "0: IN Endpoint interrupt disabled.,1: IN Endpoint interrupt enabled."
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newline
|
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bitfld.long 0x4 19. "EP3InIntEn,IN Endpoint 3 Interrupt Enable" "0: IN Endpoint interrupt disabled.,1: IN Endpoint interrupt enabled."
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|
newline
|
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bitfld.long 0x4 18. "EP2InIntEn,IN Endpoint 2 Interrupt Enable" "0: IN Endpoint interrupt disabled.,1: IN Endpoint interrupt enabled."
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newline
|
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bitfld.long 0x4 17. "EP1InIntEn,IN Endpoint 1 Interrupt Enable" "0: IN Endpoint interrupt disabled.,1: IN Endpoint interrupt enabled."
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newline
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bitfld.long 0x4 16. "EP0InIntEn,IN Endpoint 0 Interrupt Enable" "0: IN Endpoint interrupt disabled.,1: IN Endpoint interrupt enabled."
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bitfld.long 0x4 5. "EP5OutIntStat,OUT Endpoint 5 interrupt status. All interrupts are cleared when the register is read." "0: Interrupt inactive.,1: Interrupt active."
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bitfld.long 0x4 4. "EP4OutIntStat,OUT Endpoint 4 interrupt status. All interrupts are cleared when the register is read." "0: Interrupt inactive.,1: Interrupt active."
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bitfld.long 0x4 3. "EP3OutIntStat,OUT Endpoint 3 interrupt status. All interrupts are cleared when the register is read." "0: Interrupt inactive.,1: Interrupt active."
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bitfld.long 0x4 2. "EP2OutIntStat,OUT Endpoint 2 interrupt status. All interrupts are cleared when the register is read." "0: Interrupt inactive.,1: Interrupt active."
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bitfld.long 0x4 1. "EP1OutIntStat,OUT Endpoint 1 interrupt status. All interrupts are cleared when the register is read." "0: Interrupt inactive.,1: Interrupt active."
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bitfld.long 0x4 0. "EP0OutIntStat,OUT Endpoint 0 interrupt status. All interrupts are cleared when the register is read." "0: Interrupt inactive.,1: Interrupt active."
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line.long 0x8 "CFG2,Provides interrupt enable and (currently active) status bits for each of the state interrupts. as well as the IN Endpoint and OUT Endpoint nterrupts. All active interrupts are cleared when this register is read. On reset. all IN and OUT Endpoint.."
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bitfld.long 0x8 27. "SOFE,Start of Frame interrupt enable." "0: SOF interrupt disable.,1: SOF interrupt enable."
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bitfld.long 0x8 26. "ResetE,Reset Detect Interrupt Enable." "0: Reset detect interrupt disable.,1: Reset detect interrupt enable."
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bitfld.long 0x8 25. "ResumeE,Resume Interrupt Enable." "0: Resume interrupt disable.,1: Resume interrupt enable."
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bitfld.long 0x8 24. "SuspendE,Suspend Interrupt Enable." "0: Suspend interrupt disable.,1: Suspend interrupt enable."
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bitfld.long 0x8 19. "SOF,Start of Frame Interrupt Status. Set at the start of frame." "0: SOF interrupt inactive.,1: SOF interrupt active."
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bitfld.long 0x8 18. "Reset,Reset Detect Interrupt Status. Set when reset signaling is detected on the bus." "0: Reset Detect interrupt inactive.,1: Reset Detect interrupt active."
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bitfld.long 0x8 17. "Resume,Resume Interrupt Status. Set when resume signaling is detected on the bus while the USB Controller is in Suspend mode." "0: Resume interrupt inactive.,1: Resume interrupt active."
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bitfld.long 0x8 16. "Suspend,Suspend Interrupt Status. Set when suspend signaling is detected on the bus." "0: Suspend interrupt inactive.,1: Suspend interrupt active."
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bitfld.long 0x8 5. "EP5OutIntEn,Out Endpoint 5 Interrupt Enable." "0: Out Endpoint interrupt disabled.,1: Out Endpoint interrupt enabled."
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bitfld.long 0x8 4. "EP4OutIntEn,Out Endpoint 4 Interrupt Enable." "0: Out Endpoint interrupt disabled.,1: Out Endpoint interrupt enabled."
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bitfld.long 0x8 3. "EP3OutIntEn,Out Endpoint 3 Interrupt Enable." "0: Out Endpoint interrupt disabled.,1: Out Endpoint interrupt enabled."
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bitfld.long 0x8 2. "EP2OutIntEn,Out Endpoint 2 Interrupt Enable." "0: Out Endpoint interrupt disabled.,1: Out Endpoint interrupt enabled."
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bitfld.long 0x8 1. "EP1OutIntEn,Out Endpoint 1 Interrupt Enable." "0: Out Endpoint interrupt disabled.,1: Out Endpoint interrupt enabled."
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bitfld.long 0x8 0. "EP0OutIntEn,Out Endpoint 0 Interrupt Enable." "0: Out Endpoint interrupt disabled.,1: Out Endpoint interrupt enabled."
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line.long 0xC "CFG3,Provides Test fields to put the USB Controller into one of four test modes described in the USB 2.0 specification. Only one of the Test fields should be set at any time. (Not used in normal operation.) Also includes an index field that determines.."
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bitfld.long 0xC 29. "ForceFS,Force Full-speed Mode. The CPU sets this bit to force the USB Controller into Full-speed mode when it receives a USB reset." "0: Do not force FS mode upon USB reset.,1: Force FS mode upon USB reset."
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bitfld.long 0xC 28. "ForceHS,Force High-speed Mode. The CPU sets this bit to force the USB Controller into High-speed mode when it receives a USB reset." "0: Do not force HS mode upon USB reset.,1: Force HS mode upon USB reset."
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bitfld.long 0xC 27. "TestPacket,Test Packet Test Mode. The CPU sets this bit to enter the Test_Packet test mode. In this mode the USB Controller - in high-speed mode - repetitively transmits on the bus a 53-byte test packet. Note: The 53-byte test packet must be loaded into.." "0: Terminates Test Packet Test Mode.,1: Initiates Test Packet Test Mode."
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bitfld.long 0xC 26. "TestK,Test_K Test Mode. The CPU sets this bit to enter the Test_K test mode. In this mode the USB Controller - in high-speed mode - transmits a continuous K on the bus." "0: Terminates Test_K Test Mode.,1: Initiates Test_K Test Mode."
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bitfld.long 0xC 25. "TestJ,Test_J Test Mode. The CPU sets this bit to enter the Test_J test mode. In this mode the USB Controller - in high-speed mode - transmits a continuous J on the bus." "0: Terminates Test_J Test Mode.,1: Initiates Test_J Test Mode."
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bitfld.long 0xC 24. "TestSE0NAK,Test_SE0_NAK Test Mode. The CPU sets this bit to enter the Test_SE0_NAK test mode. In this mode the USB Controller remains in high-speed mode and responds to any valid IN token with a NAK." "0: Terminates Test_SE0_NAK Test Mode.,1: Initiates Test_SE0_NAK Test Mode."
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hexmask.long.byte 0xC 16.--19. 1. "ENDPOINT,Index selected endpoint."
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hexmask.long.word 0xC 0.--15. 1. "FRMNUM,Frame Number. Read-only field containing the last received frame number in bits 10:0 15:11 read 0."
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line.long 0x10 "IDX0,Provides additional control and status for IN transactions through the currently-selected endpoint. (To avoid CMSIS conflicts. the address here includes an additional offset of 0x1000. Access to this register must take this into account.) The value.."
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bitfld.long 0x10 31. "AutoSet,Automatically Set InPktRdy. When set the FIFONotEmptyInPktRdy field (for IN Endpoint 0) or InPktRdyOutPktRdy field (for IN Endpoint 1-5) in this register will be automatically set when data of the maximum packet size (set in MAXPAYLOAD field) is.." "0: InPktRdy field is not automatically set when..,1: Applicable InPktRdy field is automatically set.."
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bitfld.long 0x10 30. "ISO,Isochronous Transfers. The CPU sets this bit to enable the IN endpoint for Isochronous transfers (ISO mode) or for Bulk/Interrupt transfers." "0: Clear to enable the IN endpoint for..,1: Set to enable the IN endpoint for Isochronous.."
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bitfld.long 0x10 29. "Mode,OUT/IN Mode. The CPU sets this bit to enable the endpoint direction as IN or OUT. Note: Only valid where the endpoint FIFO is used for both IN and OUT transactions otherwise ignored." "0: Clear to enable the OUT direction for endpoint.,1: Set to enable the IN direction for endpoint."
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bitfld.long 0x10 27. "FrcDataTog,Force Data Toggle. The CPU sets this bit to force the endpoint's IN data toggle to switch after each data packet is sent regardless of whether an ACK was received. This can be used by Interrupt IN endpoints that are used to communicate rate.." "0: Keep cleared to not force data toggle.,1: Set to force the endpoint's IN data toggle to.."
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bitfld.long 0x10 25. "DPktBufDis,Double Packet Buffer Disable. This bit is used to control the use of Double Packet Buffering. It is ignored when Dynamic FIFO sizing is enabled. Clearing this bit does NOT necessarily enable Double Packet Buffering but rather allows Double.." "0: Clear to allow Double Packet Buffering.,1: Set to disable Double Packet Buffering.."
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bitfld.long 0x10 24. "D0,Unused always return 0." "0,1"
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bitfld.long 0x10 23. "IncompTxServiceSetupEnd,Incomplete Transmission / Service Setup End. When CFG3_ENDPOINT = 1 to 5 this bit serves as the IncompTx field. When CFG3_ENDPOINT = 0 this bit serves as the ServiceSetupEnd field.If CFG3_ENDPOINT = 0x1-0x5 then this bit serves.." "0: Packet has NOT been split into multiple packets..,1: A large packet has been split into 2 or 3.."
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bitfld.long 0x10 22. "ClrDataTogServicedOutPktRdy,Clear Data Toggle / Serviced OUT Packet Ready. When CFG3_ENDPOINT = 1 to 5 this bit serves as the ClrDataTog field. When CFG3_ENDPOINT = 0 this bit serves as the ServicedOutPktReady field.If CFG3_ENDPOINT = 0x1-0x5 this bit.." "0,1"
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bitfld.long 0x10 21. "SentStallSendStall,Sent Stall / Send Stall. When CFG3_ENDPOINT = 1 to 5 this bit serves as the SentStall field. When CFG3_ENDPOINT = 0 this bit serves as the SendStall function.If CFG3_ENDPOINT = 0x1-0x5 this bit serves as the SentStall field. It is.." "0,1"
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bitfld.long 0x10 20. "SendStallSetupEnd,When CFG3_ENDPOINT = 1 to 5 this bit serves as the SendStall field. When CFG3_ENDPOINT = 0 this bit serves as the SetupEnd field.If CFG3_ENDPOINT = 0x1-0x5 this bit serves as the SendStall field. Setting this bit issues a STALL.." "0,1"
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bitfld.long 0x10 19. "FlushFIFODataEnd,When CFG3_ENDPOINT = 1 to 5 this bit serves as the FlushFIFO field. When CFG3_ENDPOINT = 0 this bit serves as the DataEnd bit.If CFG3_ENDPOINT = 0x1-0x5 this bit serves as the FlushFIFO field. Setting this bit flushes the next packet.." "?,1: FlushFIFO should only be set when InPktRdy is set"
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bitfld.long 0x10 18. "UnderRunSentStall,Under Run / Sent Stall. When CFG3_ENDPOINT = 1 to 5 this bit serves as the UnderRun field. When CFG3_ENDPOINT = 0 this bit serves as the SentStall field.If CFG3_ENDPOINT = 0x1-0x5 this bit serves as the UnderRun field. In ISO mode.." "0,1"
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bitfld.long 0x10 17. "FIFONotEmptyInPktRdy,FIFO Not Empty / IN Packet Ready. When CFG3_ENDPOINT = 1 to 5 this bit serves as the FIFONotEmpty field. When CFG3_ENDPOINT = 0 this bit serves as the InPktRdy bit.If CFG3_ENDPOINT = 0x1-0x5 this bit serves as the FIFONotEmpty.." "0,1"
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bitfld.long 0x10 16. "InPktRdyOutPktRdy,IN Packet Ready / OUT Packet Ready. When CFG3_ENDPOINT > 0 this bit serves as the InPktRdy field. When CFG3_ENDPOINT = 0 this bit serves as the OutPkyRdy bit.If CFG3_ENDPOINT = 0x1-0x5 this bit serves as the InPktRdy field. Set this.." "0,1"
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hexmask.long.byte 0x10 11.--15. 1. "PKTSPLITOPTION,Packet Split Option. When IDX0_ISO = 1 this bit serves as the MAXPAYLOAD multiplier for Isochronous IN transfers. When IDX0_ISO = 0 this bit serves as the MAXPAYLOAD multiplier for Bulk IN transfers.If IDX0_ISO = 0x1 this field sets the.."
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hexmask.long.word 0x10 0.--10. 1. "MAXPAYLOAD,Maximum Payload transmitted in a single transaction. The total amount of data represented by MAXPAYLOAD x (PKTSPLITOPTION + 1) must not exceed the FIFO size for the IN endpoint and should not exceed half the FIFO size if double-buffering is.."
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line.long 0x14 "IDX1,Provides control and status bits for OUT transactions through the currently-selected endpoint. It is reset to 0. The value returned when this register is read reflects the status of an endpoint specified by setting the endpoint index in the.."
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bitfld.long 0x14 31. "AutoClear,Automatically Clear OutPktRdy." "0: OutPktRdy field will not be automatically..,1: OutPktRdy field will be automatically cleared.."
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bitfld.long 0x14 30. "ISO,Isochronous Transfers. The CPU sets this bit to enable the OUT endpoint for either Isochronous transfers (ISO mode) or for Bulk/Interrupt transfers." "0: Clear to enable the OUT endpoint for..,1: Set to enable the OUT endpoint for Isochronous.."
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bitfld.long 0x14 28. "DisNye,Disable NYET Handshakes / PID Error. For Bulk/Interrupt transactions this bit disable the sending of NYET handshakes. For Bulk/Interrupt transactions indicates PID errors.If IDX1_ISO = 0x1 this field is read-only and when set indicates a PID.." "0,1"
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bitfld.long 0x14 25. "DPktBufDis,Double Packet Buffer Disable. This bit is used to control the use of Double Packet Buffering. It is ignored when Dynamic FIFO sizing is enabled. Clearing this bit does NOT necessarily enable Double Packet Buffering but rather allows Double.." "0: Clear to allow Double Packet Buffering.,1: Set to disable Double Packet Buffering.."
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bitfld.long 0x14 24. "IncompRx,Incomplete Receive. This bit is set in a high-bandwidth Isochronous transfer if the packet in the OUT FIFO is incomplete because parts of the data were not received. It is cleared when OutPktRdy is cleared. Note: In anything other than a.." "0,1"
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bitfld.long 0x14 23. "ClrDataTog,Clear Data Toggle. Set this bit to reset the endpoint data toggle to 0." "0,1"
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bitfld.long 0x14 22. "SentStall,Sent Stall. This bit is set when a STALL handshake is transmitted. The CPU should clear this bit." "0,1"
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bitfld.long 0x14 21. "SendStall,Send Stall. Issues a STALL handshake to a DATA packet.If IDX1_ISO = 0x1 this bit has no effect when the endpoint is being used for Isochronous transfers.If IDX1_ISO = 0x0 this field enables Stall Handshakes for Bulk/Interrupt transactions." "0,1"
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bitfld.long 0x14 20. "FlushFIFO,Flush FIFO. Set this bit to flush the next packet to be read from the endpoint OUT FIFO. The FIFO pointer is reset and the OutPktRdy bit is cleared. FlushFIFO should only be used when OutPktRdy is set. At other times it may cause data to be.." "0,1"
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bitfld.long 0x14 19. "DataError,Data Error. Indicates a CRC error.If IDX1_ISO = 0x1 (ISO mode) this bit is set at the same time that OutPktRdy is set if the data packet has a CRC error. It is cleared when OutPktRdy is cleared.If IDX1_ISO = 0x0 (Bulk mode) this field always.." "0,1"
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bitfld.long 0x14 18. "OverRun,Overrun Condition. Indicates an overrun.If IDX1_ISO = 0x1 (ISO mode) this bit is set if an OUT packet arrives while FIFOFull is set i.e. the OUT packet cannot be loaded into the OUT FIFO. The CPU should clear this bit.If IDX1_ISO = 0x0 (Bulk.." "0,1"
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bitfld.long 0x14 17. "FIFOFull,FIFO Full. When set this bit indicates that no more packets can be loaded into the OUT FIFO." "0,1"
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bitfld.long 0x14 16. "OutPktRdy,OUT Packet Ready. This bit is set when a data packet has been received. Clear this bit when the packet has been unloaded from the OUT FIFO. An interrupt is generated (if enabled) when the bit is set." "0,1"
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hexmask.long.byte 0x14 11.--15. 1. "PKTSPLITOPTION,Packet Split Option. When IDX1_ISO = 1 this bit serves as the MAXPAYLOAD multiplier for Isochronous OUT transfers. When IDX1_ISO = 0 this bit serves as the MAXPAYLOAD multiplier for Bulk IN transfers.If IDX1_ISO = 0x1 this field sets.."
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hexmask.long.word 0x14 0.--10. 1. "MAXPAYLOAD,Maximum Payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk Interrupt and Isochronous transfers in Fullspeed and.."
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line.long 0x18 "IDX2,Contains the outcount value for number of received bytes in the packet in the OUT FIFO. and the configurable IN and OUT Endpoint FIFO size."
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hexmask.long.byte 0x18 24.--28. 1. "OUTFIFOSZ,OUT FIFO Size. Sets the size of the selected OUT endpoint FIFO. Bit 4 of this field defines whether double-packet buffering is supported. When set double-packet buffering is supported. When cleared only single-packet buffering is supported."
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hexmask.long.byte 0x18 16.--20. 1. "INFIFOSZ,IN FIFO Size. Sets the size of the selected IN endpoint FIFO. Bit 4 of this field defines whether double-packet buffering supported. When set double-packet buffering is supported. When cleared only single-packet buffering is supported. Bits.."
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hexmask.long.word 0x18 0.--12. 1. "ENDPTOUTCOUNT,Endpoint OUT Count. When CFG3_ENDPOINT = 1 to 5 this read-only field holds the number of received data bytes in the packet in the Endpoint's OUT FIFO. When CFG3_ENDPOINT = 0 this read-only field holds 7-bit data for number of received.."
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line.long 0x1C "FIFOADD,Sets the start address of the selected IN and OUT endpoint FIFOs."
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hexmask.long.word 0x1C 16.--28. 1. "OUTFIFOADD,Sets the start address of the selected OUT endpoint FIFO."
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hexmask.long.word 0x1C 0.--12. 1. "INFIFOADD,Sets the start address of the selected IN endpoint FIFO."
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line.long 0x20 "FIFO0,Endpoint 0 FIFO register"
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hexmask.long 0x20 0.--31. 1. "FIFO,Writing to this register loads data into the IN FIFO and reading from this register unloads data from the OUT FIFO for endpoint 0."
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line.long 0x24 "FIFO1,Endpoint 1 FIFO register"
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hexmask.long 0x24 0.--31. 1. "FIFO,Writing to this register loads data into the IN FIFO and reading from this register unloads data from the OUT FIFO for endpoint 1."
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line.long 0x28 "FIFO2,Endpoint 2 FIFO register"
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hexmask.long 0x28 0.--31. 1. "FIFO,Writing to this register loads data into the IN FIFO and reading from this register unloads data from the OUT FIFO for endpoint 2."
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line.long 0x2C "FIFO3,Endpoint 3 FIFO register"
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hexmask.long 0x2C 0.--31. 1. "FIFO,Writing to this register loads data into the IN FIFO and reading from this register unloads data from the OUT FIFO for endpoint 3."
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line.long 0x30 "FIFO4,Endpoint 4 FIFO register"
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hexmask.long 0x30 0.--31. 1. "FIFO,Writing to this register loads data into the IN FIFO and reading from this register unloads data from the OUT FIFO for endpoint 4."
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line.long 0x34 "FIFO5,Endpoint 5 FIFO register"
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hexmask.long 0x34 0.--31. 1. "FIFO,Writing to this register loads data into the IN FIFO and reading from this register unloads data from the OUT FIFO for endpoint 5."
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group.long 0x6C++0x3
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line.long 0x0 "HWVERS,Read-only register that returns version number (xx.yyy) of the core hardware."
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bitfld.long 0x0 15. "RC,Unused" "0,1"
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hexmask.long.byte 0x0 10.--14. 1. "xx,Major Version Number (Range 0 - 31)."
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hexmask.long.word 0x0 0.--9. 1. "yyy,Minor Version Number (Range 0 - 999)."
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group.long 0x78++0x3
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line.long 0x0 "INFO,Contains read-only info of the number of IN and OUT endpoints included in the design. width of the RAM. the ability to reset the USB Controller via software. a soft reset bit for the CLK clock domain and a soft reset bit for the XCLK clock domain."
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bitfld.long 0x0 17. "RSTXS,Soft reset for the XCLK domain. will cause the output signal NRSTXO to be asserted low. This bit is self-clearing. For reset to actually occur the output NRSTXO must be connected to the input NRSTX." "0,1"
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bitfld.long 0x0 16. "RSTS,Soft reset for the CLK domain. cause the output signal NRSTO to be asserted low. This bit is self-clearing. For reset to actually occur the output NRSTO must be connected to the input NRST." "0,1"
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hexmask.long.byte 0x0 8.--11. 1. "RamBits,Provides the width of the RAM address bus."
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hexmask.long.byte 0x0 4.--7. 1. "OutEndPoints,Provides the number of implemented OUT Endpoints."
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hexmask.long.byte 0x0 0.--3. 1. "InEndPoints,Provides the number of implemented IN Endpoints."
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group.long 0x80++0x7
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line.long 0x0 "TIMEOUT1,Holds the configurable chirp timeout value."
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hexmask.long.word 0x0 0.--15. 1. "CTUCH,Configurable Chirp Timeout timer; default value of 0x4074 corresponds to a delay of 1.1ms (60Mhz clock cycles * 4 * 0x4074)."
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line.long 0x4 "TIMEOUT2,Holds the configurable delay from the end of High Speed resume signal to enable UTM normal operating mode."
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hexmask.long.word 0x4 0.--15. 1. "CTHRSTN,Configurable delay from the end of High Speed resume signaling to enabling UTM normal operating mode. Default value of 0x32 corresponds to a delay of 3us. This programmed delay is equivalent to the number of 60MHz clock cycles * 4."
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group.long 0x2000++0x7
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line.long 0x0 "CLKCTRL,Provides optional control for turning off the interface clocks to USB Controller and PHY as well as the reference clock to the USB PHY."
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bitfld.long 0x0 24.--25. "PHYREFCLKSEL,USB PHY reference clock select.For Full_Speed Mode set the reference CLKSEL to use HFRC-based clock. For High-Speed Mode set the reference CLKSEL to use HFRC2-based clock. The HFRC2-based clock is higher power but meets the low-jitter.." "0: 48 MHz HFRC-based reference clock for Full-Speed..,1: 48 MHz HFRC2-based reference clock for..,2: based clock is higher power,?"
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bitfld.long 0x0 16. "PHYAPBLCLKDIS,Setting this bit turns off PHY control logic clock." "0,1"
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bitfld.long 0x0 8. "CTRLAPBCLKDIS,Setting this bit turns off the Controller logic clock." "0,1"
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bitfld.long 0x0 0. "PHYREFCLKDIS,Setting this bit turns off the PHY reference clock." "0,1"
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line.long 0x4 "SRAMCTRL,Provides optional SRAM tuning control."
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bitfld.long 0x4 14. "STOV,SRAM self-timed override" "0,1"
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bitfld.long 0x4 13. "WABL,SRAM write assist enable" "0,1"
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bitfld.long 0x4 10.--12. "WABLM,SRAM No margin adjustment" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 9. "RAWL,SRAM Read assist enable" "0,1"
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bitfld.long 0x4 7.--8. "RAWLM,SRAM Adjustment for margin for this read assist scheme" "0: Minimum margin adjustment with lowest negative..,1: Increased margin adjustment with more negative..,2: Minimum boost level with increased delay for..,3: Increased margin adjustment increased delay for.."
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bitfld.long 0x4 5.--6. "EMAW,Extra margin adjustment for write operations" "0,1,2,3"
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bitfld.long 0x4 4. "EMAS,Extra margin adjustment sense amplifier pulse" "0,1"
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bitfld.long 0x4 1.--3. "EMA,Extra margin adjustment" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 0. "RET1N,Retention mode 1 enable active-LOW" "0,1"
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group.long 0x2014++0x17
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line.long 0x0 "UTMISTICKYSTATUS,This read only register provides the results from the PHY OBS port controlled by reg 0x20[5:4]. IF any bits are set. the bits are sticky. Clear this register using the OBSCLRSTAT register."
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bitfld.long 0x0 0.--1. "obsportstciky,These bits are read only status bits from the PHY OBS port" "0: bit 1: PLL lock signal bit 0: Host Disconnect,1: bit 1: Rx squelch signal bit 0: Rx datap,2: bit 1: ODT calibration state bit 0: Current..,3: bit 1:HS BIST results bit 0:FS BIST results"
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line.long 0x4 "OBSCLRSTAT,Clears all bits in the sticky obs status register."
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bitfld.long 0x4 0. "CLRSTAT,Writing a 1 to this bit clears all bits in the UTMISTICKYSTATUS register." "0,1"
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line.long 0x8 "DPDMPULLDOWN,Enables a pulldown resistor(15K) on D+ or D-"
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bitfld.long 0x8 1. "DPPULLDOWN,Enables a pulldown resistor(15K) on D+" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "DMPULLDOWN,Enables a pulldown resistor(15K) on D-" "0,1"
|
|
line.long 0xC "BCDETSTATUS,USB Battery Charge Detenction Registers"
|
|
bitfld.long 0xC 5. "DMCOMPOUT,DM comparator output" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "DPCOMPOUT,DP comparator output" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "DCPDETECTED,Dedicated charging port detected" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "CPDETECTED,Charging port detected" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "DPATTACHED,Data pin attachment detected" "0,1"
|
|
line.long 0x10 "BCDETCRTL1,Battery Charging detection main control register"
|
|
bitfld.long 0x10 31. "USBSWRESET,Holds a USB controller and PHY in the reset for BC detection" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "USBDCOMPEN,Enables DP/DM vendor-specific detection comparator" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8.--9. "USBDCOMPREF,Sets DP/DM vendor-specific comparator ref voltage" "0: 1.65V (VCCIO/2),1: 3.10V,2: 2.35V,3: 1.25V"
|
|
newline
|
|
bitfld.long 0x10 7. "IDPSINKEN,Enables DP current sink" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. "VDMSRCEN,Enables DM voltage source" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "RDMPDWNEN,Enables DM BC 1.2 pull-down resistor" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "VDPSRCEN,Enables DP voltage source" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "IDPSRCEN,Enables DP current source" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "IDMSINKEN,Enables DM current sink" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "BCWEAKPULLDOWNEN,Enables weak sink current on DP and DM" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "BCWEAKPULLUPEN,Enables weak source current to DP and DM" "0,1"
|
|
line.long 0x14 "BCDETCRTL2,Battery Charging auxillary detection control register"
|
|
bitfld.long 0x14 10.--11. "BCWEAKPULLDOWNTUNE,Weak sink resistor to both DP and DM tuning. Trimmable." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 8.--9. "BCWEAKPULLUPTUNE,Weak source resistor to both DP and DM tuning. Trimmable." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 3. "FORCEDCPDET,Force output dedicated charging port detected" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "FORCECPDET,Force output charging port detected" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "FORCEDPATTACHED,Force output dp_attached" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "CHARGEDETBYP,BC detection bypass" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMA4B2KP")||cpuis("AMAP42KK")||cpuis("AMAP42KP"))
|
|
tree "USBPHY (Universal Serial Bus PHY)"
|
|
base ad:0x400B4000
|
|
group.long 0x0++0x87
|
|
line.long 0x0 "REG00,Register description here"
|
|
bitfld.long 0x0 5.--7. "BF75,Manually set the Rx Clock phase select. These bits will tune the HS RX path sample timing between digital and analog inside PHY: 3'b000 represents the earliest phase 3'b111 represents the latest phase The delay associated with each step is 256ps" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3.--4. "BF43,BG observation enable signal. Active low. When enabled vref 400mV can be observed through USB0PP/USB0PN" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "BF20,This bitfield is reserved." "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "REG04,Register description here"
|
|
bitfld.long 0x4 6.--7. "BF76,disconnect detector bias current tuning" "0,1,2,3"
|
|
bitfld.long 0x4 5. "BF55,This bitfield is reserved." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3.--4. "BF43,Squelch detector bias current tuning 2'b00 represents the minimum bias current 2'b11 represents the maximum bias current" "0,1,2,3"
|
|
bitfld.long 0x4 0.--2. "BF20,Manually set the Tx Clock phase select. These bits will tune the HS TX path sample timing between digital and analog inside PHY 3'b000 represents the earliest phase 3'b111 represents the latest phase The delay associated with each step is 256ps" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "REG08,Register description here"
|
|
bitfld.long 0x8 7. "BF77,digital squelch filter select this bit is used to filter the glitch on the HS RX squelch signal. 1: 1 clock cycle filter 0: 2 clock cycle fitter" "0,1"
|
|
bitfld.long 0x8 4.--6. "BF64,HS eye height tuning 3'b000:400mV(default) 3'b001:475mV 3'b010:350mV 3'b011:500mV 3'b100:412.5mV 3'b101:425mV 3'b110:437.5mV 3'b111:450mV" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "BF30,2'b00 represents the minimum bias current 2'b11 represents the maximum bias current Rx squelch trigger point configures. Allows tuning of the squelch trigger point in order to compensate for package and board level parasitic. 4'b0000:112.5mV.."
|
|
line.long 0xC "REG0C,Register description here"
|
|
bitfld.long 0xC 7. "BF77,This bitfield is reserved." "0,1"
|
|
hexmask.long.byte 0xC 2.--6. 1. "BF62,45ohm HS ODT value tuning and FS/LS driver strength tuning 5'b11111: smallest HS ODT value and largest FS/LS driver strength and fastest FS/LS slew rate 5'b10000: biggest HS ODT value and smallest FS/LS driver strength and slowest FS/LS slew rate"
|
|
newline
|
|
bitfld.long 0xC 0.--1. "BF10,BG output voltage reference adjust normally these bits are recommended to be kept as the default values. 00: standard center level around 1.25v output recommended 01: relative higher output 1x: relative higher output" "0: standard center level around 1,1: relative higher output 1x: relative higher output,?,?"
|
|
line.long 0x10 "REG10,Register description here"
|
|
hexmask.long.byte 0x10 4.--7. 1. "BF74,HOST disconnect detection trigger point. Only valid in host mode. Allows compensation for package and board level parasitics which tend to drop in the input voltage. 4'b0000:625mV 4'b0001:675mV 4'b0010:612.5mV 4'b0011:575mV 4'b0100:550mV.."
|
|
bitfld.long 0x10 3. "BF33,Single ended disconnect detection enable active high. 1: enable Single ended disconnect detection 0: disenable Single ended disconnect detection" "0: disenable Single ended disconnect detection,1: enable Single ended disconnect detection"
|
|
newline
|
|
bitfld.long 0x10 2. "BF22,Half bit pre-emphasis enable. Active high 1: half bit pre-emphasize mode recommended 0: full bit pre-emphasize mode" "0: full bit pre-emphasize mode,1: half bit pre-emphasize mode"
|
|
bitfld.long 0x10 1. "BF11,Turn off LS/FS differential receiver in suspend mode active low 1: keep the LS/FS differential receiver pin fss_rxrcv will toggling according to the DP/DM state 0: turn off the LS/FS differential receiver pin fss_rxrcv will not toggling.." "0: turn off the LS/FS differential receiver,1: keep the LS/FS differential receiver"
|
|
newline
|
|
bitfld.long 0x10 0. "BF00,Bypass squelch trigger point configure in chirp modes active high keep the default value is strongly recommended . 1: Bypass squelch trigger point configure in chirp modes 0: squelch trigger point set to 250mV in chirp modes." "0: squelch trigger point set to 250mV in chirp modes,1: Bypass squelch trigger point configure in chirp.."
|
|
line.long 0x14 "REG14,Register description here"
|
|
bitfld.long 0x14 7. "BF77,This bitfield is reserved." "0,1"
|
|
bitfld.long 0x14 6. "BF66,BF66 field description needed." "0,1"
|
|
newline
|
|
bitfld.long 0x14 5. "BF55,PLL feedback divider ratio option." "0,1"
|
|
bitfld.long 0x14 2.--4. "BF42,Tx HS pre-emphasis strength 3'b111 represents the strongest 3'b000 the weakest" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x14 1. "BF11,PLL bandwidth option 1'b0 default 1'b1 increases the PLL bandwidth" "0,1"
|
|
bitfld.long 0x14 0. "BF00,Dflop output select signal delay compared with digital clock enable signal 1'b0:3 clocks 1'b1:2 clocks" "0,1"
|
|
line.long 0x18 "REG18,Register description here"
|
|
hexmask.long.byte 0x18 3.--7. 1. "BF73,This bitfield is reserved."
|
|
bitfld.long 0x18 2. "BF22,Clk60m clk12m and clk48m enable. 1'b0:disables the clocks 1'b1:enables the clocks" "0: disables the clocks 1'b1:enables the clocks,?"
|
|
newline
|
|
bitfld.long 0x18 0.--1. "BF10,HS receiver bias current tuning. 2'b00 represents the minimum bias current 2'b11 represents the maximum bias current" "0,1,2,3"
|
|
line.long 0x1C "REG1C,Register description here"
|
|
bitfld.long 0x1C 7. "BF77,This bitfield is reserved." "0,1"
|
|
bitfld.long 0x1C 6. "BF66,This bitfield is reserved." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 5. "BF55,BG power down control bit active high 1: power down band-gap 0: normal operation mode" "0: normal operation mode,1: power down band-gap"
|
|
bitfld.long 0x1C 4. "BF44,480M clock out enable. 1'b0:pll disable 1'b1: 480M clock out enable 1'b0: 480M clock out disable" "0: pll disable 1'b1: 480M clock out enable 1'b0:..,?"
|
|
newline
|
|
bitfld.long 0x1C 3. "BF33,PLL enable value from suspend module. 1'b1:pll enable" "?,1: pll enable"
|
|
bitfld.long 0x1C 2. "BF22,PLL enable bypass from suspend module. 1'b1: bypass enable 1'b0:bypass disable" "?,1: bypass enable 1'b0:bypass disable"
|
|
newline
|
|
bitfld.long 0x1C 1. "BF11,Tx power down in suspend state. Active low." "0,1"
|
|
bitfld.long 0x1C 0. "BF00,Set IO high-Z state. Active high" "0,1"
|
|
line.long 0x20 "REG20,Register description here"
|
|
bitfld.long 0x20 6.--7. "BF76,This bitfield is reserved." "0,1,2,3"
|
|
bitfld.long 0x20 4.--5. "BF54,Analog observation port select. for detailed information please refer to section 10.3 Table 30 : Debug and OBS port" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x20 3. "BF33,This bitfield is reserved." "0,1"
|
|
bitfld.long 0x20 0.--2. "BF20,Rx enable delay select. 3'b000: 4 clocks (480Mhz clock) 3'b001: 5 clocks 3'b010: 6 clocks 3'b011: 7 clocks 3'b100: 8 clocks 3'b101: 9 clocks 3'b110: 10 clocks 3'b111: 12 clocks" "0,1,2,3,4,5,6,7"
|
|
line.long 0x24 "REG24,Register description here"
|
|
hexmask.long.byte 0x24 1.--7. 1. "BF71,This bitfield is reserved."
|
|
bitfld.long 0x24 0. "BF00,it0" "0,1"
|
|
line.long 0x28 "REG28,Register description here"
|
|
hexmask.long.byte 0x28 0.--7. 1. "BF70,This bitfield is reserved."
|
|
line.long 0x2C "REG2C,Register description here"
|
|
bitfld.long 0x2C 5.--7. "BF75,This bitfield is reserved." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x2C 4. "BF44,This bitfield is reserved." "0,1"
|
|
newline
|
|
bitfld.long 0x2C 3. "BF33,This bitfield is reserved." "0,1"
|
|
bitfld.long 0x2C 2. "BF22,HS keep alive enable. 1'b1: HS keep alive enable 1'b0: HS keep alive disable" "?,1: HS keep alive enable 1'b0: HS keep alive disable"
|
|
newline
|
|
bitfld.long 0x2C 1. "BF11,This bitfield is reserved." "0,1"
|
|
bitfld.long 0x2C 0. "BF00,All port z bypass value. 1'b1: bypass enable 1'b0:bypass disable" "?,1: bypass enable 1'b0:bypass disable"
|
|
line.long 0x30 "REG30,Register description here"
|
|
hexmask.long.byte 0x30 0.--7. 1. "BF70,This bitfield is reserved."
|
|
line.long 0x34 "REG34,Register description here"
|
|
hexmask.long.byte 0x34 0.--7. 1. "BF70,BF70 field description needed."
|
|
line.long 0x38 "REG38,Register description here"
|
|
hexmask.long.byte 0x38 0.--7. 1. "BF70,This bitfield is reserved."
|
|
line.long 0x3C "REG3C,Register description here"
|
|
bitfld.long 0x3C 5.--7. "BF75,Host disconnect filter select. 3'b100:6 clocks(480M clock) 3'b101:8 clocks 3'b111:disconnect disable Other: invalid" "?,?,?,?,?,?,?,7: disconnect disable Other: invalid"
|
|
bitfld.long 0x3C 2.--4. "BF42,This bitfield is reserved." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x3C 0.--1. "BF10,BF10 field description needed." "0,1,2,3"
|
|
line.long 0x40 "REG40,Register description here"
|
|
bitfld.long 0x40 7. "BF77,This bitfield is reserved." "0,1"
|
|
hexmask.long.byte 0x40 0.--6. 1. "BF60,This bitfield is reserved."
|
|
line.long 0x44 "REG44,Register description here"
|
|
bitfld.long 0x44 7. "BF77,This bitfield is reserved." "0,1"
|
|
bitfld.long 0x44 5.--6. "BF65,This bitfield is reserved." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x44 2.--4. "BF42,This bitfield is reserved." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x44 1. "BF11,Disconnect squelch and comparator calibration bypass active high" "0,1"
|
|
newline
|
|
bitfld.long 0x44 0. "BF00,1: DP/DM will be sampled in HS Tx or Rx state 0: DP/DM will be sampled only in Hs Rx state" "0: DP/DM will be sampled only in Hs Rx state,1: DP/DM will be sampled in HS Tx or Rx state"
|
|
line.long 0x48 "REG48,Register description here"
|
|
hexmask.long.byte 0x48 1.--7. 1. "BF71,This bitfield is reserved."
|
|
bitfld.long 0x48 0. "BF00,Enable TX shutdown active LOW. This bit is only used for debug purpose nothing to do with the normal operation and signal quality keeping the default value is strongly recommended." "0,1"
|
|
line.long 0x4C "REG4C,Register description here"
|
|
hexmask.long.byte 0x4C 0.--7. 1. "BF70,This bitfield is reserved."
|
|
line.long 0x50 "REG50,Register description here"
|
|
hexmask.long.byte 0x50 0.--7. 1. "BF70,This bitfield is reserved."
|
|
line.long 0x54 "REG54,Register description here"
|
|
hexmask.long.byte 0x54 0.--7. 1. "BF70,This bitfield is reserved."
|
|
line.long 0x58 "REG58,Register description here"
|
|
hexmask.long.byte 0x58 0.--7. 1. "BF70,This bitfield is reserved."
|
|
line.long 0x5C "REG5C,Register description here"
|
|
hexmask.long.byte 0x5C 0.--7. 1. "BF70,This bitfield is reserved."
|
|
line.long 0x60 "REG60,Register description here"
|
|
hexmask.long.byte 0x60 0.--7. 1. "BF70,This bitfield is reserved."
|
|
line.long 0x64 "REG64,Register description here"
|
|
bitfld.long 0x64 0. "BF00,This bitfield is reserved." "0,1"
|
|
line.long 0x68 "REG68,Register description here"
|
|
hexmask.long.byte 0x68 0.--7. 1. "BF70,This bitfield is reserved."
|
|
line.long 0x6C "REG6C,Register description here"
|
|
hexmask.long.byte 0x6C 0.--7. 1. "BF70,This bitfield is reserved."
|
|
line.long 0x70 "REG70,Register description here"
|
|
hexmask.long.byte 0x70 0.--7. 1. "BF70,BF70 field description needed."
|
|
line.long 0x74 "REG74,Register description here"
|
|
hexmask.long.byte 0x74 4.--7. 1. "BF74,This bitfield is reserved."
|
|
bitfld.long 0x74 1.--3. "BF31,HS driver slew rate tuning 001:SR is weakest 111:SR is strongest.000 is forbidden." "?,1: SR is weakest 111:SR is strongest,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x74 0. "BF00,Disconnect detection block input res load sel. 1'b0: disconnect detection block input res load bypass 1'b1: disconnect detection block input res load enable" "0: disconnect detection block input res load bypass..,?"
|
|
line.long 0x78 "REG78,Register description here"
|
|
hexmask.long.byte 0x78 0.--7. 1. "BF70,This bitfield is reserved."
|
|
line.long 0x7C "REG7C,Register description here"
|
|
bitfld.long 0x7C 7. "BF77,Clk60m source clock select. 1'b1: free clock 60M 1'b0: utmi_clk" "?,1: free clock 60M 1'b0: utmi_clk"
|
|
bitfld.long 0x7C 6. "BF66,Hs chirp mode amplitude increasing register active high." "0,1"
|
|
newline
|
|
bitfld.long 0x7C 5. "BF55,No leakage current on DP/DM pin when VCCA3P3 power down active low. Keeping the default value was greatly appreciated" "0,1"
|
|
hexmask.long.byte 0x7C 0.--4. 1. "BF40,This bitfield is reserved."
|
|
line.long 0x80 "REG80,Register description here"
|
|
hexmask.long.byte 0x80 3.--7. 1. "BF73,This bitfield is reserved."
|
|
bitfld.long 0x80 2. "BF22,utmi clock always on 1'b1: utmi clock always on 1'b0: utmi clock relative to suspendm" "?,1: utmi clock always on 1'b0: utmi clock relative.."
|
|
newline
|
|
bitfld.long 0x80 1. "BF11,Digital clock enable bypass value 1'b1: digital clock enable 1'b0: digital clock disable" "?,1: digital clock enable 1'b0: digital clock disable"
|
|
bitfld.long 0x80 0. "BF00,Digital clock enable bypass 1'b1: digital clock bypass enable 1'b0: digital clock bypass disable" "?,1: digital clock bypass enable 1'b0: digital clock.."
|
|
line.long 0x84 "REG84,Register description here"
|
|
hexmask.long.byte 0x84 0.--7. 1. "BF70,This bitfield is reserved."
|
|
tree.end
|
|
endif
|
|
tree "VCOMP (Voltage Comparator)"
|
|
base ad:0x4000C000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CFG,The Voltage Comparator Configuration Register contains the software control for selecting beween the 4 options for the positive input as well as the multiple options for the reference input."
|
|
hexmask.long.byte 0x0 16.--19. 1. "LVLSEL,When the reference input NSEL is set to NSEL_DAC this bitfield selects the voltage level for the negative input to the comparator."
|
|
bitfld.long 0x0 8.--9. "NSEL,This bitfield selects the negative input to the comparator." "0: Use external reference 1 for reference input.,1: Use external reference 2 for reference input.,2: Use external reference 3 for reference input.,3: Use DAC output selected by LVLSEL for reference.."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "PSEL,This bitfield selects the positive input to the comparator." "0: Use VDDADJ for the positive input.,1: Use the temperature sensor output for the..,2: Use external voltage 0 for positive input.,3: Use external voltage 1 for positive input."
|
|
line.long 0x4 "STAT,Status"
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
|
|
bitfld.long 0x4 1. "PWDSTAT,This bit indicates the power down state of the voltage comparator." "?,1: The voltage comparator is powered down."
|
|
endif
|
|
sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
|
|
bitfld.long 0x4 1. "PWDSTAT,This bit indicates the power down state of the voltage comparator." "0: The voltage comparator is powered up.,1: The voltage comparator is powered down."
|
|
newline
|
|
endif
|
|
bitfld.long 0x4 0. "CMPOUT,This bit is 1 if the positive input of the comparator is greater than the negative input." "0: The negative input of the comparator is greater..,1: The positive input of the comparator is greater.."
|
|
line.long 0x8 "PWDKEY,Write a value of 0x37 to unlock. write any other value to lock. This register also indicates lock status when read. When in the unlccked state (i.e. 0x37 has been written). it reads as 1. When in the locked state. it reads as 0."
|
|
hexmask.long 0x8 0.--31. 1. "PWDKEY,Key register value."
|
|
group.long 0x200++0xF
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 1. "OUTHI,This bit is the vcompout high interrupt." "0,1"
|
|
bitfld.long 0x0 0. "OUTLOW,This bit is the vcompout low interrupt." "0,1"
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 1. "OUTHI,This bit is the vcompout high interrupt." "0,1"
|
|
bitfld.long 0x4 0. "OUTLOW,This bit is the vcompout low interrupt." "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 1. "OUTHI,This bit is the vcompout high interrupt." "0,1"
|
|
bitfld.long 0x8 0. "OUTLOW,This bit is the vcompout low interrupt." "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 1. "OUTHI,This bit is the vcompout high interrupt." "0,1"
|
|
bitfld.long 0xC 0. "OUTLOW,This bit is the vcompout low interrupt." "0,1"
|
|
tree.end
|
|
tree "WDT (Watchdog Timer)"
|
|
base ad:0x40024000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CFG,This is the configuration register for the watch dog timer. It controls the enable. interrupt set. clocks for the timer. the compare values for the counters to trigger a reset or interrupt. This register can only be written to if the watch dog timer.."
|
|
bitfld.long 0x0 24.--26. "CLKSEL,Select the frequency for the WDT. All values not enumerated below are undefined." "0: Low Power Mode. This setting disables the watch..,1: 128 Hz LFRC clock.,2: 16 Hz LFRC clock.,3: 1 Hz LFRC clock.,4: 1/16th Hz LFRC clock.,?,?,?"
|
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hexmask.long.byte 0x0 16.--23. 1. "INTVAL,This bitfield is the compare value for counter bits 7:0 to generate a watchdog interrupt."
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hexmask.long.byte 0x0 8.--15. 1. "RESVAL,This bitfield is the compare value for counter bits 7:0 to generate a watchdog reset. This will cause a software reset."
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sif (cpuis("AMA4B2KK")||cpuis("AMA4B2KP")||cpuis("AMAP42KK")||cpuis("AMAP42KP"))
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bitfld.long 0x0 3. "DSPRESETINTEN,This bitfield enables the DSP Reset Interrupt. This interrupt is provided to the ARM CPU to notify it that a DSP's WDT has expired and a reset has been issued to one of the DSP cores." "0,1"
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endif
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bitfld.long 0x0 2. "RESEN,This bitfield enables the WDT reset. This needs to be set together with the WDREN bit in REG_RSTGEN_CFG register (in reset gen) to trigger the reset." "0,1"
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newline
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bitfld.long 0x0 1. "INTEN,This bitfield enables the WDT interrupt. Note : This bit must be set before the interrupt status bit will reflect a watchdog timer expiration. The IER interrupt register must also be enabled for a WDT interrupt to be sent to the NVIC." "0,1"
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bitfld.long 0x0 0. "WDTEN,This bitfield enables the WDT." "0,1"
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line.long 0x4 "RSTRT,This register will Restart the watchdog timer. Writing a special key value into this register will result in the watch dog timer being reset. so that the count will start again. It is expected that the software will periodically write to this.."
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sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
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hexmask.long.byte 0x4 0.--7. 1. "RSTRT,Writing 0xB2 to WDTRSTRT restarts the watchdog timer. This is a write only register. Reading this register will only provide all 0."
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endif
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sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
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hexmask.long.byte 0x4 0.--7. 1. "RSTRT,Writing 0xB2 to WDTRSTRT restarts the watchdog timer. This is a write only register. Reading this register will only provide all 0."
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endif
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line.long 0x8 "LOCK,This register locks the watch dog timer. Once it is locked. the configuration register (WDTCFG) for watch dog timer cannot be written to."
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sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
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hexmask.long.byte 0x8 0.--7. 1. "LOCK,Writing 0x3A locks the watchdog timer. Once locked the WDTCFG reg cannot be written and WDTEN is set."
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endif
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sif (cpuis("AMA4B2KL")||cpuis("AMAP42KL"))
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hexmask.long.byte 0x8 0.--7. 1. "LOCK,Writing 0x3A locks the watchdog timer. Once locked the WDTCFG reg cannot be written and WDTEN is set."
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endif
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line.long 0xC "COUNT,This register holds the current count for the watch dog timer. This is a read only register. SW cannot set the value in the counter. but can reset it."
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hexmask.long.byte 0xC 0.--7. 1. "COUNT,Read-Only current value of the WDT counter"
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sif (cpuis("AMA4B2KK")||cpuis("AMA4B2KP")||cpuis("AMAP42KK")||cpuis("AMAP42KP"))
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group.long 0x10++0x1F
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line.long 0x0 "DSP0CFG,This is the configuration register for the DSP0 watch dog timer. It controls the enable. interrupt set. clocks for the timer. the compare values for the counters to trigger a reset or interrupt. This register can only be written to if the.."
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hexmask.long.byte 0x0 24.--31. 1. "DSP0PMRESVAL,This bitfield is the compare value for counter bits 7:0 to generate a watchdog reset. This will cause a software reset to the DSP Power Management logic if the PMRESEN bit is set and optionally interrupt the CPU."
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hexmask.long.byte 0x0 16.--23. 1. "DSP0INTVAL,This bitfield is the compare value for counter bits 7:0 to generate a watchdog interrupt."
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newline
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hexmask.long.byte 0x0 8.--15. 1. "DSP0RESVAL,This bitfield is the compare value for counter bits 7:0 to generate a watchdog reset for the DSP logic. This will cause a software reset to the DSP core if the RESEN bit is set and optionally interrupt the CPU."
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bitfld.long 0x0 3. "DSP0PMRESEN,This bitfield enables the DSP0 Power Controller (PM) reset. This needs to be set together with the DSP0WDTEN bit to allow the reset to trigger." "0,1"
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newline
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bitfld.long 0x0 2. "DSP0RESEN,This bitfield enables the DSP0 reset." "0,1"
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bitfld.long 0x0 1. "DSP0INTEN,This bitfield enables the DSP0 WDT interrupt. Note : This bit must be set before the interrupt status bit will reflect a watchdog timer expiration. The IER interrupt register must also be enabled for a WDT interrupt to be sent to the NVIC." "0,1"
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newline
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bitfld.long 0x0 0. "DSP0WDTEN,This bitfield enables the WDT. Setting the lock implicitly sets the WTDEN bit as well." "0,1"
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line.long 0x4 "DSP0RSTRT,This register will restart the watchdog timer. Writing a special key value into this register will result in the watch dog timer being reset. so that the count will start again. It is expected that the software will periodically write to this.."
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sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
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hexmask.long.byte 0x4 0.--7. 1. "DSP0RSTART,Writing 0x69 to DSP0RSTRT restarts the watchdog timer. This is a write only register. Reading this register will return 0."
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endif
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line.long 0x8 "DSP0TLOCK,This register locks the watch dog timer. Once it is locked. the configuration register (DSP0CFG) for watch dog timer cannot be written to and the timer is automatically enabled (WDTEN is set)."
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sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
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hexmask.long.byte 0x8 0.--7. 1. "DSP0LOCK,Writing 0xa7 locks the watchdog timer. Once locked the WDTCFG reg cannot be written and WDTEN is set."
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endif
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line.long 0xC "DSP0COUNT,This register holds the current count for the watch dog timer. This is a read only register. SW cannot set the value in the counter. but can reset it."
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hexmask.long.byte 0xC 0.--7. 1. "DSP0COUNT,Read-Only current value of the WDT counter"
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line.long 0x10 "DSP1CFG,This is the configuration register for the DSP1 watch dog timer. It controls the enable. interrupt set. clocks for the timer. the compare values for the counters to trigger a reset or interrupt. This register can only be written to if the.."
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hexmask.long.byte 0x10 24.--31. 1. "DSP1PMRESVAL,This bitfield is the compare value for counter bits 7:0 to generate a watchdog reset. This will cause a software reset to the DSP Power Management logic if the PMRESEN bit is set and optionally interrupt the CPU."
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hexmask.long.byte 0x10 16.--23. 1. "DSP1INTVAL,This bitfield is the compare value for counter bits 7:0 to generate a watchdog interrupt."
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|
newline
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hexmask.long.byte 0x10 8.--15. 1. "DSP1RESVAL,This bitfield is the compare value for counter bits 7:0 to generate a watchdog reset for the DSP logic. This will cause a software reset to the DSP core if the RESEN bit is set and optionally interrupt the CPU."
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bitfld.long 0x10 3. "DSP1PMRESEN,This bitfield enables the DSP1 Power Controller (PM) reset. This needs to be set together with the DSP1WDTEN bit to allow the reset to trigger." "0,1"
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newline
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bitfld.long 0x10 2. "DSP1RESEN,This bitfield enables the DSP1 reset." "0,1"
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bitfld.long 0x10 1. "DSP1INTEN,This bitfield enables the DSP1 WDT interrupt. Note : This bit must be set before the interrupt status bit will reflect a watchdog timer expiration. The IER interrupt register must also be enabled for a WDT interrupt to be sent to the NVIC." "0,1"
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newline
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bitfld.long 0x10 0. "DSP1WDTEN,This bitfield enables the WDT. Setting the lock implicitly sets the WTDEN bit as well." "0,1"
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line.long 0x14 "DSP1RSTRT,This register will restart the watchdog timer. Writing a special key value into this register will result in the watch dog timer being reset. so that the count will start again. It is expected that the software will periodically write to this.."
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|
sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
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hexmask.long.byte 0x14 0.--7. 1. "DSP1RSTART,Writing 0xd2 to DSP1RSTRT restarts the watchdog timer. This is a write only register. Reading this register will return 0."
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|
endif
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line.long 0x18 "DSP1TLOCK,This register locks the watch dog timer. Once it is locked. the configuration register (DSP1CFG) for watch dog timer cannot be written to and the timer is automatically enabled (WDTEN is set)."
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sif (cpuis("AMA4B2KK")||cpuis("AMAP42KK"))
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hexmask.long.byte 0x18 0.--7. 1. "DSP1LOCK,Writing 0x4e locks the watchdog timer. Once locked the WDTCFG reg cannot be written and WDTEN is set."
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|
endif
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line.long 0x1C "DSP1COUNT,This register holds the current count for the watch dog timer. This is a read only register. SW cannot set the value in the counter. but can reset it."
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hexmask.long.byte 0x1C 0.--7. 1. "DSP1COUNT,Read-Only current value of the WDT counter"
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group.long 0x210++0x1F
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line.long 0x0 "DSP0IEREN,Set bits in this register to allow this module to generate the corresponding interrupt."
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bitfld.long 0x0 0. "DSP0INT,DSP0 Watchdog Timer Interrupt." "0,1"
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line.long 0x4 "DSP0IERSTAT,Read bits from this register to discover the cause of a recent interrupt."
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bitfld.long 0x4 0. "DSP0INT,DSP0 Watchdog Timer Interrupt." "0,1"
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line.long 0x8 "DSP0IERCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
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bitfld.long 0x8 0. "DSP0INT,DSP0 Watchdog Timer Interrupt." "0,1"
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line.long 0xC "DSP0IERSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
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bitfld.long 0xC 0. "DSP0INT,DSP0 Watchdog Timer Interrupt." "0,1"
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line.long 0x10 "DSP1IEREN,Set bits in this register to allow this module to generate the corresponding interrupt."
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bitfld.long 0x10 0. "DSP1INT,DSP0 Watchdog Timer Interrupt." "0,1"
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line.long 0x14 "DSP1IERSTAT,Read bits from this register to discover the cause of a recent interrupt."
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|
bitfld.long 0x14 0. "DSP1INT,DSP0 Watchdog Timer Interrupt." "0,1"
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|
line.long 0x18 "DSP1IERCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x18 0. "DSP1INT,DSP0 Watchdog Timer Interrupt." "0,1"
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|
line.long 0x1C "DSP1IERSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
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|
bitfld.long 0x1C 0. "DSP1INT,DSP0 Watchdog Timer Interrupt." "0,1"
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|
endif
|
|
group.long 0x200++0xF
|
|
line.long 0x0 "WDTIEREN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMA4B2KP")||cpuis("AMAP42KK")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x0 1. "DSPRESETINT,Indicates that one of the DSP timers has issued a reset or pmreset to the DSP core. This is used to interrupt the main CPU." "0,1"
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|
endif
|
|
bitfld.long 0x0 0. "WDTINT,Watchdog Timer Interrupt." "0,1"
|
|
line.long 0x4 "WDTIERSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMA4B2KP")||cpuis("AMAP42KK")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x4 1. "DSPRESETINT,Indicates that one of the DSP timers has issued a reset or pmreset to the DSP core. This is used to interrupt the main CPU." "0,1"
|
|
endif
|
|
bitfld.long 0x4 0. "WDTINT,Watchdog Timer Interrupt." "0,1"
|
|
line.long 0x8 "WDTIERCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMA4B2KP")||cpuis("AMAP42KK")||cpuis("AMAP42KP"))
|
|
bitfld.long 0x8 1. "DSPRESETINT,Indicates that one of the DSP timers has issued a reset or pmreset to the DSP core. This is used to interrupt the main CPU." "0,1"
|
|
endif
|
|
bitfld.long 0x8 0. "WDTINT,Watchdog Timer Interrupt." "0,1"
|
|
line.long 0xC "WDTIERSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
sif (cpuis("AMA4B2KK")||cpuis("AMA4B2KP")||cpuis("AMAP42KK")||cpuis("AMAP42KP"))
|
|
bitfld.long 0xC 1. "DSPRESETINT,Indicates that one of the DSP timers has issued a reset or pmreset to the DSP core. This is used to interrupt the main CPU." "0,1"
|
|
endif
|
|
bitfld.long 0xC 0. "WDTINT,Watchdog Timer Interrupt." "0,1"
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|
tree.end
|
|
AUTOINDENT.OFF
|