16661 lines
1.5 MiB
16661 lines
1.5 MiB
; --------------------------------------------------------------------------------
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; @Title: Apollo3 On-Chip Peripherals
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; @Props: Released
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; @Author: KWI, KRZ, JDU, NEJ
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; @Changelog: 2020-07-28 KWI
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; 2022-02-16 KRZ
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; 2023-02-23 JDU
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; 2023-11-03 NEJ
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; @Manufacturer: AMBIQ - Ambiq Micro, Inc.
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; @Doc: Generated (TRACE32, build: 164232.), based on:
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; apollo3.svd (Ver. 1.0), apollo3p.svd (Ver. 1.0)
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; @Core: Cortex-M4F
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; @Chip: AMA3B1KK, AMAP31KK, AMA3B2KK
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; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perapollo3.per 16944 2023-11-08 10:24:44Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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tree.close "Core Registers (Cortex-M4F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes"
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bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes"
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bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes"
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group.long 0x10++0x0B
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending"
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bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x07
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line.long 0x00 "HFSR,Hard Fault Status Register"
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bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
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bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
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bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested"
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group.long 0xD34++0x0B
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line.long 0x00 "MMFAR,MemManage Fault Address Register"
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line.long 0x04 "BFAR,BusFault Address Register"
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line.long 0x08 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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width 10.
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tree "Feature Registers"
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
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bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
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bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
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textline " "
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bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
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line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
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bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
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bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
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bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
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textline " "
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bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
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|
bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM4F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x07
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline ""
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
|
|
hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "ADC (Analog-to-Digital Converter)"
|
|
base ad:0x50010000
|
|
group.long 0x0++0x3F
|
|
line.long 0x0 "CFG,The ADC Configuration Register contains the software control for selecting the clock frequency used for the SAR conversions. the trigger polarity. the trigger select. the reference voltage select. the low power mode. the operating mode (single scan.."
|
|
bitfld.long 0x0 24.--25. "CLKSEL,Select the source and frequency for the ADC clock. All values not enumerated below are undefined." "0: Off mode. The HFRC or HFRC_DIV2 clock must be..,1: HFRC Core Clock divided by (CORESEL+1),2: HFRC Core Clock / 2 further divided by (CORESEL+1),?"
|
|
bitfld.long 0x0 19. "TRIGPOL,This bit selects the ADC trigger polarity for external off chip triggers." "0: Trigger on rising edge.,1: Trigger on falling edge."
|
|
newline
|
|
bitfld.long 0x0 16.--18. "TRIGSEL,Select the ADC trigger source." "0: Off chip External Trigger0 (ADC_ET0),1: Off chip External Trigger1 (ADC_ET1),2: Off chip External Trigger2 (ADC_ET2),3: Off chip External Trigger3 (ADC_ET3),4: Voltage Comparator Output,?,?,7: Software Trigger"
|
|
bitfld.long 0x0 12. "DFIFORDEN,Destructive FIFO Read Enable. Setting this will enable FIFO pop upon reading the FIFOPR register." "0: Destructive Reads are prevented. Reads to the..,1: Reads to the FIFOPR register will automatically.."
|
|
newline
|
|
bitfld.long 0x0 8.--9. "REFSEL,Select the ADC reference voltage." "0: Internal 2.0V Bandgap Reference Voltage,1: Internal 1.5V Bandgap Reference Voltage,2: Off Chip 2.0V Reference,3: Off Chip 1.5V Reference"
|
|
bitfld.long 0x0 4. "CKMODE,Clock mode register" "0: Disable the clock between scans for LPMODE0. Set..,1: Low Latency Clock Mode. When set HFRC and the.."
|
|
newline
|
|
bitfld.long 0x0 3. "LPMODE,Select power mode to enter between active scans." "0: Low Power Mode 0. Leaves the ADC fully powered..,1: Low Power Mode 1. Powers down all circuity and.."
|
|
bitfld.long 0x0 2. "RPTEN,This bit enables Repeating Scan Mode." "0: In Single Scan Mode the ADC will complete a..,1: In Repeating Scan Mode the ADC will complete.."
|
|
newline
|
|
bitfld.long 0x0 0. "ADCEN,This bit enables the ADC module. While the ADC is enabled the ADCCFG and SLOT Configuration register settings must remain stable and unchanged. All configuration register settings slot configuration settings and window comparison settings should.." "0: Disable the ADC module.,1: Enable the ADC module."
|
|
line.long 0x4 "STAT,This register indicates the basic power status for the ADC. For detailed power status. see the power control power status register. ADC power mode 0 indicates the ADC is in it's full power state and is ready to process scans. ADC Power mode 1.."
|
|
bitfld.long 0x4 0. "PWDSTAT,Indicates the power-status of the ADC." "0: Powered on.,1: ADC Low Power Mode 1."
|
|
line.long 0x8 "SWT,This register enables initiating an ADC scan through software."
|
|
hexmask.long.byte 0x8 0.--7. 1. "SWT,Writing 0x37 to this register generates a software trigger."
|
|
line.long 0xC "SL0CFG,Slot 0 Configuration Register"
|
|
bitfld.long 0xC 24.--26. "ADSEL0,Select the number of measurements to average in the accumulate divide module for this slot." "0: Average in 1 measurement in the accumulate..,1: Average in 2 measurements in the accumulate..,2: Average in 4 measurements in the accumulate..,3: Average in 8 measurements in the accumulate..,4: Average in 16 measurements in the accumulate..,5: Average in 32 measurements in the accumulate..,6: Average in 64 measurements in the accumulate..,7: Average in 128 measurements in the accumulate.."
|
|
bitfld.long 0xC 16.--17. "PRMODE0,Set the Precision Mode For Slot." "0: 14-bit precision mode,1: 12-bit precision mode,2: 10-bit precision mode,3: 8-bit precision mode"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--11. 1. "CHSEL0,Select one of the 14 channel inputs for this slot."
|
|
bitfld.long 0xC 1. "WCEN0,This bit enables the window compare function for slot 0." "?,1: Enable the window compare for slot 0."
|
|
newline
|
|
bitfld.long 0xC 0. "SLEN0,This bit enables slot 0 for ADC conversions." "?,1: Enable slot 0 for ADC conversions."
|
|
line.long 0x10 "SL1CFG,Slot 1 Configuration Register"
|
|
bitfld.long 0x10 24.--26. "ADSEL1,Select the number of measurements to average in the accumulate divide module for this slot." "0: Average in 1 measurement in the accumulate..,1: Average in 2 measurements in the accumulate..,2: Average in 4 measurements in the accumulate..,3: Average in 8 measurements in the accumulate..,4: Average in 16 measurements in the accumulate..,5: Average in 32 measurements in the accumulate..,6: Average in 64 measurements in the accumulate..,7: Average in 128 measurements in the accumulate.."
|
|
bitfld.long 0x10 16.--17. "PRMODE1,Set the Precision Mode For Slot." "0: 14-bit precision mode,1: 12-bit precision mode,2: 10-bit precision mode,3: 8-bit precision mode"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--11. 1. "CHSEL1,Select one of the 14 channel inputs for this slot."
|
|
bitfld.long 0x10 1. "WCEN1,This bit enables the window compare function for slot 1." "?,1: Enable the window compare for slot 1."
|
|
newline
|
|
bitfld.long 0x10 0. "SLEN1,This bit enables slot 1 for ADC conversions." "?,1: Enable slot 1 for ADC conversions."
|
|
line.long 0x14 "SL2CFG,Slot 2 Configuration Register"
|
|
bitfld.long 0x14 24.--26. "ADSEL2,Select the number of measurements to average in the accumulate divide module for this slot." "0: Average in 1 measurement in the accumulate..,1: Average in 2 measurements in the accumulate..,2: Average in 4 measurements in the accumulate..,3: Average in 8 measurements in the accumulate..,4: Average in 16 measurements in the accumulate..,5: Average in 32 measurements in the accumulate..,6: Average in 64 measurements in the accumulate..,7: Average in 128 measurements in the accumulate.."
|
|
bitfld.long 0x14 16.--17. "PRMODE2,Set the Precision Mode For Slot." "0: 14-bit precision mode,1: 12-bit precision mode,2: 10-bit precision mode,3: 8-bit precision mode"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--11. 1. "CHSEL2,Select one of the 14 channel inputs for this slot."
|
|
bitfld.long 0x14 1. "WCEN2,This bit enables the window compare function for slot 2." "?,1: Enable the window compare for slot 2."
|
|
newline
|
|
bitfld.long 0x14 0. "SLEN2,This bit enables slot 2 for ADC conversions." "?,1: Enable slot 2 for ADC conversions."
|
|
line.long 0x18 "SL3CFG,Slot 3 Configuration Register"
|
|
bitfld.long 0x18 24.--26. "ADSEL3,Select the number of measurements to average in the accumulate divide module for this slot." "0: Average in 1 measurement in the accumulate..,1: Average in 2 measurements in the accumulate..,2: Average in 4 measurements in the accumulate..,3: Average in 8 measurements in the accumulate..,4: Average in 16 measurements in the accumulate..,5: Average in 32 measurements in the accumulate..,6: Average in 64 measurements in the accumulate..,7: Average in 128 measurements in the accumulate.."
|
|
bitfld.long 0x18 16.--17. "PRMODE3,Set the Precision Mode For Slot." "0: 14-bit precision mode,1: 12-bit precision mode,2: 10-bit precision mode,3: 8-bit precision mode"
|
|
newline
|
|
hexmask.long.byte 0x18 8.--11. 1. "CHSEL3,Select one of the 14 channel inputs for this slot."
|
|
bitfld.long 0x18 1. "WCEN3,This bit enables the window compare function for slot 3." "?,1: Enable the window compare for slot 3."
|
|
newline
|
|
bitfld.long 0x18 0. "SLEN3,This bit enables slot 3 for ADC conversions." "?,1: Enable slot 3 for ADC conversions."
|
|
line.long 0x1C "SL4CFG,Slot 4 Configuration Register"
|
|
bitfld.long 0x1C 24.--26. "ADSEL4,Select the number of measurements to average in the accumulate divide module for this slot." "0: Average in 1 measurement in the accumulate..,1: Average in 2 measurements in the accumulate..,2: Average in 4 measurements in the accumulate..,3: Average in 8 measurements in the accumulate..,4: Average in 16 measurements in the accumulate..,5: Average in 32 measurements in the accumulate..,6: Average in 64 measurements in the accumulate..,7: Average in 128 measurements in the accumulate.."
|
|
bitfld.long 0x1C 16.--17. "PRMODE4,Set the Precision Mode For Slot." "0: 14-bit precision mode,1: 12-bit precision mode,2: 10-bit precision mode,3: 8-bit precision mode"
|
|
newline
|
|
hexmask.long.byte 0x1C 8.--11. 1. "CHSEL4,Select one of the 14 channel inputs for this slot."
|
|
bitfld.long 0x1C 1. "WCEN4,This bit enables the window compare function for slot 4." "?,1: Enable the window compare for slot 4."
|
|
newline
|
|
bitfld.long 0x1C 0. "SLEN4,This bit enables slot 4 for ADC conversions." "?,1: Enable slot 4 for ADC conversions."
|
|
line.long 0x20 "SL5CFG,Slot 5 Configuration Register"
|
|
bitfld.long 0x20 24.--26. "ADSEL5,Select number of measurements to average in the accumulate divide module for this slot." "0: Average in 1 measurement in the accumulate..,1: Average in 2 measurements in the accumulate..,2: Average in 4 measurements in the accumulate..,3: Average in 8 measurements in the accumulate..,4: Average in 16 measurements in the accumulate..,5: Average in 32 measurements in the accumulate..,6: Average in 64 measurements in the accumulate..,7: Average in 128 measurements in the accumulate.."
|
|
bitfld.long 0x20 16.--17. "PRMODE5,Set the Precision Mode For Slot." "0: 14-bit precision mode,1: 12-bit precision mode,2: 10-bit precision mode,3: 8-bit precision mode"
|
|
newline
|
|
hexmask.long.byte 0x20 8.--11. 1. "CHSEL5,Select one of the 14 channel inputs for this slot."
|
|
bitfld.long 0x20 1. "WCEN5,This bit enables the window compare function for slot 5." "?,1: Enable the window compare for slot 5."
|
|
newline
|
|
bitfld.long 0x20 0. "SLEN5,This bit enables slot 5 for ADC conversions." "?,1: Enable slot 5 for ADC conversions."
|
|
line.long 0x24 "SL6CFG,Slot 6 Configuration Register"
|
|
bitfld.long 0x24 24.--26. "ADSEL6,Select the number of measurements to average in the accumulate divide module for this slot." "0: Average in 1 measurement in the accumulate..,1: Average in 2 measurements in the accumulate..,2: Average in 4 measurements in the accumulate..,3: Average in 8 measurements in the accumulate..,4: Average in 16 measurements in the accumulate..,5: Average in 32 measurements in the accumulate..,6: Average in 64 measurements in the accumulate..,7: Average in 128 measurements in the accumulate.."
|
|
bitfld.long 0x24 16.--17. "PRMODE6,Set the Precision Mode For Slot." "0: 14-bit precision mode,1: 12-bit precision mode,2: 10-bit precision mode,3: 8-bit precision mode"
|
|
newline
|
|
hexmask.long.byte 0x24 8.--11. 1. "CHSEL6,Select one of the 14 channel inputs for this slot."
|
|
bitfld.long 0x24 1. "WCEN6,This bit enables the window compare function for slot 6." "?,1: Enable the window compare for slot 6."
|
|
newline
|
|
bitfld.long 0x24 0. "SLEN6,This bit enables slot 6 for ADC conversions." "?,1: Enable slot 6 for ADC conversions."
|
|
line.long 0x28 "SL7CFG,Slot 7 Configuration Register"
|
|
bitfld.long 0x28 24.--26. "ADSEL7,Select the number of measurements to average in the accumulate divide module for this slot." "0: Average in 1 measurement in the accumulate..,1: Average in 2 measurements in the accumulate..,2: Average in 4 measurements in the accumulate..,3: Average in 8 measurements in the accumulate..,4: Average in 16 measurements in the accumulate..,5: Average in 32 measurements in the accumulate..,6: Average in 64 measurements in the accumulate..,7: Average in 128 measurements in the accumulate.."
|
|
bitfld.long 0x28 16.--17. "PRMODE7,Set the Precision Mode For Slot." "0: 14-bit precision mode,1: 12-bit precision mode,2: 10-bit precision mode,3: 8-bit precision mode"
|
|
newline
|
|
hexmask.long.byte 0x28 8.--11. 1. "CHSEL7,Select one of the 14 channel inputs for this slot."
|
|
bitfld.long 0x28 1. "WCEN7,This bit enables the window compare function for slot 7." "?,1: Enable the window compare for slot 7."
|
|
newline
|
|
bitfld.long 0x28 0. "SLEN7,This bit enables slot 7 for ADC conversions." "?,1: Enable slot 7 for ADC conversions."
|
|
line.long 0x2C "WULIM,Window Comparator Upper Limits Register"
|
|
hexmask.long.tbyte 0x2C 0.--19. 1. "ULIM,Sets the upper limit for the window comparator."
|
|
line.long 0x30 "WLLIM,Window Comparator Lower Limits Register"
|
|
hexmask.long.tbyte 0x30 0.--19. 1. "LLIM,Sets the lower limit for the window comparator."
|
|
line.long 0x34 "SCWLIM,Scale Window Comparator Limits"
|
|
bitfld.long 0x34 0. "SCWLIMEN,Scale the window limits compare values per precision mode. When set to 0x0 (default) the values in the 20-bit limits registers will compare directly with the FIFO values regardless of the precision mode the slot is configured to. When set to.." "0,1"
|
|
line.long 0x38 "FIFO,The ADC FIFO Register contains the slot number and FIFO data for the oldest conversion data in the FIFO. The COUNT field indicates the total number of valid entries in the FIFO. A write to this register will pop one of the FIFO entries off the FIFO.."
|
|
bitfld.long 0x38 31. "RSVD,RESERVED." "0,1"
|
|
bitfld.long 0x38 28.--30. "SLOTNUM,Slot number associated with this FIFO data." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x38 20.--27. 1. "COUNT,Number of valid entries in the ADC FIFO."
|
|
hexmask.long.tbyte 0x38 0.--19. 1. "DATA,Oldest data in the FIFO."
|
|
line.long 0x3C "FIFOPR,This is a Pop Read mirrored copy of the ADCFIFO register with the only difference being that reading this register will result in a simultaneous FIFO POP which is also achieved by writing to the ADCFIFO Register. Note: The DFIFORDEN bit must be.."
|
|
bitfld.long 0x3C 31. "RSVDPR,RESERVED." "0,1"
|
|
bitfld.long 0x3C 28.--30. "SLOTNUMPR,Slot number associated with this FIFO data." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x3C 20.--27. 1. "COUNT,Number of valid entries in the ADC FIFO."
|
|
hexmask.long.tbyte 0x3C 0.--19. 1. "DATA,Oldest data in the FIFO."
|
|
group.long 0x200++0xF
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 7. "DERR,DMA Error Condition" "?,1: DMA Error Condition Occurred"
|
|
bitfld.long 0x0 6. "DCMP,DMA Transfer Complete" "?,1: DMA Completed a transfer"
|
|
newline
|
|
bitfld.long 0x0 5. "WCINC,Window comparator voltage incursion interrupt." "?,1: Window comparator voltage incursion interrupt."
|
|
bitfld.long 0x0 4. "WCEXC,Window comparator voltage excursion interrupt." "?,1: Window comparator voltage excursion interrupt."
|
|
newline
|
|
bitfld.long 0x0 3. "FIFOOVR2,FIFO 100 percent full interrupt." "?,1: FIFO 100 percent full interrupt."
|
|
bitfld.long 0x0 2. "FIFOOVR1,FIFO 75 percent full interrupt." "?,1: FIFO 75 percent full interrupt."
|
|
newline
|
|
bitfld.long 0x0 1. "SCNCMP,ADC scan complete interrupt." "?,1: ADC scan complete interrupt."
|
|
bitfld.long 0x0 0. "CNVCMP,ADC conversion complete interrupt." "?,1: ADC conversion complete interrupt."
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 7. "DERR,DMA Error Condition" "?,1: DMA Error Condition Occurred"
|
|
bitfld.long 0x4 6. "DCMP,DMA Transfer Complete" "?,1: DMA Completed a transfer"
|
|
newline
|
|
bitfld.long 0x4 5. "WCINC,Window comparator voltage incursion interrupt." "?,1: Window comparator voltage incursion interrupt."
|
|
bitfld.long 0x4 4. "WCEXC,Window comparator voltage excursion interrupt." "?,1: Window comparator voltage excursion interrupt."
|
|
newline
|
|
bitfld.long 0x4 3. "FIFOOVR2,FIFO 100 percent full interrupt." "?,1: FIFO 100 percent full interrupt."
|
|
bitfld.long 0x4 2. "FIFOOVR1,FIFO 75 percent full interrupt." "?,1: FIFO 75 percent full interrupt."
|
|
newline
|
|
bitfld.long 0x4 1. "SCNCMP,ADC scan complete interrupt." "?,1: ADC scan complete interrupt."
|
|
bitfld.long 0x4 0. "CNVCMP,ADC conversion complete interrupt." "?,1: ADC conversion complete interrupt."
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 7. "DERR,DMA Error Condition" "?,1: DMA Error Condition Occurred"
|
|
bitfld.long 0x8 6. "DCMP,DMA Transfer Complete" "?,1: DMA Completed a transfer"
|
|
newline
|
|
bitfld.long 0x8 5. "WCINC,Window comparator voltage incursion interrupt." "?,1: Window comparator voltage incursion interrupt."
|
|
bitfld.long 0x8 4. "WCEXC,Window comparator voltage excursion interrupt." "?,1: Window comparator voltage excursion interrupt."
|
|
newline
|
|
bitfld.long 0x8 3. "FIFOOVR2,FIFO 100 percent full interrupt." "?,1: FIFO 100 percent full interrupt."
|
|
bitfld.long 0x8 2. "FIFOOVR1,FIFO 75 percent full interrupt." "?,1: FIFO 75 percent full interrupt."
|
|
newline
|
|
bitfld.long 0x8 1. "SCNCMP,ADC scan complete interrupt." "?,1: ADC scan complete interrupt."
|
|
bitfld.long 0x8 0. "CNVCMP,ADC conversion complete interrupt." "?,1: ADC conversion complete interrupt."
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 7. "DERR,DMA Error Condition" "?,1: DMA Error Condition Occurred"
|
|
bitfld.long 0xC 6. "DCMP,DMA Transfer Complete" "?,1: DMA Completed a transfer"
|
|
newline
|
|
bitfld.long 0xC 5. "WCINC,Window comparator voltage incursion interrupt." "?,1: Window comparator voltage incursion interrupt."
|
|
bitfld.long 0xC 4. "WCEXC,Window comparator voltage excursion interrupt." "?,1: Window comparator voltage excursion interrupt."
|
|
newline
|
|
bitfld.long 0xC 3. "FIFOOVR2,FIFO 100 percent full interrupt." "?,1: FIFO 100 percent full interrupt."
|
|
bitfld.long 0xC 2. "FIFOOVR1,FIFO 75 percent full interrupt." "?,1: FIFO 75 percent full interrupt."
|
|
newline
|
|
bitfld.long 0xC 1. "SCNCMP,ADC scan complete interrupt." "?,1: ADC scan complete interrupt."
|
|
bitfld.long 0xC 0. "CNVCMP,ADC conversion complete interrupt." "?,1: ADC conversion complete interrupt."
|
|
group.long 0x240++0x7
|
|
line.long 0x0 "DMATRIGEN,DMA Trigger Enable Register"
|
|
bitfld.long 0x0 1. "DFIFOFULL,Trigger DMA upon FIFO 100 percent Full" "0,1"
|
|
bitfld.long 0x0 0. "DFIFO75,Trigger DMA upon FIFO 75 percent Full" "0,1"
|
|
line.long 0x4 "DMATRIGSTAT,DMA Trigger Status Register"
|
|
bitfld.long 0x4 1. "DFULLSTAT,Triggered DMA from FIFO 100 percent Full" "0,1"
|
|
bitfld.long 0x4 0. "D75STAT,Triggered DMA from FIFO 75 percent Full" "0,1"
|
|
group.long 0x280++0x3
|
|
line.long 0x0 "DMACFG,DMA Configuration Register"
|
|
bitfld.long 0x0 18. "DPWROFF,Power Off the ADC System upon DMACPL." "0,1"
|
|
bitfld.long 0x0 17. "DMAMSK,Mask the FIFOCNT and SLOTNUM when transferring FIFO contents to memory" "0: FIFO Contents are copied directly to memory..,1: Only the FIFODATA contents are copied to memory.."
|
|
newline
|
|
bitfld.long 0x0 16. "DMAHONSTAT,Halt New ADC conversions until DMA Status DMAERR and DMACPL Cleared." "0: ADC conversions will continue regardless of DMA..,1: ADC conversions will not progress if DMAERR or.."
|
|
bitfld.long 0x0 9. "DMADYNPRI,Enables dynamic priority based on FIFO fullness. When FIFO is full priority is automatically set to HIGH. Otherwise DMAPRI is used." "0: Disable dynamic priority (use DMAPRI setting only),1: Enable dynamic priority"
|
|
newline
|
|
bitfld.long 0x0 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
|
|
bitfld.long 0x0 2. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction,1: Memory to Peripheral transaction"
|
|
newline
|
|
bitfld.long 0x0 0. "DMAEN,DMA Enable" "0: Disable DMA Function,1: Enable DMA Function"
|
|
group.long 0x288++0xB
|
|
line.long 0x0 "DMATOTCOUNT,DMA Total Transfer Count"
|
|
hexmask.long.word 0x0 2.--17. 1. "TOTCOUNT,Total Transfer Count"
|
|
line.long 0x4 "DMATARGADDR,DMA Target Address Register"
|
|
sif (cpuis("AMA3B2KK"))
|
|
hexmask.long.word 0x4 20.--31. 1. "UTARGADDR,SRAM Target"
|
|
endif
|
|
sif (cpuis("AMA3B1KK")||cpuis("AMAP31KK"))
|
|
hexmask.long.word 0x4 19.--31. 1. "UTARGADDR,SRAM Target"
|
|
newline
|
|
hexmask.long.tbyte 0x4 0.--18. 1. "LTARGADDR,DMA Target Address"
|
|
endif
|
|
sif (cpuis("AMA3B2KK"))
|
|
hexmask.long.tbyte 0x4 0.--19. 1. "LTARGADDR,DMA Target Address"
|
|
endif
|
|
line.long 0x8 "DMASTAT,DMA Status Register"
|
|
bitfld.long 0x8 2. "DMAERR,DMA Error" "0,1"
|
|
bitfld.long 0x8 1. "DMACPL,DMA Transfer Complete" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "DMATIP,DMA Transfer In Progress" "0,1"
|
|
tree.end
|
|
tree "APBDMA (APB DMA Register Interfaces)"
|
|
base ad:0x40011000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "BBVALUE,Control Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "PIN,PIO values"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATAOUT,Data Output Values"
|
|
line.long 0x4 "BBSETCLEAR,Set/Clear Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "CLEAR,Write 1 to clear PIO value"
|
|
hexmask.long.byte 0x4 0.--7. 1. "SET,Write 1 to set PIO value (set higher priority then clear if both bits are set)"
|
|
line.long 0x8 "BBINPUT,PIO Input Values"
|
|
hexmask.long.byte 0x8 0.--7. 1. "DATAIN,PIO values"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "DEBUGDATA,PIO Input Values"
|
|
hexmask.long 0x0 0.--31. 1. "DEBUGDATA,Debug Data"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "DEBUG,PIO Input Values"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DEBUGEN,Debug Enable"
|
|
tree.end
|
|
tree "BLEIF (BLE Interface)"
|
|
base ad:0x5000C000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FIFO,Provides direct random access to both input and output FIFOs. The state of the FIFO is not disturbed by reading these locations (i.e.. no POP will occur). FIFO0 is accessible from addresses 0x0 - 0x1C. and is used for data output from the IOM to.."
|
|
hexmask.long 0x0 0.--31. 1. "FIFO,FIFO direct access. Only locations 0 - 3F will return valid information."
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|
group.long 0x100++0x17
|
|
line.long 0x0 "FIFOPTR,Provides the current valid byte count of data within the FIFO as seen from the internal state machines. FIFO0 is dedicated to outgoing transactions and FIFO1 is dedicated to incoming transactions. All counts are specified in units of bytes."
|
|
hexmask.long.byte 0x0 24.--31. 1. "FIFO1REM,The number of remaining data bytes slots currently in FIFO 1 (written by interface read by MCU)"
|
|
hexmask.long.byte 0x0 16.--23. 1. "FIFO1SIZ,The number of valid data bytes currently in FIFO 1 (written by interface read by MCU)"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "FIFO0REM,The number of remaining data bytes slots currently in FIFO 0 (written by MCU read by interface)"
|
|
hexmask.long.byte 0x0 0.--7. 1. "FIFO0SIZ,The number of valid data bytes currently in the FIFO 0 (written by MCU read by interface)"
|
|
line.long 0x4 "FIFOTHR,Sets the threshold values for incoming and outgoing transactions. The threshold values are used to assert the interrupt if enabled. and also used during DMA to set the transfer size as a result of DMATHR trigger."
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|
hexmask.long.byte 0x4 8.--13. 1. "FIFOWTHR,FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the write FIFO contains FIFOWTHR free bytes as.."
|
|
hexmask.long.byte 0x4 0.--5. 1. "FIFORTHR,FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the read FIFO contains FIFORTHR valid bytes of data as.."
|
|
line.long 0x8 "FIFOPOP,Will advance the internal read pointer of the incoming FIFO (FIFO1) when read. if POPWR is not active. If POPWR is active. a write to this register is needed to advance the internal FIFO pointer."
|
|
hexmask.long 0x8 0.--31. 1. "FIFODOUT,This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0) the FIFO read pointer will be advanced by one word as a result of the read."
|
|
line.long 0xC "FIFOPUSH,Will write new data into the outgoing FIFO and advance the internal write pointer."
|
|
hexmask.long 0xC 0.--31. 1. "FIFODIN,This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes)."
|
|
line.long 0x10 "FIFOCTRL,Provides controls for the operation of the internal FIFOs. Contains fields used to control the operation of the POP register. and also controls to reset the internal pointers of the FIFOs."
|
|
bitfld.long 0x10 1. "FIFORSTN,Active low manual reset of the FIFO. Write to 0 to reset FIFO and then write to 1 to remove the reset." "0,1"
|
|
bitfld.long 0x10 0. "POPWR,Selects the mode in which 'pop' events are done for the FIFO read operations. A value of '1' will prevent a pop event on a read operation and will require a write to the FIFOPOP register to create a pop event." "0,1"
|
|
line.long 0x14 "FIFOLOC,Provides a read only value of the current read and write pointers. This register is read only and can be used along with the FIFO direct access method to determine the next data to be used for input and output functions."
|
|
hexmask.long.byte 0x14 8.--11. 1. "FIFORPTR,Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1) which is used to store read data returned from external devices during a read operation."
|
|
hexmask.long.byte 0x14 0.--3. 1. "FIFOWPTR,Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0) which is used during write operations to external devices."
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "CLKCFG,Provides clock related controls used internal to the BLEIF module. and enablement of 32KHz clock to the BLE Core module. The internal clock sourced is selected via the FSEL and can be further divided by 3 using the DIV3 control."
|
|
bitfld.long 0x0 12. "DIV3,Enable of the divide by 3 of the source IOCLK." "0,1"
|
|
bitfld.long 0x0 11. "CLK32KEN,Enable for the 32Khz clock to the BLE module" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "FSEL,Select the input clock frequency." "0: Selects the minimum power clock. This setting..,1: Selects the HFRC as the input clock.,2: Selects the HFRC / 2 as the input clock.,3: Selects the HFRC / 4 as the input clock.,4: Selects the HFRC / 8 as the input clock.,5: Selects the HFRC / 16 as the input clock.,6: Selects the HFRC / 32 as the input clock.,7: Selects the HFRC / 64 as the input clock."
|
|
bitfld.long 0x0 0. "IOCLKEN,Enable for the interface clock. Must be enabled prior to executing any IO operations." "0,1"
|
|
group.long 0x20C++0xF
|
|
line.long 0x0 "CMD,Writes to this register will start an IO transaction. as well as set various parameters for the command itself. Reads will return the command value written to the CMD register."
|
|
hexmask.long.byte 0x0 24.--31. 1. "OFFSETLO,This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command. Offset bytes are transferred starting from the highest byte first."
|
|
bitfld.long 0x0 20.--21. "CMDSEL,Command Specific selection information" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x0 8.--19. 1. "TSIZE,Defines the transaction size in bytes. The offset transfer is not included in this size."
|
|
bitfld.long 0x0 7. "CONT,Continue to hold the bus after the current transaction if set to a 1 with a new command issued." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5.--6. "OFFSETCNT,Number of offset bytes to use for the command - 0 1 2 3 are valid selections. The second (byte 1) and third byte (byte 2) are read from the OFFSETHI register and the low order byte is pulled from this register in the OFFSETLO field." "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--4. 1. "CMD,Command for submodule."
|
|
line.long 0x4 "CMDRPT,Will repeat the next command for CMDRPT number of times. If CMDRPT is set to 1. the next command will be done 2 times in series. A repeat count of up to 31 is possible. Each command will be done as a separate command. but the data will"
|
|
hexmask.long.byte 0x4 0.--4. 1. "CMDRPT,Count of number of times to repeat the next command."
|
|
line.long 0x8 "OFFSETHI,Provides the high order bytes of 2 or 3 byte offset transactions of the current command. Usage of these bytes is dependent on the OFFSETCNT field in the CMD register. If the OFFSETCNT == 3. the data located at OFFSETHI[15:0] will first be.."
|
|
hexmask.long.word 0x8 0.--15. 1. "OFFSETHI,Holds the high order bytes of the 2 or 3 byte offset phase of a transaction."
|
|
line.long 0xC "CMDSTAT,Provides status on the execution of the command currently in progress. The fields in this register will reflect the real time status of the internal state machines and data transfers within the IOM."
|
|
hexmask.long.word 0xC 8.--19. 1. "CTSIZE,The current number of bytes still to be transferred with this command. This field will count down to zero."
|
|
bitfld.long 0xC 5.--7. "CMDSTAT,The current status of the command execution." "?,1: Error encountered with command,2: Actively processing command,?,4: Idle state no active command no error,?,6: Command in progress but waiting on data from host,?"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--4. 1. "CCMD,current command that is being executed"
|
|
group.long 0x220++0x4B
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 16. "B2MSHUTDN,Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is deasserted (1 -> 0)" "0,1"
|
|
bitfld.long 0x0 15. "B2MACTIVE,Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is deasserted (1 -> 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "B2MSLEEP,The B2M_STATE from the BLE Core transitioned into the sleep state" "0,1"
|
|
bitfld.long 0x0 13. "CQERR,Command queue error during processing. When an error occurs the system will stop processing and halt operations to allow software to take recovery actions" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "CQUPD,Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is.." "0,1"
|
|
bitfld.long 0x0 11. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
bitfld.long 0x0 9. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "BLECSSTAT,BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted indicating that SPI writes can be done to the BLE Core." "0,1"
|
|
bitfld.long 0x0 7. "BLECIRQ,BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted indicating the availability of read data from the BLE Core." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x0 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "B2MST,B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core." "0,1"
|
|
bitfld.long 0x0 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "FUNDFL,Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO." "0,1"
|
|
bitfld.long 0x0 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 16. "B2MSHUTDN,Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is deasserted (1 -> 0)" "0,1"
|
|
bitfld.long 0x4 15. "B2MACTIVE,Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is deasserted (1 -> 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "B2MSLEEP,The B2M_STATE from the BLE Core transitioned into the sleep state" "0,1"
|
|
bitfld.long 0x4 13. "CQERR,Command queue error during processing. When an error occurs the system will stop processing and halt operations to allow software to take recovery actions" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CQUPD,Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is.." "0,1"
|
|
bitfld.long 0x4 11. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
bitfld.long 0x4 9. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "BLECSSTAT,BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted indicating that SPI writes can be done to the BLE Core." "0,1"
|
|
bitfld.long 0x4 7. "BLECIRQ,BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted indicating the availability of read data from the BLE Core." "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x4 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x4 4. "B2MST,B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core." "0,1"
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bitfld.long 0x4 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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bitfld.long 0x4 2. "FUNDFL,Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO." "0,1"
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bitfld.long 0x4 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x4 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
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bitfld.long 0x8 16. "B2MSHUTDN,Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is deasserted (1 -> 0)" "0,1"
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bitfld.long 0x8 15. "B2MACTIVE,Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is deasserted (1 -> 0)" "0,1"
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bitfld.long 0x8 14. "B2MSLEEP,The B2M_STATE from the BLE Core transitioned into the sleep state" "0,1"
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bitfld.long 0x8 13. "CQERR,Command queue error during processing. When an error occurs the system will stop processing and halt operations to allow software to take recovery actions" "0,1"
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bitfld.long 0x8 12. "CQUPD,Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is.." "0,1"
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bitfld.long 0x8 11. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x8 10. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x8 9. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x8 8. "BLECSSTAT,BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted indicating that SPI writes can be done to the BLE Core." "0,1"
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bitfld.long 0x8 7. "BLECIRQ,BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted indicating the availability of read data from the BLE Core." "0,1"
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bitfld.long 0x8 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x8 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x8 4. "B2MST,B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core." "0,1"
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bitfld.long 0x8 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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bitfld.long 0x8 2. "FUNDFL,Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO." "0,1"
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bitfld.long 0x8 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x8 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
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bitfld.long 0xC 16. "B2MSHUTDN,Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is deasserted (1 -> 0)" "0,1"
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bitfld.long 0xC 15. "B2MACTIVE,Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is deasserted (1 -> 0)" "0,1"
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bitfld.long 0xC 14. "B2MSLEEP,The B2M_STATE from the BLE Core transitioned into the sleep state" "0,1"
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bitfld.long 0xC 13. "CQERR,Command queue error during processing. When an error occurs the system will stop processing and halt operations to allow software to take recovery actions" "0,1"
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bitfld.long 0xC 12. "CQUPD,Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is.." "0,1"
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bitfld.long 0xC 11. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0xC 10. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0xC 9. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0xC 8. "BLECSSTAT,BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted indicating that SPI writes can be done to the BLE Core." "0,1"
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bitfld.long 0xC 7. "BLECIRQ,BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted indicating the availability of read data from the BLE Core." "0,1"
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bitfld.long 0xC 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0xC 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0xC 4. "B2MST,B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core." "0,1"
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bitfld.long 0xC 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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bitfld.long 0xC 2. "FUNDFL,Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO." "0,1"
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bitfld.long 0xC 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0xC 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x10 "DMATRIGEN,Provides control on which event will trigger the DMA transfer after the DMA operation is setup and enabled. The trigger event will cause a number of bytes (depending on trigger event) to be"
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bitfld.long 0x10 1. "DTHREN,Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes) the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO and will transfer (WTHR/4) number of words" "0,1"
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bitfld.long 0x10 0. "DCMDCMPEN,Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered the number of words transferred will be the lesser of the remaining TOTCOUNT bytes or the number of bytes in the FIFO.." "0,1"
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line.long 0x14 "DMATRIGSTAT,Provides the status of trigger events that have occurred for the transaction. Some of the bits are read only and some can be reset via a write of 0."
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bitfld.long 0x14 2. "DTOTCMP,DMA triggered when DCMDCMP = 0 and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is" "0,1"
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bitfld.long 0x14 1. "DTHR,Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA." "0,1"
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bitfld.long 0x14 0. "DCMDCMP,Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA." "0,1"
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line.long 0x18 "DMACFG,Configuration control of the DMA process. including the direction of DMA. and enablement of DMA"
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sif (cpuis("AMA3B1KK")||cpuis("AMAP31KK"))
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bitfld.long 0x18 9. "DPWROFF,Power off module after DMA is complete. If this bit is active the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain power down will not be performed." "0: Power off disabled,1: Power off enabled"
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endif
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bitfld.long 0x18 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x18 1. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction. To be..,1: Memory to Peripheral transaction. To be set when.."
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bitfld.long 0x18 0. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable DMA Function,1: Enable DMA Function"
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line.long 0x1C "DMATOTCOUNT,Contains the number of bytes to be transferred for this DMA transaction. This register is decremented as the data is transferred. and will be 0 at the completion of the DMA operation."
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hexmask.long.word 0x1C 0.--11. 1. "TOTCOUNT,Triggered DMA from Command complete event occurred. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."
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line.long 0x20 "DMATARGADDR,The source or destination address internal the SRAM for the DMA data. For write operations. this can only be SRAM data (ADDR bit 28 = 1); For read operations. this can be either SRAM or FLASH (ADDR bit 28 = 0)"
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bitfld.long 0x20 28. "TARGADDR28,Bit 28 of the target byte address for source of DMA (either read or write). In cases of non-word aligned addresses the DMA logic will take care for ensuring only the target bytes are read/written." "0,1"
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sif (cpuis("AMA3B2KK"))
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hexmask.long.tbyte 0x20 0.--20. 1. "TARGADDR,Bits [19:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment and does not have to be word aligned. In cases of non-word aligned addresses the DMA logic will take care for ensuring only.."
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endif
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sif (cpuis("AMA3B1KK")||cpuis("AMAP31KK"))
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hexmask.long.tbyte 0x20 0.--19. 1. "TARGADDR,Bits [19:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment and does not have to be word aligned. In cases of non-word aligned addresses the DMA logic will take care for ensuring only.."
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endif
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line.long 0x24 "DMASTAT,Status of the DMA operation currently in progress."
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bitfld.long 0x24 2. "DMAERR,DMA Error. This active high bit signals that an error was encountered during the DMA operation." "0,1"
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bitfld.long 0x24 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0." "0,1"
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bitfld.long 0x24 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
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line.long 0x28 "CQCFG,Controls parameters and options for execution of the command queue operation. To enable command queue. create this in memory. set the address. and enable it with a write to CQEN"
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bitfld.long 0x28 1. "CQPRI,Sets the Priority of the command queue DMA request." "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x28 0. "CQEN,Command queue enable. When set will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled" "0: Disable CQ Function,1: Enable CQ Function"
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line.long 0x2C "CQADDR,The SRAM address which will be fetched next execution of the CQ operation. This register is updated as the CQ operation progresses. and is the live version of the register. The register can also be"
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bitfld.long 0x2C 28. "CQADDR28,Bit 28 of target byte address for source of CQ (read only). Used to denote Flash (0) or SRAM (1) access" "0,1"
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sif (cpuis("AMA3B2KK"))
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hexmask.long.tbyte 0x2C 2.--20. 1. "CQADDR,Bits 19:2 of target byte address for source of CQ (read only). The buffer must be aligned on a word boundary"
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endif
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sif (cpuis("AMA3B1KK")||cpuis("AMAP31KK"))
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hexmask.long.tbyte 0x2C 2.--19. 1. "CQADDR,Bits 19:2 of target byte address for source of CQ (read only). The buffer must be aligned on a word boundary"
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endif
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line.long 0x30 "CQSTAT,Provides the status of the command queue operation. If the command queue is disabled. these bits will be cleared. The bits are read only"
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bitfld.long 0x30 2. "CQERR,Command queue processing error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
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bitfld.long 0x30 1. "CQPAUSED,Command queue operation is currently paused." "0,1"
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bitfld.long 0x30 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
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line.long 0x34 "CQFLAGS,Provides the current status of the SWFLAGS (bits 7:0) and the hardware generated flags (15:8). A '1' will pause the CQ operation if it the same bit is enabled in the CQPAUSEEN register"
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hexmask.long.word 0x34 16.--31. 1. "CQIRQMASK,Provides for a per-bit mask of the flags used to invoke an interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt if the CQWT_int interrupt is enabled."
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hexmask.long.word 0x34 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
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line.long 0x38 "CQSETCLEAR,Set/Clear the command queue software pause flags on a per-bit basis. Contains 3 fields. allowing for setting. clearing or toggling the value in the software flags. Priority when the same bit"
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hexmask.long.byte 0x38 16.--23. 1. "CQFCLR,Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x38 8.--15. 1. "CQFTGL,Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x38 0.--7. 1. "CQFSET,Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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line.long 0x3C "CQPAUSEEN,Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the CQFLAG register is '1'. CQ processing will halt until either value is changed to '0'."
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hexmask.long.word 0x3C 0.--15. 1. "CQPEN,Enables the specified event to pause command processing when active"
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line.long 0x40 "CQCURIDX,Current index value. targeted to be written by register write operations within the command queue. This is compared to the CQENDIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and"
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hexmask.long.byte 0x40 0.--7. 1. "CQCURIDX,Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x44 "CQENDIDX,End index value. targeted to be written by software to indicate the last valid register pair contained within the command queue for register write operations within the command queue."
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hexmask.long.byte 0x44 0.--7. 1. "CQENDIDX,Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x48 "STATUS,General status of the IOM module command execution."
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bitfld.long 0x48 2. "IDLEST,indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to hold-offs from data availability or as the command gets propagated into the logic from the registers." "?,1: The I/O state machine is in the idle state."
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bitfld.long 0x48 1. "CMDACT,Indicates if the active I/O Command is currently processing a transaction or command is complete but the FIFO pointers are still synchronizing internally. This bit will go high at" "?,1: An I/O command is active. Indicates the active.."
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bitfld.long 0x48 0. "ERR,Bit has been deprecated. Please refer to the other error indicators. This will always return 0." "?,1: Bit has been deprecated and will always return 0."
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group.long 0x300++0xF
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line.long 0x0 "MSPICFG,Controls the configuration of the SPI master module. including POL/PHA. LSB. flow control. and delays for MISO and MOSI"
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bitfld.long 0x0 30. "MSPIRST,Bit is deprecated. setting it will have no effect." "0,1"
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bitfld.long 0x0 27.--29. "DOUTDLY,Delay tap to use for the output signal (MOSI). This give more hold time on the output data." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 24.--26. "DINDLY,Delay tap to use for the input signal (MISO). This gives more hold time on the input data." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "SPILSB,Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first." "0: Send and receive MSB bit first,1: Send and receive LSB bit first"
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bitfld.long 0x0 22. "RDFCPOL,Selects the read flow control signal polarity. When set the clock will be held low until the flow control is deasserted." "0: SPI_STATUS signal from BLE Core high(1) creates..,1: SPI_STATUS signal from BLE Core low(0) creates.."
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bitfld.long 0x0 21. "WTFCPOL,Selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of this bit. (For example: WTFCPOL = 0 will allow a SPI_STATUS=1 to pause transfers)." "0: SPI_STATUS signal from BLE Core high(1) creates..,1: SPI_STATUS signal from BLE Core high(1) creates.."
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bitfld.long 0x0 17. "RDFC,Enables flow control of new read transactions based on the SPI_STATUS signal from the BLE Core." "0: Read mode flow control disabled.,1: Read mode flow control enabled."
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bitfld.long 0x0 16. "WTFC,Enables flow control of new write transactions based on the SPI_STATUS signal from the BLE Core." "0: Write mode flow control disabled.,1: Write mode flow control enabled."
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bitfld.long 0x0 2. "FULLDUP,Full Duplex mode. Capture read data during writes operations" "0,1"
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bitfld.long 0x0 1. "SPHA,Selects the SPI phase; When 1 will shift the sampling edge by 1/2 clock." "0: Sample on the leading (first) clock edge rising..,1: Sample on the trailing (second) clock edge.."
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newline
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bitfld.long 0x0 0. "SPOL,This bit selects SPI polarity." "0: The initial value of the clock is 0.,1: The initial value of the clock is 1."
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line.long 0x4 "BLECFG,Provides control of isolation and IO signals between the interface module and the BLE Core."
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bitfld.long 0x4 14.--15. "SPIISOCTL,Configuration of BLEH isolation controls for SPI related signals." "0: SPI signals from BLE Core to/from MCU Core are..,?,2: SPI signals from BLE Core to/from MCU Core are..,3: SPI signals from BLE Core to/from MCU Core are.."
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bitfld.long 0x4 12.--13. "PWRISOCTL,Configuration of BLEH isolation control for power related signals." "0: BLEH Power signal isolation is controlled..,?,2: BLEH power signal isolation to off (not isolated).,3: BLEH power signal isolation to on (isolated)."
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newline
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bitfld.long 0x4 11. "STAYASLEEP,Set to prevent the BLE power control module from waking up the BLE Core after going into power down. To be used for graceful shutdown set by software prior to powering off and will allow assertion of reset from sleep state." "0,1"
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bitfld.long 0x4 10. "FRCCLK,Force the clock in the BLEIF to be always running" "0,1"
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newline
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bitfld.long 0x4 9. "MCUFRCSLP,Force power state machine to go to the sleep state. Intended for debug only. Has no effect on the actual BLE Core state only the state of the BLEIF interface state machine." "0,1"
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bitfld.long 0x4 8. "WT4ACTOFF,Debug control of BLEIF power state machine. Allows transition into the active state in the BLEIF state without waiting for DCDC request from BLE Core." "0,1"
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bitfld.long 0x4 6.--7. "BLEHREQCTL,BLEH power on request override. The value of this field will be sent to the BLE Core when the PWRSM is off. Otherwise the value is supplied from internal logic." "0: BLEH Power-on signal is controlled by the PWRSM..,?,2: BLEH Power-on signal is set to off (0).,3: BLEH Power-on reg signal is set to on (1)."
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bitfld.long 0x4 4.--5. "DCDCFLGCTL,DCDCFLG signal override. The value of this field will be sent to the BLE Core when the PWRSM is off. Otherwise the value is supplied from internal logic." "0: DCDC Flag signal is controlled by the PWRSM..,?,2: DCDC Flag signal is set to off (0).,3: DCDC Flag signal is set to on (1)."
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bitfld.long 0x4 2.--3. "WAKEUPCTL,WAKE signal override. Controls the source of the WAKE signal to the BLE Core." "0: Wake signal is controlled by the PWRSM logic and..,?,2: Wake signal is set to off (0).,3: Wake signal is set to on (1)."
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bitfld.long 0x4 1. "BLERSTN,Reset line to the BLE Core. This will reset the BLE core when asserted ('0') and must be written to '1' prior to performing any BTLE related operations to the core." "0: The reset signal is inactive (1),1: The reset signal is active (0)"
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bitfld.long 0x4 0. "PWRSMEN,Enable the power state machine for automatic sequencing and control of power states of the BLE Core module." "0: Internal power state machine is disabled and..,1: Internal power state machine is enabled and will.."
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line.long 0x8 "PWRCMD,Sends power related commands to the power state machine in the BLE IF module."
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bitfld.long 0x8 1. "RESTART,Restart the BLE Core after going into the shutdown state. Only valid when in the shutdown state." "0,1"
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bitfld.long 0x8 0. "WAKEREQ,Wake request from the MCU. When asserted (1) the BLE Interface logic will assert the wakeup request signal to the BLE Core. Only recognized when in the sleep state" "0,1"
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line.long 0xC "BSTATUS,Status of the BLE Core interface signals"
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bitfld.long 0xC 12. "BLEHREQ,Value of the BLEHREQ signal to the power control unit. The BLEHREQ signal is sent from the BLEIF module to the power control module to request the BLEH power up. When the BLEHACK signal is asserted " "0,1"
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bitfld.long 0xC 11. "BLEHACK,Value of the BLEHACK signal from the power control unit. If the signal is '1' the BLEH power is active and ready for use." "0,1"
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|
|
bitfld.long 0xC 8.--10. "PWRST,Current status of the power state machine" "0: Internal power state machine is disabled and..,1: Initialization state. BLEH not powered,2: Waiting for the power-up of the BLEH,3: The BLE Core is powered and active,4: The BLE Core is in shutdown mode,?,6: The BLE Core has entered sleep mode and the..,?"
|
|
bitfld.long 0xC 7. "BLEIRQ,Status of the BLEIRQ signal from the BLE Core. A value of 1 indicates that read data is available in the core and a read operation needs to be performed." "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "WAKEUP,Value of the WAKEUP signal to the BLE Core . The WAKEUP signals is sent from the BLEIF to the BLECORE to request the BLE Core transition from sleep state to active state." "0,1"
|
|
bitfld.long 0xC 5. "DCDCFLAG,Value of the DCDCFLAG signal to the BLE Core. The DCDCFLAG is a signal to the BLE Core indicating that the BLEH power is active." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "DCDCREQ,Value of the DCDCREQ signal from the BLE Core. The DCDCREQ signal is sent from the core to the BLEIF module when the BLE core requires BLEH power to be active. When activated this is" "0,1"
|
|
bitfld.long 0xC 3. "SPISTATUS,Value of the SPISTATUS signal from the BLE Core. The signal is asserted when the BLE Core is able to accept write data via the SPI interface. Data should be transmitted to the" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0.--2. "B2MSTATE,State of the BLE Core logic." "0: Reset State,1: Sleep state.,2: Standby State,3: Idle state,4: Active state.,?,?,?"
|
|
group.long 0x410++0x3
|
|
line.long 0x0 "BLEDBG,Debug control"
|
|
hexmask.long 0x0 3.--31. 1. "DBGDATA,Debug data"
|
|
bitfld.long 0x0 2. "APBCLKON,APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "IOCLKON,IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
|
|
bitfld.long 0x0 0. "DBGEN,Debug Enable. Setting this bit will enable the update of data within this register otherwise it is clock gated for power savings" "0,1"
|
|
tree.end
|
|
tree "CACHECTRL (Flash Cache Controller)"
|
|
base ad:0x40018000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CACHECFG,FLASH Cache Control"
|
|
bitfld.long 0x0 24. "ENABLE_MONITOR,Enable Cache Monitoring Stats. Cache monitoring consumes additional power and should only be enabled when profiling code and counters will increment when this bit is set. Counter values will be retained when this is set to 0 allowing.." "0,1"
|
|
bitfld.long 0x0 20. "DATA_CLKGATE,Enable aggressive clock gating of entire data array. This bit should be set to 1 for optimal power efficiency." "0,1"
|
|
bitfld.long 0x0 11. "CACHE_LS,Enable LS (light sleep) of cache RAMs. Software should DISABLE this bit since cache activity is too high to benefit from LS usage." "0,1"
|
|
bitfld.long 0x0 10. "CACHE_CLKGATE,Enable clock gating of cache TAG RAM. Software should enable this bit for optimal power efficiency." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "DCACHE_ENABLE,Enable FLASH Data Caching" "0,1"
|
|
bitfld.long 0x0 8. "ICACHE_ENABLE,Enable FLASH Instruction Caching" "0,1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CONFIG,Sets the cache configuration"
|
|
bitfld.long 0x0 3. "ENABLE_NC1,Enable Non-cacheable region 1. See NCR1 registers to define the region." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "ENABLE_NC0,Enable Non-cacheable region 0. See NCR0 registers to define the region." "0,1"
|
|
bitfld.long 0x0 1. "LRU,Sets the cache replacement policy. 0=LRR (least recently replaced) 1=LRU (least recently used). LRR minimizes writes to the TAG SRAM." "0: LRR,1: LRU"
|
|
bitfld.long 0x0 0. "ENABLE,Enables the FLASH cache controller and enables power to the cache SRAMs. The ICACHE_ENABLE and DCACHE_ENABLE should be set to enable caching for each type of access." "0,1"
|
|
sif (cpuis("AMA3B1KK")||cpuis("AMAP31KK"))
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "FLASHCFG,FLASH Control Register"
|
|
bitfld.long 0x0 12.--13. "LPMMODE,Controls FLASH low power modes (control of LPM pin)." "0: High power mode (LPM not used).,1: Fast Standby mode. LPM deasserted for read..,2: Low Power mode. LPM always asserted for reads.,?"
|
|
hexmask.long.byte 0x0 8.--11. 1. "LPM_RD_WAIT,Sets FLASH waitstates when in LPM Mode 2 (RD_WAIT in LPM mode 2 only)"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "SEDELAY,Sets SE delay (FLASH address setup). A value of 5 is recommended." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--3. 1. "RD_WAIT,Sets read waitstates for normal (fast) operation. A value of 1 is recommended."
|
|
endif
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CTRL,Cache Control"
|
|
sif (cpuis("AMA3B2KK"))
|
|
bitfld.long 0x0 18. "FLASH3_SLM_ENABLE,Enable FLASH Sleep Mode. Write to 1 to put FLASH1 into sleep mode. NOTE: there is a 5 us latency after waking FLASH until the first access will be returned." "0,1"
|
|
endif
|
|
sif (cpuis("AMA3B2KK"))
|
|
bitfld.long 0x0 17. "FLASH3_SLM_DISABLE,Disable FLASH Sleep Mode. Write 1 to wake FLASH1 from sleep mode (reading the array will also automatically wake it)." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA3B2KK"))
|
|
bitfld.long 0x0 16. "FLASH3_SLM_STATUS,FLASH Sleep Mode Status. 1 indicates that FLASH1 is in sleep mode 0 indicates FLASH1 is in normal mode." "0,1"
|
|
endif
|
|
sif (cpuis("AMA3B2KK"))
|
|
bitfld.long 0x0 14. "FLASH2_SLM_ENABLE,Enable FLASH Sleep Mode. Write to 1 to put FLASH1 into sleep mode. NOTE: there is a 5 us latency after waking FLASH until the first access will be returned." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA3B2KK"))
|
|
bitfld.long 0x0 13. "FLASH2_SLM_DISABLE,Disable FLASH Sleep Mode. Write 1 to wake FLASH2 from sleep mode (reading the array will also automatically wake it)." "0,1"
|
|
endif
|
|
sif (cpuis("AMA3B2KK"))
|
|
bitfld.long 0x0 12. "FLASH2_SLM_STATUS,FLASH Sleep Mode Status. 1 indicates that FLASH2 is in sleep mode 0 indicates FLASH2 is in normal mode." "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 10. "FLASH1_SLM_ENABLE,Enable FLASH Sleep Mode. Write to 1 to put FLASH1 into sleep mode. NOTE: there is a 5 us latency after waking FLASH until the first access will be returned." "0,1"
|
|
bitfld.long 0x0 9. "FLASH1_SLM_DISABLE,Disable FLASH Sleep Mode. Write 1 to wake FLASH1 from sleep mode (reading the array will also automatically wake it)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FLASH1_SLM_STATUS,FLASH Sleep Mode Status. 1 indicates that FLASH1 is in sleep mode 0 indicates FLASH1 is in normal mode." "0,1"
|
|
bitfld.long 0x0 6. "FLASH0_SLM_ENABLE,Enable FLASH Sleep Mode. Write to 1 to put FLASH0 into sleep mode. NOTE: there is a 5 us latency after waking FLASH until the first access will be returned." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "FLASH0_SLM_DISABLE,Disable FLASH Sleep Mode. Write 1 to wake FLASH0 from sleep mode (reading the array will also automatically wake it)." "0,1"
|
|
bitfld.long 0x0 4. "FLASH0_SLM_STATUS,FLASH Sleep Mode Status. 1 indicates that FLASH0 is in sleep mode 0 indicates FLASH0 is in normal mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CACHE_READY,Cache Ready Status (enabled and not processing an invalidate operation)" "0,1"
|
|
bitfld.long 0x0 1. "RESET_STAT,Reset Cache Statistics. When written to a 1 the cache monitor counters will be cleared. The monitor counters can be reset only when the CACHECFG.ENABLE_MONITOR bit is set." "?,1: Clear Cache Stats"
|
|
newline
|
|
bitfld.long 0x0 0. "INVALIDATE,Writing a 1 to this bit field invalidates the FLASH cache contents." "0,1"
|
|
group.long 0x10++0xF
|
|
line.long 0x0 "NCR0START,FLASH Cache Noncacheable Region 0 Start"
|
|
hexmask.long.tbyte 0x0 4.--26. 1. "ADDR,Start address for non-cacheable region 0"
|
|
line.long 0x4 "NCR0END,FLASH Cache Noncacheable Region 0 End"
|
|
hexmask.long.tbyte 0x4 4.--26. 1. "ADDR,End address for non-cacheable region 0"
|
|
line.long 0x8 "NCR1START,FLASH Cache Noncacheable Region 1 Start"
|
|
hexmask.long.tbyte 0x8 4.--26. 1. "ADDR,Start address for non-cacheable region 1"
|
|
line.long 0xC "NCR1END,FLASH Cache Noncacheable Region 1 End"
|
|
hexmask.long.tbyte 0xC 4.--26. 1. "ADDR,End address for non-cacheable region 1"
|
|
group.long 0x40++0x1F
|
|
line.long 0x0 "DMON0,Data Cache Total Accesses"
|
|
hexmask.long 0x0 0.--31. 1. "DACCESS_COUNT,Total accesses to data cache. All performance metrics should be relative to the number of accesses performed."
|
|
line.long 0x4 "DMON1,Data Cache Tag Lookups"
|
|
hexmask.long 0x4 0.--31. 1. "DLOOKUP_COUNT,Total tag lookups from data cache."
|
|
line.long 0x8 "DMON2,Data Cache Hits"
|
|
hexmask.long 0x8 0.--31. 1. "DHIT_COUNT,Cache hits from lookup operations."
|
|
line.long 0xC "DMON3,Data Cache Line Hits"
|
|
hexmask.long 0xC 0.--31. 1. "DLINE_COUNT,Cache hits from line cache"
|
|
line.long 0x10 "IMON0,Instruction Cache Total Accesses"
|
|
hexmask.long 0x10 0.--31. 1. "IACCESS_COUNT,Total accesses to Instruction cache"
|
|
line.long 0x14 "IMON1,Instruction Cache Tag Lookups"
|
|
hexmask.long 0x14 0.--31. 1. "ILOOKUP_COUNT,Total tag lookups from Instruction cache"
|
|
line.long 0x18 "IMON2,Instruction Cache Hits"
|
|
hexmask.long 0x18 0.--31. 1. "IHIT_COUNT,Cache hits from lookup operations"
|
|
line.long 0x1C "IMON3,Instruction Cache Line Hits"
|
|
hexmask.long 0x1C 0.--31. 1. "ILINE_COUNT,Cache hits from line cache"
|
|
sif (cpuis("AMA3B2KK"))
|
|
group.long 0x100++0xF
|
|
line.long 0x0 "FLASH0CFG,FLASH 0 Control"
|
|
bitfld.long 0x0 12.--13. "LPMMODE0,Controls FLASH low power modes (control of LPM pin)." "0: High power mode (LPM not used).,1: Fast Standby mode. LPM deasserted for read..,2: Low Power mode. LPM always asserted for reads.,?"
|
|
hexmask.long.byte 0x0 8.--11. 1. "LPMRDWAIT0,Sets FLASH wait states when in LPM Mode 2 (RD_WAIT in LPM mode 2 only)"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "SEDELAY0,Sets SE delay (FLASH address setup). A value of 5 is recommended." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--3. 1. "RDWAIT0,Sets read wait states for normal (fast) operation. A value of 1 is recommended."
|
|
line.long 0x4 "FLASH1CFG,FLASH 1 Control"
|
|
bitfld.long 0x4 12.--13. "LPMMODE1,Controls FLASH low power modes (control of LPM pin)." "0: High power mode (LPM not used).,1: Fast Standby mode. LPM deasserted for read..,2: Low Power mode. LPM always asserted for reads.,?"
|
|
hexmask.long.byte 0x4 8.--11. 1. "LPMRDWAIT1,Sets FLASH wait states when in LPM Mode 2 (RD_WAIT in LPM mode 2 only)"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "SEDELAY1,Sets SE delay (FLASH address setup). A value of 5 is recommended." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 0.--3. 1. "RDWAIT1,Sets read wait states for normal (fast) operation. A value of 1 is recommended."
|
|
line.long 0x8 "FLASH2CFG,FLASH 2 Control"
|
|
bitfld.long 0x8 12.--13. "LPMMODE2,Controls FLASH low power modes (control of LPM pin)." "0: High power mode (LPM not used).,1: Fast Standby mode. LPM deasserted for read..,2: Low Power mode. LPM always asserted for reads.,?"
|
|
hexmask.long.byte 0x8 8.--11. 1. "LPMRDWAIT2,Sets FLASH wait states when in LPM Mode 2 (RD_WAIT in LPM mode 2 only)"
|
|
newline
|
|
bitfld.long 0x8 4.--6. "SEDELAY2,Sets SE delay (FLASH address setup). A value of 5 is recommended." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x8 0.--3. 1. "RDWAIT2,Sets read wait states for normal (fast) operation. A value of 1 is recommended."
|
|
line.long 0xC "FLASH3CFG,FLASH 3 Control"
|
|
bitfld.long 0xC 12.--13. "LPMMODE3,Controls FLASH low power modes (control of LPM pin)." "0: High power mode (LPM not used).,1: Fast Standby mode. LPM deasserted for read..,2: Low Power mode. LPM always asserted for reads.,?"
|
|
hexmask.long.byte 0xC 8.--11. 1. "LPMRDWAIT3,Sets FLASH wait states when in LPM Mode 2 (RD_WAIT in LPM mode 2 only)"
|
|
newline
|
|
bitfld.long 0xC 4.--6. "SEDELAY3,Sets SE delay (FLASH address setup). A value of 5 is recommended." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 0.--3. 1. "RDWAIT3,Sets read wait states for normal (fast) operation. A value of 1 is recommended."
|
|
endif
|
|
tree.end
|
|
tree "CLKGEN (Clock Generator)"
|
|
base ad:0x40004000
|
|
group.long 0x0++0x23
|
|
line.long 0x0 "CALXT,This is the XT Oscillator Calibration value. This value allows any derived XT clocks to be calibrated. This means that the original 32KHz version of XT will not be changed. but a 16KHz version (divided down version) can be modified. This register.."
|
|
hexmask.long.word 0x0 0.--10. 1. "CALXT,XT Oscillator calibration value. This register will enable the hardware to increase or decrease the number of cycles in a 16KHz clock derived from the original 32KHz version. The most significant bit is the sign. A '1' is a reduction and a '0' is.."
|
|
line.long 0x4 "CALRC,This is the LFRC Calibration value. Similar to the XT calibration. it allows the derived LFRC clock to be calibrated. The original 1024Hz clock source will not change. but a 512Hz version (divided down version) can be modified. This register will.."
|
|
hexmask.long.tbyte 0x4 0.--17. 1. "CALRC,LFRC Oscillator calibration value. This register will enable the hardware to increase or decrease the number of cycles in a 512 Hz clock derived from the original 1024 version. The most significant bit is the sign. A '1' is a reduction and a '0'.."
|
|
line.long 0x8 "ACALCTR,This register can be used for 2 purposes. The first is to calibrate the LFRC clock using the XT clock source. The second is to measure an internal clock signal relative to the external clock. In that case. the ACALCTR will show the multiple of.."
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "ACALCTR,Autocalibration Counter result. Bits 17 down to 0 of this is feed directly to the CALRC register if ACAL register in OCTRL register is set to 1024SEC or 512SEC."
|
|
line.long 0xC "OCTRL,This register includes controls for autocalibration in addition to the RTC oscillator controls."
|
|
bitfld.long 0xC 8.--10. "ACAL,Autocalibration control. This selects the source to be used in the autocalibration flow. This flow can also be used to measure an internal clock against an external clock source with the external clock normally used as the reference." "0: Disable Autocalibration,?,2: Autocalibrate every 1024 seconds. Once..,3: Autocalibrate every 512 seconds. Once..,?,?,6: Frequency measurement using XT. The XT clock is..,7: Frequency measurement using external clock."
|
|
newline
|
|
bitfld.long 0xC 7. "OSEL,Selects the RTC oscillator (1 => LFRC 0 => XT)" "0: XT),1: LFRC"
|
|
newline
|
|
bitfld.long 0xC 6. "FOS,Oscillator switch on failure function. If this is set then LFRC clock source will switch from XT to RC." "0: Disable the oscillator switch on failure function.,1: Enable the oscillator switch on failure function."
|
|
newline
|
|
bitfld.long 0xC 1. "STOPRC,Stop the LFRC Oscillator to the RTC" "0: Enable the LFRC Oscillator to drive the RTC,1: Stop the LFRC Oscillator when driving the RTC"
|
|
newline
|
|
bitfld.long 0xC 0. "STOPXT,Stop the XT Oscillator to the RTC" "0: Enable the XT Oscillator to drive the RTC,1: Stop the XT Oscillator when driving the RTC"
|
|
line.long 0x10 "CLKOUT,This register enables the CLKOUT to the GPIOs. and selects the clock source to that."
|
|
bitfld.long 0x10 7. "CKEN,Enable the CLKOUT signal" "0: Disable CLKOUT,1: Enable CLKOUT"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--5. 1. "CKSEL,CLKOUT signal select"
|
|
line.long 0x14 "CLKKEY,This controls the write access to the CCTRL register. This prevents customers from accidentally setting the HFRC clocks to be half of what they are set to."
|
|
hexmask.long 0x14 0.--31. 1. "CLKKEY,Key register value."
|
|
line.long 0x18 "CCTRL,This register controls the main divider for HFRC clock. If this is set. all internal HFRC clock sources are divided by 2."
|
|
bitfld.long 0x18 0. "CORESEL,Core Clock divisor" "0: Core Clock is HFRC,1: Core Clock is HFRC / 2"
|
|
line.long 0x1C "STATUS,This register provides status to the XT oscillator and the source of the RTC."
|
|
bitfld.long 0x1C 1. "OSCF,XT Oscillator is enabled but not oscillating" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "OMODE,Current RTC oscillator (1 => LFRC 0 => XT). After an RTC oscillator change it may take up to 2 seconds for this field to reflect the new oscillator." "0: XT),1: LFRC"
|
|
line.long 0x20 "HFADJ,This register controls the HFRC adjustment. The HFRC clock can change with temperature and process corners. and this register controls the HFRC adjustment logic which reduces the fluctuations to the clock."
|
|
bitfld.long 0x20 21.--23. "HFADJGAIN,Gain control for HFRC adjustment" "0: HF Adjust with Gain of 1,1: HF Adjust with Gain of 0.5,2: HF Adjust with Gain of 0.25,3: HF Adjust with Gain of 0.125,4: HF Adjust with Gain of 0.0625,5: HF Adjust with Gain of 0.03125,?,?"
|
|
newline
|
|
bitfld.long 0x20 20. "HFWARMUP,XT warm-up period for HFRC adjustment" "0: Autoadjust XT warm-up period = 1-2 seconds,1: Autoadjust XT warm-up period = 2-4 seconds"
|
|
newline
|
|
hexmask.long.word 0x20 8.--19. 1. "HFXTADJ,Target HFRC adjustment value."
|
|
newline
|
|
bitfld.long 0x20 1.--3. "HFADJCK,Repeat period for HFRC adjustment" "0: Autoadjust repeat period = 4 seconds,1: Autoadjust repeat period = 16 seconds,2: Autoadjust repeat period = 32 seconds,3: Autoadjust repeat period = 64 seconds,4: Autoadjust repeat period = 128 seconds,5: Autoadjust repeat period = 256 seconds,6: Autoadjust repeat period = 512 seconds,7: Autoadjust repeat period = 1024 seconds"
|
|
newline
|
|
bitfld.long 0x20 0. "HFADJEN,HFRC adjustment control" "0: Disable the HFRC adjustment,1: Enable the HFRC adjustment"
|
|
group.long 0x28++0xF
|
|
line.long 0x0 "CLOCKENSTAT,This register provides the enable status to all the peripheral clocks."
|
|
sif (cpuis("AMA3B1KK")||cpuis("AMAP31KK"))
|
|
hexmask.long 0x0 0.--31. 1. "CLOCKENSTAT,Clock enable status"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA3B2KK"))
|
|
hexmask.long 0x0 0.--31. 1. "CLOCKENSTAT,Clock enable status"
|
|
endif
|
|
line.long 0x4 "CLOCKEN2STAT,This is a continuation of the clock enable status."
|
|
sif (cpuis("AMA3B1KK")||cpuis("AMAP31KK"))
|
|
hexmask.long 0x4 0.--31. 1. "CLOCKEN2STAT,Clock enable status 2"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA3B2KK"))
|
|
hexmask.long 0x4 0.--31. 1. "CLOCKEN2STAT,Clock enable status 2"
|
|
endif
|
|
line.long 0x8 "CLOCKEN3STAT,This is a continuation of the clock enable status."
|
|
hexmask.long 0x8 0.--31. 1. "CLOCKEN3STAT,Clock enable status 3"
|
|
line.long 0xC "FREQCTRL,This register provides the burst control and burst status."
|
|
bitfld.long 0xC 2. "BURSTSTATUS,This represents frequency burst status." "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "BURSTACK,Frequency Burst Request Acknowledge. Frequency burst requested is always acknowledged whether burst is granted or not depending on feature enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "BURSTREQ,Frequency Burst Enable Request" "0: Frequency for ARM core stays at 48MHz,1: Frequency for ARM core is increased to 96MHz"
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "BLEBUCKTONADJ,This is the register control for BLE ton adjustment logic."
|
|
bitfld.long 0x0 27. "ZEROLENDETECTEN,BLEBUCK ZERO LENGTH DETECT ENABLE" "0: Disable Zero Length Detect,1: Enable Zero Length Detect"
|
|
newline
|
|
hexmask.long.byte 0x0 23.--26. 1. "ZEROLENDETECTTRIM,BLEBUCK ZERO LENGTH DETECT TRIM"
|
|
newline
|
|
bitfld.long 0x0 22. "TONADJUSTEN,TON ADJUST ENABLE" "0: Disable Adjust for BLE BUCK TON trim,1: Enable Adjust for BLE BUCK TON trim"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "TONADJUSTPERIOD,TON ADJUST PERIOD" "0: Adjust done for every 1 94KHz period,1: Adjust done for every 1 47KHz period,2: Adjust done for every 1 12KHz period,3: Adjust done for every 1 3KHz period"
|
|
newline
|
|
hexmask.long.word 0x0 10.--19. 1. "TONHIGHTHRESHOLD,TON ADJUST HIGH THRESHOLD. Suggested values are #15(94KHz) #2A(47Khz) #A6(12Khz) #29A(3Khz)"
|
|
newline
|
|
hexmask.long.word 0x0 0.--9. 1. "TONLOWTHRESHOLD,TON ADJUST LOW THRESHOLD. Suggested values are #A(94KHz) #15(47KHz) #53(12Khz) #14D(3Khz)"
|
|
group.long 0x100++0xF
|
|
line.long 0x0 "INTRPTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 2. "OF,XT Oscillator Fail interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ACC,Autocalibration Complete interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ACF,Autocalibration Fail interrupt" "0,1"
|
|
line.long 0x4 "INTRPTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 2. "OF,XT Oscillator Fail interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ACC,Autocalibration Complete interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "ACF,Autocalibration Fail interrupt" "0,1"
|
|
line.long 0x8 "INTRPTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 2. "OF,XT Oscillator Fail interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "ACC,Autocalibration Complete interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "ACF,Autocalibration Fail interrupt" "0,1"
|
|
line.long 0xC "INTRPTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 2. "OF,XT Oscillator Fail interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "ACC,Autocalibration Complete interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "ACF,Autocalibration Fail interrupt" "0,1"
|
|
tree.end
|
|
tree "CTIMER (Counter/Timer)"
|
|
base ad:0x40008000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "TMR0,This register holds the running time or event count for CTIMER 0. This is either for each 16 bit half or for the whole 32 bit count when the pair is linked. If the pair is not linked. they can be running on separate clocks and are completely.."
|
|
hexmask.long.word 0x0 16.--31. 1. "CTTMRB0,Counter/Timer B0."
|
|
hexmask.long.word 0x0 0.--15. 1. "CTTMRA0,Counter/Timer A0."
|
|
line.long 0x4 "CMPRA0,This contains the Compare limits for timer 0 half A."
|
|
hexmask.long.word 0x4 16.--31. 1. "CMPR1A0,Counter/Timer A0 Compare Register 1. Holds the upper limit for timer half A."
|
|
hexmask.long.word 0x4 0.--15. 1. "CMPR0A0,Counter/Timer A0 Compare Register 0. Holds the lower limit for timer half A."
|
|
line.long 0x8 "CMPRB0,This contains the Compare limits for timer 0 B half."
|
|
hexmask.long.word 0x8 16.--31. 1. "CMPR1B0,Counter/Timer B0 Compare Register 1. Holds the upper limit for timer half B."
|
|
hexmask.long.word 0x8 0.--15. 1. "CMPR0B0,Counter/Timer B0 Compare Register 0. Holds the lower limit for timer half B."
|
|
line.long 0xC "CTRL0,This includes the Control bit fields for both halves of timer 0."
|
|
bitfld.long 0xC 31. "CTLINK0,Counter/Timer A0/B0 Link bit." "0: Use A0/B0 timers as two independent 16-bit..,1: Link A0/B0 timers into a single 32-bit timer."
|
|
bitfld.long 0xC 28. "TMRB0POL,Counter/Timer B0 output polarity." "0: The polarity of the TMRPINB0 pin is the same as..,1: The polarity of the TMRPINB0 pin is the inverse.."
|
|
newline
|
|
bitfld.long 0xC 27. "TMRB0CLR,Counter/Timer B0 Clear bit." "0: Allow counter/timer B0 to run,1: Holds counter/timer B0 at 0x0000."
|
|
bitfld.long 0xC 26. "TMRB0IE1,Counter/Timer B0 Interrupt Enable bit for COMPR1." "0: Disable counter/timer B0 from generating an..,1: Enable counter/timer B0 to generate an interrupt.."
|
|
newline
|
|
bitfld.long 0xC 25. "TMRB0IE0,Counter/Timer B0 Interrupt Enable bit for COMPR0." "0: Disable counter/timer B0 from generating an..,1: Enable counter/timer B0 to generate an interrupt.."
|
|
bitfld.long 0xC 22.--24. "TMRB0FN,Counter/Timer B0 Function Select." "0: Single count (output toggles and sticks). Count..,1: Repeated count (periodic 1-clock-cycle-wide..,2: Pulse once (aka one-shot). Count to CMPR0B0..,3: Pulse continuously. Count to CMPR0B0 assert..,4: Single pattern.,5: Repeated pattern.,6: Continuous run (aka Free Run). Count continuously.,7: Alternate PWM"
|
|
newline
|
|
hexmask.long.byte 0xC 17.--21. 1. "TMRB0CLK,Counter/Timer B0 Clock Select."
|
|
bitfld.long 0xC 16. "TMRB0EN,Counter/Timer B0 Enable bit." "0: Counter/Timer B0 Disable.,1: Counter/Timer B0 Enable."
|
|
newline
|
|
bitfld.long 0xC 12. "TMRA0POL,Counter/Timer A0 output polarity." "0: The polarity of the TMRPINA0 pin is the same as..,1: The polarity of the TMRPINA0 pin is the inverse.."
|
|
bitfld.long 0xC 11. "TMRA0CLR,Counter/Timer A0 Clear bit." "0: Allow counter/timer A0 to run,1: Holds counter/timer A0 at 0x0000."
|
|
newline
|
|
bitfld.long 0xC 10. "TMRA0IE1,Counter/Timer A0 Interrupt Enable bit based on COMPR1." "0: Disable counter/timer A0 from generating an..,1: Enable counter/timer A0 to generate an interrupt.."
|
|
bitfld.long 0xC 9. "TMRA0IE0,Counter/Timer A0 Interrupt Enable bit based on COMPR0." "0: Disable counter/timer A0 from generating an..,1: Enable counter/timer A0 to generate an interrupt.."
|
|
newline
|
|
bitfld.long 0xC 6.--8. "TMRA0FN,Counter/Timer A0 Function Select." "0: Single count (output toggles and sticks). Count..,1: Repeated count (periodic 1-clock-cycle-wide..,2: Pulse once (aka one-shot). Count to CMPR0A0..,3: Pulse continuously. Count to CMPR0A0 assert..,4: Single pattern.,5: Repeated pattern.,6: Continuous run (aka Free Run). Count continuously.,7: Alternate PWM"
|
|
hexmask.long.byte 0xC 1.--5. 1. "TMRA0CLK,Counter/Timer A0 Clock Select."
|
|
newline
|
|
bitfld.long 0xC 0. "TMRA0EN,Counter/Timer A0 Enable bit." "0: Counter/Timer A0 Disable.,1: Counter/Timer A0 Enable."
|
|
group.long 0x14++0x1B
|
|
line.long 0x0 "CMPRAUXA0,Enhanced compare limits for timer half A. This is valid if timer 0 is set to function 4 and function 5."
|
|
hexmask.long.word 0x0 16.--31. 1. "CMPR3A0,Counter/Timer A0 Compare Register 3. Holds the upper limit for timer half A."
|
|
hexmask.long.word 0x0 0.--15. 1. "CMPR2A0,Counter/Timer A0 Compare Register 2. Holds the lower limit for timer half A."
|
|
line.long 0x4 "CMPRAUXB0,Enhanced compare limits for timer half B. This is valid if timer 0 is set to function 4 and function 5."
|
|
hexmask.long.word 0x4 16.--31. 1. "CMPR3B0,Counter/Timer B0 Compare Register 3. Holds the upper limit for timer half B."
|
|
hexmask.long.word 0x4 0.--15. 1. "CMPR2B0,Counter/Timer B0 Compare Register 2. Holds the lower limit for timer half B."
|
|
line.long 0x8 "AUX0,Control bit fields for both halves of timer 0."
|
|
bitfld.long 0x8 30. "TMRB0EN23,Counter/Timer B0 Upper compare enable." "0: Enable enhanced functions.,1: Disable enhanced functions."
|
|
bitfld.long 0x8 29. "TMRB0POL23,Upper output polarity" "0: Upper output normal polarity,1: Upper output inverted polarity."
|
|
newline
|
|
bitfld.long 0x8 28. "TMRB0TINV,Counter/Timer B0 Invert on trigger." "0: Disable invert on trigger,1: Enable invert on trigger"
|
|
bitfld.long 0x8 27. "TMRB0NOSYNC,Source clock synchronization control." "0: Synchronization on source clock,1: No synchronization on source clock"
|
|
newline
|
|
hexmask.long.byte 0x8 23.--26. 1. "TMRB0TRIG,Counter/Timer B0 Trigger Select."
|
|
hexmask.long.byte 0x8 16.--21. 1. "TMRB0LMT,Counter/Timer B0 Pattern Limit Count."
|
|
newline
|
|
bitfld.long 0x8 14. "TMRA0EN23,Counter/Timer A0 Upper compare enable." "0: Enable enhanced functions.,1: Disable enhanced functions."
|
|
bitfld.long 0x8 13. "TMRA0POL23,Counter/Timer A0 Upper output polarity" "0: Upper output normal polarity,1: Upper output inverted polarity."
|
|
newline
|
|
bitfld.long 0x8 12. "TMRA0TINV,Counter/Timer A0 Invert on trigger." "0: Disable invert on trigger,1: Enable invert on trigger"
|
|
bitfld.long 0x8 11. "TMRA0NOSYNC,Source clock synchronization control." "0: Synchronization on source clock,1: No synchronization on source clock"
|
|
newline
|
|
hexmask.long.byte 0x8 7.--10. 1. "TMRA0TRIG,Counter/Timer A0 Trigger Select."
|
|
hexmask.long.byte 0x8 0.--6. 1. "TMRA0LMT,Counter/Timer A0 Pattern Limit Count."
|
|
line.long 0xC "TMR1,This register holds the running time or event count for CTIMER 1. This is either for each 16 bit half or for the whole 32 bit count when the pair is linked. If the pair is not linked. they can be running on separate clocks and are completely.."
|
|
hexmask.long.word 0xC 16.--31. 1. "CTTMRB1,Counter/Timer B1."
|
|
hexmask.long.word 0xC 0.--15. 1. "CTTMRA1,Counter/Timer A1."
|
|
line.long 0x10 "CMPRA1,This contains the Compare limits for timer 1 A half."
|
|
hexmask.long.word 0x10 16.--31. 1. "CMPR1A1,Counter/Timer A1 Compare Register 1."
|
|
hexmask.long.word 0x10 0.--15. 1. "CMPR0A1,Counter/Timer A1 Compare Register 0."
|
|
line.long 0x14 "CMPRB1,This contains the Compare limits for timer 1 B half."
|
|
hexmask.long.word 0x14 16.--31. 1. "CMPR1B1,Counter/Timer B1 Compare Register 1."
|
|
hexmask.long.word 0x14 0.--15. 1. "CMPR0B1,Counter/Timer B1 Compare Register 0."
|
|
line.long 0x18 "CTRL1,This includes the Control bit fields for both halves of timer 1."
|
|
bitfld.long 0x18 31. "CTLINK1,Counter/Timer A1/B1 Link bit." "0: Use A1/B1 timers as two independent 16-bit..,1: Link A1/B1 timers into a single 32-bit timer."
|
|
bitfld.long 0x18 28. "TMRB1POL,Counter/Timer B1 output polarity." "0: The polarity of the TMRPINB1 pin is the same as..,1: The polarity of the TMRPINB1 pin is the inverse.."
|
|
newline
|
|
bitfld.long 0x18 27. "TMRB1CLR,Counter/Timer B1 Clear bit." "0: Allow counter/timer B1 to run,1: Holds counter/timer B1 at 0x0000."
|
|
bitfld.long 0x18 26. "TMRB1IE1,Counter/Timer B1 Interrupt Enable bit for COMPR1." "0: Disable counter/timer B1 from generating an..,1: Enable counter/timer B1 to generate an interrupt.."
|
|
newline
|
|
bitfld.long 0x18 25. "TMRB1IE0,Counter/Timer B1 Interrupt Enable bit for COMPR0." "0: Disable counter/timer B1 from generating an..,1: Enable counter/timer B1 to generate an interrupt.."
|
|
bitfld.long 0x18 22.--24. "TMRB1FN,Counter/Timer B1 Function Select." "0: Single count (output toggles and sticks). Count..,1: Repeated count (periodic 1-clock-cycle-wide..,2: Pulse once (aka one-shot). Count to CMPR0B1..,3: Pulse continuously. Count to CMPR0B1 assert..,4: Single pattern.,5: Repeated pattern.,6: Continuous run (aka Free Run). Count continuously.,7: Alternate PWM"
|
|
newline
|
|
hexmask.long.byte 0x18 17.--21. 1. "TMRB1CLK,Counter/Timer B1 Clock Select."
|
|
bitfld.long 0x18 16. "TMRB1EN,Counter/Timer B1 Enable bit." "0: Counter/Timer B1 Disable.,1: Counter/Timer B1 Enable."
|
|
newline
|
|
bitfld.long 0x18 12. "TMRA1POL,Counter/Timer A1 output polarity." "0: The polarity of the TMRPINA1 pin is the same as..,1: The polarity of the TMRPINA1 pin is the inverse.."
|
|
bitfld.long 0x18 11. "TMRA1CLR,Counter/Timer A1 Clear bit." "0: Allow counter/timer A1 to run,1: Holds counter/timer A1 at 0x0000."
|
|
newline
|
|
bitfld.long 0x18 10. "TMRA1IE1,Counter/Timer A1 Interrupt Enable bit based on COMPR1." "0: Disable counter/timer A1 from generating an..,1: Enable counter/timer A1 to generate an interrupt.."
|
|
bitfld.long 0x18 9. "TMRA1IE0,Counter/Timer A1 Interrupt Enable bit based on COMPR0." "0: Disable counter/timer A1 from generating an..,1: Enable counter/timer A1 to generate an interrupt.."
|
|
newline
|
|
bitfld.long 0x18 6.--8. "TMRA1FN,Counter/Timer A1 Function Select." "0: Single count (output toggles and sticks). Count..,1: Repeated count (periodic 1-clock-cycle-wide..,2: Pulse once (aka one-shot). Count to CMPR0A1..,3: Pulse continuously. Count to CMPR0A1 assert..,4: Single pattern.,5: Repeated pattern.,6: Continuous run (aka Free Run). Count continuously.,7: Alternate PWM"
|
|
hexmask.long.byte 0x18 1.--5. 1. "TMRA1CLK,Counter/Timer A1 Clock Select."
|
|
newline
|
|
bitfld.long 0x18 0. "TMRA1EN,Counter/Timer A1 Enable bit." "0: Counter/Timer A1 Disable.,1: Counter/Timer A1 Enable."
|
|
group.long 0x34++0x1B
|
|
line.long 0x0 "CMPRAUXA1,Enhanced compare limits for timer half A. This is valid if timer 1 is set to function 4 and function 5."
|
|
hexmask.long.word 0x0 16.--31. 1. "CMPR3A1,Counter/Timer A1 Compare Register 3. Holds the upper limit for timer half A."
|
|
hexmask.long.word 0x0 0.--15. 1. "CMPR2A1,Counter/Timer A1 Compare Register 2. Holds the lower limit for timer half A."
|
|
line.long 0x4 "CMPRAUXB1,Enhanced compare limits for timer half B. This is valid if timer 1 is set to function 4 and function 5."
|
|
hexmask.long.word 0x4 16.--31. 1. "CMPR3B1,Counter/Timer B1 Compare Register 3. Holds the upper limit for timer half B."
|
|
hexmask.long.word 0x4 0.--15. 1. "CMPR2B1,Counter/Timer B1 Compare Register 2. Holds the lower limit for timer half B."
|
|
line.long 0x8 "AUX1,Control bit fields for both halves of timer 0."
|
|
bitfld.long 0x8 30. "TMRB1EN23,Counter/Timer B1 Upper compare enable." "0: Enable enhanced functions.,1: Disable enhanced functions."
|
|
bitfld.long 0x8 29. "TMRB1POL23,Upper output polarity" "0: Upper output normal polarity,1: Upper output inverted polarity."
|
|
newline
|
|
bitfld.long 0x8 28. "TMRB1TINV,Counter/Timer B1 Invert on trigger." "0: Disable invert on trigger,1: Enable invert on trigger"
|
|
bitfld.long 0x8 27. "TMRB1NOSYNC,Source clock synchronization control." "0: Synchronization on source clock,1: No synchronization on source clock"
|
|
newline
|
|
hexmask.long.byte 0x8 23.--26. 1. "TMRB1TRIG,Counter/Timer B1 Trigger Select."
|
|
hexmask.long.byte 0x8 16.--21. 1. "TMRB1LMT,Counter/Timer B1 Pattern Limit Count."
|
|
newline
|
|
bitfld.long 0x8 14. "TMRA1EN23,Counter/Timer A1 Upper compare enable." "0: Enable enhanced functions.,1: Disable enhanced functions."
|
|
bitfld.long 0x8 13. "TMRA1POL23,Counter/Timer A1 Upper output polarity" "0: Upper output normal polarity,1: Upper output inverted polarity."
|
|
newline
|
|
bitfld.long 0x8 12. "TMRA1TINV,Counter/Timer A1 Invert on trigger." "0: Disable invert on trigger,1: Enable invert on trigger"
|
|
bitfld.long 0x8 11. "TMRA1NOSYNC,Source clock synchronization control." "0: Synchronization on source clock,1: No synchronization on source clock"
|
|
newline
|
|
hexmask.long.byte 0x8 7.--10. 1. "TMRA1TRIG,Counter/Timer A1 Trigger Select."
|
|
hexmask.long.byte 0x8 0.--6. 1. "TMRA1LMT,Counter/Timer A1 Pattern Limit Count."
|
|
line.long 0xC "TMR2,This register holds the running time or event count for CTIMER 2. This is either for each 16 bit half or for the whole 32 bit count when the pair is linked. If the pair is not linked. they can be running on separate clocks and are completely.."
|
|
hexmask.long.word 0xC 16.--31. 1. "CTTMRB2,Counter/Timer B2."
|
|
hexmask.long.word 0xC 0.--15. 1. "CTTMRA2,Counter/Timer A2."
|
|
line.long 0x10 "CMPRA2,This register holds the compare limits for timer 2 A half."
|
|
hexmask.long.word 0x10 16.--31. 1. "CMPR1A2,Counter/Timer A2 Compare Register 1."
|
|
hexmask.long.word 0x10 0.--15. 1. "CMPR0A2,Counter/Timer A2 Compare Register 0."
|
|
line.long 0x14 "CMPRB2,This register holds the compare limits for timer 2 B half."
|
|
hexmask.long.word 0x14 16.--31. 1. "CMPR1B2,Counter/Timer B2 Compare Register 1."
|
|
hexmask.long.word 0x14 0.--15. 1. "CMPR0B2,Counter/Timer B2 Compare Register 0."
|
|
line.long 0x18 "CTRL2,This register holds the control bit fields for both halves of timer 2."
|
|
bitfld.long 0x18 31. "CTLINK2,Counter/Timer A2/B2 Link bit." "0: Use A2/B2 timers as two independent 16-bit..,1: Link A2/B2 timers into a single 32-bit timer."
|
|
bitfld.long 0x18 28. "TMRB2POL,Counter/Timer B2 output polarity." "0: The polarity of the TMRPINB2 pin is the same as..,1: The polarity of the TMRPINB2 pin is the inverse.."
|
|
newline
|
|
bitfld.long 0x18 27. "TMRB2CLR,Counter/Timer B2 Clear bit." "0: Allow counter/timer B2 to run,1: Holds counter/timer B2 at 0x0000."
|
|
bitfld.long 0x18 26. "TMRB2IE1,Counter/Timer B2 Interrupt Enable bit for COMPR1." "0: Disable counter/timer B2 from generating an..,1: Enable counter/timer B2 to generate an interrupt.."
|
|
newline
|
|
bitfld.long 0x18 25. "TMRB2IE0,Counter/Timer B2 Interrupt Enable bit for COMPR0." "0: Disable counter/timer B2 from generating an..,1: Enable counter/timer B2 to generate an interrupt.."
|
|
bitfld.long 0x18 22.--24. "TMRB2FN,Counter/Timer B2 Function Select." "0: Single count (output toggles and sticks). Count..,1: Repeated count (periodic 1-clock-cycle-wide..,2: Pulse once (aka one-shot). Count to CMPR0B2..,3: Pulse continuously. Count to CMPR0B2 assert..,4: Single pattern.,5: Repeated pattern.,6: Continuous run (aka Free Run). Count continuously.,7: Alternate PWM"
|
|
newline
|
|
hexmask.long.byte 0x18 17.--21. 1. "TMRB2CLK,Counter/Timer B2 Clock Select."
|
|
bitfld.long 0x18 16. "TMRB2EN,Counter/Timer B2 Enable bit." "0: Counter/Timer B2 Disable.,1: Counter/Timer B2 Enable."
|
|
newline
|
|
bitfld.long 0x18 12. "TMRA2POL,Counter/Timer A2 output polarity." "0: The polarity of the TMRPINA2 pin is the same as..,1: The polarity of the TMRPINA2 pin is the inverse.."
|
|
bitfld.long 0x18 11. "TMRA2CLR,Counter/Timer A2 Clear bit." "0: Allow counter/timer A2 to run,1: Holds counter/timer A2 at 0x0000."
|
|
newline
|
|
bitfld.long 0x18 10. "TMRA2IE1,Counter/Timer A2 Interrupt Enable bit based on COMPR1." "0: Disable counter/timer A2 from generating an..,1: Enable counter/timer A2 to generate an interrupt.."
|
|
bitfld.long 0x18 9. "TMRA2IE0,Counter/Timer A2 Interrupt Enable bit based on COMPR0." "0: Disable counter/timer A2 from generating an..,1: Enable counter/timer A2 to generate an interrupt.."
|
|
newline
|
|
bitfld.long 0x18 6.--8. "TMRA2FN,Counter/Timer A2 Function Select." "0: Single count (output toggles and sticks). Count..,1: Repeated count (periodic 1-clock-cycle-wide..,2: Pulse once (aka one-shot). Count to CMPR0A2..,3: Pulse continuously. Count to CMPR0A2 assert..,4: Single pattern.,5: Repeated pattern.,6: Continuous run (aka Free Run). Count continuously.,7: Alternate PWM"
|
|
hexmask.long.byte 0x18 1.--5. 1. "TMRA2CLK,Counter/Timer A2 Clock Select."
|
|
newline
|
|
bitfld.long 0x18 0. "TMRA2EN,Counter/Timer A2 Enable bit." "0: Counter/Timer A2 Disable.,1: Counter/Timer A2 Enable."
|
|
group.long 0x54++0x1B
|
|
line.long 0x0 "CMPRAUXA2,Enhanced compare limits for timer half A."
|
|
hexmask.long.word 0x0 16.--31. 1. "CMPR3A2,Counter/Timer A2 Compare Register 3. Holds the upper limit for timer half A."
|
|
hexmask.long.word 0x0 0.--15. 1. "CMPR2A2,Counter/Timer A2 Compare Register 2. Holds the lower limit for timer half A."
|
|
line.long 0x4 "CMPRAUXB2,Enhanced compare limits for timer half B."
|
|
hexmask.long.word 0x4 16.--31. 1. "CMPR3B2,Counter/Timer B2 Compare Register 3. Holds the upper limit for timer half B."
|
|
hexmask.long.word 0x4 0.--15. 1. "CMPR2B2,Counter/Timer B2 Compare Register 2. Holds the lower limit for timer half B."
|
|
line.long 0x8 "AUX2,Control bit fields for both halves of timer 0."
|
|
bitfld.long 0x8 30. "TMRB2EN23,Counter/Timer B2 Upper compare enable." "0: Enable enhanced functions.,1: Disable enhanced functions."
|
|
bitfld.long 0x8 29. "TMRB2POL23,Upper output polarity" "0: Upper output normal polarity,1: Upper output inverted polarity."
|
|
newline
|
|
bitfld.long 0x8 28. "TMRB2TINV,Counter/Timer B2 Invert on trigger." "0: Disable invert on trigger,1: Enable invert on trigger"
|
|
bitfld.long 0x8 27. "TMRB2NOSYNC,Source clock synchronization control." "0: Synchronization on source clock,1: No synchronization on source clock"
|
|
newline
|
|
hexmask.long.byte 0x8 23.--26. 1. "TMRB2TRIG,Counter/Timer B2 Trigger Select."
|
|
hexmask.long.byte 0x8 16.--21. 1. "TMRB2LMT,Counter/Timer B2 Pattern Limit Count."
|
|
newline
|
|
bitfld.long 0x8 14. "TMRA2EN23,Counter/Timer A2 Upper compare enable." "0: Enable enhanced functions.,1: Disable enhanced functions."
|
|
bitfld.long 0x8 13. "TMRA2POL23,Counter/Timer A2 Upper output polarity" "0: Upper output normal polarity,1: Upper output inverted polarity."
|
|
newline
|
|
bitfld.long 0x8 12. "TMRA2TINV,Counter/Timer A2 Invert on trigger." "0: Disable invert on trigger,1: Enable invert on trigger"
|
|
bitfld.long 0x8 11. "TMRA2NOSYNC,Source clock synchronization control." "0: Synchronization on source clock,1: No synchronization on source clock"
|
|
newline
|
|
hexmask.long.byte 0x8 7.--10. 1. "TMRA2TRIG,Counter/Timer A2 Trigger Select."
|
|
hexmask.long.byte 0x8 0.--6. 1. "TMRA2LMT,Counter/Timer A2 Pattern Limit Count."
|
|
line.long 0xC "TMR3,Counter/Timer 3"
|
|
hexmask.long.word 0xC 16.--31. 1. "CTTMRB3,Counter/Timer B3."
|
|
hexmask.long.word 0xC 0.--15. 1. "CTTMRA3,Counter/Timer A3."
|
|
line.long 0x10 "CMPRA3,This register holds the compare limits for timer half A."
|
|
hexmask.long.word 0x10 16.--31. 1. "CMPR1A3,Counter/Timer A3 Compare Register 1."
|
|
hexmask.long.word 0x10 0.--15. 1. "CMPR0A3,Counter/Timer A3 Compare Register 0."
|
|
line.long 0x14 "CMPRB3,This register holds the compare limits for timer half B."
|
|
hexmask.long.word 0x14 16.--31. 1. "CMPR1B3,Counter/Timer B3 Compare Register 1."
|
|
hexmask.long.word 0x14 0.--15. 1. "CMPR0B3,Counter/Timer B3 Compare Register 0."
|
|
line.long 0x18 "CTRL3,This register holds the control bit fields for both halves of timer 3."
|
|
bitfld.long 0x18 31. "CTLINK3,Counter/Timer A3/B3 Link bit." "0: Use A3/B3 timers as two independent 16-bit..,1: Link A3/B3 timers into a single 32-bit timer."
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bitfld.long 0x18 28. "TMRB3POL,Counter/Timer B3 output polarity." "0: The polarity of the TMRPINB3 pin is the same as..,1: The polarity of the TMRPINB3 pin is the inverse.."
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newline
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bitfld.long 0x18 27. "TMRB3CLR,Counter/Timer B3 Clear bit." "0: Allow counter/timer B3 to run,1: Holds counter/timer B3 at 0x0000."
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bitfld.long 0x18 26. "TMRB3IE1,Counter/Timer B3 Interrupt Enable bit for COMPR1." "0: Disable counter/timer B3 from generating an..,1: Enable counter/timer B3 to generate an interrupt.."
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newline
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bitfld.long 0x18 25. "TMRB3IE0,Counter/Timer B3 Interrupt Enable bit for COMPR0." "0: Disable counter/timer B3 from generating an..,1: Enable counter/timer B3 to generate an interrupt.."
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bitfld.long 0x18 22.--24. "TMRB3FN,Counter/Timer B3 Function Select." "0: Single count (output toggles and sticks). Count..,1: Repeated count (periodic 1-clock-cycle-wide..,2: Pulse once (aka one-shot). Count to CMPR0B3..,3: Pulse continuously. Count to CMPR0B3 assert..,4: Single pattern.,5: Repeated pattern.,6: Continuous run (aka Free Run). Count continuously.,7: Alternate PWM"
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newline
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hexmask.long.byte 0x18 17.--21. 1. "TMRB3CLK,Counter/Timer B3 Clock Select."
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bitfld.long 0x18 16. "TMRB3EN,Counter/Timer B3 Enable bit." "0: Counter/Timer B3 Disable.,1: Counter/Timer B3 Enable."
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newline
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bitfld.long 0x18 15. "ADCEN,Special Timer A3 enable for ADC function." "0,1"
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bitfld.long 0x18 12. "TMRA3POL,Counter/Timer A3 output polarity." "0: The polarity of the TMRPINA3 pin is the same as..,1: The polarity of the TMRPINA3 pin is the inverse.."
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newline
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bitfld.long 0x18 11. "TMRA3CLR,Counter/Timer A3 Clear bit." "0: Allow counter/timer A3 to run,1: Holds counter/timer A3 at 0x0000."
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bitfld.long 0x18 10. "TMRA3IE1,Counter/Timer A3 Interrupt Enable bit based on COMPR1." "0: Disable counter/timer A3 from generating an..,1: Enable counter/timer A3 to generate an interrupt.."
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newline
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bitfld.long 0x18 9. "TMRA3IE0,Counter/Timer A3 Interrupt Enable bit based on COMPR0." "0: Disable counter/timer A3 from generating an..,1: Enable counter/timer A3 to generate an interrupt.."
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bitfld.long 0x18 6.--8. "TMRA3FN,Counter/Timer A3 Function Select." "0: Single count (output toggles and sticks). Count..,1: Repeated count (periodic 1-clock-cycle-wide..,2: Pulse once (aka one-shot). Count to CMPR0A3..,3: Pulse continuously. Count to CMPR0A3 assert..,4: Single pattern.,5: Repeated pattern.,6: Continuous run (aka Free Run). Count continuously.,7: Alternate PWM"
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newline
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hexmask.long.byte 0x18 1.--5. 1. "TMRA3CLK,Counter/Timer A3 Clock Select."
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bitfld.long 0x18 0. "TMRA3EN,Counter/Timer A3 Enable bit." "0: Counter/Timer A3 Disable.,1: Counter/Timer A3 Enable."
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group.long 0x74++0x1B
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line.long 0x0 "CMPRAUXA3,Enhanced compare limits for timer half A."
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hexmask.long.word 0x0 16.--31. 1. "CMPR3A3,Counter/Timer A3 Compare Register 3. Holds the upper limit for timer half A."
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hexmask.long.word 0x0 0.--15. 1. "CMPR2A3,Counter/Timer A3 Compare Register 2. Holds the lower limit for timer half A."
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line.long 0x4 "CMPRAUXB3,Enhanced compare limits for timer half B."
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hexmask.long.word 0x4 16.--31. 1. "CMPR3B3,Counter/Timer B3 Compare Register 3. Holds the upper limit for timer half B."
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hexmask.long.word 0x4 0.--15. 1. "CMPR2B3,Counter/Timer B3 Compare Register 2. Holds the lower limit for timer half B."
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line.long 0x8 "AUX3,Control bit fields for both halves of timer 0."
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bitfld.long 0x8 30. "TMRB3EN23,Counter/Timer B3 Upper compare enable." "0: Enable enhanced functions.,1: Disable enhanced functions."
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bitfld.long 0x8 29. "TMRB3POL23,Upper output polarity" "0: Upper output normal polarity,1: Upper output inverted polarity."
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newline
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bitfld.long 0x8 28. "TMRB3TINV,Counter/Timer B3 Invert on trigger." "0: Disable invert on trigger,1: Enable invert on trigger"
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bitfld.long 0x8 27. "TMRB3NOSYNC,Source clock synchronization control." "0: Synchronization on source clock,1: No synchronization on source clock"
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newline
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hexmask.long.byte 0x8 23.--26. 1. "TMRB3TRIG,Counter/Timer B3 Trigger Select."
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hexmask.long.byte 0x8 16.--21. 1. "TMRB3LMT,Counter/Timer B3 Pattern Limit Count."
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newline
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bitfld.long 0x8 14. "TMRA3EN23,Counter/Timer A3 Upper compare enable." "0: Enable enhanced functions.,1: Disable enhanced functions."
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bitfld.long 0x8 13. "TMRA3POL23,Counter/Timer A3 Upper output polarity" "0: Upper output normal polarity,1: Upper output inverted polarity."
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newline
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bitfld.long 0x8 12. "TMRA3TINV,Counter/Timer A3 Invert on trigger." "0: Disable invert on trigger,1: Enable invert on trigger"
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bitfld.long 0x8 11. "TMRA3NOSYNC,Source clock synchronization control." "0: Synchronization on source clock,1: No synchronization on source clock"
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newline
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hexmask.long.byte 0x8 7.--10. 1. "TMRA3TRIG,Counter/Timer A3 Trigger Select."
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hexmask.long.byte 0x8 0.--6. 1. "TMRA3LMT,Counter/Timer A3 Pattern Limit Count."
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line.long 0xC "TMR4,This register holds the running time or event count. either for each 16 bit half or for the whole 32 bit count when the pair is linked."
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hexmask.long.word 0xC 16.--31. 1. "CTTMRB4,Counter/Timer B4."
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hexmask.long.word 0xC 0.--15. 1. "CTTMRA4,Counter/Timer A4."
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line.long 0x10 "CMPRA4,Compare limits for timer half A."
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hexmask.long.word 0x10 16.--31. 1. "CMPR1A4,Counter/Timer A4 Compare Register 1. Holds the upper limit for timer half A."
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hexmask.long.word 0x10 0.--15. 1. "CMPR0A4,Counter/Timer A4 Compare Register 0. Holds the lower limit for timer half A."
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line.long 0x14 "CMPRB4,Compare limits for timer half B."
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hexmask.long.word 0x14 16.--31. 1. "CMPR1B4,Counter/Timer B4 Compare Register 1. Holds the upper limit for timer half B."
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hexmask.long.word 0x14 0.--15. 1. "CMPR0B4,Counter/Timer B4 Compare Register 0. Holds the lower limit for timer half B."
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line.long 0x18 "CTRL4,Control bit fields for both halves of timer 4."
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bitfld.long 0x18 31. "CTLINK4,Counter/Timer A4/B4 Link bit." "0: Use A4/B4 timers as two independent 16-bit..,1: Link A4/B4 timers into a single 32-bit timer."
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bitfld.long 0x18 28. "TMRB4POL,Counter/Timer B4 output polarity." "0: The polarity of the TMRPINB4 pin is the same as..,1: The polarity of the TMRPINB4 pin is the inverse.."
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newline
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bitfld.long 0x18 27. "TMRB4CLR,Counter/Timer B4 Clear bit." "0: Allow counter/timer B4 to run,1: Holds counter/timer B4 at 0x0000."
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bitfld.long 0x18 26. "TMRB4IE1,Counter/Timer B4 Interrupt Enable bit for COMPR1." "0: Disable counter/timer B4 from generating an..,1: Enable counter/timer B4 to generate an interrupt.."
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newline
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bitfld.long 0x18 25. "TMRB4IE0,Counter/Timer B4 Interrupt Enable bit for COMPR0." "0: Disable counter/timer B4 from generating an..,1: Enable counter/timer B4 to generate an interrupt.."
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bitfld.long 0x18 22.--24. "TMRB4FN,Counter/Timer B4 Function Select." "0: Single count (output toggles and sticks). Count..,1: Repeated count (periodic 1-clock-cycle-wide..,2: Pulse once (aka one-shot). Count to CMPR0B4..,3: Pulse continuously. Count to CMPR0B4 assert..,4: Single pattern.,5: Repeated pattern.,6: Continuous run (aka Free Run). Count continuously.,7: Alternate PWM"
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newline
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hexmask.long.byte 0x18 17.--21. 1. "TMRB4CLK,Counter/Timer B4 Clock Select."
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bitfld.long 0x18 16. "TMRB4EN,Counter/Timer B4 Enable bit." "0: Counter/Timer B4 Disable.,1: Counter/Timer B4 Enable."
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newline
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bitfld.long 0x18 12. "TMRA4POL,Counter/Timer A4 output polarity." "0: The polarity of the TMRPINA4 pin is the same as..,1: The polarity of the TMRPINA4 pin is the inverse.."
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bitfld.long 0x18 11. "TMRA4CLR,Counter/Timer A4 Clear bit." "0: Allow counter/timer A4 to run,1: Holds counter/timer A4 at 0x0000."
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newline
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bitfld.long 0x18 10. "TMRA4IE1,Counter/Timer A4 Interrupt Enable bit based on COMPR1." "0: Disable counter/timer A4 from generating an..,1: Enable counter/timer A4 to generate an interrupt.."
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bitfld.long 0x18 9. "TMRA4IE0,Counter/Timer A4 Interrupt Enable bit based on COMPR0." "0: Disable counter/timer A4 from generating an..,1: Enable counter/timer A4 to generate an interrupt.."
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newline
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bitfld.long 0x18 6.--8. "TMRA4FN,Counter/Timer A4 Function Select." "0: Single count (output toggles and sticks). Count..,1: Repeated count (periodic 1-clock-cycle-wide..,2: Pulse once (aka one-shot). Count to CMPR0A4..,3: Pulse continuously. Count to CMPR0A4 assert..,4: Single pattern.,5: Repeated pattern.,6: Continuous run (aka Free Run). Count continuously.,7: Alternate PWM"
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hexmask.long.byte 0x18 1.--5. 1. "TMRA4CLK,Counter/Timer A4 Clock Select."
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newline
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bitfld.long 0x18 0. "TMRA4EN,Counter/Timer A4 Enable bit." "0: Counter/Timer A4 Disable.,1: Counter/Timer A4 Enable."
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group.long 0x94++0x1B
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line.long 0x0 "CMPRAUXA4,Enhanced compare limits for timer half A."
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hexmask.long.word 0x0 16.--31. 1. "CMPR3A4,Counter/Timer A4 Compare Register 3. Holds the upper limit for timer half A."
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hexmask.long.word 0x0 0.--15. 1. "CMPR2A4,Counter/Timer A4 Compare Register 2. Holds the lower limit for timer half A."
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line.long 0x4 "CMPRAUXB4,Enhanced compare limits for timer half B."
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hexmask.long.word 0x4 16.--31. 1. "CMPR3B4,Counter/Timer B4 Compare Register 3. Holds the upper limit for timer half B."
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hexmask.long.word 0x4 0.--15. 1. "CMPR2B4,Counter/Timer B4 Compare Register 2. Holds the lower limit for timer half B."
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line.long 0x8 "AUX4,Control bit fields for both halves of timer 4."
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bitfld.long 0x8 30. "TMRB4EN23,Counter/Timer B4 Upper compare enable." "0: Enable enhanced functions.,1: Disable enhanced functions."
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bitfld.long 0x8 29. "TMRB4POL23,Upper output polarity" "0: Upper output normal polarity,1: Upper output inverted polarity."
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newline
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bitfld.long 0x8 28. "TMRB4TINV,Counter/Timer B4 Invert on trigger." "0: Disable invert on trigger,1: Enable invert on trigger"
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bitfld.long 0x8 27. "TMRB4NOSYNC,Source clock synchronization control." "0: Synchronization on source clock,1: No synchronization on source clock"
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newline
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hexmask.long.byte 0x8 23.--26. 1. "TMRB4TRIG,Counter/Timer B4 Trigger Select."
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hexmask.long.byte 0x8 16.--21. 1. "TMRB4LMT,Counter/Timer B4 Pattern Limit Count."
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newline
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bitfld.long 0x8 14. "TMRA4EN23,Counter/Timer A4 Upper compare enable." "0: Enable enhanced functions.,1: Disable enhanced functions."
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bitfld.long 0x8 13. "TMRA4POL23,Counter/Timer A4 Upper output polarity" "0: Upper output normal polarity,1: Upper output inverted polarity."
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newline
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bitfld.long 0x8 12. "TMRA4TINV,Counter/Timer A4 Invert on trigger." "0: Disable invert on trigger,1: Enable invert on trigger"
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bitfld.long 0x8 11. "TMRA4NOSYNC,Source clock synchronization control." "0: Synchronization on source clock,1: No synchronization on source clock"
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newline
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hexmask.long.byte 0x8 7.--10. 1. "TMRA4TRIG,Counter/Timer A4 Trigger Select."
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hexmask.long.byte 0x8 0.--6. 1. "TMRA4LMT,Counter/Timer A4 Pattern Limit Count."
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line.long 0xC "TMR5,This register holds the running time or event count. either for each 16 bit half or for the whole 32 bit count when the pair is linked."
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hexmask.long.word 0xC 16.--31. 1. "CTTMRB5,Counter/Timer B5."
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hexmask.long.word 0xC 0.--15. 1. "CTTMRA5,Counter/Timer A5."
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line.long 0x10 "CMPRA5,This register holds the compare limits for timer half A."
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hexmask.long.word 0x10 16.--31. 1. "CMPR1A5,Counter/Timer A5 Compare Register 1."
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hexmask.long.word 0x10 0.--15. 1. "CMPR0A5,Counter/Timer A5 Compare Register 0."
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line.long 0x14 "CMPRB5,This register holds the compare limits for timer half B."
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hexmask.long.word 0x14 16.--31. 1. "CMPR1B5,Counter/Timer B5 Compare Register 1."
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hexmask.long.word 0x14 0.--15. 1. "CMPR0B5,Counter/Timer B5 Compare Register 0."
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line.long 0x18 "CTRL5,Control bit fields for both halves of timer 0."
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bitfld.long 0x18 31. "CTLINK5,Counter/Timer A5/B5 Link bit." "0: Use A5/B5 timers as two independent 16-bit..,1: Link A5/B5 timers into a single 32-bit timer."
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bitfld.long 0x18 28. "TMRB5POL,Counter/Timer B5 output polarity." "0: The polarity of the TMRPINB5 pin is the same as..,1: The polarity of the TMRPINB5 pin is the inverse.."
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newline
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bitfld.long 0x18 27. "TMRB5CLR,Counter/Timer B5 Clear bit." "0: Allow counter/timer B5 to run,1: Holds counter/timer B5 at 0x0000."
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bitfld.long 0x18 26. "TMRB5IE1,Counter/Timer B5 Interrupt Enable bit for COMPR1." "0: Disable counter/timer B5 from generating an..,1: Enable counter/timer B5 to generate an interrupt.."
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newline
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bitfld.long 0x18 25. "TMRB5IE0,Counter/Timer B5 Interrupt Enable bit for COMPR0." "0: Disable counter/timer B5 from generating an..,1: Enable counter/timer B5 to generate an interrupt.."
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bitfld.long 0x18 22.--24. "TMRB5FN,Counter/Timer B5 Function Select." "0: Single count (output toggles and sticks). Count..,1: Repeated count (periodic 1-clock-cycle-wide..,2: Pulse once (aka one-shot). Count to CMPR0B5..,3: Pulse continuously. Count to CMPR0B5 assert..,4: Single pattern.,5: Repeated pattern.,6: Continuous run (aka Free Run). Count continuously.,7: Alternate PWM"
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newline
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hexmask.long.byte 0x18 17.--21. 1. "TMRB5CLK,Counter/Timer B5 Clock Select."
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bitfld.long 0x18 16. "TMRB5EN,Counter/Timer B5 Enable bit." "0: Counter/Timer B5 Disable.,1: Counter/Timer B5 Enable."
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newline
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bitfld.long 0x18 12. "TMRA5POL,Counter/Timer A5 output polarity." "0: The polarity of the TMRPINA5 pin is the same as..,1: The polarity of the TMRPINA5 pin is the inverse.."
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bitfld.long 0x18 11. "TMRA5CLR,Counter/Timer A5 Clear bit." "0: Allow counter/timer A5 to run,1: Holds counter/timer A5 at 0x0000."
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newline
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bitfld.long 0x18 10. "TMRA5IE1,Counter/Timer A5 Interrupt Enable bit based on COMPR1." "0: Disable counter/timer A5 from generating an..,1: Enable counter/timer A5 to generate an interrupt.."
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bitfld.long 0x18 9. "TMRA5IE0,Counter/Timer A5 Interrupt Enable bit based on COMPR0." "0: Disable counter/timer A5 from generating an..,1: Enable counter/timer A5 to generate an interrupt.."
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newline
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bitfld.long 0x18 6.--8. "TMRA5FN,Counter/Timer A5 Function Select." "0: Single count (output toggles and sticks). Count..,1: Repeated count (periodic 1-clock-cycle-wide..,2: Pulse once (aka one-shot). Count to CMPR0A5..,3: Pulse continuously. Count to CMPR0A5 assert..,4: Single pattern.,5: Repeated pattern.,6: Continuous run (aka Free Run). Count continuously.,7: Alternate PWM"
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hexmask.long.byte 0x18 1.--5. 1. "TMRA5CLK,Counter/Timer A5 Clock Select."
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newline
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bitfld.long 0x18 0. "TMRA5EN,Counter/Timer A5 Enable bit." "0: Counter/Timer A5 Disable.,1: Counter/Timer A5 Enable."
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group.long 0xB4++0x1B
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line.long 0x0 "CMPRAUXA5,Enhanced compare limits for timer half A."
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hexmask.long.word 0x0 16.--31. 1. "CMPR3A5,Counter/Timer A5 Compare Register 3. Holds the upper limit for timer half A."
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hexmask.long.word 0x0 0.--15. 1. "CMPR2A5,Counter/Timer A5 Compare Register 2. Holds the lower limit for timer half A."
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line.long 0x4 "CMPRAUXB5,Enhanced compare limits for timer half B."
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hexmask.long.word 0x4 16.--31. 1. "CMPR3B5,Counter/Timer B5 Compare Register 3. Holds the upper limit for timer half B."
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hexmask.long.word 0x4 0.--15. 1. "CMPR2B5,Counter/Timer B5 Compare Register 2. Holds the lower limit for timer half B."
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line.long 0x8 "AUX5,Control bit fields for both halves of timer 0."
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bitfld.long 0x8 30. "TMRB5EN23,Counter/Timer B5 Upper compare enable." "0: Enable enhanced functions.,1: Disable enhanced functions."
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bitfld.long 0x8 29. "TMRB5POL23,Upper output polarity" "0: Upper output normal polarity,1: Upper output inverted polarity."
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newline
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bitfld.long 0x8 28. "TMRB5TINV,Counter/Timer B5 Invert on trigger." "0: Disable invert on trigger,1: Enable invert on trigger"
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bitfld.long 0x8 27. "TMRB5NOSYNC,Source clock synchronization control." "0: Synchronization on source clock,1: No synchronization on source clock"
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newline
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hexmask.long.byte 0x8 23.--26. 1. "TMRB5TRIG,Counter/Timer B5 Trigger Select."
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hexmask.long.byte 0x8 16.--21. 1. "TMRB5LMT,Counter/Timer B5 Pattern Limit Count."
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newline
|
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bitfld.long 0x8 14. "TMRA5EN23,Counter/Timer A5 Upper compare enable." "0: Enable enhanced functions.,1: Disable enhanced functions."
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bitfld.long 0x8 13. "TMRA5POL23,Counter/Timer A5 Upper output polarity" "0: Upper output normal polarity,1: Upper output inverted polarity."
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newline
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bitfld.long 0x8 12. "TMRA5TINV,Counter/Timer A5 Invert on trigger." "0: Disable invert on trigger,1: Enable invert on trigger"
|
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bitfld.long 0x8 11. "TMRA5NOSYNC,Source clock synchronization control." "0: Synchronization on source clock,1: No synchronization on source clock"
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newline
|
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hexmask.long.byte 0x8 7.--10. 1. "TMRA5TRIG,Counter/Timer A5 Trigger Select."
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hexmask.long.byte 0x8 0.--6. 1. "TMRA5LMT,Counter/Timer A5 Pattern Limit Count."
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line.long 0xC "TMR6,Counter/Timer 6"
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hexmask.long.word 0xC 16.--31. 1. "CTTMRB6,Counter/Timer B6."
|
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hexmask.long.word 0xC 0.--15. 1. "CTTMRA6,Counter/Timer A6."
|
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line.long 0x10 "CMPRA6,This register holds the compare limits for timer half A."
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|
hexmask.long.word 0x10 16.--31. 1. "CMPR1A6,Counter/Timer A6 Compare Register 1."
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hexmask.long.word 0x10 0.--15. 1. "CMPR0A6,Counter/Timer A6 Compare Register 0."
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line.long 0x14 "CMPRB6,This register holds the compare limits for timer half B."
|
|
hexmask.long.word 0x14 16.--31. 1. "CMPR1B6,Counter/Timer B6 Compare Register 1."
|
|
hexmask.long.word 0x14 0.--15. 1. "CMPR0B6,Counter/Timer B6 Compare Register 0."
|
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line.long 0x18 "CTRL6,This register holds the control bit fields for both halves of timer 6."
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bitfld.long 0x18 31. "CTLINK6,Counter/Timer A6/B6 Link bit." "0: Use A6/B6 timers as two independent 16-bit..,1: Link A6/B6 timers into a single 32-bit timer."
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bitfld.long 0x18 28. "TMRB6POL,Counter/Timer B6 output polarity." "0: The polarity of the TMRPINB6 pin is the same as..,1: The polarity of the TMRPINB6 pin is the inverse.."
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newline
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bitfld.long 0x18 27. "TMRB6CLR,Counter/Timer B6 Clear bit." "0: Allow counter/timer B6 to run,1: Holds counter/timer B6 at 0x0000."
|
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bitfld.long 0x18 26. "TMRB6IE1,Counter/Timer B6 Interrupt Enable bit for COMPR1." "0: Disable counter/timer B6 from generating an..,1: Enable counter/timer B6 to generate an interrupt.."
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newline
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bitfld.long 0x18 25. "TMRB6IE0,Counter/Timer B6 Interrupt Enable bit for COMPR0." "0: Disable counter/timer B6 from generating an..,1: Enable counter/timer B6 to generate an interrupt.."
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bitfld.long 0x18 22.--24. "TMRB6FN,Counter/Timer B6 Function Select." "0: Single count (output toggles and sticks). Count..,1: Repeated count (periodic 1-clock-cycle-wide..,2: Pulse once (aka one-shot). Count to CMPR0B6..,3: Pulse continuously. Count to CMPR0B6 assert..,4: Single pattern.,5: Repeated pattern.,6: Continuous run (aka Free Run). Count continuously.,7: Alternate PWM"
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newline
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hexmask.long.byte 0x18 17.--21. 1. "TMRB6CLK,Counter/Timer B6 Clock Select."
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bitfld.long 0x18 16. "TMRB6EN,Counter/Timer B6 Enable bit." "0: Counter/Timer B6 Disable.,1: Counter/Timer B6 Enable."
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newline
|
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bitfld.long 0x18 12. "TMRA6POL,Counter/Timer A6 output polarity." "0: The polarity of the TMRPINA6 pin is the same as..,1: The polarity of the TMRPINA6 pin is the inverse.."
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bitfld.long 0x18 11. "TMRA6CLR,Counter/Timer A6 Clear bit." "0: Allow counter/timer A6 to run,1: Holds counter/timer A6 at 0x0000."
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newline
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bitfld.long 0x18 10. "TMRA6IE1,Counter/Timer A6 Interrupt Enable bit based on COMPR1." "0: Disable counter/timer A6 from generating an..,1: Enable counter/timer A6 to generate an interrupt.."
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bitfld.long 0x18 9. "TMRA6IE0,Counter/Timer A6 Interrupt Enable bit based on COMPR0." "0: Disable counter/timer A6 from generating an..,1: Enable counter/timer A6 to generate an interrupt.."
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newline
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bitfld.long 0x18 6.--8. "TMRA6FN,Counter/Timer A6 Function Select." "0: Single count (output toggles and sticks). Count..,1: Repeated count (periodic 1-clock-cycle-wide..,2: Pulse once (aka one-shot). Count to CMPR0A6..,3: Pulse continuously. Count to CMPR0A6 assert..,4: Single pattern.,5: Repeated pattern.,6: Continuous run (aka Free Run). Count continuously.,7: Alternate PWM"
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hexmask.long.byte 0x18 1.--5. 1. "TMRA6CLK,Counter/Timer A6 Clock Select."
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newline
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bitfld.long 0x18 0. "TMRA6EN,Counter/Timer A6 Enable bit." "0: Counter/Timer A6 Disable.,1: Counter/Timer A6 Enable."
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group.long 0xD4++0x1B
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line.long 0x0 "CMPRAUXA6,Enhanced compare limits for timer half A."
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hexmask.long.word 0x0 16.--31. 1. "CMPR3A6,Counter/Timer A6 Compare Register 3. Holds the upper limit for timer half A."
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hexmask.long.word 0x0 0.--15. 1. "CMPR2A6,Counter/Timer A6 Compare Register 2. Holds the lower limit for timer half A."
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line.long 0x4 "CMPRAUXB6,Enhanced compare limits for timer half B."
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hexmask.long.word 0x4 16.--31. 1. "CMPR3B6,Counter/Timer B6 Compare Register 3. Holds the upper limit for timer half B."
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hexmask.long.word 0x4 0.--15. 1. "CMPR2B6,Counter/Timer B6 Compare Register 2. Holds the lower limit for timer half B."
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line.long 0x8 "AUX6,Control bit fields for both halves of timer 0."
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bitfld.long 0x8 30. "TMRB6EN23,Counter/Timer B6 Upper compare enable." "0: Enable enhanced functions.,1: Disable enhanced functions."
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bitfld.long 0x8 29. "TMRB6POL23,Upper output polarity" "0: Upper output normal polarity,1: Upper output inverted polarity."
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bitfld.long 0x8 28. "TMRB6TINV,Counter/Timer B6 Invert on trigger." "0: Disable invert on trigger,1: Enable invert on trigger"
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bitfld.long 0x8 27. "TMRB6NOSYNC,Source clock synchronization control." "0: Synchronization on source clock,1: No synchronization on source clock"
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newline
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hexmask.long.byte 0x8 23.--26. 1. "TMRB6TRIG,Counter/Timer B6 Trigger Select."
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hexmask.long.byte 0x8 16.--21. 1. "TMRB6LMT,Counter/Timer B6 Pattern Limit Count."
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newline
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bitfld.long 0x8 14. "TMRA6EN23,Counter/Timer A6 Upper compare enable." "0: Enable enhanced functions.,1: Disable enhanced functions."
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bitfld.long 0x8 13. "TMRA6POL23,Counter/Timer A6 Upper output polarity" "0: Upper output normal polarity,1: Upper output inverted polarity."
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newline
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bitfld.long 0x8 12. "TMRA6TINV,Counter/Timer A6 Invert on trigger." "0: Disable invert on trigger,1: Enable invert on trigger"
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bitfld.long 0x8 11. "TMRA6NOSYNC,Source clock synchronization control." "0: Synchronization on source clock,1: No synchronization on source clock"
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newline
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hexmask.long.byte 0x8 7.--10. 1. "TMRA6TRIG,Counter/Timer A6 Trigger Select."
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hexmask.long.byte 0x8 0.--6. 1. "TMRA6LMT,Counter/Timer A6 Pattern Limit Count."
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line.long 0xC "TMR7,Counter/Timer 7"
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hexmask.long.word 0xC 16.--31. 1. "CTTMRB7,Counter/Timer B7."
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hexmask.long.word 0xC 0.--15. 1. "CTTMRA7,Counter/Timer A7."
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line.long 0x10 "CMPRA7,This register holds the compare limits for timer half A."
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hexmask.long.word 0x10 16.--31. 1. "CMPR1A7,Counter/Timer A7 Compare Register 1."
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hexmask.long.word 0x10 0.--15. 1. "CMPR0A7,Counter/Timer A7 Compare Register 0."
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line.long 0x14 "CMPRB7,This register holds the compare limits for timer half B."
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hexmask.long.word 0x14 16.--31. 1. "CMPR1B7,Counter/Timer B3 Compare Register 1."
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hexmask.long.word 0x14 0.--15. 1. "CMPR0B7,Counter/Timer B3 Compare Register 0."
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line.long 0x18 "CTRL7,This register holds the control bit fields for both halves of timer 7."
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bitfld.long 0x18 31. "CTLINK7,Counter/Timer A7/B7 Link bit." "0: Use A7/B7 timers as two independent 16-bit..,1: Link A7/B7 timers into a single 32-bit timer."
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bitfld.long 0x18 28. "TMRB7POL,Counter/Timer B7 output polarity." "0: The polarity of the TMRPINB7 pin is the same as..,1: The polarity of the TMRPINB7 pin is the inverse.."
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bitfld.long 0x18 27. "TMRB7CLR,Counter/Timer B7 Clear bit." "0: Allow counter/timer B7 to run,1: Holds counter/timer B7 at 0x0000."
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bitfld.long 0x18 26. "TMRB7IE1,Counter/Timer B7 Interrupt Enable bit for COMPR1." "0: Disable counter/timer B7 from generating an..,1: Enable counter/timer B7 to generate an interrupt.."
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bitfld.long 0x18 25. "TMRB7IE0,Counter/Timer B7 Interrupt Enable bit for COMPR0." "0: Disable counter/timer B7 from generating an..,1: Enable counter/timer B7 to generate an interrupt.."
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bitfld.long 0x18 22.--24. "TMRB7FN,Counter/Timer B7 Function Select." "0: Single count (output toggles and sticks). Count..,1: Repeated count (periodic 1-clock-cycle-wide..,2: Pulse once (aka one-shot). Count to CMPR0B7..,3: Pulse continuously. Count to CMPR0B7 assert..,4: Single pattern.,5: Repeated pattern.,6: Continuous run (aka Free Run). Count continuously.,7: Alternate PWM"
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hexmask.long.byte 0x18 17.--21. 1. "TMRB7CLK,Counter/Timer B7 Clock Select."
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bitfld.long 0x18 16. "TMRB7EN,Counter/Timer B7 Enable bit." "0: Counter/Timer B7 Disable.,1: Counter/Timer B7 Enable."
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bitfld.long 0x18 12. "TMRA7POL,Counter/Timer A7 output polarity." "0: The polarity of the TMRPINA7 pin is the same as..,1: The polarity of the TMRPINA7 pin is the inverse.."
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bitfld.long 0x18 11. "TMRA7CLR,Counter/Timer A7 Clear bit." "0: Allow counter/timer A7 to run,1: Holds counter/timer A7 at 0x0000."
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newline
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bitfld.long 0x18 10. "TMRA7IE1,Counter/Timer A7 Interrupt Enable bit based on COMPR1." "0: Disable counter/timer A7 from generating an..,1: Enable counter/timer A7 to generate an interrupt.."
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bitfld.long 0x18 9. "TMRA7IE0,Counter/Timer A7 Interrupt Enable bit based on COMPR0." "0: Disable counter/timer A7 from generating an..,1: Enable counter/timer A7 to generate an interrupt.."
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bitfld.long 0x18 6.--8. "TMRA7FN,Counter/Timer A7 Function Select." "0: Single count (output toggles and sticks). Count..,1: Repeated count (periodic 1-clock-cycle-wide..,2: Pulse once (aka one-shot). Count to CMPR0A7..,3: Pulse continuously. Count to CMPR0A7 assert..,4: Single pattern.,5: Repeated pattern.,6: Continuous run (aka Free Run). Count continuously.,7: Alternate PWM"
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hexmask.long.byte 0x18 1.--5. 1. "TMRA7CLK,Counter/Timer A7 Clock Select."
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newline
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bitfld.long 0x18 0. "TMRA7EN,Counter/Timer A7 Enable bit." "0: Counter/Timer A7 Disable.,1: Counter/Timer A7 Enable."
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group.long 0xF4++0x1B
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line.long 0x0 "CMPRAUXA7,Enhanced compare limits for timer half A."
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hexmask.long.word 0x0 16.--31. 1. "CMPR3A7,Counter/Timer A7 Compare Register 3. Holds the upper limit for timer half A."
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hexmask.long.word 0x0 0.--15. 1. "CMPR2A7,Counter/Timer A7 Compare Register 2. Holds the lower limit for timer half A."
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line.long 0x4 "CMPRAUXB7,Enhanced compare limits for timer half B."
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hexmask.long.word 0x4 16.--31. 1. "CMPR3B7,Counter/Timer B7 Compare Register 3. Holds the upper limit for timer half B."
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hexmask.long.word 0x4 0.--15. 1. "CMPR2B7,Counter/Timer B7 Compare Register 2. Holds the lower limit for timer half B."
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line.long 0x8 "AUX7,Control bit fields for both halves of timer 0."
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bitfld.long 0x8 30. "TMRB7EN23,Counter/Timer B7 Upper compare enable." "0: Enable enhanced functions.,1: Disable enhanced functions."
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bitfld.long 0x8 29. "TMRB7POL23,Upper output polarity" "0: Upper output normal polarity,1: Upper output inverted polarity."
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bitfld.long 0x8 28. "TMRB7TINV,Counter/Timer B7 Invert on trigger." "0: Disable invert on trigger,1: Enable invert on trigger"
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bitfld.long 0x8 27. "TMRB7NOSYNC,Source clock synchronization control." "0: Synchronization on source clock,1: No synchronization on source clock"
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hexmask.long.byte 0x8 23.--26. 1. "TMRB7TRIG,Counter/Timer B7 Trigger Select."
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hexmask.long.byte 0x8 16.--21. 1. "TMRB7LMT,Counter/Timer B7 Pattern Limit Count."
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newline
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bitfld.long 0x8 14. "TMRA7EN23,Counter/Timer A7 Upper compare enable." "0: Enable enhanced functions.,1: Disable enhanced functions."
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bitfld.long 0x8 13. "TMRA7POL23,Counter/Timer A7 Upper output polarity" "0: Upper output normal polarity,1: Upper output inverted polarity."
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newline
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bitfld.long 0x8 12. "TMRA7TINV,Counter/Timer A7 Invert on trigger." "0: Disable invert on trigger,1: Enable invert on trigger"
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bitfld.long 0x8 11. "TMRA7NOSYNC,Source clock synchronization control." "0: Synchronization on source clock,1: No synchronization on source clock"
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newline
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hexmask.long.byte 0x8 7.--10. 1. "TMRA7TRIG,Counter/Timer A7 Trigger Select."
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hexmask.long.byte 0x8 0.--6. 1. "TMRA7LMT,Counter/Timer A7 Pattern Limit Count."
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line.long 0xC "GLOBEN,Alternate enables for all CTIMERs."
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bitfld.long 0xC 15. "ENB7,Alternate enable for B7." "0: Disable CTIMER.,1: Use local enable."
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bitfld.long 0xC 14. "ENA7,Alternate enable for A7" "0: Disable CTIMER.,1: Use local enable."
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bitfld.long 0xC 13. "ENB6,Alternate enable for B6" "0: Disable CTIMER.,1: Use local enable."
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bitfld.long 0xC 12. "ENA6,Alternate enable for A6" "0: Disable CTIMER.,1: Use local enable."
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bitfld.long 0xC 11. "ENB5,Alternate enable for B5" "0: Disable CTIMER.,1: Use local enable."
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bitfld.long 0xC 10. "ENA5,Alternate enable for A5" "0: Disable CTIMER.,1: Use local enable."
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newline
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bitfld.long 0xC 9. "ENB4,Alternate enable for B4" "0: Disable CTIMER.,1: Use local enable."
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bitfld.long 0xC 8. "ENA4,Alternate enable for A4" "0: Disable CTIMER.,1: Use local enable."
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newline
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bitfld.long 0xC 7. "ENB3,Alternate enable for B3." "0: Disable CTIMER.,1: Use local enable."
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bitfld.long 0xC 6. "ENA3,Alternate enable for A3" "0: Disable CTIMER.,1: Use local enable."
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newline
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bitfld.long 0xC 5. "ENB2,Alternate enable for B2" "0: Disable CTIMER.,1: Use local enable."
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bitfld.long 0xC 4. "ENA2,Alternate enable for A2" "0: Disable CTIMER.,1: Use local enable."
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newline
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bitfld.long 0xC 3. "ENB1,Alternate enable for B1" "0: Disable CTIMER.,1: Use local enable."
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bitfld.long 0xC 2. "ENA1,Alternate enable for A1" "0: Disable CTIMER.,1: Use local enable."
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newline
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bitfld.long 0xC 1. "ENB0,Alternate enable for B0" "0: Disable CTIMER.,1: Use local enable."
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bitfld.long 0xC 0. "ENA0,Alternate enable for A0" "0: Disable CTIMER.,1: Use local enable."
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line.long 0x10 "OUTCFG0,Pad output configuration 0."
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bitfld.long 0x10 28.--30. "CFG9,Pad output 9 configuration" "0: Force output to 0,1: Force output to 1.,2: Output is A2OUT2,3: Output is A2OUT.,4: Output is A4OUT.,5: Output is B0OUT.,6: Output is A6OUT2.,7: Output is A7OUT2."
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bitfld.long 0x10 25.--27. "CFG8,Pad output 8 configuration" "0: Force output to 0,1: Force output to 1.,2: Output is A2OUT,3: Output is A3OUT.,4: Output is A4OUT2.,5: Output is B6OUT.,6: Output is A6OUT2.,7: Output is A7OUT2."
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bitfld.long 0x10 22.--24. "CFG7,Pad output 7 configuration" "0: Force output to 0,1: Force output to 1.,2: Output is B1OUT2,3: Output is B1OUT.,4: Output is B5OUT.,5: Output is A7OUT.,6: Output is A6OUT2.,7: Output is A7OUT2."
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bitfld.long 0x10 19.--21. "CFG6,Pad output 6 configuration" "0: Force output to 0,1: Force output to 1.,2: Output is B1OUT,3: Output is A1OUT.,4: Output is B5OUT2.,5: Output is B7OUT.,6: Output is A6OUT2.,7: Output is A7OUT2."
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bitfld.long 0x10 16.--18. "CFG5,Pad output 5 configuration" "0: Force output to 0,1: Force output to 1.,2: Output is A1OUT2,3: Output is A1OUT.,4: Output is A5OUT.,5: Output is A7OUT.,6: Output is A6OUT2.,7: Output is A7OUT2."
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bitfld.long 0x10 12.--14. "CFG4,Pad output 4 configuration" "0: Force output to 0,1: Force output to 1.,2: Output is A1OUT,3: Output is A2OUT2.,4: Output is A5OUT2.,5: Output is B5OUT.,6: Output is A6OUT2.,7: Output is A7OUT2."
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bitfld.long 0x10 9.--11. "CFG3,Pad output 3 configuration" "0: Force output to 0,1: Force output to 1.,2: Output is B0OUT2,3: Output is B0OUT.,4: Output is A1OUT.,5: Output is A6OUT.,6: Output is A6OUT2.,7: Output is A7OUT2."
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bitfld.long 0x10 6.--8. "CFG2,Pad output 2 configuration" "0: Force output to 0,1: Force output to 1.,2: Output is B0OUT,3: Output is B1OUT2.,4: Output is B6OUT2.,5: Output is A7OUT.,6: Output is A6OUT2.,7: Output is A7OUT2."
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bitfld.long 0x10 3.--5. "CFG1,Pad output 1 configuration" "0: Force output to 0,1: Force output to 1.,2: Output is A0OUT2,3: Output is A0OUT.,4: Output is A5OUT.,5: Output is B7OUT2.,6: Output is A6OUT2.,7: Output is A7OUT2."
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bitfld.long 0x10 0.--2. "CFG0,Pad output 0 configuration" "0: Force output to 0,1: Force output to 1.,2: Output is A0OUT,3: Output is B2OUT2.,4: Output is A5OUT2.,5: Output is A6OUT.,6: Output is A6OUT2.,7: Output is A7OUT2."
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line.long 0x14 "OUTCFG1,Pad output configuration 1."
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bitfld.long 0x14 28.--30. "CFG19,Pad output 19 configuration" "0: Force output to 0,1: Force output to 1.,2: Output is B4OUT2,3: Output is A2OUT.,4: Output is B4OUT.,5: Output is B1OUT2.,6: Output is A6OUT2.,7: Output is A7OUT2."
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bitfld.long 0x14 25.--27. "CFG18,Pad output 18 configuration" "0: Force output to 0,1: Force output to 1.,2: Output is B4OUT,3: Output is B0OUT.,4: Output is A0OUT.,5: Output is A3OUT2.,6: Output is A6OUT2.,7: Output is A7OUT2."
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bitfld.long 0x14 22.--24. "CFG17,Pad output 17 configuration" "0: Force output to 0,1: Force output to 1.,2: Output is A4OUT2,3: Output is B7OUT.,4: Output is A4OUT.,5: Output is A1OUT2.,6: Output is A6OUT2.,7: Output is A7OUT2."
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bitfld.long 0x14 19.--21. "CFG16,Pad output 16 configuration" "0: Force output to 0,1: Force output to 1.,2: Output is A4OUT,3: Output is A0OUT.,4: Output is A0OUT2.,5: Output is B3OUT2.,6: Output is A6OUT2.,7: Output is A7OUT2."
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bitfld.long 0x14 16.--18. "CFG15,Pad output 15 configuration" "0: Force output to 0,1: Force output to 1.,2: Output is B3OUT2,3: Output is B3OUT.,4: Output is A7OUT.,5: Output is A4OUT2.,6: Output is A6OUT2.,7: Output is A7OUT2."
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bitfld.long 0x14 12.--14. "CFG14,Pad output 14 configuration" "0: Force output to 0,1: Force output to 1.,2: Output is B3OUT,3: Output is B1OUT.,4: Output is B7OUT2.,5: Output is A7OUT.,6: Output is A6OUT2.,7: Output is A7OUT2."
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bitfld.long 0x14 9.--11. "CFG13,Pad output 13 configuration" "0: Force output to 0,1: Force output to 1.,2: Output is A3OUT2,3: Output is A3OUT.,4: Output is A6OUT.,5: Output is B4OUT2.,6: Output is A6OUT2.,7: Output is A7OUT2."
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bitfld.long 0x14 6.--8. "CFG12,Pad output 12 configuration" "0: Force output to 0,1: Force output to 1.,2: Output is A3OUT,3: Output is B1OUT.,4: Output is B0OUT2.,5: Output is B6OUT2.,6: Output is A6OUT2.,7: Output is A7OUT2."
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bitfld.long 0x14 3.--5. "CFG11,Pad output 11 configuration" "0: Force output to 0,1: Force output to 1.,2: Output is B2OUT2,3: Output is B2OUT.,4: Output is B4OUT.,5: Output is B5OUT2.,6: Output is A6OUT2.,7: Output is A7OUT2."
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bitfld.long 0x14 0.--2. "CFG10,Pad output 10 configuration" "0: Force output to 0,1: Force output to 1.,2: Output is B2OUT,3: Output is B3OUT2.,4: Output is B4OUT2.,5: Output is A6OUT.,6: Output is A6OUT2.,7: Output is A7OUT2."
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line.long 0x18 "OUTCFG2,Pad output configuration 2."
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bitfld.long 0x18 28.--30. "CFG29,Pad output 29 configuration" "0: Force output to 0,1: Force output to 1.,2: Output is B5OUT2,3: Output is A1OUT.,4: Output is A7OUT.,5: Output is A3OUT2.,6: Output is A6OUT2.,7: Output is A7OUT2."
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bitfld.long 0x18 25.--27. "CFG28,Pad output 28 configuration" "0: Force output to 0,1: Force output to 1.,2: Output is A7OUT,3: Output is A3OUT.,4: Output is A5OUT2.,5: Output is B0OUT2.,6: Output is A6OUT2.,7: Output is A7OUT2."
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bitfld.long 0x18 22.--24. "CFG27,Pad output 27 configuration" "0: Force output to 0,1: Force output to 1.,2: Output is B6OUT2,3: Output is A1OUT.,4: Output is B6OUT.,5: Output is B2OUT2.,6: Output is A6OUT2.,7: Output is A7OUT2."
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bitfld.long 0x18 19.--21. "CFG26,Pad output 26 configuration" "0: Force output to 0,1: Force output to 1.,2: Output is B6OUT,3: Output is B2OUT.,4: Output is A5OUT.,5: Output is A1OUT2.,6: Output is A6OUT2.,7: Output is A7OUT2."
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bitfld.long 0x18 16.--18. "CFG25,Pad output 25 configuration" "0: Force output to 0,1: Force output to 1.,2: Output is B4OUT2,3: Output is B2OUT.,4: Output is A6OUT.,5: Output is A2OUT2.,6: Output is A6OUT2.,7: Output is A7OUT2."
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bitfld.long 0x18 12.--14. "CFG24,Pad output 24 configuration" "0: Force output to 0,1: Force output to 1.,2: Output is A6OUT,3: Output is A2OUT.,4: Output is A1OUT.,5: Output is B1OUT2.,6: Output is A6OUT2.,7: Output is A7OUT2."
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bitfld.long 0x18 9.--11. "CFG23,Pad output 23 configuration" "0: Force output to 0,1: Force output to 1.,2: Output is B5OUT2,3: Output is A7OUT.,4: Output is A5OUT.,5: Output is B0OUT2.,6: Output is A6OUT2.,7: Output is A7OUT2."
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bitfld.long 0x18 6.--8. "CFG22,Pad output 22 configuration" "0: Force output to 0,1: Force output to 1.,2: Output is B5OUT,3: Output is A6OUT.,4: Output is A1OUT.,5: Output is A2OUT2.,6: Output is A6OUT2.,7: Output is A7OUT2."
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bitfld.long 0x18 3.--5. "CFG21,Pad output 21 configuration" "0: Force output to 0,1: Force output to 1.,2: Output is A5OUT2,3: Output is A1OUT.,4: Output is B5OUT.,5: Output is A0OUT2.,6: Output is A6OUT2.,7: Output is A7OUT2."
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bitfld.long 0x18 0.--2. "CFG20,Pad output 20 configuration" "0: Force output to 0,1: Force output to 1.,2: Output is A5OUT,3: Output is A1OUT.,4: Output is A1OUT2.,5: Output is B2OUT2.,6: Output is A6OUT2.,7: Output is A7OUT2."
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group.long 0x114++0x7
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line.long 0x0 "OUTCFG3,Pad output configuration 3."
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bitfld.long 0x0 3.--5. "CFG31,Pad output 31 configuration" "0: Force output to 0,1: Force output to 1.,2: Output is B7OUT2,3: Output is A6OUT.,4: Output is B7OUT.,5: Output is B3OUT2.,6: Output is A6OUT2.,7: Output is A7OUT2."
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bitfld.long 0x0 0.--2. "CFG30,Pad output 30 configuration" "0: Force output to 0,1: Force output to 1.,2: Output is B7OUT,3: Output is B3OUT.,4: Output is A4OUT2.,5: Output is A0OUT2.,6: Output is A6OUT2.,7: Output is A7OUT2."
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line.long 0x4 "INCFG,Pad input configuration."
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bitfld.long 0x4 15. "CFGB7,CTIMER B7 input configuration" "0: Input is CT30,1: Input is CT31"
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bitfld.long 0x4 14. "CFGA7,CTIMER A7 input configuration" "0: Input is CT28,1: Input is CT29"
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bitfld.long 0x4 13. "CFGB6,CTIMER B6 input configuration" "0: Input is CT26,1: Input is CT27"
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bitfld.long 0x4 12. "CFGA6,CTIMER A6 input configuration" "0: Input is CT24,1: Input is CT25"
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bitfld.long 0x4 11. "CFGB5,CTIMER B5 input configuration" "0: Input is CT22,1: Input is CT23"
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bitfld.long 0x4 10. "CFGA5,CTIMER A5 input configuration" "0: Input is CT20,1: Input is CT21"
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bitfld.long 0x4 9. "CFGB4,CTIMER B4 input configuration" "0: Input is CT18,1: Input is CT19"
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bitfld.long 0x4 8. "CFGA4,CTIMER A4 input configuration" "0: Input is CT16,1: Input is CT17"
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bitfld.long 0x4 7. "CFGB3,CTIMER B3 input configuration" "0: Input is CT14,1: Input is CT15"
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bitfld.long 0x4 6. "CFGA3,CTIMER A3 input configuration" "0: Input is CT12,1: Input is CT13"
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bitfld.long 0x4 5. "CFGB2,CTIMER B2 input configuration" "0: Input is CT10,1: Input is CT11"
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bitfld.long 0x4 4. "CFGA2,CTIMER A2 input configuration" "0: Input is CT8,1: Input is CT9"
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bitfld.long 0x4 3. "CFGB1,CTIMER B1 input configuration" "0: Input is CT6,1: Input is CT7"
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bitfld.long 0x4 2. "CFGA1,CTIMER A1 input configuration" "0: Input is CT4,1: Input is CT5"
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bitfld.long 0x4 1. "CFGB0,CTIMER B0 input configuration" "0: Input is CT2,1: Input is CT3"
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bitfld.long 0x4 0. "CFGA0,CTIMER A0 input configuration" "0: Input is CT0,1: Input is CT1"
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group.long 0x140++0xB
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line.long 0x0 "STCFG,The STIMER Configuration Register contains the software control for selecting the clock divider and source feeding the system timer."
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bitfld.long 0x0 31. "FREEZE,Set this bit to one to freeze the clock input to the COUNTER register. Once frozen the value can be safely written from the MCU. Unfreeze to resume." "0: Let the COUNTER register run on its input clock.,1: Stop the COUNTER register for loading."
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bitfld.long 0x0 30. "CLEAR,Set this bit to one to clear the System Timer register. If this bit is set to '1' the system timer register will stay cleared. It needs to be set to '0' for the system timer to start running." "0: Let the COUNTER register run on its input clock.,1: Stop the COUNTER register for loading."
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bitfld.long 0x0 15. "COMPARE_H_EN,Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled the interrupt status is set once the comparison is met." "0: Compare H disabled.,1: Compare H enabled."
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bitfld.long 0x0 14. "COMPARE_G_EN,Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled the interrupt status is set once the comparison is met." "0: Compare G disabled.,1: Compare G enabled."
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bitfld.long 0x0 13. "COMPARE_F_EN,Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled the interrupt status is set once the comparison is met." "0: Compare F disabled.,1: Compare F enabled."
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bitfld.long 0x0 12. "COMPARE_E_EN,Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled the interrupt status is set once the comparison is met." "0: Compare E disabled.,1: Compare E enabled."
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bitfld.long 0x0 11. "COMPARE_D_EN,Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled the interrupt status is set once the comparison is met." "0: Compare D disabled.,1: Compare D enabled."
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bitfld.long 0x0 10. "COMPARE_C_EN,Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled the interrupt status is set once the comparison is met." "0: Compare C disabled.,1: Compare C enabled."
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bitfld.long 0x0 9. "COMPARE_B_EN,Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled the interrupt status is set once the comparison is met." "0: Compare B disabled.,1: Compare B enabled."
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bitfld.long 0x0 8. "COMPARE_A_EN,Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled the interrupt status is set once the comparison is met." "0: Compare A disabled.,1: Compare A enabled."
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hexmask.long.byte 0x0 0.--3. 1. "CLKSEL,Selects an appropriate clock source and divider to use for the System Timer clock."
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line.long 0x4 "STTMR,The COUNTER Register contains the running count of time as maintained by incrementing for every rising clock edge of the clock source selected in the configuration register. It is this counter value that captured in the capture registers and it is.."
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hexmask.long 0x4 0.--31. 1. "STTMR,Value of the 32-bit counter as it ticks over."
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line.long 0x8 "CAPTURECONTROL,The STIMER Capture Control Register controls each of the 4 capture registers. It selects their GPIO pin number for a trigger source. enables a capture operation and sets the input polarity for the capture. NOTE: 8-bit writes can control.."
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bitfld.long 0x8 3. "CAPTURE3,Selects whether capture is enabled for the specified capture register." "0: Capture function disabled.,1: Capture function enabled."
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bitfld.long 0x8 2. "CAPTURE2,Selects whether capture is enabled for the specified capture register." "0: Capture function disabled.,1: Capture function enabled."
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bitfld.long 0x8 1. "CAPTURE1,Selects whether capture is enabled for the specified capture register." "0: Capture function disabled.,1: Capture function enabled."
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bitfld.long 0x8 0. "CAPTURE0,Selects whether capture is enabled for the specified capture register." "0: Capture function disabled.,1: Capture function enabled."
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group.long 0x150++0x1F
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line.long 0x0 "SCMPR0,The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal.."
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hexmask.long 0x0 0.--31. 1. "SCMPR0,Compare this value to the value in the COUNTER register according to the match criterion as selected in the COMPARE_A_EN bit in the REG_CTIMER_STCGF register."
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line.long 0x4 "SCMPR1,The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal.."
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hexmask.long 0x4 0.--31. 1. "SCMPR1,Compare this value to the value in the COUNTER register according to the match criterion as selected in the COMPARE_B_EN bit in the REG_CTIMER_STCGF register."
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line.long 0x8 "SCMPR2,The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal.."
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hexmask.long 0x8 0.--31. 1. "SCMPR2,Compare this value to the value in the COUNTER register according to the match criterion as selected in the COMPARE_C_EN bit in the REG_CTIMER_STCGF register."
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line.long 0xC "SCMPR3,The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal.."
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hexmask.long 0xC 0.--31. 1. "SCMPR3,Compare this value to the value in the COUNTER register according to the match criterion as selected in the COMPARE_D_EN bit in the REG_CTIMER_STCGF register."
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line.long 0x10 "SCMPR4,The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal.."
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hexmask.long 0x10 0.--31. 1. "SCMPR4,Compare this value to the value in the COUNTER register according to the match criterion as selected in the COMPARE_E_EN bit in the REG_CTIMER_STCGF register."
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line.long 0x14 "SCMPR5,The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal.."
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hexmask.long 0x14 0.--31. 1. "SCMPR5,Compare this value to the value in the COUNTER register according to the match criterion as selected in the COMPARE_F_EN bit in the REG_CTIMER_STCGF register."
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line.long 0x18 "SCMPR6,The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal.."
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hexmask.long 0x18 0.--31. 1. "SCMPR6,Compare this value to the value in the COUNTER register according to the match criterion as selected in the COMPARE_G_EN bit in the REG_CTIMER_STCGF register."
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line.long 0x1C "SCMPR7,The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal.."
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hexmask.long 0x1C 0.--31. 1. "SCMPR7,Compare this value to the value in the COUNTER register according to the match criterion as selected in the COMPARE_H_EN bit in the REG_CTIMER_STCGF register."
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group.long 0x1E0++0x2F
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line.long 0x0 "SCAPT0,The STIMER Capture Register A grabs the VALUE in the COUNTER register whenever capture condition (event) A is asserted. This register holds a time stamp for the event."
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hexmask.long 0x0 0.--31. 1. "SCAPT0,Whenever the event is detected the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set."
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line.long 0x4 "SCAPT1,The STIMER Capture Register B grabs the VALUE in the COUNTER register whenever capture condition (event) B is asserted. This register holds a time stamp for the event."
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hexmask.long 0x4 0.--31. 1. "SCAPT1,Whenever the event is detected the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set."
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line.long 0x8 "SCAPT2,The STIMER Capture Register C grabs the VALUE in the COUNTER register whenever capture condition (event) C is asserted. This register holds a time stamp for the event."
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hexmask.long 0x8 0.--31. 1. "SCAPT2,Whenever the event is detected the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set."
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line.long 0xC "SCAPT3,The STIMER Capture Register D grabs the VALUE in the COUNTER register whenever capture condition (event) D is asserted. This register holds a time stamp for the event."
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hexmask.long 0xC 0.--31. 1. "SCAPT3,Whenever the event is detected the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set."
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line.long 0x10 "SNVR0,The NVRAM_A Register contains a portion of the stored epoch offset associated with the time in the COUNTER register. This register is only reset by POI not by HRESETn. Its contents are intended to survive all reset level except POI and full power.."
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hexmask.long 0x10 0.--31. 1. "SNVR0,Value of the 32-bit counter as it ticks over."
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line.long 0x14 "SNVR1,The NVRAM_B Register contains a portion of the stored epoch offset associated with the time in the COUNTER register. This register is only reset by POI not by HRESETn. Its contents are intended to survive all reset level except POI and full power.."
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hexmask.long 0x14 0.--31. 1. "SNVR1,Value of the 32-bit counter as it ticks over."
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line.long 0x18 "SNVR2,The NVRAM_C Register contains a portion of the stored epoch offset associated with the time in the COUNTER register. This register is only reset by POI not by HRESETn. Its contents are intended to survive all reset level except POI and full power.."
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hexmask.long 0x18 0.--31. 1. "SNVR2,Value of the 32-bit counter as it ticks over."
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line.long 0x1C "SNVR3,The NVRAM_D Register contains a portion of the stored epoch offset associated with the time in the COUNTER register. This register is only reset by POI not by HRESETn. Its contents are intended to survive all reset level except POI and full power.."
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hexmask.long 0x1C 0.--31. 1. "SNVR3,Value of the 32-bit counter as it ticks over."
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line.long 0x20 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
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bitfld.long 0x20 31. "CTMRB7C1INT,Counter/Timer B7 interrupt based on COMPR1." "0,1"
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bitfld.long 0x20 30. "CTMRA7C1INT,Counter/Timer A7 interrupt based on COMPR1." "0,1"
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bitfld.long 0x20 29. "CTMRB6C1INT,Counter/Timer B6 interrupt based on COMPR1." "0,1"
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bitfld.long 0x20 28. "CTMRA6C1INT,Counter/Timer A6 interrupt based on COMPR1." "0,1"
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bitfld.long 0x20 27. "CTMRB5C1INT,Counter/Timer B5 interrupt based on COMPR1." "0,1"
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bitfld.long 0x20 26. "CTMRA5C1INT,Counter/Timer A5 interrupt based on COMPR1." "0,1"
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bitfld.long 0x20 25. "CTMRB4C1INT,Counter/Timer B4 interrupt based on COMPR1." "0,1"
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bitfld.long 0x20 24. "CTMRA4C1INT,Counter/Timer A4 interrupt based on COMPR1." "0,1"
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bitfld.long 0x20 23. "CTMRB3C1INT,Counter/Timer B3 interrupt based on COMPR1." "0,1"
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bitfld.long 0x20 22. "CTMRA3C1INT,Counter/Timer A3 interrupt based on COMPR1." "0,1"
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bitfld.long 0x20 21. "CTMRB2C1INT,Counter/Timer B2 interrupt based on COMPR1." "0,1"
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bitfld.long 0x20 20. "CTMRA2C1INT,Counter/Timer A2 interrupt based on COMPR1." "0,1"
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bitfld.long 0x20 19. "CTMRB1C1INT,Counter/Timer B1 interrupt based on COMPR1." "0,1"
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bitfld.long 0x20 18. "CTMRA1C1INT,Counter/Timer A1 interrupt based on COMPR1." "0,1"
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bitfld.long 0x20 17. "CTMRB0C1INT,Counter/Timer B0 interrupt based on COMPR1." "0,1"
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bitfld.long 0x20 16. "CTMRA0C1INT,Counter/Timer A0 interrupt based on COMPR1." "0,1"
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bitfld.long 0x20 15. "CTMRB7C0INT,Counter/Timer B7 interrupt based on COMPR0." "0,1"
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bitfld.long 0x20 14. "CTMRA7C0INT,Counter/Timer A7 interrupt based on COMPR0." "0,1"
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bitfld.long 0x20 13. "CTMRB6C0INT,Counter/Timer B6 interrupt based on COMPR0." "0,1"
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bitfld.long 0x20 12. "CTMRA6C0INT,Counter/Timer A6 interrupt based on COMPR0." "0,1"
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|
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bitfld.long 0x20 11. "CTMRB5C0INT,Counter/Timer B5 interrupt based on COMPR0." "0,1"
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bitfld.long 0x20 10. "CTMRA5C0INT,Counter/Timer A5 interrupt based on COMPR0." "0,1"
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bitfld.long 0x20 9. "CTMRB4C0INT,Counter/Timer B4 interrupt based on COMPR0." "0,1"
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bitfld.long 0x20 8. "CTMRA4C0INT,Counter/Timer A4 interrupt based on COMPR0." "0,1"
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bitfld.long 0x20 7. "CTMRB3C0INT,Counter/Timer B3 interrupt based on COMPR0." "0,1"
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bitfld.long 0x20 6. "CTMRA3C0INT,Counter/Timer A3 interrupt based on COMPR0." "0,1"
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bitfld.long 0x20 5. "CTMRB2C0INT,Counter/Timer B2 interrupt based on COMPR0." "0,1"
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bitfld.long 0x20 4. "CTMRA2C0INT,Counter/Timer A2 interrupt based on COMPR0." "0,1"
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bitfld.long 0x20 3. "CTMRB1C0INT,Counter/Timer B1 interrupt based on COMPR0." "0,1"
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bitfld.long 0x20 2. "CTMRA1C0INT,Counter/Timer A1 interrupt based on COMPR0." "0,1"
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bitfld.long 0x20 1. "CTMRB0C0INT,Counter/Timer B0 interrupt based on COMPR0." "0,1"
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bitfld.long 0x20 0. "CTMRA0C0INT,Counter/Timer A0 interrupt based on COMPR0." "0,1"
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line.long 0x24 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
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bitfld.long 0x24 31. "CTMRB7C1INT,Counter/Timer B7 interrupt based on COMPR1." "0,1"
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bitfld.long 0x24 30. "CTMRA7C1INT,Counter/Timer A7 interrupt based on COMPR1." "0,1"
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bitfld.long 0x24 29. "CTMRB6C1INT,Counter/Timer B6 interrupt based on COMPR1." "0,1"
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bitfld.long 0x24 28. "CTMRA6C1INT,Counter/Timer A6 interrupt based on COMPR1." "0,1"
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|
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bitfld.long 0x24 27. "CTMRB5C1INT,Counter/Timer B5 interrupt based on COMPR1." "0,1"
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bitfld.long 0x24 26. "CTMRA5C1INT,Counter/Timer A5 interrupt based on COMPR1." "0,1"
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|
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bitfld.long 0x24 25. "CTMRB4C1INT,Counter/Timer B4 interrupt based on COMPR1." "0,1"
|
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bitfld.long 0x24 24. "CTMRA4C1INT,Counter/Timer A4 interrupt based on COMPR1." "0,1"
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bitfld.long 0x24 23. "CTMRB3C1INT,Counter/Timer B3 interrupt based on COMPR1." "0,1"
|
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bitfld.long 0x24 22. "CTMRA3C1INT,Counter/Timer A3 interrupt based on COMPR1." "0,1"
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|
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bitfld.long 0x24 21. "CTMRB2C1INT,Counter/Timer B2 interrupt based on COMPR1." "0,1"
|
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bitfld.long 0x24 20. "CTMRA2C1INT,Counter/Timer A2 interrupt based on COMPR1." "0,1"
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|
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bitfld.long 0x24 19. "CTMRB1C1INT,Counter/Timer B1 interrupt based on COMPR1." "0,1"
|
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bitfld.long 0x24 18. "CTMRA1C1INT,Counter/Timer A1 interrupt based on COMPR1." "0,1"
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|
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bitfld.long 0x24 17. "CTMRB0C1INT,Counter/Timer B0 interrupt based on COMPR1." "0,1"
|
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bitfld.long 0x24 16. "CTMRA0C1INT,Counter/Timer A0 interrupt based on COMPR1." "0,1"
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|
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bitfld.long 0x24 15. "CTMRB7C0INT,Counter/Timer B7 interrupt based on COMPR0." "0,1"
|
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bitfld.long 0x24 14. "CTMRA7C0INT,Counter/Timer A7 interrupt based on COMPR0." "0,1"
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bitfld.long 0x24 13. "CTMRB6C0INT,Counter/Timer B6 interrupt based on COMPR0." "0,1"
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bitfld.long 0x24 12. "CTMRA6C0INT,Counter/Timer A6 interrupt based on COMPR0." "0,1"
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bitfld.long 0x24 11. "CTMRB5C0INT,Counter/Timer B5 interrupt based on COMPR0." "0,1"
|
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bitfld.long 0x24 10. "CTMRA5C0INT,Counter/Timer A5 interrupt based on COMPR0." "0,1"
|
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newline
|
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bitfld.long 0x24 9. "CTMRB4C0INT,Counter/Timer B4 interrupt based on COMPR0." "0,1"
|
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bitfld.long 0x24 8. "CTMRA4C0INT,Counter/Timer A4 interrupt based on COMPR0." "0,1"
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bitfld.long 0x24 7. "CTMRB3C0INT,Counter/Timer B3 interrupt based on COMPR0." "0,1"
|
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bitfld.long 0x24 6. "CTMRA3C0INT,Counter/Timer A3 interrupt based on COMPR0." "0,1"
|
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newline
|
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bitfld.long 0x24 5. "CTMRB2C0INT,Counter/Timer B2 interrupt based on COMPR0." "0,1"
|
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bitfld.long 0x24 4. "CTMRA2C0INT,Counter/Timer A2 interrupt based on COMPR0." "0,1"
|
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newline
|
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bitfld.long 0x24 3. "CTMRB1C0INT,Counter/Timer B1 interrupt based on COMPR0." "0,1"
|
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bitfld.long 0x24 2. "CTMRA1C0INT,Counter/Timer A1 interrupt based on COMPR0." "0,1"
|
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newline
|
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bitfld.long 0x24 1. "CTMRB0C0INT,Counter/Timer B0 interrupt based on COMPR0." "0,1"
|
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bitfld.long 0x24 0. "CTMRA0C0INT,Counter/Timer A0 interrupt based on COMPR0." "0,1"
|
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line.long 0x28 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
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bitfld.long 0x28 31. "CTMRB7C1INT,Counter/Timer B7 interrupt based on COMPR1." "0,1"
|
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bitfld.long 0x28 30. "CTMRA7C1INT,Counter/Timer A7 interrupt based on COMPR1." "0,1"
|
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newline
|
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bitfld.long 0x28 29. "CTMRB6C1INT,Counter/Timer B6 interrupt based on COMPR1." "0,1"
|
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bitfld.long 0x28 28. "CTMRA6C1INT,Counter/Timer A6 interrupt based on COMPR1." "0,1"
|
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newline
|
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bitfld.long 0x28 27. "CTMRB5C1INT,Counter/Timer B5 interrupt based on COMPR1." "0,1"
|
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bitfld.long 0x28 26. "CTMRA5C1INT,Counter/Timer A5 interrupt based on COMPR1." "0,1"
|
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newline
|
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bitfld.long 0x28 25. "CTMRB4C1INT,Counter/Timer B4 interrupt based on COMPR1." "0,1"
|
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bitfld.long 0x28 24. "CTMRA4C1INT,Counter/Timer A4 interrupt based on COMPR1." "0,1"
|
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newline
|
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bitfld.long 0x28 23. "CTMRB3C1INT,Counter/Timer B3 interrupt based on COMPR1." "0,1"
|
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bitfld.long 0x28 22. "CTMRA3C1INT,Counter/Timer A3 interrupt based on COMPR1." "0,1"
|
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newline
|
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bitfld.long 0x28 21. "CTMRB2C1INT,Counter/Timer B2 interrupt based on COMPR1." "0,1"
|
|
bitfld.long 0x28 20. "CTMRA2C1INT,Counter/Timer A2 interrupt based on COMPR1." "0,1"
|
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newline
|
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bitfld.long 0x28 19. "CTMRB1C1INT,Counter/Timer B1 interrupt based on COMPR1." "0,1"
|
|
bitfld.long 0x28 18. "CTMRA1C1INT,Counter/Timer A1 interrupt based on COMPR1." "0,1"
|
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newline
|
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bitfld.long 0x28 17. "CTMRB0C1INT,Counter/Timer B0 interrupt based on COMPR1." "0,1"
|
|
bitfld.long 0x28 16. "CTMRA0C1INT,Counter/Timer A0 interrupt based on COMPR1." "0,1"
|
|
newline
|
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bitfld.long 0x28 15. "CTMRB7C0INT,Counter/Timer B7 interrupt based on COMPR0." "0,1"
|
|
bitfld.long 0x28 14. "CTMRA7C0INT,Counter/Timer A7 interrupt based on COMPR0." "0,1"
|
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newline
|
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bitfld.long 0x28 13. "CTMRB6C0INT,Counter/Timer B6 interrupt based on COMPR0." "0,1"
|
|
bitfld.long 0x28 12. "CTMRA6C0INT,Counter/Timer A6 interrupt based on COMPR0." "0,1"
|
|
newline
|
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bitfld.long 0x28 11. "CTMRB5C0INT,Counter/Timer B5 interrupt based on COMPR0." "0,1"
|
|
bitfld.long 0x28 10. "CTMRA5C0INT,Counter/Timer A5 interrupt based on COMPR0." "0,1"
|
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newline
|
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bitfld.long 0x28 9. "CTMRB4C0INT,Counter/Timer B4 interrupt based on COMPR0." "0,1"
|
|
bitfld.long 0x28 8. "CTMRA4C0INT,Counter/Timer A4 interrupt based on COMPR0." "0,1"
|
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newline
|
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bitfld.long 0x28 7. "CTMRB3C0INT,Counter/Timer B3 interrupt based on COMPR0." "0,1"
|
|
bitfld.long 0x28 6. "CTMRA3C0INT,Counter/Timer A3 interrupt based on COMPR0." "0,1"
|
|
newline
|
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bitfld.long 0x28 5. "CTMRB2C0INT,Counter/Timer B2 interrupt based on COMPR0." "0,1"
|
|
bitfld.long 0x28 4. "CTMRA2C0INT,Counter/Timer A2 interrupt based on COMPR0." "0,1"
|
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newline
|
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bitfld.long 0x28 3. "CTMRB1C0INT,Counter/Timer B1 interrupt based on COMPR0." "0,1"
|
|
bitfld.long 0x28 2. "CTMRA1C0INT,Counter/Timer A1 interrupt based on COMPR0." "0,1"
|
|
newline
|
|
bitfld.long 0x28 1. "CTMRB0C0INT,Counter/Timer B0 interrupt based on COMPR0." "0,1"
|
|
bitfld.long 0x28 0. "CTMRA0C0INT,Counter/Timer A0 interrupt based on COMPR0." "0,1"
|
|
line.long 0x2C "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0x2C 31. "CTMRB7C1INT,Counter/Timer B7 interrupt based on COMPR1." "0,1"
|
|
bitfld.long 0x2C 30. "CTMRA7C1INT,Counter/Timer A7 interrupt based on COMPR1." "0,1"
|
|
newline
|
|
bitfld.long 0x2C 29. "CTMRB6C1INT,Counter/Timer B6 interrupt based on COMPR1." "0,1"
|
|
bitfld.long 0x2C 28. "CTMRA6C1INT,Counter/Timer A6 interrupt based on COMPR1." "0,1"
|
|
newline
|
|
bitfld.long 0x2C 27. "CTMRB5C1INT,Counter/Timer B5 interrupt based on COMPR1." "0,1"
|
|
bitfld.long 0x2C 26. "CTMRA5C1INT,Counter/Timer A5 interrupt based on COMPR1." "0,1"
|
|
newline
|
|
bitfld.long 0x2C 25. "CTMRB4C1INT,Counter/Timer B4 interrupt based on COMPR1." "0,1"
|
|
bitfld.long 0x2C 24. "CTMRA4C1INT,Counter/Timer A4 interrupt based on COMPR1." "0,1"
|
|
newline
|
|
bitfld.long 0x2C 23. "CTMRB3C1INT,Counter/Timer B3 interrupt based on COMPR1." "0,1"
|
|
bitfld.long 0x2C 22. "CTMRA3C1INT,Counter/Timer A3 interrupt based on COMPR1." "0,1"
|
|
newline
|
|
bitfld.long 0x2C 21. "CTMRB2C1INT,Counter/Timer B2 interrupt based on COMPR1." "0,1"
|
|
bitfld.long 0x2C 20. "CTMRA2C1INT,Counter/Timer A2 interrupt based on COMPR1." "0,1"
|
|
newline
|
|
bitfld.long 0x2C 19. "CTMRB1C1INT,Counter/Timer B1 interrupt based on COMPR1." "0,1"
|
|
bitfld.long 0x2C 18. "CTMRA1C1INT,Counter/Timer A1 interrupt based on COMPR1." "0,1"
|
|
newline
|
|
bitfld.long 0x2C 17. "CTMRB0C1INT,Counter/Timer B0 interrupt based on COMPR1." "0,1"
|
|
bitfld.long 0x2C 16. "CTMRA0C1INT,Counter/Timer A0 interrupt based on COMPR1." "0,1"
|
|
newline
|
|
bitfld.long 0x2C 15. "CTMRB7C0INT,Counter/Timer B7 interrupt based on COMPR0." "0,1"
|
|
bitfld.long 0x2C 14. "CTMRA7C0INT,Counter/Timer A7 interrupt based on COMPR0." "0,1"
|
|
newline
|
|
bitfld.long 0x2C 13. "CTMRB6C0INT,Counter/Timer B6 interrupt based on COMPR0." "0,1"
|
|
bitfld.long 0x2C 12. "CTMRA6C0INT,Counter/Timer A6 interrupt based on COMPR0." "0,1"
|
|
newline
|
|
bitfld.long 0x2C 11. "CTMRB5C0INT,Counter/Timer B5 interrupt based on COMPR0." "0,1"
|
|
bitfld.long 0x2C 10. "CTMRA5C0INT,Counter/Timer A5 interrupt based on COMPR0." "0,1"
|
|
newline
|
|
bitfld.long 0x2C 9. "CTMRB4C0INT,Counter/Timer B4 interrupt based on COMPR0." "0,1"
|
|
bitfld.long 0x2C 8. "CTMRA4C0INT,Counter/Timer A4 interrupt based on COMPR0." "0,1"
|
|
newline
|
|
bitfld.long 0x2C 7. "CTMRB3C0INT,Counter/Timer B3 interrupt based on COMPR0." "0,1"
|
|
bitfld.long 0x2C 6. "CTMRA3C0INT,Counter/Timer A3 interrupt based on COMPR0." "0,1"
|
|
newline
|
|
bitfld.long 0x2C 5. "CTMRB2C0INT,Counter/Timer B2 interrupt based on COMPR0." "0,1"
|
|
bitfld.long 0x2C 4. "CTMRA2C0INT,Counter/Timer A2 interrupt based on COMPR0." "0,1"
|
|
newline
|
|
bitfld.long 0x2C 3. "CTMRB1C0INT,Counter/Timer B1 interrupt based on COMPR0." "0,1"
|
|
bitfld.long 0x2C 2. "CTMRA1C0INT,Counter/Timer A1 interrupt based on COMPR0." "0,1"
|
|
newline
|
|
bitfld.long 0x2C 1. "CTMRB0C0INT,Counter/Timer B0 interrupt based on COMPR0." "0,1"
|
|
bitfld.long 0x2C 0. "CTMRA0C0INT,Counter/Timer A0 interrupt based on COMPR0." "0,1"
|
|
group.long 0x300++0xF
|
|
line.long 0x0 "STMINTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 12. "CAPTURED,CAPTURE register D has grabbed the value in the counter" "?,1: Capture D interrupt status bit was set."
|
|
bitfld.long 0x0 11. "CAPTUREC,CAPTURE register C has grabbed the value in the counter" "?,1: CAPTURE C interrupt status bit was set."
|
|
newline
|
|
bitfld.long 0x0 10. "CAPTUREB,CAPTURE register B has grabbed the value in the counter" "?,1: CAPTURE B interrupt status bit was set."
|
|
bitfld.long 0x0 9. "CAPTUREA,CAPTURE register A has grabbed the value in the counter" "?,1: CAPTURE A interrupt status bit was set."
|
|
newline
|
|
bitfld.long 0x0 8. "OVERFLOW,COUNTER over flowed from 0xFFFFFFFF back to 0x00000000." "?,1: Overflow interrupt status bit was set."
|
|
bitfld.long 0x0 7. "COMPAREH,COUNTER is greater than or equal to COMPARE register H." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
bitfld.long 0x0 6. "COMPAREG,COUNTER is greater than or equal to COMPARE register G." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
bitfld.long 0x0 5. "COMPAREF,COUNTER is greater than or equal to COMPARE register F." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
bitfld.long 0x0 4. "COMPAREE,COUNTER is greater than or equal to COMPARE register E." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
bitfld.long 0x0 3. "COMPARED,COUNTER is greater than or equal to COMPARE register D." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
bitfld.long 0x0 2. "COMPAREC,COUNTER is greater than or equal to COMPARE register C." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
bitfld.long 0x0 1. "COMPAREB,COUNTER is greater than or equal to COMPARE register B." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
bitfld.long 0x0 0. "COMPAREA,COUNTER is greater than or equal to COMPARE register A." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
line.long 0x4 "STMINTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 12. "CAPTURED,CAPTURE register D has grabbed the value in the counter" "?,1: Capture D interrupt status bit was set."
|
|
bitfld.long 0x4 11. "CAPTUREC,CAPTURE register C has grabbed the value in the counter" "?,1: CAPTURE C interrupt status bit was set."
|
|
newline
|
|
bitfld.long 0x4 10. "CAPTUREB,CAPTURE register B has grabbed the value in the counter" "?,1: CAPTURE B interrupt status bit was set."
|
|
bitfld.long 0x4 9. "CAPTUREA,CAPTURE register A has grabbed the value in the counter" "?,1: CAPTURE A interrupt status bit was set."
|
|
newline
|
|
bitfld.long 0x4 8. "OVERFLOW,COUNTER over flowed from 0xFFFFFFFF back to 0x00000000." "?,1: Overflow interrupt status bit was set."
|
|
bitfld.long 0x4 7. "COMPAREH,COUNTER is greater than or equal to COMPARE register H." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
bitfld.long 0x4 6. "COMPAREG,COUNTER is greater than or equal to COMPARE register G." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
bitfld.long 0x4 5. "COMPAREF,COUNTER is greater than or equal to COMPARE register F." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
bitfld.long 0x4 4. "COMPAREE,COUNTER is greater than or equal to COMPARE register E." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
bitfld.long 0x4 3. "COMPARED,COUNTER is greater than or equal to COMPARE register D." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
bitfld.long 0x4 2. "COMPAREC,COUNTER is greater than or equal to COMPARE register C." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
bitfld.long 0x4 1. "COMPAREB,COUNTER is greater than or equal to COMPARE register B." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
bitfld.long 0x4 0. "COMPAREA,COUNTER is greater than or equal to COMPARE register A." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
line.long 0x8 "STMINTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 12. "CAPTURED,CAPTURE register D has grabbed the value in the counter" "?,1: Capture D interrupt status bit was set."
|
|
bitfld.long 0x8 11. "CAPTUREC,CAPTURE register C has grabbed the value in the counter" "?,1: CAPTURE C interrupt status bit was set."
|
|
newline
|
|
bitfld.long 0x8 10. "CAPTUREB,CAPTURE register B has grabbed the value in the counter" "?,1: CAPTURE B interrupt status bit was set."
|
|
bitfld.long 0x8 9. "CAPTUREA,CAPTURE register A has grabbed the value in the counter" "?,1: CAPTURE A interrupt status bit was set."
|
|
newline
|
|
bitfld.long 0x8 8. "OVERFLOW,COUNTER over flowed from 0xFFFFFFFF back to 0x00000000." "?,1: Overflow interrupt status bit was set."
|
|
bitfld.long 0x8 7. "COMPAREH,COUNTER is greater than or equal to COMPARE register H." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
bitfld.long 0x8 6. "COMPAREG,COUNTER is greater than or equal to COMPARE register G." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
bitfld.long 0x8 5. "COMPAREF,COUNTER is greater than or equal to COMPARE register F." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
bitfld.long 0x8 4. "COMPAREE,COUNTER is greater than or equal to COMPARE register E." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
bitfld.long 0x8 3. "COMPARED,COUNTER is greater than or equal to COMPARE register D." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
bitfld.long 0x8 2. "COMPAREC,COUNTER is greater than or equal to COMPARE register C." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
bitfld.long 0x8 1. "COMPAREB,COUNTER is greater than or equal to COMPARE register B." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
bitfld.long 0x8 0. "COMPAREA,COUNTER is greater than or equal to COMPARE register A." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
line.long 0xC "STMINTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 12. "CAPTURED,CAPTURE register D has grabbed the value in the counter" "?,1: Capture D interrupt status bit was set."
|
|
bitfld.long 0xC 11. "CAPTUREC,CAPTURE register C has grabbed the value in the counter" "?,1: CAPTURE C interrupt status bit was set."
|
|
newline
|
|
bitfld.long 0xC 10. "CAPTUREB,CAPTURE register B has grabbed the value in the counter" "?,1: CAPTURE B interrupt status bit was set."
|
|
bitfld.long 0xC 9. "CAPTUREA,CAPTURE register A has grabbed the value in the counter" "?,1: CAPTURE A interrupt status bit was set."
|
|
newline
|
|
bitfld.long 0xC 8. "OVERFLOW,COUNTER over flowed from 0xFFFFFFFF back to 0x00000000." "?,1: Overflow interrupt status bit was set."
|
|
bitfld.long 0xC 7. "COMPAREH,COUNTER is greater than or equal to COMPARE register H." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
bitfld.long 0xC 6. "COMPAREG,COUNTER is greater than or equal to COMPARE register G." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
bitfld.long 0xC 5. "COMPAREF,COUNTER is greater than or equal to COMPARE register F." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
bitfld.long 0xC 4. "COMPAREE,COUNTER is greater than or equal to COMPARE register E." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
bitfld.long 0xC 3. "COMPARED,COUNTER is greater than or equal to COMPARE register D." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
bitfld.long 0xC 2. "COMPAREC,COUNTER is greater than or equal to COMPARE register C." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
bitfld.long 0xC 1. "COMPAREB,COUNTER is greater than or equal to COMPARE register B." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
newline
|
|
bitfld.long 0xC 0. "COMPAREA,COUNTER is greater than or equal to COMPARE register A." "?,1: COUNTER greater than or equal to COMPARE register."
|
|
tree.end
|
|
tree "GPIO (General Purpose I/O)"
|
|
base ad:0x40010000
|
|
group.long 0x0++0x33
|
|
line.long 0x0 "PADREGA,This register controls the pad configuration controls for PAD3 through PAD0. Writes to this register must be unlocked by the PADKEY register."
|
|
bitfld.long 0x0 30. "PAD3PWRUP,Pad 3 VDD power switch enable" "0: Power switch disabled,1: Power switch enabled (switched to VDD)"
|
|
bitfld.long 0x0 27.--29. "PAD3FNCSEL,Pad 3 function select" "0: Configure as the UART0 RTS output,1: Configure as the IOSLAVE SPI nCE signal,2: IOM/MSPI nCE group 3,3: Configure as GPIO3,?,5: MSPI data connection 7,6: Configure as the ADC Trigger 1 signal,7: Configure as the PDM I2S Word Clock input"
|
|
newline
|
|
bitfld.long 0x0 26. "PAD3STRNG,Pad 3 drive strength." "0: Low drive strength,1: High drive strength"
|
|
bitfld.long 0x0 25. "PAD3INPEN,Pad 3 input enable." "0: Pad input disabled,1: Pad input enabled"
|
|
newline
|
|
bitfld.long 0x0 24. "PAD3PULL,Pad 3 pullup enable" "0: Pullup disabled,1: Pullup enabled"
|
|
bitfld.long 0x0 19.--21. "PAD2FNCSEL,Pad 2 function select" "0: Configure as the UART1 RX input.,1: Configure as the IOSLAVE SPI MISO signal.,2: Configure as the UART0 RX input.,3: Configure as GPIO2.,?,5: MSPI data connection 6.,?,7: IOM/MSPI nCE group 2"
|
|
newline
|
|
bitfld.long 0x0 18. "PAD2STRNG,Pad 2 drive strength" "0: Low drive strength,1: High drive strength"
|
|
bitfld.long 0x0 17. "PAD2INPEN,Pad 2 input enable" "0: Pad input disabled,1: Pad input enabled"
|
|
newline
|
|
bitfld.long 0x0 16. "PAD2PULL,Pad 2 pullup enable" "0: Pullup disabled,1: Pullup enabled"
|
|
bitfld.long 0x0 14.--15. "PAD1RSEL,Pad 1 pullup resistor selection." "0: Pullup is ~1.5 KOhms,1: Pullup is ~6 KOhms,2: Pullup is ~12 KOhms,3: Pullup is ~24 KOhms"
|
|
newline
|
|
bitfld.long 0x0 11.--13. "PAD1FNCSEL,Pad 1 function select" "0: Configure as the IOSLAVE I2C SDA or SPI WIR3..,1: Configure as the IOSLAVE SPI MOSI signal,2: Configure as the UART0 TX output signal,3: Configure as GPIO1,?,5: MSPI data connection 5,?,7: IOM/MSPI nCE group 1"
|
|
bitfld.long 0x0 10. "PAD1STRNG,Pad 1 drive strength" "0: Low drive strength,1: High drive strength"
|
|
newline
|
|
bitfld.long 0x0 9. "PAD1INPEN,Pad 1 input enable" "0: Pad input disabled,1: Pad input enabled"
|
|
bitfld.long 0x0 8. "PAD1PULL,Pad 1 pullup enable" "0: Pullup disabled,1: Pullup enabled"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "PAD0RSEL,Pad 0 pullup resistor selection." "0: Pullup is ~1.5 KOhms,1: Pullup is ~6 KOhms,2: Pullup is ~12 KOhms,3: Pullup is ~24 KOhms"
|
|
bitfld.long 0x0 3.--5. "PAD0FNCSEL,Pad 0 function select" "0: Configure as the IOSLAVE I2C SCL signal,1: Configure as the IOSLAVE SPI SCK signal,2: Configure as the CLKOUT signal,3: Configure as GPIO0,?,5: MSPI data connection 4,?,7: IOM/MSPI nCE group 0"
|
|
newline
|
|
bitfld.long 0x0 2. "PAD0STRNG,Pad 0 drive strength" "0: Low drive strength,1: High drive strength"
|
|
bitfld.long 0x0 1. "PAD0INPEN,Pad 0 input enable" "0: Pad input disabled,1: Pad input enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "PAD0PULL,Pad 0 pullup enable" "0: Pullup disabled,1: Pullup enabled"
|
|
line.long 0x4 "PADREGB,This register controls the pad configuration controls for PAD7 through PAD4. Writes to this register must be unlocked by the PADKEY register."
|
|
bitfld.long 0x4 27.--29. "PAD7FNCSEL,Pad 7 function select" "0: IOM/MSPI nCE group 7,1: Configure as the IOMSTR0 SPI MOSI signal,2: Configure as the CLKOUT signal,3: Configure as GPIO7,4: Configure as the ADC Trigger 0 signal,5: Configure as the UART0 TX output signal,?,7: CTIMER connection 19"
|
|
bitfld.long 0x4 26. "PAD7STRNG,Pad 7 drive strength" "0: Low drive strength,1: High drive strength"
|
|
newline
|
|
bitfld.long 0x4 25. "PAD7INPEN,Pad 7 input enable" "0: Pad input disabled,1: Pad input enabled"
|
|
bitfld.long 0x4 24. "PAD7PULL,Pad 7 pullup enable" "0: Pullup disabled,1: Pullup enabled"
|
|
newline
|
|
bitfld.long 0x4 22.--23. "PAD6RSEL,Pad 6 pullup resistor selection." "0: Pullup is ~1.5 KOhms,1: Pullup is ~6 KOhms,2: Pullup is ~12 KOhms,3: Pullup is ~24 KOhms"
|
|
bitfld.long 0x4 19.--21. "PAD6FNCSEL,Pad 6 function select" "0: Configure as the IOMSTR0 I2C SDA or SPI WIR3..,1: Configure as the IOMSTR0 SPI MISO signal,2: Configure as the UART0 CTS input signal,3: Configure as GPIO6,?,5: CTIMER connection 10,?,7: Configure as the PDM I2S Data output signal"
|
|
newline
|
|
bitfld.long 0x4 18. "PAD6STRNG,Pad 6 drive strength" "0: Low drive strength,1: High drive strength"
|
|
bitfld.long 0x4 17. "PAD6INPEN,Pad 6 input enable" "0: Pad input disabled,1: Pad input enabled"
|
|
newline
|
|
bitfld.long 0x4 16. "PAD6PULL,Pad 6 pullup enable" "0: Pullup disabled,1: Pullup enabled"
|
|
bitfld.long 0x4 14.--15. "PAD5RSEL,Pad 5 pullup resistor selection." "0: Pullup is ~1.5 KOhms,1: Pullup is ~6 KOhms,2: Pullup is ~12 KOhms,3: Pullup is ~24 KOhms"
|
|
newline
|
|
bitfld.long 0x4 11.--13. "PAD5FNCSEL,Pad 5 function select" "0: Configure as the IOMSTR0 I2C SCL signal,1: Configure as the IOMSTR0 SPI SCK signal,2: Configure as the UART0 RTS signal output,3: Configure as GPIO5,?,5: Configure as the External HFA input clock,?,7: CTIMER connection 8"
|
|
bitfld.long 0x4 10. "PAD5STRNG,Pad 5 drive strength" "0: Low drive strength,1: High drive strength"
|
|
newline
|
|
bitfld.long 0x4 9. "PAD5INPEN,Pad 5 input enable" "0: Pad input disabled,1: Pad input enabled"
|
|
bitfld.long 0x4 8. "PAD5PULL,Pad 5 pullup enable" "0: Pullup disabled,1: Pullup enabled"
|
|
newline
|
|
sif (cpuis("AMA3B2KK"))
|
|
bitfld.long 0x4 3.--5. "PAD4FNCSEL,Pad 4 function select" "0: Configure as the UART0 CTS input signal,1: Configure as the IOSLAVE interrupt out signal,2: IOM/SPI nCE group 4,3: Configure as GPIO4,?,5: Configure as the UART0 RX input,6: CTIMER connection 17,7: MSPI data connection 2"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA3B1KK")||cpuis("AMAP31KK"))
|
|
bitfld.long 0x4 3.--5. "PAD4FNCSEL,Pad 4 function select" "0: Configure as the UART0 CTS input signal,1: Configure as the IOSLAVE interrupt out signal,2: IOM/SPI nCE group 4,3: Configure as GPIO4,?,5: Configure as the UART1 RX input,6: CTIMER connection 17,7: MSPI data connection 2"
|
|
newline
|
|
endif
|
|
bitfld.long 0x4 2. "PAD4STRNG,Pad 4 drive strength" "0: Low drive strength,1: High drive strength"
|
|
bitfld.long 0x4 1. "PAD4INPEN,Pad 4 input enable" "0: Pad input disabled,1: Pad input enabled"
|
|
newline
|
|
bitfld.long 0x4 0. "PAD4PULL,Pad 4 pullup enable" "0: Pullup disabled,1: Pullup enabled"
|
|
line.long 0x8 "PADREGC,This register controls the pad configuration controls for PAD11 through PAD8. Writes to this register must be unlocked by the PADKEY register."
|
|
bitfld.long 0x8 27.--29. "PAD11FNCSEL,Pad 11 function select" "0: Configure as the analog input for ADC single..,1: IOM/MSPI nCE group 11,2: CTIMER connection 31,3: Configure as GPIO11,4: Configure as the IOSLAVE interrupt out signal,5: Configure as the UART1 CTS input signal,6: Configure as the UART0 RX input signal,7: Configure as the PDM Data input signal"
|
|
bitfld.long 0x8 26. "PAD11STRNG,Pad 11 drive strength" "0: Low drive strength,1: High drive strength"
|
|
newline
|
|
bitfld.long 0x8 25. "PAD11INPEN,Pad 11 input enable" "0: Pad input disabled,1: Pad input enabled"
|
|
bitfld.long 0x8 24. "PAD11PULL,Pad 11 pullup enable" "0: Pullup disabled,1: Pullup enabled"
|
|
newline
|
|
sif (cpuis("AMA3B2KK"))
|
|
bitfld.long 0x8 19.--21. "PAD10FNCSEL,Pad 10 function select" "?,1: Configure as the IOMSTR1 SPI MOSI signal,2: IOM/MSPI nCE group 10,3: Configure as GPIO10,4: PDM serial clock out,5: Configure as the UART1 RTS output signal,?,?"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA3B1KK")||cpuis("AMAP31KK"))
|
|
bitfld.long 0x8 19.--21. "PAD10FNCSEL,Pad 10 function select" "0: Configure as the UART1 TX output signal,1: Configure as the IOMSTR1 SPI MOSI signal,2: IOM/MSPI nCE group 10,3: Configure as GPIO10,4: PDM serial clock out,5: Configure as the UART1 RTS output signal,?,?"
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newline
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endif
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bitfld.long 0x8 18. "PAD10STRNG,Pad 10 drive strength" "0: Low drive strength,1: High drive strength"
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bitfld.long 0x8 17. "PAD10INPEN,Pad 10 input enable" "0: Pad input disabled,1: Pad input enabled"
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newline
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bitfld.long 0x8 16. "PAD10PULL,Pad 10 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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bitfld.long 0x8 14.--15. "PAD9RSEL,Pad 9 pullup resistor selection" "0: Pullup is ~1.5 KOhms,1: Pullup is ~6 KOhms,2: Pullup is ~12 KOhms,3: Pullup is ~24 KOhms"
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bitfld.long 0x8 11.--13. "PAD9FNCSEL,Pad 9 function select" "0: Configure as the IOMSTR1 I2C SDA or SPI WIR3..,1: Configure as the IOMSTR1 SPI MISO signal,2: IOM/MSPI nCE group 9,3: Configure as GPIO9,4: SCARD data I/O connection,?,6: Configure as UART1 RX input signal,?"
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bitfld.long 0x8 10. "PAD9STRNG,Pad 9 drive strength" "0: Low drive strength,1: High drive strength"
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newline
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bitfld.long 0x8 9. "PAD9INPEN,Pad 9 input enable" "0: Pad input disabled,1: Pad input enabled"
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bitfld.long 0x8 8. "PAD9PULL,Pad 9 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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newline
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bitfld.long 0x8 6.--7. "PAD8RSEL,Pad 8 pullup resistor selection." "0: Pullup is ~1.5 KOhms,1: Pullup is ~6 KOhms,2: Pullup is ~12 KOhms,3: Pullup is ~24 KOhms"
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bitfld.long 0x8 3.--5. "PAD8FNCSEL,Pad 8 function select" "0: Configure as the IOMSTR1 I2C SCL signal,1: Configure as the IOMSTR1 SPI SCK signal,2: IOM/MSPI nCE group 8,3: Configure as GPIO8,4: SCARD serial clock output,?,6: Configure as the UART1 TX output signal,?"
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newline
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bitfld.long 0x8 2. "PAD8STRNG,Pad 8 drive strength" "0: Low drive strength,1: High drive strength"
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bitfld.long 0x8 1. "PAD8INPEN,Pad 8 input enable" "0: Pad input disabled,1: Pad input enabled"
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newline
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bitfld.long 0x8 0. "PAD8PULL,Pad 8 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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line.long 0xC "PADREGD,This register controls the pad configuration controls for PAD15 through PAD12. Writes to this register must be unlocked by the PADKEY register."
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bitfld.long 0xC 27.--29. "PAD15FNCSEL,Pad 15 function select" "0: Configure as the analog ADC differential pair 1..,1: IOM/MSPI nCE group 15,2: Configure as the UART1 RX signal,3: Configure as GPIO15,4: PDM serial data input,5: Configure as the external XTAL oscillator input,6: Configure as an alternate port for the SWDIO I/O..,7: Configure as an SWO (Serial Wire Trace output)"
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bitfld.long 0xC 26. "PAD15STRNG,Pad 15 drive strength" "0: Low drive strength,1: High drive strength"
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newline
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bitfld.long 0xC 25. "PAD15INPEN,Pad 15 input enable" "0: Pad input disabled,1: Pad input enabled"
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bitfld.long 0xC 24. "PAD15PULL,Pad 15 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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newline
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bitfld.long 0xC 19.--21. "PAD14FNCSEL,Pad 14 function select" "0: Configure as the analog ADC differential pair 1..,1: IOM/MSPI nCE group 14,2: Configure as the UART1 TX output signal,3: Configure as GPIO14,4: PDM serial clock output,5: Configure as the External HFRC oscillator input..,6: Configure as the alternate input for the SWDCK..,7: Configure as the 32kHz crystal output signal"
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bitfld.long 0xC 18. "PAD14STRNG,Pad 14 drive strength" "0: Low drive strength,1: High drive strength"
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newline
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bitfld.long 0xC 17. "PAD14INPEN,Pad 14 input enable" "0: Pad input disabled,1: Pad input enabled"
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bitfld.long 0xC 16. "PAD14PULL,Pad 14 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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newline
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bitfld.long 0xC 11.--13. "PAD13FNCSEL,Pad 13 function select" "0: Configure as the ADC Differential pair 0 P or..,1: IOM/MSPI nCE group 13,2: CTIMER connection 2,3: Configure as GPIO13,4: I2C interface bit clock,5: Configure as the external HFRC oscillator input,6: Configure as the UART0 RTS signal output,7: Configure as the UART1 RX input signal"
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bitfld.long 0xC 10. "PAD13STRNG,Pad 13 drive strength" "0: Low drive strength,1: High drive strength"
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newline
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bitfld.long 0xC 9. "PAD13INPEN,Pad 13 input enable" "0: Pad input disabled,1: Pad input enabled"
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bitfld.long 0xC 8. "PAD13PULL,Pad 13 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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newline
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bitfld.long 0xC 3.--5. "PAD12FNCSEL,Pad 12 function select" "0: Configure as the ADC Differential pair 0 N or..,1: IOM/MSPI nCE group 12,2: CTIMER connection 0,3: Configure as GPIO12,?,5: PDM serial clock output,6: Configure as the UART0 CTS input signal,7: Configure as the UART1 TX output signal"
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bitfld.long 0xC 2. "PAD12STRNG,Pad 12 drive strength" "0: Low drive strength,1: High drive strength"
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newline
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bitfld.long 0xC 1. "PAD12INPEN,Pad 12 input enable" "0: Pad input disabled,1: Pad input enabled"
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bitfld.long 0xC 0. "PAD12PULL,Pad 12 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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line.long 0x10 "PADREGE,This register controls the pad configuration controls for PAD19 through PAD16. Writes to this register must be unlocked by the PADKEY register."
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bitfld.long 0x10 27.--29. "PAD19FNCSEL,Pad 19 function select" "0: Configure as the analog comparator reference 0..,1: IOM/MSPI nCE group 19,2: CTIMER conenction 6,3: Configure as GPIO19,4: SCARD serial clock,5: Configure as the ANATEST1 I/O signal,6: Configure as the UART1 RX input signal,7: Configure as the PDM I2S bit clock input signal"
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bitfld.long 0x10 26. "PAD19STRNG,Pad 19 drive strength" "0: Low drive strength,1: High drive strength"
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bitfld.long 0x10 25. "PAD19INPEN,Pad 19 input enable" "0: Pad input disabled,1: Pad input enabled"
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bitfld.long 0x10 24. "PAD19PULL,Pad 19 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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newline
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bitfld.long 0x10 19.--21. "PAD18FNCSEL,Pad 18 function select" "0: Configure as the analog comparator input 1 signal,1: IOM/MSPI nCE group 18,2: CTIMER connection 4,3: Configure as GPIO18,4: Configure as UART0 RTS output signal,5: Configure as ANATEST2 I/O signal,6: Configure as UART1 TX output signal,7: SCARD data input/output connection"
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bitfld.long 0x10 18. "PAD18STRNG,Pad 18 drive strength" "0: Low drive strength,1: High drive strength"
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newline
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bitfld.long 0x10 17. "PAD18INPEN,Pad 18 input enable" "0: Pad input disabled,1: Pad input enabled"
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bitfld.long 0x10 16. "PAD18PULL,Pad 18 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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newline
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bitfld.long 0x10 11.--13. "PAD17FNCSEL,Pad 17 function select" "0: Configure as the analog comparator reference..,1: IOM/MSPI nCE group 17,2: Configure as the ADC Trigger 1 signal,3: Configure as GPIO17,4: SCARD serial clock output,?,6: Configure as UART0 RX input signal,7: Configure as UART1 CTS input signal"
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bitfld.long 0x10 10. "PAD17STRNG,Pad 17 drive strength" "0: Low drive strength,1: High drive strength"
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newline
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bitfld.long 0x10 9. "PAD17INPEN,Pad 17 input enable" "0: Pad input disabled,1: Pad input enabled"
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bitfld.long 0x10 8. "PAD17PULL,Pad 17 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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newline
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bitfld.long 0x10 3.--5. "PAD16FNCSEL,Pad 16 function select" "0: Configure as the analog ADC single ended port 0..,1: IOM/MSPI nCE group 16,2: Configure as the ADC Trigger 0 signal,3: Configure as GPIO16,4: SCARD reset output,5: Configure as comparator input 0 signal,6: Configure as UART0 TX output signal,7: Configure as UART1 RTS output signal"
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bitfld.long 0x10 2. "PAD16STRNG,Pad 16 drive strength" "0: Low drive strength,1: High drive strength"
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newline
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bitfld.long 0x10 1. "PAD16INPEN,Pad 16 input enable" "0: Pad input disabled,1: Pad input enabled"
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bitfld.long 0x10 0. "PAD16PULL,Pad 16 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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line.long 0x14 "PADREGF,This register controls the pad configuration controls for PAD23 through PAD20. Writes to this register must be unlocked by the PADKEY register."
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bitfld.long 0x14 27.--29. "PAD23FNCSEL,Pad 23 function select" "0: Configure as the UART0 RX signal,1: IOM/MSPI nCE group 23,2: CTIMER connection 14,3: Configure as GPIO23,4: I2S word clock input,5: Configure as voltage comparator output,6: MSPI data connection 3,7: External XTAL oscillator input"
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bitfld.long 0x14 26. "PAD23STRNG,Pad 23 drive strength" "0: Low drive strength,1: High drive strength"
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newline
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bitfld.long 0x14 25. "PAD23INPEN,Pad 23 input enable" "0: Pad input disabled,1: Pad input enabled"
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bitfld.long 0x14 24. "PAD23PULL,Pad 23 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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newline
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bitfld.long 0x14 19.--21. "PAD22FNCSEL,Pad 22 function select" "0: Configure as the UART0 TX signal,1: IOM/MSPI nCE group 22,2: CTIMER connection 12,3: Configure as GPIO22,4: Configure as the PDM CLK output,5: External LFRC input,6: MSPI data connection 0,7: Configure as the serial trace data output signal"
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bitfld.long 0x14 18. "PAD22STRNG,Pad 22 drive strength" "0: Low drive strength,1: High drive strength"
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newline
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bitfld.long 0x14 17. "PAD22INPEN,Pad 22 input enable" "0: Pad input disabled,1: Pad input enabled"
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bitfld.long 0x14 16. "PAD22PULL,Pad 22 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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newline
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bitfld.long 0x14 11.--13. "PAD21FNCSEL,Pad 21 function select" "0: Configure as the serial wire debug data signal,1: IOM/MSPI nCE group 21,?,3: Configure as GPIO21,4: Configure as UART0 RX input signal,5: Configure as UART1 RX input signal,6: I2S byte clock input,7: Configure as UART1 CTS input signal"
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bitfld.long 0x14 10. "PAD21STRNG,Pad 21 drive strength" "0: Low drive strength,1: High drive strength"
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newline
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bitfld.long 0x14 9. "PAD21INPEN,Pad 21 input enable" "0: Pad input disabled,1: Pad input enabled"
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bitfld.long 0x14 8. "PAD21PULL,Pad 21 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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newline
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bitfld.long 0x14 3.--5. "PAD20FNCSEL,Pad 20 function select" "0: Configure as the serial wire debug clock signal,1: IOM/MSPI nCE group 20,?,3: Configure as GPIO20,4: Configure as UART0 TX output signal,5: Configure as UART1 TX output signal,6: I2S byte clock input,7: Configure as UART1 RTS output signal"
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bitfld.long 0x14 2. "PAD20STRNG,Pad 20 drive strength" "0: Low drive strength,1: High drive strength"
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newline
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bitfld.long 0x14 1. "PAD20INPEN,Pad 20 input enable" "0: Pad input disabled,1: Pad input enabled"
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bitfld.long 0x14 0. "PAD20PULL,Pad 20 pulldown enable" "0: Pulldown disabled,1: Pulldown enabled"
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line.long 0x18 "PADREGG,This register controls the pad configuration controls for PAD27 through PAD24. Writes to this register must be unlocked by the PADKEY register."
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bitfld.long 0x18 30.--31. "PAD27RSEL,Pad 27 pullup resistor selection." "0: Pullup is ~1.5 KOhms,1: Pullup is ~6 KOhms,2: Pullup is ~12 KOhms,3: Pullup is ~24 KOhms"
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bitfld.long 0x18 27.--29. "PAD27FNCSEL,Pad 27 function select" "0: Configure as UART0 RX input signal,1: IOM/MSPI nCE group 27,2: CTIMER connection 5,3: Configure as GPIO27,4: Configure as I2C clock I/O signal from IOMSTR2,5: Configure as SPI clock output signal from IOMSTR2,?,?"
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newline
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bitfld.long 0x18 26. "PAD27STRNG,Pad 27 drive strength" "0: Low drive strength,1: High drive strength"
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bitfld.long 0x18 25. "PAD27INPEN,Pad 27 input enable" "0: Pad input disabled,1: Pad input enabled"
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newline
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bitfld.long 0x18 24. "PAD27PULL,Pad 27 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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bitfld.long 0x18 19.--21. "PAD26FNCSEL,Pad 26 function select" "0: Configure as the external HFRC oscillator input,1: IOM/MSPI nCE group 26,2: CTIMER connection 3,3: Configure as GPIO26,4: SCARD reset output,5: MSPI data connection 1,6: Configure as UART0 TX output signal,7: Configure as UART1 CTS input signal"
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newline
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bitfld.long 0x18 18. "PAD26STRNG,Pad 26 drive strength" "0: Low drive strength,1: High drive strength"
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bitfld.long 0x18 17. "PAD26INPEN,Pad 26 input enable" "0: Pad input disabled,1: Pad input enabled"
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newline
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bitfld.long 0x18 16. "PAD26PULL,Pad 26 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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bitfld.long 0x18 14.--15. "PAD25RSEL,Pad 25 pullup resistor selection." "0: Pullup is ~1.5 KOhms,1: Pullup is ~6 KOhms,2: Pullup is ~12 KOhms,3: Pullup is ~24 KOhms"
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newline
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bitfld.long 0x18 11.--13. "PAD25FNCSEL,Pad 25 function select" "0: Configure as UART1 RX input signal,1: IOM/MSPI nCE group 25,2: CTIMER connection 1,3: Configure as GPIO25,4: Configure as the IOMSTR2 I2C SDA or SPI WIR3..,5: Configure as the IOMSTR2 SPI MISO input signal,?,?"
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bitfld.long 0x18 10. "PAD25STRNG,Pad 25 drive strength" "0: Low drive strength,1: High drive strength"
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newline
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bitfld.long 0x18 9. "PAD25INPEN,Pad 25 input enable" "0: Pad input disabled,1: Pad input enabled"
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bitfld.long 0x18 8. "PAD25PULL,Pad 25 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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newline
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bitfld.long 0x18 3.--5. "PAD24FNCSEL,Pad 24 function select" "0: Configure as UART1 TX output signal,1: IOM/MSPI nCE group 24,2: MSPI data connection 8,3: Configure as GPIO24,4: Configure as UART0 CTS input signal,5: CTIMER connection 21,6: Configure as the 32kHz crystal output signal,7: Configure as the serial trace data output signal"
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bitfld.long 0x18 2. "PAD24STRNG,Pad 24 drive strength" "0: Low drive strength,1: High drive strength"
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newline
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bitfld.long 0x18 1. "PAD24INPEN,Pad 24 input enable" "0: Pad input disabled,1: Pad input enabled"
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bitfld.long 0x18 0. "PAD24PULL,Pad 24 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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line.long 0x1C "PADREGH,This register controls the pad configuration controls for PAD31 through PAD28. Writes to this register must be unlocked by the PADKEY register."
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bitfld.long 0x1C 27.--29. "PAD31FNCSEL,Pad 31 function select" "0: Configure as the analog input for ADC single..,1: IOM/MSPI nCE group 31,2: CTIMER connection 13,3: Configure as GPIO31,4: Configure as the UART0 RX input signal,5: SCARD serial clock output,?,7: Configure as UART1 RTS output signal"
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bitfld.long 0x1C 26. "PAD31STRNG,Pad 31 drive strength" "0: Low drive strength,1: High drive strength"
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newline
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bitfld.long 0x1C 25. "PAD31INPEN,Pad 31 input enable" "0: Pad input disabled,1: Pad input enabled"
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bitfld.long 0x1C 24. "PAD31PULL,Pad 31 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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newline
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bitfld.long 0x1C 19.--21. "PAD30FNCSEL,Pad 30 function select" "0: Configure as the ANATEST1 I/O signal,1: IOM/MSPI nCE group 30,2: CTIMER connection 11,3: Configure as GPIO30,4: Configure as UART0 TX output signal,5: Configure as UART1 RTS output signal,?,7: Configure as the PDM I2S Data output signal"
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bitfld.long 0x1C 18. "PAD30STRNG,Pad 30 drive strength" "0: Low drive strength,1: High drive strength"
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newline
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bitfld.long 0x1C 17. "PAD30INPEN,Pad 30 input enable" "0: Pad input disabled,1: Pad input enabled"
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bitfld.long 0x1C 16. "PAD30PULL,Pad 30 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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newline
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bitfld.long 0x1C 11.--13. "PAD29FNCSEL,Pad 29 function select" "0: Configure as the analog input for ADC single..,1: IOM/MSPI nCE group 29,2: CTIMER connection 9,3: Configure as GPIO29,4: Configure as the UART0 CTS input signal,5: Configure as the UART1 CTS input signal,6: Configure as the UART0 RX input signal,7: Configure as PDM DATA input"
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bitfld.long 0x1C 10. "PAD29STRNG,Pad 29 drive strength" "0: Low drive strength,1: High drive strength"
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newline
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bitfld.long 0x1C 9. "PAD29INPEN,Pad 29 input enable" "0: Pad input disabled,1: Pad input enabled"
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bitfld.long 0x1C 8. "PAD29PULL,Pad 29 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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newline
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bitfld.long 0x1C 3.--5. "PAD28FNCSEL,Pad 28 function select" "0: Configure as the PDM I2S Word Clock input,1: IOM/MSPI nCE group 28,2: CTIMER connection 7,3: Configure as GPIO28,?,5: Configure as the IOMSTR2 SPI MOSI output signal,6: Configure as the UART0 TX output signal,?"
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bitfld.long 0x1C 2. "PAD28STRNG,Pad 28 drive strength" "0: Low drive strength,1: High drive strength"
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newline
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bitfld.long 0x1C 1. "PAD28INPEN,Pad 28 input enable" "0: Pad input disabled,1: Pad input enabled"
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bitfld.long 0x1C 0. "PAD28PULL,Pad 28 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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line.long 0x20 "PADREGI,This register controls the pad configuration controls for PAD35 through PAD32. Writes to this register must be unlocked by the PADKEY register."
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bitfld.long 0x20 27.--29. "PAD35FNCSEL,Pad 35 function select" "0: Configure as the analog input for ADC single..,1: IOM/MSPI nCE group 35,2: Configure as the UART1 TX signal,3: Configure as GPIO35,4: I2S serial data output,5: CTIMER connection 27,6: Configure as the UART0 RTS output,?"
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bitfld.long 0x20 26. "PAD35STRNG,Pad 35 drive strength" "0: Low drive strength,1: High drive strength"
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newline
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bitfld.long 0x20 25. "PAD35INPEN,Pad 35 input enable" "0: Pad input disabled,1: Pad input enabled"
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bitfld.long 0x20 24. "PAD35PULL,Pad 35 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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newline
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bitfld.long 0x20 19.--21. "PAD34FNCSEL,Pad 34 function select" "0: Configure as the analog input for ADC single..,1: IOM/MSPI nCE group 34,2: Configure as the UART1 RTS output,3: Configure as GPIO34,4: Configure as the analog comparator reference 2..,5: Configure as the UART0 RTS output,6: Configure as the UART0 RX input,7: PDM serial data input"
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bitfld.long 0x20 18. "PAD34STRNG,Pad 34 drive strength" "0: Low drive strength,1: High drive strength"
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newline
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bitfld.long 0x20 17. "PAD34INPEN,Pad 34 input enable" "0: Pad input disabled,1: Pad input enabled"
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|
bitfld.long 0x20 16. "PAD34PULL,Pad 34 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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newline
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bitfld.long 0x20 11.--13. "PAD33FNCSEL,Pad 33 function select" "0: Configure as the analog ADC single ended port 5..,1: IOM/MSPI nCE group 33,2: Configure as the 32kHz crystal output signal,3: Configure as GPIO33,?,5: Configure as the UART0 CTS input,6: CTIMER connection 23,7: Configure as the serial trace data output signal"
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bitfld.long 0x20 10. "PAD33STRNG,Pad 33 drive strength" "0: Low drive strength,1: High drive strength"
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newline
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bitfld.long 0x20 9. "PAD33INPEN,Pad 33 input enable" "0: Pad input disabled,1: Pad input enabled"
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bitfld.long 0x20 8. "PAD33PULL,Pad 33 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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newline
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bitfld.long 0x20 3.--5. "PAD32FNCSEL,Pad 32 function select" "0: Configure as the analog input for ADC single..,1: IOM/MSPI nCE group 32,2: CTIMER connection 15,3: Configure as GPIO32,4: SCARD serial data input/output,5: External input to the LFRC oscillator,?,7: Configure as the UART1 CTS input"
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bitfld.long 0x20 2. "PAD32STRNG,Pad 32 drive strength" "0: Low drive strength,1: High drive strength"
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newline
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bitfld.long 0x20 1. "PAD32INPEN,Pad 32 input enable" "0: Pad input disabled,1: Pad input enabled"
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|
bitfld.long 0x20 0. "PAD32PULL,Pad 32 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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line.long 0x24 "PADREGJ,This register controls the pad configuration controls for PAD39 through PAD36. Writes to this register must be unlocked by the PADKEY register."
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bitfld.long 0x24 30.--31. "PAD39RSEL,Pad 39 pullup resistor selection." "0: Pullup is ~1.5 KOhms,1: Pullup is ~6 KOhms,2: Pullup is ~12 KOhms,3: Pullup is ~24 KOhms"
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bitfld.long 0x24 27.--29. "PAD39FNCSEL,Pad 39 function select" "0: Configure as the UART0 TX output signal,1: Configure as the UART1 TX output signal,2: CTIMER connection 25,3: Configure as GPIO39,4: Configure as the IOMSTR4 I2C SCL signal,5: Configure as the IOMSTR4 SPI SCK signal,?,?"
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newline
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bitfld.long 0x24 26. "PAD39STRNG,Pad 39 drive strength" "0: Low drive strength,1: High drive strength"
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bitfld.long 0x24 25. "PAD39INPEN,Pad 39 input enable" "0: Pad input disabled,1: Pad input enabled"
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newline
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bitfld.long 0x24 24. "PAD39PULL,Pad 39 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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bitfld.long 0x24 19.--21. "PAD38FNCSEL,Pad 38 function select" "0: Configure as the ADC Trigger 3 signal,1: IOM/MSPI nCE group 38,2: Configure as the UART0 CTS signal,3: Configure as GPIO38,?,5: Configure as the IOMSTR3 SPI MOSI output signal,6: Configure as the UART1 RX input signal,?"
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newline
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bitfld.long 0x24 18. "PAD38STRNG,Pad 38 drive strength" "0: Low drive strength,1: High drive strength"
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bitfld.long 0x24 17. "PAD38INPEN,Pad 38 input enable" "0: Pad input disabled,1: Pad input enabled"
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newline
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bitfld.long 0x24 16. "PAD38PULL,Pad 38 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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bitfld.long 0x24 15. "PAD37PWRDN,Pad 37 VSS power switch enable" "0: Power switch disabled,1: Power switch enabled (switch to GND)"
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newline
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bitfld.long 0x24 11.--13. "PAD37FNCSEL,Pad 37 function select" "0: Configure as the ADC Trigger 2 signal,1: IOM/MSPI nCE group 37,2: Configure as the UART0 RTS output signal,3: Configure as GPIO37,4: SCARD serial data input/output,5: Configure as the UART1 TX output signal,6: Configure as the PDM CLK output signal,7: CTIMER connection 29"
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bitfld.long 0x24 10. "PAD37STRNG,Pad 37 drive strength" "0: Low drive strength,1: High drive strength"
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newline
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bitfld.long 0x24 9. "PAD37INPEN,Pad 37 input enable" "0: Pad input disabled,1: Pad input enabled"
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bitfld.long 0x24 8. "PAD37PULL,Pad 37 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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newline
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sif (cpuis("AMA3B1KK")||cpuis("AMAP31KK"))
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bitfld.long 0x24 6. "PAD36PWRUP,Pad 36 VDD power switch enable" "0: Power switch disabled,1: Power switch enabled (switched to VDD)"
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endif
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bitfld.long 0x24 3.--5. "PAD36FNCSEL,Pad 36 function select" "0: Configure as the ADC Trigger 1 signal,1: IOM/MSPI nCE group 36,2: Configure as the UART1 RX input signal,3: Configure as GPIO36,4: Configure as the 32kHz output clock from the..,5: Configure as the UART1 CTS input signal,6: Configure as the UART0 CTS input signal,7: PDM serial data input"
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newline
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bitfld.long 0x24 2. "PAD36STRNG,Pad 36 drive strength" "0: Low drive strength,1: High drive strength"
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bitfld.long 0x24 1. "PAD36INPEN,Pad 36 input enable" "0: Pad input disabled,1: Pad input enabled"
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newline
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bitfld.long 0x24 0. "PAD36PULL,Pad 36 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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line.long 0x28 "PADREGK,This register controls the pad configuration controls for PAD43 through PAD40. Writes to this register must be unlocked by the PADKEY register."
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bitfld.long 0x28 30.--31. "PAD43RSEL,Pad 43 pullup resistor selection." "0: Pullup is ~1.5 KOhms,1: Pullup is ~6 KOhms,2: Pullup is ~12 KOhms,3: Pullup is ~24 KOhms"
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bitfld.long 0x28 27.--29. "PAD43FNCSEL,Pad 43 function select" "0: Configure as the UART1 RX input signal,1: IOM/MSPI nCE group 43,2: CTIMER connection 18,3: Configure as GPIO43,4: Configure as the IOMSTR3 I2C SDA or SPI WIR3..,5: Configure as the IOMSTR3 SPI MISO signal,?,?"
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newline
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bitfld.long 0x28 26. "PAD43STRNG,Pad 43 drive strength" "0: Low drive strength,1: High drive strength"
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bitfld.long 0x28 25. "PAD43INPEN,Pad 43 input enable" "0: Pad input disabled,1: Pad input enabled"
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newline
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bitfld.long 0x28 24. "PAD43PULL,Pad 43 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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bitfld.long 0x28 22.--23. "PAD42RSEL,Pad 42 pullup resistor selection." "0: Pullup is ~1.5 KOhms,1: Pullup is ~6 KOhms,2: Pullup is ~12 KOhms,3: Pullup is ~24 KOhms"
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newline
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bitfld.long 0x28 19.--21. "PAD42FNCSEL,Pad 42 function select" "0: Configure as the UART1 TX output signal,1: IOM/MSPI nCE group 42,2: CTIMER connection 16,3: Configure as GPIO42,4: Configure as the IOMSTR3 I2C SCL clock I/O signal,5: Configure as the IOMSTR3 SPI SCK output,?,?"
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bitfld.long 0x28 18. "PAD42STRNG,Pad 42 drive strength" "0: Low drive strength,1: High drive strength"
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newline
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bitfld.long 0x28 17. "PAD42INPEN,Pad 42 input enable" "0: Pad input disabled,1: Pad input enabled"
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bitfld.long 0x28 16. "PAD42PULL,Pad 42 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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newline
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bitfld.long 0x28 15. "PAD41PWRDN,Pad 41 power switch enable" "0: Power switch disabled,1: Power switch enabled (Switch pad to VSS)"
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bitfld.long 0x28 11.--13. "PAD41FNCSEL,Pad 41 function select" "0: IOM/MSPI nCE group 41,?,2: Configure as the serial wire debug SWO signal,3: Configure as GPIO41,4: I2S word clock input,5: Configure as the UART1 RTS output signal,6: Configure as the UART0 TX output signal,7: Configure as the UART0 RTS output signal"
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newline
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bitfld.long 0x28 10. "PAD41STRNG,Pad 41 drive strength" "0: Low drive strength,1: High drive strength"
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bitfld.long 0x28 9. "PAD41INPEN,Pad 41 input enable" "0: Pad input disabled,1: Pad input enabled"
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newline
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bitfld.long 0x28 8. "PAD41PULL,Pad 41 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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bitfld.long 0x28 6.--7. "PAD40RSEL,Pad 40 pullup resistor selection." "0: Pullup is ~1.5 KOhms,1: Pullup is ~6 KOhms,2: Pullup is ~12 KOhms,3: Pullup is ~24 KOhms"
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newline
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bitfld.long 0x28 3.--5. "PAD40FNCSEL,Pad 40 function select" "0: Configure as the UART0 RX input signal,1: Configure as the UART1 RX input signal,2: Configure as the ADC Trigger 0 signal,3: Configure as GPIO40,4: Configure as the IOMSTR4 I2C SDA or SPI WIR3..,5: Configure as the IOMSTR4 SPI MISO input signal,?,?"
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bitfld.long 0x28 2. "PAD40STRNG,Pad 40 drive strength" "0: Low drive strength,1: High drive strength"
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newline
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bitfld.long 0x28 1. "PAD40INPEN,Pad 40 input enable" "0: Pad input disabled,1: Pad input enabled"
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bitfld.long 0x28 0. "PAD40PULL,Pad 40 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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line.long 0x2C "PADREGL,This register controls the pad configuration controls for PAD47 through PAD44. Writes to this register must be unlocked by the PADKEY register."
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bitfld.long 0x2C 27.--29. "PAD47FNCSEL,Pad 47 function select" "0: Configure as the 32kHz output clock from the..,1: IOM/MSPI nCE group 47,2: CTIMER connection 26,3: Configure as GPIO47,?,5: Configure as the IOMSTR5 SPI MOSI output signal,6: Configure as the UART1 RX input signal,?"
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bitfld.long 0x2C 26. "PAD47STRNG,Pad 47 drive strength" "0: Low drive strength,1: High drive strength"
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newline
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bitfld.long 0x2C 25. "PAD47INPEN,Pad 47 input enable" "0: Pad input disabled,1: Pad input enabled"
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bitfld.long 0x2C 24. "PAD47PULL,Pad 47 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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newline
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bitfld.long 0x2C 19.--21. "PAD46FNCSEL,Pad 46 function select" "0: Configure as the 32kHz output clock from the..,1: IOM/MSPI nCE group 46,2: CTIMER connection 24,3: Configure as GPIO46,4: SCARD reset output,5: PDM serial clock output,6: Configure as the UART1 TX output signal,7: Configure as the serial wire debug SWO signal"
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bitfld.long 0x2C 18. "PAD46STRNG,Pad 46 drive strength" "0: Low drive strength,1: High drive strength"
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newline
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bitfld.long 0x2C 17. "PAD46INPEN,Pad 46 input enable" "0: Pad input disabled,1: Pad input enabled"
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bitfld.long 0x2C 16. "PAD46PULL,Pad 46 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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newline
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bitfld.long 0x2C 11.--13. "PAD45FNCSEL,Pad 45 function select" "0: Configure as the UART1 CTS input signal,1: IOM/MSPI nCE group 45,2: CTIMER connection 22,3: Configure as GPIO45,4: I2S serial data output,5: PDM serial data input,6: Configure as the SPI channel 5 nCE signal from..,7: Configure as the serial wire debug SWO signal"
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bitfld.long 0x2C 10. "PAD45STRNG,Pad 45 drive strength" "0: Low drive strength,1: High drive strength"
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newline
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bitfld.long 0x2C 9. "PAD45INPEN,Pad 45 input enable" "0: Pad input disabled,1: Pad input enabled"
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bitfld.long 0x2C 8. "PAD45PULL,Pad 45 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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newline
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sif (cpuis("AMA3B2KK"))
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bitfld.long 0x2C 3.--5. "PAD44FNCSEL,Pad 44 function select" "0: Configure as the UART1 RTS output signal,1: IOM/MSPI nCE group 44,2: CTIMER connection 20,3: Configure as GPIO44,?,5: Configure as the IOMSTR4 SPI MOSI signal,6: Configure as the SPI channel 6 nCE signal from..,?"
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|
newline
|
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endif
|
|
sif (cpuis("AMA3B1KK")||cpuis("AMAP31KK"))
|
|
bitfld.long 0x2C 3.--5. "PAD44FNCSEL,Pad 44 function select" "0: Configure as the UART1 RTS output signal,1: IOM/MSPI nCE group 44,2: CTIMER connection 20,3: Configure as GPIO44,?,5: Configure as the IOMSTR4 SPI MOSI signal,6: Configure as the UART0 TX output signal,?"
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newline
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endif
|
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bitfld.long 0x2C 2. "PAD44STRNG,Pad 44 drive strength" "0: Low drive strength,1: High drive strength"
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bitfld.long 0x2C 1. "PAD44INPEN,Pad 44 input enable" "0: Pad input disabled,1: Pad input enabled"
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newline
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bitfld.long 0x2C 0. "PAD44PULL,Pad 44 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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line.long 0x30 "PADREGM,This register controls the pad configuration controls for PAD49 through PAD48. Writes to this register must be unlocked by the PADKEY register."
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sif (cpuis("AMA3B2KK"))
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bitfld.long 0x30 27.--29. "PAD51FNCSEL,Pad 51 function select" "0: Configure as the MSPI1 0 signal,1: IOM/MSPI nCE group 51,2: CTIMER connection 1,3: Configure as GPIO51,?,?,?,?"
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endif
|
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sif (cpuis("AMA3B2KK"))
|
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bitfld.long 0x30 26. "PAD51STRNG,Pad 51 drive strength" "0: Low drive strength,1: High drive strength"
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newline
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endif
|
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sif (cpuis("AMA3B2KK"))
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bitfld.long 0x30 25. "PAD51INPEN,Pad 51 input enable" "0: Pad input disabled,1: Pad input enabled"
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endif
|
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sif (cpuis("AMA3B2KK"))
|
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bitfld.long 0x30 24. "PAD51PULL,Pad 51 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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newline
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endif
|
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sif (cpuis("AMA3B2KK"))
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bitfld.long 0x30 19.--21. "PAD50FNCSEL,Pad 50 function select" "0: Configure as the SWO output,1: IOM/MSPI nCE group 50,2: CTIMER connection 0,3: Configure as GPIO50,4: Configure as the UART0 TX output,5: Configure as the UART0 RX input,6: Configure as the UART1 TX output,7: Configure as the UART1 RX input"
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endif
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sif (cpuis("AMA3B2KK"))
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bitfld.long 0x30 18. "PAD50STRNG,Pad 50 drive strength" "0: Low drive strength,1: High drive strength"
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newline
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endif
|
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sif (cpuis("AMA3B2KK"))
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bitfld.long 0x30 17. "PAD50INPEN,Pad 50 input enable" "0: Pad input disabled,1: Pad input enabled"
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endif
|
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sif (cpuis("AMA3B2KK"))
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bitfld.long 0x30 16. "PAD50PULL,Pad 50 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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newline
|
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endif
|
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bitfld.long 0x30 14.--15. "PAD49RSEL,Pad 49 pullup resistor selection." "0: Pullup is ~1.5 KOhms,1: Pullup is ~6 KOhms,2: Pullup is ~12 KOhms,3: Pullup is ~24 KOhms"
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bitfld.long 0x30 11.--13. "PAD49FNCSEL,Pad 49 function select" "0: Configure as the UART0 RX input signal,1: IOM/MSPPI nCE group 49,2: CTIMER connection 30,3: Configure as GPIO49,4: Configure as the IOMSTR5 I2C SDA or SPI WIR3..,5: Configure as the IOMSTR5 SPI MISO input signal,?,?"
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newline
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bitfld.long 0x30 10. "PAD49STRNG,Pad 49 drive strength" "0: Low drive strength,1: High drive strength"
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bitfld.long 0x30 9. "PAD49INPEN,Pad 49 input enable" "0: Pad input disabled,1: Pad input enabled"
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newline
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bitfld.long 0x30 8. "PAD49PULL,Pad 49 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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bitfld.long 0x30 6.--7. "PAD48RSEL,Pad 48 pullup resistor selection." "0: Pullup is ~1.5 KOhms,1: Pullup is ~6 KOhms,2: Pullup is ~12 KOhms,3: Pullup is ~24 KOhms"
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newline
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bitfld.long 0x30 3.--5. "PAD48FNCSEL,Pad 48 function select" "0: Configure as the UART0 TX output signal,1: IOM/MSPI nCE group 48,2: CTIMER connection 28,3: Configure as GPIO48,4: Configure as the IOMSTR5 I2C SCL clock I/O signal,5: Configure as the IOMSTR5 SPI SCK output,?,?"
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bitfld.long 0x30 2. "PAD48STRNG,Pad 48 drive strength" "0: Low drive strength,1: High drive strength"
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newline
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bitfld.long 0x30 1. "PAD48INPEN,Pad 48 input enable" "0: Pad input disabled,1: Pad input enabled"
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bitfld.long 0x30 0. "PAD48PULL,Pad 48 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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|
sif (cpuis("AMA3B1KK")||cpuis("AMAP31KK"))
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group.long 0x40++0x1B
|
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line.long 0x0 "CFGA,GPIO configuration controls for GPIO[7:0]. Writes to this register must be unlocked by the PADKEY register."
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|
bitfld.long 0x0 31. "GPIO7INTD,GPIO7 interrupt direction nCE polarity." "0: FNCSEL = 0x0 - nCE polarity active low,1: FNCSEL = 0x0 - nCE polarity active high"
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bitfld.long 0x0 29.--30. "GPIO7OUTCFG,GPIO7 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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newline
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bitfld.long 0x0 28. "GPIO7INCFG,GPIO7 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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|
bitfld.long 0x0 27. "GPIO6INTD,GPIO6 interrupt direction." "0: INCFG = 1 - No interrupt on GPIO transition,1: INCFG = 1 - Interrupt on either low to high or.."
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|
newline
|
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bitfld.long 0x0 25.--26. "GPIO6OUTCFG,GPIO6 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0x0 24. "GPIO6INCFG,GPIO6 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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|
newline
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bitfld.long 0x0 23. "GPIO5INTD,GPIO5 interrupt direction." "0: INCFG = 1 - No interrupt on GPIO transition,1: INCFG = 1 - Interrupt on either low to high or.."
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|
bitfld.long 0x0 21.--22. "GPIO5OUTCFG,GPIO5 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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newline
|
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bitfld.long 0x0 20. "GPIO5INCFG,GPIO5 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
|
|
bitfld.long 0x0 19. "GPIO4INTD,GPIO4 interrupt direction." "0: FNCSEL = 0x2 - nCE polarity active low,1: FNCSEL = 0x2 - nCE polarity active high"
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newline
|
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bitfld.long 0x0 17.--18. "GPIO4OUTCFG,GPIO4 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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|
bitfld.long 0x0 16. "GPIO4INCFG,GPIO4 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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|
newline
|
|
bitfld.long 0x0 15. "GPIO3INTD,GPIO3 interrupt direction." "0: FNCSEL = 0x2 - nCE polarity active low,1: FNCSEL = 0x2 - nCE polarity active high"
|
|
bitfld.long 0x0 13.--14. "GPIO3OUTCFG,GPIO3 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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newline
|
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bitfld.long 0x0 12. "GPIO3INCFG,GPIO3 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
|
|
bitfld.long 0x0 11. "GPIO2INTD,GPIO2 interrupt direction." "0: FNCSEL = 0x7 - nCE polarity active low,1: FNCSEL = 0x7 - nCE polarity active high"
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newline
|
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bitfld.long 0x0 9.--10. "GPIO2OUTCFG,GPIO2 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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|
bitfld.long 0x0 8. "GPIO2INCFG,GPIO2 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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|
newline
|
|
bitfld.long 0x0 7. "GPIO1INTD,GPIO1 interrupt direction." "0: FNCSEL = 0x7 - nCE polarity active low,1: FNCSEL = 0x7 - nCE polarity active high"
|
|
bitfld.long 0x0 5.--6. "GPIO1OUTCFG,GPIO1 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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|
newline
|
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bitfld.long 0x0 4. "GPIO1INCFG,GPIO1 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
|
|
bitfld.long 0x0 3. "GPIO0INTD,GPIO0 interrupt direction." "0: FNCSEL = 0x7 - nCE polarity active low,1: FNCSEL = 0x7 - nCE polarity active high"
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|
newline
|
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bitfld.long 0x0 1.--2. "GPIO0OUTCFG,GPIO0 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
|
|
bitfld.long 0x0 0. "GPIO0INCFG,GPIO0 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
|
|
line.long 0x4 "CFGB,GPIO configuration controls for GPIO[15:8]. Writes to this register must be unlocked by the PADKEY register."
|
|
bitfld.long 0x4 31. "GPIO15INTD,GPIO15 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
|
|
bitfld.long 0x4 29.--30. "GPIO15OUTCFG,GPIO15 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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|
newline
|
|
bitfld.long 0x4 28. "GPIO15INCFG,GPIO15 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
|
|
bitfld.long 0x4 27. "GPIO14INTD,GPIO14 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
|
|
newline
|
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bitfld.long 0x4 25.--26. "GPIO14OUTCFG,GPIO14 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
|
|
bitfld.long 0x4 24. "GPIO14INCFG,GPIO14 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
|
|
newline
|
|
bitfld.long 0x4 23. "GPIO13INTD,GPIO13 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
|
|
bitfld.long 0x4 21.--22. "GPIO13OUTCFG,GPIO13 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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|
newline
|
|
bitfld.long 0x4 20. "GPIO13INCFG,GPIO13 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
|
|
bitfld.long 0x4 19. "GPIO12INTD,GPIO12 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
|
|
newline
|
|
bitfld.long 0x4 17.--18. "GPIO12OUTCFG,GPIO12 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
|
|
bitfld.long 0x4 16. "GPIO12INCFG,GPIO12 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
|
|
newline
|
|
bitfld.long 0x4 15. "GPIO11INTD,GPIO11 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
|
|
bitfld.long 0x4 13.--14. "GPIO11OUTCFG,GPIO11 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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|
newline
|
|
bitfld.long 0x4 12. "GPIO11INCFG,GPIO11 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
|
|
bitfld.long 0x4 11. "GPIO10INTD,GPIO10 interrupt direction." "0: FNCSEL = 0x2 - nCE polarity active low,1: FNCSEL = 0x2 - nCE polarity active high"
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|
newline
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bitfld.long 0x4 9.--10. "GPIO10OUTCFG,GPIO10 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0x4 8. "GPIO10INCFG,GPIO10 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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bitfld.long 0x4 7. "GPIO9INTD,GPIO9 interrupt direction." "0: FNCSEL = 0x2 - nCE polarity active low,1: FNCSEL = 0x2 - nCE polarity active high"
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bitfld.long 0x4 5.--6. "GPIO9OUTCFG,GPIO9 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0x4 4. "GPIO9INCFG,GPIO9 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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bitfld.long 0x4 3. "GPIO8INTD,GPIO8 interrupt direction." "0: FNCSEL = 0x2 - nCE polarity active low,1: FNCSEL = 0x2 - nCE polarity active high"
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bitfld.long 0x4 1.--2. "GPIO8OUTCFG,GPIO8 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0x4 0. "GPIO8INCFG,GPIO8 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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line.long 0x8 "CFGC,GPIO configuration controls for GPIO[23:16]. Writes to this register must be unlocked by the PADKEY register."
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bitfld.long 0x8 31. "GPIO23INTD,GPIO23 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
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bitfld.long 0x8 29.--30. "GPIO23OUTCFG,GPIO23 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0x8 28. "GPIO23INCFG,GPIO23 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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bitfld.long 0x8 27. "GPIO22INTD,GPIO22 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
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bitfld.long 0x8 25.--26. "GPIO22OUTCFG,GPIO22 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0x8 24. "GPIO22INCFG,GPIO22 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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bitfld.long 0x8 23. "GPIO21INTD,GPIO21 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
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bitfld.long 0x8 21.--22. "GPIO21OUTCFG,GPIO21 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0x8 20. "GPIO21INCFG,GPIO21 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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bitfld.long 0x8 19. "GPIO20INTD,GPIO20 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
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bitfld.long 0x8 17.--18. "GPIO20OUTCFG,GPIO20 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0x8 16. "GPIO20INCFG,GPIO20 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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bitfld.long 0x8 15. "GPIO19INTD,GPIO19 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
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bitfld.long 0x8 13.--14. "GPIO19OUTCFG,GPIO19 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0x8 12. "GPIO19INCFG,GPIO19 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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bitfld.long 0x8 11. "GPIO18INTD,GPIO18 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
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bitfld.long 0x8 9.--10. "GPIO18OUTCFG,GPIO18 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0x8 8. "GPIO18INCFG,GPIO18 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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bitfld.long 0x8 7. "GPIO17INTD,GPIO17 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
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bitfld.long 0x8 5.--6. "GPIO17OUTCFG,GPIO17 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0x8 4. "GPIO17INCFG,GPIO17 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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bitfld.long 0x8 3. "GPIO16INTD,GPIO16 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
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bitfld.long 0x8 1.--2. "GPIO16OUTCFG,GPIO16 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0x8 0. "GPIO16INCFG,GPIO16 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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line.long 0xC "CFGD,GPIO configuration controls for GPIO[31:24]. Writes to this register must be unlocked by the PADKEY register."
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bitfld.long 0xC 31. "GPIO31INTD,GPIO31 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
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bitfld.long 0xC 29.--30. "GPIO31OUTCFG,GPIO31 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0xC 28. "GPIO31INCFG,GPIO31 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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bitfld.long 0xC 27. "GPIO30INTD,GPIO30 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
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bitfld.long 0xC 25.--26. "GPIO30OUTCFG,GPIO30 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0xC 24. "GPIO30INCFG,GPIO30 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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bitfld.long 0xC 23. "GPIO29INTD,GPIO29 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
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bitfld.long 0xC 21.--22. "GPIO29OUTCFG,GPIO29 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0xC 20. "GPIO29INCFG,GPIO29 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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bitfld.long 0xC 19. "GPIO28INTD,GPIO28 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
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bitfld.long 0xC 17.--18. "GPIO28OUTCFG,GPIO28 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0xC 16. "GPIO28INCFG,GPIO28 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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bitfld.long 0xC 15. "GPIO27INTD,GPIO27 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
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bitfld.long 0xC 13.--14. "GPIO27OUTCFG,GPIO27 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0xC 12. "GPIO27INCFG,GPIO27 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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bitfld.long 0xC 11. "GPIO26INTD,GPIO26 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
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bitfld.long 0xC 9.--10. "GPIO26OUTCFG,GPIO26 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0xC 8. "GPIO26INCFG,GPIO26 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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bitfld.long 0xC 7. "GPIO25INTD,GPIO25 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
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bitfld.long 0xC 5.--6. "GPIO25OUTCFG,GPIO25 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0xC 4. "GPIO25INCFG,GPIO25 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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bitfld.long 0xC 3. "GPIO24INTD,GPIO24 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
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bitfld.long 0xC 1.--2. "GPIO24OUTCFG,GPIO24 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0xC 0. "GPIO24INCFG,GPIO24 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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line.long 0x10 "CFGE,GPIO configuration controls for GPIO[39:32]. Writes to this register must be unlocked by the PADKEY register."
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bitfld.long 0x10 31. "GPIO39INTD,GPIO39 interrupt direction." "0: INCFG = 1 - No interrupt on GPIO transition,1: INCFG = 1 - Interrupt on either low to high or.."
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bitfld.long 0x10 29.--30. "GPIO39OUTCFG,GPIO39 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0x10 28. "GPIO39INCFG,GPIO39 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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bitfld.long 0x10 27. "GPIO38INTD,GPIO38 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
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bitfld.long 0x10 25.--26. "GPIO38OUTCFG,GPIO38 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0x10 24. "GPIO38INCFG,GPIO38 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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bitfld.long 0x10 23. "GPIO37INTD,GPIO37 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
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bitfld.long 0x10 21.--22. "GPIO37OUTCFG,GPIO37 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0x10 20. "GPIO37INCFG,GPIO37 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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bitfld.long 0x10 19. "GPIO36INTD,GPIO36 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
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bitfld.long 0x10 17.--18. "GPIO36OUTCFG,GPIO36 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0x10 16. "GPIO36INCFG,GPIO36 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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bitfld.long 0x10 15. "GPIO35INTD,GPIO35 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
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bitfld.long 0x10 13.--14. "GPIO35OUTCFG,GPIO35 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0x10 12. "GPIO35INCFG,GPIO35 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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bitfld.long 0x10 11. "GPIO34INTD,GPIO34 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
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bitfld.long 0x10 9.--10. "GPIO34OUTCFG,GPIO34 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0x10 8. "GPIO34INCFG,GPIO34 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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bitfld.long 0x10 7. "GPIO33INTD,GPIO33 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
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bitfld.long 0x10 5.--6. "GPIO33OUTCFG,GPIO33 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0x10 4. "GPIO33INCFG,GPIO33 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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bitfld.long 0x10 3. "GPIO32INTD,GPIO32 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
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bitfld.long 0x10 1.--2. "GPIO32OUTCFG,GPIO32 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0x10 0. "GPIO32INCFG,GPIO32 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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line.long 0x14 "CFGF,GPIO configuration controls for GPIO[47:40]. Writes to this register must be unlocked by the PADKEY register."
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bitfld.long 0x14 31. "GPIO47INTD,GPIO47 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
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bitfld.long 0x14 29.--30. "GPIO47OUTCFG,GPIO47 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0x14 28. "GPIO47INCFG,GPIO47 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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bitfld.long 0x14 27. "GPIO46INTD,GPIO46 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
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bitfld.long 0x14 25.--26. "GPIO46OUTCFG,GPIO46 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0x14 24. "GPIO46INCFG,GPIO46 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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bitfld.long 0x14 23. "GPIO45INTD,GPIO45 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
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bitfld.long 0x14 21.--22. "GPIO45OUTCFG,GPIO45 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0x14 20. "GPIO45INCFG,GPIO45 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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bitfld.long 0x14 19. "GPIO44INTD,GPIO44 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
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bitfld.long 0x14 17.--18. "GPIO44OUTCFG,GPIO44 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0x14 16. "GPIO44INCFG,GPIO44 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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bitfld.long 0x14 15. "GPIO43INTD,GPIO43 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
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bitfld.long 0x14 13.--14. "GPIO43OUTCFG,GPIO43 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0x14 12. "GPIO43INCFG,GPIO43 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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bitfld.long 0x14 11. "GPIO42INTD,GPIO42 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
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bitfld.long 0x14 9.--10. "GPIO42OUTCFG,GPIO42 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0x14 8. "GPIO42INCFG,GPIO42 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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bitfld.long 0x14 7. "GPIO41INTD,GPIO41 interrupt direction." "0: FNCSEL = 0x0 - nCE polarity active low,1: FNCSEL = 0x0 - nCE polarity active high"
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bitfld.long 0x14 5.--6. "GPIO41OUTCFG,GPIO41 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0x14 4. "GPIO41INCFG,GPIO41 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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bitfld.long 0x14 3. "GPIO40INTD,GPIO40 interrupt direction." "0: INCFG = 1 - No interrupt on GPIO transition,1: INCFG = 1 - Interrupt on either low to high or.."
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bitfld.long 0x14 1.--2. "GPIO40OUTCFG,GPIO40 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0x14 0. "GPIO40INCFG,GPIO40 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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line.long 0x18 "CFGG,GPIO configuration controls for GPIO[49:48]. Writes to this register must be unlocked by the PADKEY register."
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bitfld.long 0x18 7. "GPIO49INTD,GPIO49 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
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bitfld.long 0x18 5.--6. "GPIO49OUTCFG,GPIO49 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
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bitfld.long 0x18 4. "GPIO49INCFG,GPIO49 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
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bitfld.long 0x18 3. "GPIO48INTD,GPIO48 interrupt direction." "0: FNCSEL = 0x1 - nCE polarity active low,1: FNCSEL = 0x1 - nCE polarity active high"
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bitfld.long 0x18 1.--2. "GPIO48OUTCFG,GPIO48 output configuration." "0: FNCSEL = 0x3 - Output disabled,1: FNCSEL = 0x3 - Output is push-pull,2: FNCSEL = 0x3 - Output is open drain,3: FNCSEL = 0x3 - Output is tri-state"
|
|
bitfld.long 0x18 0. "GPIO48INCFG,GPIO48 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Readback will always be zero"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "PADKEY,Lock state of the PINCFG and GPIO configuration registers. Write a value of 0x73 to unlock write access to the PAD and GPIO configuration registers. Write any other value to lock access to PAD and GPIO registers. This register also indicates lock.."
|
|
hexmask.long 0x0 0.--31. 1. "PADKEY,Key register value."
|
|
group.long 0x88++0x27
|
|
line.long 0x0 "WTA,GPIO Output Register A (31-0)"
|
|
hexmask.long 0x0 0.--31. 1. "WTA,GPIO31-0 write data."
|
|
line.long 0x4 "WTB,GPIO Output Register B (49-32)"
|
|
hexmask.long.tbyte 0x4 0.--17. 1. "WTB,GPIO49-32 write data."
|
|
line.long 0x8 "WTSA,GPIO Output Register A Set (31-0)"
|
|
hexmask.long 0x8 0.--31. 1. "WTSA,Set the GPIO31-0 write data."
|
|
line.long 0xC "WTSB,GPIO Output Register B Set (49-32)"
|
|
hexmask.long.tbyte 0xC 0.--17. 1. "WTSB,Set the GPIO49-32 write data."
|
|
line.long 0x10 "WTCA,GPIO Output Register A Clear (31-0)"
|
|
hexmask.long 0x10 0.--31. 1. "WTCA,Clear the GPIO31-0 write data."
|
|
line.long 0x14 "WTCB,GPIO Output Register B Clear (49-32)"
|
|
hexmask.long.tbyte 0x14 0.--17. 1. "WTCB,Clear the GPIO49-32 write data."
|
|
line.long 0x18 "ENA,GPIO Enable Register A (31-0)"
|
|
hexmask.long 0x18 0.--31. 1. "ENA,GPIO31-0 output enables"
|
|
line.long 0x1C "ENB,GPIO Enable Register B (49-32)"
|
|
hexmask.long.tbyte 0x1C 0.--17. 1. "ENB,GPIO49-32 output enables"
|
|
line.long 0x20 "ENSA,GPIO Enable Register A Set (31-0)"
|
|
hexmask.long 0x20 0.--31. 1. "ENSA,Set the GPIO31-0 output enables"
|
|
line.long 0x24 "ENSB,GPIO Enable Register B Set (49-32)"
|
|
hexmask.long.tbyte 0x24 0.--17. 1. "ENSB,Set the GPIO49-32 output enables"
|
|
group.long 0xB4++0x67
|
|
line.long 0x0 "ENCA,GPIO Enable Register A Clear (31-0)"
|
|
hexmask.long 0x0 0.--31. 1. "ENCA,Clear the GPIO31-0 output enables"
|
|
line.long 0x4 "ENCB,GPIO Enable Register B Clear (49-32)"
|
|
hexmask.long.tbyte 0x4 0.--17. 1. "ENCB,Clear the GPIO49-32 output enables"
|
|
line.long 0x8 "STMRCAP,STIMER Capture trigger select and enable."
|
|
bitfld.long 0x8 30. "STPOL3,STIMER Capture 3 Polarity." "0: Capture on low to high GPIO transition,1: Capture on high to low GPIO transition"
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|
hexmask.long.byte 0x8 24.--29. 1. "STSEL3,STIMER Capture 3 Select."
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|
newline
|
|
bitfld.long 0x8 22. "STPOL2,STIMER Capture 2 Polarity." "0: Capture on low to high GPIO transition,1: Capture on high to low GPIO transition"
|
|
hexmask.long.byte 0x8 16.--21. 1. "STSEL2,STIMER Capture 2 Select."
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|
newline
|
|
bitfld.long 0x8 14. "STPOL1,STIMER Capture 1 Polarity." "0: Capture on low to high GPIO transition,1: Capture on high to low GPIO transition"
|
|
hexmask.long.byte 0x8 8.--13. 1. "STSEL1,STIMER Capture 1 Select."
|
|
newline
|
|
bitfld.long 0x8 6. "STPOL0,STIMER Capture 0 Polarity." "0: Capture on low to high GPIO transition,1: Capture on high to low GPIO transition"
|
|
hexmask.long.byte 0x8 0.--5. 1. "STSEL0,STIMER Capture 0 Select."
|
|
line.long 0xC "IOM0IRQ,IOMSTR0 IRQ select for flow control."
|
|
hexmask.long.byte 0xC 0.--5. 1. "IOM0IRQ,IOMSTR0 IRQ pad select."
|
|
line.long 0x10 "IOM1IRQ,IOMSTR1 IRQ select for flow control."
|
|
hexmask.long.byte 0x10 0.--5. 1. "IOM1IRQ,IOMSTR1 IRQ pad select."
|
|
line.long 0x14 "IOM2IRQ,IOMSTR2 IRQ select for flow control."
|
|
hexmask.long.byte 0x14 0.--5. 1. "IOM2IRQ,IOMSTR2 IRQ pad select."
|
|
line.long 0x18 "IOM3IRQ,IOMSTR3 IRQ select for flow control."
|
|
hexmask.long.byte 0x18 0.--5. 1. "IOM3IRQ,IOMSTR3 IRQ pad select."
|
|
line.long 0x1C "IOM4IRQ,IOMSTR4 IRQ select for flow control."
|
|
hexmask.long.byte 0x1C 0.--5. 1. "IOM4IRQ,IOMSTR4 IRQ pad select."
|
|
line.long 0x20 "IOM5IRQ,IOMSTR5 IRQ select for flow control."
|
|
hexmask.long.byte 0x20 0.--5. 1. "IOM5IRQ,IOMSTR5 IRQ pad select."
|
|
line.long 0x24 "BLEIFIRQ,BLE IF IRQ select for flow control."
|
|
hexmask.long.byte 0x24 0.--5. 1. "BLEIFIRQ,BLEIF IRQ pad select."
|
|
line.long 0x28 "GPIOOBS,GPIO Observation mode sample register"
|
|
hexmask.long.word 0x28 0.--15. 1. "OBS_DATA,Sample of the data output on the GPIO observation port. May have async sampling issues as the data is not synronized to the read operation. Intended for debug purposes only"
|
|
line.long 0x2C "ALTPADCFGA,This register has additional configuration control for pads 3. 2. 1. 0"
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|
bitfld.long 0x2C 28. "PAD3_SR,Pad 3 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x2C 24. "PAD3_DS1,Pad 3 high order drive strength selection. Used in conjunction with PAD3STRNG field to set the pad drive strength." "0,1"
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|
newline
|
|
bitfld.long 0x2C 20. "PAD2_SR,Pad 2 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x2C 16. "PAD2_DS1,Pad 2 high order drive strength selection. Used in conjunction with PAD2STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x2C 12. "PAD1_SR,Pad 1 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x2C 8. "PAD1_DS1,Pad 1 high order drive strength selection. Used in conjunction with PAD1STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x2C 4. "PAD0_SR,Pad 0 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x2C 0. "PAD0_DS1,Pad 0 high order drive strength selection. Used in conjunction with PAD0STRNG field to set the pad drive strength." "0,1"
|
|
line.long 0x30 "ALTPADCFGB,This register has additional configuration control for pads 7. 6. 5. 4"
|
|
bitfld.long 0x30 28. "PAD7_SR,Pad 7 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x30 24. "PAD7_DS1,Pad 7 high order drive strength selection. Used in conjunction with PAD7STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x30 20. "PAD6_SR,Pad 6 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x30 16. "PAD6_DS1,Pad 6 high order drive strength selection. Used in conjunction with PAD6STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x30 12. "PAD5_SR,Pad 5 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x30 8. "PAD5_DS1,Pad 5 high order drive strength selection. Used in conjunction with PAD5STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x30 4. "PAD4_SR,Pad 4 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x30 0. "PAD4_DS1,Pad 4 high order drive strength selection. Used in conjunction with PAD4STRNG field to set the pad drive strength." "0,1"
|
|
line.long 0x34 "ALTPADCFGC,This register has additional configuration control for pads 11. 10. 9. 8"
|
|
bitfld.long 0x34 28. "PAD11_SR,Pad 11 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x34 24. "PAD11_DS1,Pad 11 high order drive strength selection. Used in conjunction with PAD11STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x34 20. "PAD10_SR,Pad 10 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x34 16. "PAD10_DS1,Pad 10 high order drive strength selection. Used in conjunction with PAD10STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x34 12. "PAD9_SR,Pad 9 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x34 8. "PAD9_DS1,Pad 9 high order drive strength selection. Used in conjunction with PAD9STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x34 4. "PAD8_SR,Pad 8 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x34 0. "PAD8_DS1,Pad 8 high order drive strength selection. Used in conjunction with PAD8STRNG field to set the pad drive strength." "0,1"
|
|
line.long 0x38 "ALTPADCFGD,This register has additional configuration control for pads 15. 14. 13. 12"
|
|
bitfld.long 0x38 28. "PAD15_SR,Pad 15 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x38 24. "PAD15_DS1,Pad 15 high order drive strength selection. Used in conjunction with PAD15STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x38 20. "PAD14_SR,Pad 14 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x38 16. "PAD14_DS1,Pad 14 high order drive strength selection. Used in conjunction with PAD14STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x38 12. "PAD13_SR,Pad 13 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x38 8. "PAD13_DS1,Pad 13 high order drive strength selection. Used in conjunction with PAD13STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x38 4. "PAD12_SR,Pad 12 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x38 0. "PAD12_DS1,Pad 12 high order drive strength selection. Used in conjunction with PAD12STRNG field to set the pad drive strength." "0,1"
|
|
line.long 0x3C "ALTPADCFGE,This register has additional configuration control for pads 19. 18. 17. 16"
|
|
bitfld.long 0x3C 28. "PAD19_SR,Pad 19 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x3C 24. "PAD19_DS1,Pad 19 high order drive strength selection. Used in conjunction with PAD19STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x3C 20. "PAD18_SR,Pad 18 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x3C 16. "PAD18_DS1,Pad 18 high order drive strength selection. Used in conjunction with PAD18STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x3C 12. "PAD17_SR,Pad 17 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x3C 8. "PAD17_DS1,Pad 17 high order drive strength selection. Used in conjunction with PAD17STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x3C 4. "PAD16_SR,Pad 16 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x3C 0. "PAD16_DS1,Pad 16 high order drive strength selection. Used in conjunction with PAD16STRNG field to set the pad drive strength." "0,1"
|
|
line.long 0x40 "ALTPADCFGF,This register has additional configuration control for pads 23. 22. 21. 20"
|
|
bitfld.long 0x40 28. "PAD23_SR,Pad 23 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x40 24. "PAD23_DS1,Pad 23 high order drive strength selection. Used in conjunction with PAD23STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x40 20. "PAD22_SR,Pad 22 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x40 16. "PAD22_DS1,Pad 22 high order drive strength selection. Used in conjunction with PAD22STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x40 12. "PAD21_SR,Pad 21 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x40 8. "PAD21_DS1,Pad 21 high order drive strength selection. Used in conjunction with PAD21STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x40 4. "PAD20_SR,Pad 20 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x40 0. "PAD20_DS1,Pad 20 high order drive strength selection. Used in conjunction with PAD20STRNG field to set the pad drive strength." "0,1"
|
|
line.long 0x44 "ALTPADCFGG,This register has additional configuration control for pads 27. 26. 25. 24"
|
|
bitfld.long 0x44 28. "PAD27_SR,Pad 27 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x44 24. "PAD27_DS1,Pad 27 high order drive strength selection. Used in conjunction with PAD27STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x44 20. "PAD26_SR,Pad 26 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x44 16. "PAD26_DS1,Pad 26 high order drive strength selection. Used in conjunction with PAD26STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x44 12. "PAD25_SR,Pad 25 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x44 8. "PAD25_DS1,Pad 25 high order drive strength selection. Used in conjunction with PAD25STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x44 4. "PAD24_SR,Pad 24 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x44 0. "PAD24_DS1,Pad 24 high order drive strength selection. Used in conjunction with PAD24STRNG field to set the pad drive strength." "0,1"
|
|
line.long 0x48 "ALTPADCFGH,This register has additional configuration control for pads 31. 30. 29. 28"
|
|
bitfld.long 0x48 28. "PAD31_SR,Pad 31 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x48 24. "PAD31_DS1,Pad 31 high order drive strength selection. Used in conjunction with PAD31STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x48 20. "PAD30_SR,Pad 30 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x48 16. "PAD30_DS1,Pad 30 high order drive strength selection. Used in conjunction with PAD30STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x48 12. "PAD29_SR,Pad 29 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x48 8. "PAD29_DS1,Pad 29 high order drive strength selection. Used in conjunction with PAD29STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x48 4. "PAD28_SR,Pad 28 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x48 0. "PAD28_DS1,Pad 28 high order drive strength selection. Used in conjunction with PAD28STRNG field to set the pad drive strength." "0,1"
|
|
line.long 0x4C "ALTPADCFGI,This register has additional configuration control for pads 35. 34. 33. 32"
|
|
bitfld.long 0x4C 28. "PAD35_SR,Pad 35 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x4C 24. "PAD35_DS1,Pad 35 high order drive strength selection. Used in conjunction with PAD35STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x4C 20. "PAD34_SR,Pad 34 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x4C 16. "PAD34_DS1,Pad 34 high order drive strength selection. Used in conjunction with PAD34STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x4C 12. "PAD33_SR,Pad 33 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x4C 8. "PAD33_DS1,Pad 33 high order drive strength selection. Used in conjunction with PAD33STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x4C 4. "PAD32_SR,Pad 32 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x4C 0. "PAD32_DS1,Pad 32 high order drive strength selection. Used in conjunction with PAD32STRNG field to set the pad drive strength." "0,1"
|
|
line.long 0x50 "ALTPADCFGJ,This register has additional configuration control for pads 39. 38. 37. 36"
|
|
bitfld.long 0x50 28. "PAD39_SR,Pad 39 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x50 24. "PAD39_DS1,Pad 39 high order drive strength selection. Used in conjunction with PAD39STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x50 20. "PAD38_SR,Pad 38 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x50 16. "PAD38_DS1,Pad 38 high order drive strength selection. Used in conjunction with PAD38STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x50 12. "PAD37_SR,Pad 37 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x50 8. "PAD37_DS1,Pad 37 high order drive strength selection. Used in conjunction with PAD37STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x50 4. "PAD36_SR,Pad 36 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x50 0. "PAD36_DS1,Pad 36 high order drive strength selection. Used in conjunction with PAD36STRNG field to set the pad drive strength." "0,1"
|
|
line.long 0x54 "ALTPADCFGK,This register has additional configuration control for pads 43. 42. 41. 40"
|
|
bitfld.long 0x54 28. "PAD43_SR,Pad 43 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x54 24. "PAD43_DS1,Pad 43 high order drive strength selection. Used in conjunction with PAD43STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x54 20. "PAD42_SR,Pad 42 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x54 16. "PAD42_DS1,Pad 42 high order drive strength selection. Used in conjunction with PAD42STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x54 12. "PAD41_SR,Pad 41 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x54 8. "PAD41_DS1,Pad 41 high order drive strength selection. Used in conjunction with PAD41STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x54 4. "PAD40_SR,Pad 40 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x54 0. "PAD40_DS1,Pad 40 high order drive strength selection. Used in conjunction with PAD40STRNG field to set the pad drive strength." "0,1"
|
|
line.long 0x58 "ALTPADCFGL,This register has additional configuration control for pads 47. 46. 45. 44"
|
|
bitfld.long 0x58 28. "PAD47_SR,Pad 47 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x58 24. "PAD47_DS1,Pad 47 high order drive strength selection. Used in conjunction with PAD47STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x58 20. "PAD46_SR,Pad 46 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x58 16. "PAD46_DS1,Pad 46 high order drive strength selection. Used in conjunction with PAD46STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x58 12. "PAD45_SR,Pad 45 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x58 8. "PAD45_DS1,Pad 45 high order drive strength selection. Used in conjunction with PAD45STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x58 4. "PAD44_SR,Pad 44 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x58 0. "PAD44_DS1,Pad 44 high order drive strength selection. Used in conjunction with PAD44STRNG field to set the pad drive strength." "0,1"
|
|
line.long 0x5C "ALTPADCFGM,This register has additional configuration control for pads 49. 48"
|
|
bitfld.long 0x5C 12. "PAD49_SR,Pad 49 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x5C 8. "PAD49_DS1,Pad 49 high order drive strength selection. Used in conjunction with PAD49STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x5C 4. "PAD48_SR,Pad 48 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x5C 0. "PAD48_DS1,Pad 48 high order drive strength selection. Used in conjunction with PAD48STRNG field to set the pad drive strength." "0,1"
|
|
line.long 0x60 "SCDET,Scard card detect select."
|
|
hexmask.long.byte 0x60 0.--5. 1. "SCDET,SCARD card detect pad select."
|
|
line.long 0x64 "CTENCFG,Pad enable configuration."
|
|
bitfld.long 0x64 31. "EN31,CT31 Enable" "0: Enable CT31 for output,1: Disable CT31 for output"
|
|
bitfld.long 0x64 30. "EN30,CT30 Enable" "0: Enable CT30 for output,1: Disable CT30 for output"
|
|
newline
|
|
bitfld.long 0x64 29. "EN29,CT29 Enable" "0: Enable CT29 for output,1: Disable CT29 for output"
|
|
bitfld.long 0x64 28. "EN28,CT28 Enable" "0: Enable CT28 for output,1: Disable CT28 for output"
|
|
newline
|
|
bitfld.long 0x64 27. "EN27,CT27 Enable" "0: Enable CT27 for output,1: Disable CT27 for output"
|
|
bitfld.long 0x64 26. "EN26,CT26 Enable" "0: Enable CT26 for output,1: Disable CT26 for output"
|
|
newline
|
|
bitfld.long 0x64 25. "EN25,CT25 Enable" "0: Enable CT25 for output,1: Disable CT25 for output"
|
|
bitfld.long 0x64 24. "EN24,CT24 Enable" "0: Enable CT24 for output,1: Disable CT24 for output"
|
|
newline
|
|
bitfld.long 0x64 23. "EN23,CT23 Enable" "0: Enable CT23 for output,1: Disable CT23 for output"
|
|
bitfld.long 0x64 22. "EN22,CT22 Enable" "0: Enable CT22 for output,1: Disable CT22 for output"
|
|
newline
|
|
bitfld.long 0x64 21. "EN21,CT21 Enable" "0: Enable CT21 for output,1: Disable CT21 for output"
|
|
bitfld.long 0x64 20. "EN20,CT20 Enable" "0: Enable CT20 for output,1: Disable CT20 for output"
|
|
newline
|
|
bitfld.long 0x64 19. "EN19,CT19 Enable" "0: Enable CT19 for output,1: Disable CT19 for output"
|
|
bitfld.long 0x64 18. "EN18,CT18 Enable" "0: Enable CT18 for output,1: Disable CT18 for output"
|
|
newline
|
|
bitfld.long 0x64 17. "EN17,CT17 Enable" "0: Enable CT17 for output,1: Disable CT17 for output"
|
|
bitfld.long 0x64 16. "EN16,CT16 Enable" "0: Enable CT16 for output,1: Disable CT16 for output"
|
|
newline
|
|
bitfld.long 0x64 15. "EN15,CT15 Enable" "0: Enable CT15 for output,1: Disable CT15 for output"
|
|
bitfld.long 0x64 14. "EN14,CT14 Enable" "0: Enable CT14 for output,1: Disable CT14 for output"
|
|
newline
|
|
bitfld.long 0x64 13. "EN13,CT13 Enable" "0: Enable CT13 for output,1: Disable CT13 for output"
|
|
bitfld.long 0x64 12. "EN12,CT12 Enable" "0: Enable CT12 for output,1: Disable CT12 for output"
|
|
newline
|
|
bitfld.long 0x64 11. "EN11,CT11 Enable" "0: Enable CT11 for output,1: Disable CT11 for output"
|
|
bitfld.long 0x64 10. "EN10,CT10 Enable" "0: Enable CT10 for output,1: Disable CT10 for output"
|
|
newline
|
|
bitfld.long 0x64 9. "EN9,CT9 Enable" "0: Disable CT9 for output,?"
|
|
bitfld.long 0x64 8. "EN8,CT8 Enable" "0: Enable CT8 for output,1: Disable CT8 for output"
|
|
newline
|
|
bitfld.long 0x64 7. "EN7,CT7 Enable" "0: Enable CT7 for output,1: Disable CT7 for output"
|
|
bitfld.long 0x64 6. "EN6,CT6 Enable" "0: Enable CT6 for output,1: Disable CT6 for output"
|
|
newline
|
|
bitfld.long 0x64 5. "EN5,CT5 Enable" "0: Enable CT5 for output,1: Disable CT5 for output"
|
|
bitfld.long 0x64 4. "EN4,CT4 Enable" "0: Enable CT4 for output,1: Disable CT4 for output"
|
|
newline
|
|
bitfld.long 0x64 3. "EN3,CT3 Enable" "0: Enable CT3 for output,1: Disable CT3 for output"
|
|
bitfld.long 0x64 2. "EN2,CT2 Enable" "0: Enable CT2 for output,1: Disable CT2 for output"
|
|
newline
|
|
bitfld.long 0x64 1. "EN1,CT1 Enable" "0: Enable CT1 for output,1: Disable CT1 for output"
|
|
bitfld.long 0x64 0. "EN0,CT0 Enable" "0: Enable CT0 for output,1: Disable CT0 for output"
|
|
group.long 0x210++0xF
|
|
line.long 0x0 "INT1EN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 17. "GPIO49,GPIO49 interrupt." "0,1"
|
|
bitfld.long 0x0 16. "GPIO48,GPIO48 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "GPIO47,GPIO47 interrupt." "0,1"
|
|
bitfld.long 0x0 14. "GPIO46,GPIO46 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "GPIO45,GPIO45 interrupt." "0,1"
|
|
bitfld.long 0x0 12. "GPIO44,GPIO44 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "GPIO43,GPIO43 interrupt." "0,1"
|
|
bitfld.long 0x0 10. "GPIO42,GPIO42 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "GPIO41,GPIO41 interrupt." "0,1"
|
|
bitfld.long 0x0 8. "GPIO40,GPIO40 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "GPIO39,GPIO39 interrupt." "0,1"
|
|
bitfld.long 0x0 6. "GPIO38,GPIO38 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GPIO37,GPIO37 interrupt." "0,1"
|
|
bitfld.long 0x0 4. "GPIO36,GPIO36 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "GPIO35,GPIO35 interrupt." "0,1"
|
|
bitfld.long 0x0 2. "GPIO34,GPIO34 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "GPIO33,GPIO33 interrupt." "0,1"
|
|
bitfld.long 0x0 0. "GPIO32,GPIO32 interrupt." "0,1"
|
|
line.long 0x4 "INT1STAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 17. "GPIO49,GPIO49 interrupt." "0,1"
|
|
bitfld.long 0x4 16. "GPIO48,GPIO48 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "GPIO47,GPIO47 interrupt." "0,1"
|
|
bitfld.long 0x4 14. "GPIO46,GPIO46 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "GPIO45,GPIO45 interrupt." "0,1"
|
|
bitfld.long 0x4 12. "GPIO44,GPIO44 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "GPIO43,GPIO43 interrupt." "0,1"
|
|
bitfld.long 0x4 10. "GPIO42,GPIO42 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "GPIO41,GPIO41 interrupt." "0,1"
|
|
bitfld.long 0x4 8. "GPIO40,GPIO40 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "GPIO39,GPIO39 interrupt." "0,1"
|
|
bitfld.long 0x4 6. "GPIO38,GPIO38 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "GPIO37,GPIO37 interrupt." "0,1"
|
|
bitfld.long 0x4 4. "GPIO36,GPIO36 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "GPIO35,GPIO35 interrupt." "0,1"
|
|
bitfld.long 0x4 2. "GPIO34,GPIO34 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "GPIO33,GPIO33 interrupt." "0,1"
|
|
bitfld.long 0x4 0. "GPIO32,GPIO32 interrupt." "0,1"
|
|
line.long 0x8 "INT1CLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 17. "GPIO49,GPIO49 interrupt." "0,1"
|
|
bitfld.long 0x8 16. "GPIO48,GPIO48 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "GPIO47,GPIO47 interrupt." "0,1"
|
|
bitfld.long 0x8 14. "GPIO46,GPIO46 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "GPIO45,GPIO45 interrupt." "0,1"
|
|
bitfld.long 0x8 12. "GPIO44,GPIO44 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "GPIO43,GPIO43 interrupt." "0,1"
|
|
bitfld.long 0x8 10. "GPIO42,GPIO42 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "GPIO41,GPIO41 interrupt." "0,1"
|
|
bitfld.long 0x8 8. "GPIO40,GPIO40 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "GPIO39,GPIO39 interrupt." "0,1"
|
|
bitfld.long 0x8 6. "GPIO38,GPIO38 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "GPIO37,GPIO37 interrupt." "0,1"
|
|
bitfld.long 0x8 4. "GPIO36,GPIO36 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "GPIO35,GPIO35 interrupt." "0,1"
|
|
bitfld.long 0x8 2. "GPIO34,GPIO34 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "GPIO33,GPIO33 interrupt." "0,1"
|
|
bitfld.long 0x8 0. "GPIO32,GPIO32 interrupt." "0,1"
|
|
line.long 0xC "INT1SET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 17. "GPIO49,GPIO49 interrupt." "0,1"
|
|
bitfld.long 0xC 16. "GPIO48,GPIO48 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "GPIO47,GPIO47 interrupt." "0,1"
|
|
bitfld.long 0xC 14. "GPIO46,GPIO46 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "GPIO45,GPIO45 interrupt." "0,1"
|
|
bitfld.long 0xC 12. "GPIO44,GPIO44 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "GPIO43,GPIO43 interrupt." "0,1"
|
|
bitfld.long 0xC 10. "GPIO42,GPIO42 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "GPIO41,GPIO41 interrupt." "0,1"
|
|
bitfld.long 0xC 8. "GPIO40,GPIO40 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "GPIO39,GPIO39 interrupt." "0,1"
|
|
bitfld.long 0xC 6. "GPIO38,GPIO38 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "GPIO37,GPIO37 interrupt." "0,1"
|
|
bitfld.long 0xC 4. "GPIO36,GPIO36 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "GPIO35,GPIO35 interrupt." "0,1"
|
|
bitfld.long 0xC 2. "GPIO34,GPIO34 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "GPIO33,GPIO33 interrupt." "0,1"
|
|
bitfld.long 0xC 0. "GPIO32,GPIO32 interrupt." "0,1"
|
|
endif
|
|
sif (cpuis("AMA3B2KK"))
|
|
group.long 0x34++0x43
|
|
line.long 0x0 "PADREGN,This register controls the pad configuration controls for PAD52 through PAD55. Writes to this register must be unlocked by the PADKEY register."
|
|
bitfld.long 0x0 27.--29. "PAD55FNCSEL,Pad 55 function select" "0: Configure as the MSPI1 4 signal,1: IOM/MSPI nCE group 55,2: CTIMER connection 5,3: Configure as GPIO55,?,?,?,?"
|
|
bitfld.long 0x0 26. "PAD55STRNG,Pad 55 drive strength" "0: Low drive strength,1: High drive strength"
|
|
newline
|
|
bitfld.long 0x0 25. "PAD55INPEN,Pad 55 input enable" "0: Pad input disabled,1: Pad input enabled"
|
|
bitfld.long 0x0 24. "PAD55PULL,Pad 55 pullup enable" "0: Pullup disabled,1: Pullup enabled"
|
|
newline
|
|
bitfld.long 0x0 19.--21. "PAD54FNCSEL,Pad 54 function select" "0: Configure as the MSPI1 3 signal,1: IOM/MSPI nCE group 54,2: CTIMER connection 4,3: Configure as GPIO54,?,?,?,?"
|
|
bitfld.long 0x0 18. "PAD54STRNG,Pad 54 drive strength" "0: Low drive strength,1: High drive strength"
|
|
newline
|
|
bitfld.long 0x0 17. "PAD54INPEN,Pad 54 input enable" "0: Pad input disabled,1: Pad input enabled"
|
|
bitfld.long 0x0 16. "PAD54PULL,Pad 54 pullup enable" "0: Pullup disabled,1: Pullup enabled"
|
|
newline
|
|
bitfld.long 0x0 11.--13. "PAD53FNCSEL,Pad 53 function select" "0: Configure as the MSPI1 2 signal,1: IOM/MSPI nCE group 53,2: CTIMER connection 3,3: Configure as GPIO53,?,?,?,?"
|
|
bitfld.long 0x0 10. "PAD53STRNG,Pad 53 drive strength" "0: Low drive strength,1: High drive strength"
|
|
newline
|
|
bitfld.long 0x0 9. "PAD53INPEN,Pad 53 input enable" "0: Pad input disabled,1: Pad input enabled"
|
|
bitfld.long 0x0 8. "PAD53PULL,Pad 53 pullup enable" "0: Pullup disabled,1: Pullup enabled"
|
|
newline
|
|
bitfld.long 0x0 3.--5. "PAD52FNCSEL,Pad 52 function select" "0: Configure as the MSPI1 1 signal,1: IOM/MSPI nCE group 52,2: CTIMER connection 2,3: Configure as GPIO52,?,?,?,?"
|
|
bitfld.long 0x0 2. "PAD52STRNG,Pad 52 drive strength" "0: Low drive strength,1: High drive strength"
|
|
newline
|
|
bitfld.long 0x0 1. "PAD52INPEN,Pad 52 input enable" "0: Pad input disabled,1: Pad input enabled"
|
|
bitfld.long 0x0 0. "PAD52PULL,Pad 52 pullup enable" "0: Pullup disabled,1: Pullup enabled"
|
|
line.long 0x4 "PADREGO,This register controls the pad configuration controls for PAD56 through PAD59. Writes to this register must be unlocked by the PADKEY register."
|
|
bitfld.long 0x4 27.--29. "PAD59FNCSEL,Pad 59 function select" "0: Configure as the MSPI1 8 signal,1: IOM/MSPI nCE group 59,2: CTIMER connection 9,3: Configure as GPIO59,?,?,?,?"
|
|
bitfld.long 0x4 26. "PAD59STRNG,Pad 59 drive strength" "0: Low drive strength,1: High drive strength"
|
|
newline
|
|
bitfld.long 0x4 25. "PAD59INPEN,Pad 59 input enable" "0: Pad input disabled,1: Pad input enabled"
|
|
bitfld.long 0x4 24. "PAD59PULL,Pad 59 pullup enable" "0: Pullup disabled,1: Pullup enabled"
|
|
newline
|
|
bitfld.long 0x4 19.--21. "PAD58FNCSEL,Pad 58 function select" "0: Configure as the MSPI1 7 signal,1: IOM/MSPI nCE group 58,2: CTIMER connection 8,3: Configure as GPIO58,?,?,?,?"
|
|
bitfld.long 0x4 18. "PAD58STRNG,Pad 58 drive strength" "0: Low drive strength,1: High drive strength"
|
|
newline
|
|
bitfld.long 0x4 17. "PAD58INPEN,Pad 58 input enable" "0: Pad input disabled,1: Pad input enabled"
|
|
bitfld.long 0x4 16. "PAD58PULL,Pad 58 pullup enable" "0: Pullup disabled,1: Pullup enabled"
|
|
newline
|
|
bitfld.long 0x4 11.--13. "PAD57FNCSEL,Pad 57 function select" "0: Configure as the MSPI1 6 signal,1: IOM/MSPI nCE group 57,2: CTIMER connection 7,3: Configure as GPIO57,?,?,?,?"
|
|
bitfld.long 0x4 10. "PAD57STRNG,Pad 57 drive strength" "0: Low drive strength,1: High drive strength"
|
|
newline
|
|
bitfld.long 0x4 9. "PAD57INPEN,Pad 57 input enable" "0: Pad input disabled,1: Pad input enabled"
|
|
bitfld.long 0x4 8. "PAD57PULL,Pad 57 pullup enable" "0: Pullup disabled,1: Pullup enabled"
|
|
newline
|
|
bitfld.long 0x4 3.--5. "PAD56FNCSEL,Pad 56 function select" "0: Configure as the MSPI1 5 signal,1: IOM/MSPI nCE group 56,2: CTIMER connection 6,3: Configure as GPIO56,?,?,?,?"
|
|
bitfld.long 0x4 2. "PAD56STRNG,Pad 56 drive strength" "0: Low drive strength,1: High drive strength"
|
|
newline
|
|
bitfld.long 0x4 1. "PAD56INPEN,Pad 56 input enable" "0: Pad input disabled,1: Pad input enabled"
|
|
bitfld.long 0x4 0. "PAD56PULL,Pad 56 pullup enable" "0: Pullup disabled,1: Pullup enabled"
|
|
line.long 0x8 "PADREGP,This register controls the pad configuration controls for PAD60 through PAD63. Writes to this register must be unlocked by the PADKEY register."
|
|
bitfld.long 0x8 27.--29. "PAD63FNCSEL,Pad 63 function select" "0: Configure as the SWO output,1: IOM/MSPI nCE group 63,2: CTIMER connection 13,3: Configure as GPIO63,4: Configure as the UART0 TX output,5: Configure as the UART0 RX input,6: Configure as the UART1 TX output,7: Configure as the UART1 RX input"
|
|
bitfld.long 0x8 26. "PAD63STRNG,Pad 63 drive strength" "0: Low drive strength,1: High drive strength"
|
|
newline
|
|
bitfld.long 0x8 25. "PAD63INPEN,Pad 63 input enable" "0: Pad input disabled,1: Pad input enabled"
|
|
bitfld.long 0x8 24. "PAD63PULL,Pad 63 pullup enable" "0: Pullup disabled,1: Pullup enabled"
|
|
newline
|
|
bitfld.long 0x8 19.--21. "PAD62FNCSEL,Pad 62 function select" "0: Configure as the SWO output,1: IOM/MSPI nCE group 62,2: CTIMER connection 12,3: Configure as GPIO62,4: Configure as the UART0 CTS input,5: Configure as the UART0 RTS output,6: Configure as the UART1 CTS input,7: Configure as the UART1 RTS output"
|
|
bitfld.long 0x8 18. "PAD62STRNG,Pad 62 drive strength" "0: Low drive strength,1: High drive strength"
|
|
newline
|
|
bitfld.long 0x8 17. "PAD62INPEN,Pad 62 input enable" "0: Pad input disabled,1: Pad input enabled"
|
|
bitfld.long 0x8 16. "PAD62PULL,Pad 62 pullup enable" "0: Pullup disabled,1: Pullup enabled"
|
|
newline
|
|
bitfld.long 0x8 11.--13. "PAD61FNCSEL,Pad 61 function select" "0: Configure as the SWO output,1: IOM/MSPI nCE group 61,2: CTIMER connection 11,3: Configure as GPIO61,4: Configure as the UART0 TX output,5: Configure as the UART0 RX input,6: Configure as the UART1 TX output,7: Configure as the UART1 RX input"
|
|
bitfld.long 0x8 10. "PAD61STRNG,Pad 61 drive strength" "0: Low drive strength,1: High drive strength"
|
|
newline
|
|
bitfld.long 0x8 9. "PAD61INPEN,Pad 61 input enable" "0: Pad input disabled,1: Pad input enabled"
|
|
bitfld.long 0x8 8. "PAD61PULL,Pad 61 pullup enable" "0: Pullup disabled,1: Pullup enabled"
|
|
newline
|
|
bitfld.long 0x8 3.--5. "PAD60FNCSEL,Pad 60 function select" "0: Configure as the MSPI1 9 signal,1: IOM/MSPI nCE group 60,2: CTIMER connection 10,3: Configure as GPIO60,?,?,?,?"
|
|
bitfld.long 0x8 2. "PAD60STRNG,Pad 60 drive strength" "0: Low drive strength,1: High drive strength"
|
|
newline
|
|
bitfld.long 0x8 1. "PAD60INPEN,Pad 60 input enable" "0: Pad input disabled,1: Pad input enabled"
|
|
bitfld.long 0x8 0. "PAD60PULL,Pad 60 pullup enable" "0: Pullup disabled,1: Pullup enabled"
|
|
line.long 0xC "PADREGQ,This register controls the pad configuration controls for PAD64 through PAD67. Writes to this register must be unlocked by the PADKEY register."
|
|
bitfld.long 0xC 27.--29. "PAD67FNCSEL,Pad 67 function select" "0: Configure as the MSPI2 3 signal,1: IOM/MSPI nCE group 67,2: CTIMER connection 17,3: Configure as GPIO67,?,?,?,?"
|
|
bitfld.long 0xC 26. "PAD67STRNG,Pad 67 drive strength" "0: Low drive strength,1: High drive strength"
|
|
newline
|
|
bitfld.long 0xC 25. "PAD67INPEN,Pad 67 input enable" "0: Pad input disabled,1: Pad input enabled"
|
|
bitfld.long 0xC 24. "PAD67PULL,Pad 67 pullup enable" "0: Pullup disabled,1: Pullup enabled"
|
|
newline
|
|
bitfld.long 0xC 19.--21. "PAD66FNCSEL,Pad 66 function select" "0: Configure as the MSPI2 2 signal,1: IOM/MSPI nCE group 66,2: CTIMER connection 16,3: Configure as GPIO66,?,?,?,?"
|
|
bitfld.long 0xC 18. "PAD66STRNG,Pad 66 drive strength" "0: Low drive strength,1: High drive strength"
|
|
newline
|
|
bitfld.long 0xC 17. "PAD66INPEN,Pad 66 input enable" "0: Pad input disabled,1: Pad input enabled"
|
|
bitfld.long 0xC 16. "PAD66PULL,Pad 66 pullup enable" "0: Pullup disabled,1: Pullup enabled"
|
|
newline
|
|
bitfld.long 0xC 11.--13. "PAD65FNCSEL,Pad 65 function select" "0: Configure as the MSPI2 1 signal,1: IOM/MSPI nCE group 65,2: CTIMER connection 15,3: Configure as GPIO65,?,?,?,?"
|
|
bitfld.long 0xC 10. "PAD65STRNG,Pad 65 drive strength" "0: Low drive strength,1: High drive strength"
|
|
newline
|
|
bitfld.long 0xC 9. "PAD65INPEN,Pad 65 input enable" "0: Pad input disabled,1: Pad input enabled"
|
|
bitfld.long 0xC 8. "PAD65PULL,Pad 65 pullup enable" "0: Pullup disabled,1: Pullup enabled"
|
|
newline
|
|
bitfld.long 0xC 3.--5. "PAD64FNCSEL,Pad 64 function select" "0: Configure as the MSPI2 0 signal,1: IOM/MSPI nCE group 64,2: CTIMER connection 14,3: Configure as GPIO64,?,?,?,?"
|
|
bitfld.long 0xC 2. "PAD64STRNG,Pad 64 drive strength" "0: Low drive strength,1: High drive strength"
|
|
newline
|
|
bitfld.long 0xC 1. "PAD64INPEN,Pad 64 input enable" "0: Pad input disabled,1: Pad input enabled"
|
|
bitfld.long 0xC 0. "PAD64PULL,Pad 64 pullup enable" "0: Pullup disabled,1: Pullup enabled"
|
|
line.long 0x10 "PADREGR,This register controls the pad configuration controls for PAD68 through PAD71. Writes to this register must be unlocked by the PADKEY register."
|
|
bitfld.long 0x10 27.--29. "PAD71FNCSEL,Pad 71 function select" "0: Configure as the SWO output,1: IOM/MSPI nCE group 71,2: CTIMER connection 21,3: Configure as GPIO71,4: Configure as the UART0 TX output,5: Configure as the UART0 RX input,6: Configure as the UART1 TX output,7: Configure as the UART1 RX input"
|
|
bitfld.long 0x10 26. "PAD71STRNG,Pad 71 drive strength" "0: Low drive strength,1: High drive strength"
|
|
newline
|
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bitfld.long 0x10 25. "PAD71INPEN,Pad 71 input enable" "0: Pad input disabled,1: Pad input enabled"
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bitfld.long 0x10 24. "PAD71PULL,Pad 71 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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bitfld.long 0x10 19.--21. "PAD70FNCSEL,Pad 70 function select" "0: Configure as the SWO output,1: IOM/MSPI nCE group 70,2: CTIMER connection 20,3: Configure as GPIO70,4: Configure as the UART0 TX output,5: Configure as the UART0 RX input,6: Configure as the UART1 TX output,7: Configure as the UART1 RX input"
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bitfld.long 0x10 18. "PAD70STRNG,Pad 70 drive strength" "0: Low drive strength,1: High drive strength"
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bitfld.long 0x10 17. "PAD70INPEN,Pad 70 input enable" "0: Pad input disabled,1: Pad input enabled"
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bitfld.long 0x10 16. "PAD70PULL,Pad 70 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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bitfld.long 0x10 11.--13. "PAD69FNCSEL,Pad 69 function select" "0: Configure as the SWO output,1: IOM/MSPI nCE group 69,2: CTIMER connection 19,3: Configure as GPIO69,4: Configure as the UART0 TX output,5: Configure as the UART0 RX input,6: Configure as the UART1 TX output,7: Configure as the UART1 RX input"
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bitfld.long 0x10 10. "PAD69STRNG,Pad 69 drive strength" "0: Low drive strength,1: High drive strength"
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bitfld.long 0x10 9. "PAD69INPEN,Pad 69 input enable" "0: Pad input disabled,1: Pad input enabled"
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bitfld.long 0x10 8. "PAD69PULL,Pad 69 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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bitfld.long 0x10 3.--5. "PAD68FNCSEL,Pad 68 function select" "0: Configure as the MSPI2 4 signal,1: IOM/MSPI nCE group 68,2: CTIMER connection 18,3: Configure as GPIO68,?,?,?,?"
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bitfld.long 0x10 2. "PAD68STRNG,Pad 68 drive strength" "0: Low drive strength,1: High drive strength"
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bitfld.long 0x10 1. "PAD68INPEN,Pad 68 input enable" "0: Pad input disabled,1: Pad input enabled"
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bitfld.long 0x10 0. "PAD68PULL,Pad 68 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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line.long 0x14 "PADREGS,This register controls the pad configuration controls for PAD72 through PAD73. Writes to this register must be unlocked by the PADKEY register."
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bitfld.long 0x14 11.--13. "PAD73FNCSEL,Pad 73 function select" "0: Configure as the SWO output,1: IOM/MSPI nCE group 73,2: CTIMER connection 23,3: Configure as GPIO73,4: Configure as the UART0 CTS input,5: Configure as the UART0 RTS output,6: Configure as the UART1 CTS input,7: Configure as the UART1 RTS output"
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bitfld.long 0x14 10. "PAD73STRNG,Pad 73 drive strength" "0: Low drive strength,1: High drive strength"
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bitfld.long 0x14 9. "PAD73INPEN,Pad 73 input enable" "0: Pad input disabled,1: Pad input enabled"
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bitfld.long 0x14 8. "PAD73PULL,Pad 73 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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bitfld.long 0x14 3.--5. "PAD72FNCSEL,Pad 72 function select" "0: Configure as the SWO output,1: IOM/MSPI nCE group 72,2: CTIMER connection 22,3: Configure as GPIO72,4: Configure as the UART0 TX output,5: Configure as the UART0 RX input,6: Configure as the UART1 TX output,7: Configure as the UART1 RX input"
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bitfld.long 0x14 2. "PAD72STRNG,Pad 72 drive strength" "0: Low drive strength,1: High drive strength"
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bitfld.long 0x14 1. "PAD72INPEN,Pad 72 input enable" "0: Pad input disabled,1: Pad input enabled"
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bitfld.long 0x14 0. "PAD72PULL,Pad 72 pullup enable" "0: Pullup disabled,1: Pullup enabled"
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line.long 0x18 "CFGA,GPIO configuration controls for GPIO[7:0]. Writes to this register must be unlocked by the PADKEY register."
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bitfld.long 0x18 31. "GPIO7INTD,GPIO7 interrupt direction nCE polarity." "0: Applies when PAD7FNCSEL = NCE7 - nCE polarity..,1: Applies when PAD7FNCSEL = NCE7 - nCE polarity.."
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bitfld.long 0x18 29.--30. "GPIO7OUTCFG,GPIO7 output configuration." "0: Applies when PAD7FNCSEL = GPIO - Output disabled,1: Applies when PAD7FNCSEL = GPIO - Output is..,2: Applies when PAD7FNCSEL = GPIO - Output is open..,3: Applies when PAD7FNCSEL = GPIO - Output is.."
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bitfld.long 0x18 28. "GPIO7INCFG,GPIO7 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x18 27. "GPIO6INTD,GPIO6 interrupt direction nCE polarity." "0: Applies when GPIO6INCFG = 1 - No interrupt on..,1: Applies when GPIO6INCFG = 1 - Interrupt on.."
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bitfld.long 0x18 25.--26. "GPIO6OUTCFG,GPIO6 output configuration." "0: Applies when PAD6FNCSEL = GPIO - Output disabled,1: Applies when PAD6FNCSEL = GPIO - Output is..,2: Applies when PAD6FNCSEL = GPIO - Output is open..,3: Applies when PAD6FNCSEL = GPIO - Output is.."
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bitfld.long 0x18 24. "GPIO6INCFG,GPIO6 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x18 23. "GPIO5INTD,GPIO5 interrupt direction nCE polarity." "0: Applies when GPIO5INCFG = 1 - No interrupt on..,1: Applies when GPIO5INCFG = 1 - Interrupt on.."
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bitfld.long 0x18 21.--22. "GPIO5OUTCFG,GPIO5 output configuration." "0: Applies when PAD5FNCSEL = GPIO - Output disabled,1: Applies when PAD5FNCSEL = GPIO - Output is..,2: Applies when PAD5FNCSEL = GPIO - Output is open..,3: Applies when PAD5FNCSEL = GPIO - Output is.."
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bitfld.long 0x18 20. "GPIO5INCFG,GPIO5 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x18 19. "GPIO4INTD,GPIO4 interrupt direction nCE polarity." "0: Applies when PAD4FNCSEL = NCE4 - nCE polarity..,1: Applies when PAD4FNCSEL = NCE4 - nCE polarity.."
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bitfld.long 0x18 17.--18. "GPIO4OUTCFG,GPIO4 output configuration." "0: Applies when PAD4FNCSEL = GPIO - Output disabled,1: Applies when PAD4FNCSEL = GPIO - Output is..,2: Applies when PAD4FNCSEL = GPIO - Output is open..,3: Applies when PAD4FNCSEL = GPIO - Output is.."
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bitfld.long 0x18 16. "GPIO4INCFG,GPIO4 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x18 15. "GPIO3INTD,GPIO3 interrupt direction nCE polarity." "0: Applies when PAD3FNCSEL = NCE3 - nCE polarity..,1: Applies when PAD3FNCSEL = NCE3 - nCE polarity.."
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bitfld.long 0x18 13.--14. "GPIO3OUTCFG,GPIO3 output configuration." "0: Applies when PAD3FNCSEL = GPIO - Output disabled,1: Applies when PAD3FNCSEL = GPIO - Output is..,2: Applies when PAD3FNCSEL = GPIO - Output is open..,3: Applies when PAD3FNCSEL = GPIO - Output is.."
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bitfld.long 0x18 12. "GPIO3INCFG,GPIO3 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x18 11. "GPIO2INTD,GPIO2 interrupt direction nCE polarity." "0: Applies when PAD2FNCSEL = NCE2 - nCE polarity..,1: Applies when PAD2FNCSEL = NCE2 - nCE polarity.."
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bitfld.long 0x18 9.--10. "GPIO2OUTCFG,GPIO2 output configuration." "0: Applies when PAD2FNCSEL = GPIO - Output disabled,1: Applies when PAD2FNCSEL = GPIO - Output is..,2: Applies when PAD2FNCSEL = GPIO - Output is open..,3: Applies when PAD2FNCSEL = GPIO - Output is.."
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bitfld.long 0x18 8. "GPIO2INCFG,GPIO2 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x18 7. "GPIO1INTD,GPIO1 interrupt direction nCE polarity." "0: Applies when PAD1FNCSEL = NCE1 - nCE polarity..,1: Applies when PAD1FNCSEL = NCE1 - nCE polarity.."
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bitfld.long 0x18 5.--6. "GPIO1OUTCFG,GPIO1 output configuration." "0: Applies when PAD1FNCSEL = GPIO - Output disabled,1: Applies when PAD1FNCSEL = GPIO - Output is..,2: Applies when PAD1FNCSEL = GPIO - Output is open..,3: Applies when PAD1FNCSEL = GPIO - Output is.."
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bitfld.long 0x18 4. "GPIO1INCFG,GPIO1 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x18 3. "GPIO0INTD,GPIO0 interrupt direction nCE polarity." "0: Applies when PAD0FNCSEL = NCE0 - nCE polarity..,1: Applies when PAD0FNCSEL = NCE0 - nCE polarity.."
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bitfld.long 0x18 1.--2. "GPIO0OUTCFG,GPIO0 output configuration." "0: Applies when PAD0FNCSEL = GPIO - Output disabled,1: Applies when PAD0FNCSEL = GPIO - Output is..,2: Applies when PAD0FNCSEL = GPIO - Output is open..,3: Applies when PAD0FNCSEL = GPIO - Output is.."
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bitfld.long 0x18 0. "GPIO0INCFG,GPIO0 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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line.long 0x1C "CFGB,GPIO configuration controls for GPIO[15:8]. Writes to this register must be unlocked by the PADKEY register."
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bitfld.long 0x1C 31. "GPIO15INTD,GPIO15 interrupt direction nCE polarity." "0: Applies when PAD15FNCSEL = NCE15 - nCE polarity..,1: Applies when PAD15FNCSEL = NCE15 - nCE polarity.."
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bitfld.long 0x1C 29.--30. "GPIO15OUTCFG,GPIO15 output configuration." "0: Applies when PAD15FNCSEL = GPIO - Output disabled,1: Applies when PAD15FNCSEL = GPIO - Output is..,2: Applies when PAD15FNCSEL = GPIO - Output is open..,3: Applies when PAD15FNCSEL = GPIO - Output is.."
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bitfld.long 0x1C 28. "GPIO15INCFG,GPIO15 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x1C 27. "GPIO14INTD,GPIO14 interrupt direction nCE polarity." "0: Applies when PAD14FNCSEL = NCE14 - nCE polarity..,1: Applies when PAD14FNCSEL = NCE14 - nCE polarity.."
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bitfld.long 0x1C 25.--26. "GPIO14OUTCFG,GPIO14 output configuration." "0: Applies when PAD14FNCSEL = GPIO - Output disabled,1: Applies when PAD14FNCSEL = GPIO - Output is..,2: Applies when PAD14FNCSEL = GPIO - Output is open..,3: Applies when PAD14FNCSEL = GPIO - Output is.."
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bitfld.long 0x1C 24. "GPIO14INCFG,GPIO14 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x1C 23. "GPIO13INTD,GPIO13 interrupt direction nCE polarity." "0: Applies when PAD13FNCSEL = NCE13 - nCE polarity..,1: Applies when PAD13FNCSEL = NCE13 - nCE polarity.."
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bitfld.long 0x1C 21.--22. "GPIO13OUTCFG,GPIO13 output configuration." "0: Applies when PAD13FNCSEL = GPIO - Output disabled,1: Applies when PAD13FNCSEL = GPIO - Output is..,2: Applies when PAD13FNCSEL = GPIO - Output is open..,3: Applies when PAD13FNCSEL = GPIO - Output is.."
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bitfld.long 0x1C 20. "GPIO13INCFG,GPIO13 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x1C 19. "GPIO12INTD,GPIO12 interrupt direction nCE polarity." "0: Applies when PAD12FNCSEL = NCE12 - nCE polarity..,1: Applies when PAD12FNCSEL = NCE12 - nCE polarity.."
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bitfld.long 0x1C 17.--18. "GPIO12OUTCFG,GPIO12 output configuration." "0: Applies when PAD12FNCSEL = GPIO - Output disabled,1: Applies when PAD12FNCSEL = GPIO - Output is..,2: Applies when PAD12FNCSEL = GPIO - Output is open..,3: Applies when PAD12FNCSEL = GPIO - Output is.."
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bitfld.long 0x1C 16. "GPIO12INCFG,GPIO12 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x1C 15. "GPIO11INTD,GPIO11 interrupt direction nCE polarity." "0: Applies when PAD11FNCSEL = NCE11 - nCE polarity..,1: Applies when PAD11FNCSEL = NCE11 - nCE polarity.."
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bitfld.long 0x1C 13.--14. "GPIO11OUTCFG,GPIO11 output configuration." "0: Applies when PAD11FNCSEL = GPIO - Output disabled,1: Applies when PAD11FNCSEL = GPIO - Output is..,2: Applies when PAD11FNCSEL = GPIO - Output is open..,3: Applies when PAD11FNCSEL = GPIO - Output is.."
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bitfld.long 0x1C 12. "GPIO11INCFG,GPIO11 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x1C 11. "GPIO10INTD,GPIO10 interrupt direction nCE polarity." "0: Applies when PAD10FNCSEL = NCE10 - nCE polarity..,1: Applies when PAD10FNCSEL = NCE10 - nCE polarity.."
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bitfld.long 0x1C 9.--10. "GPIO10OUTCFG,GPIO10 output configuration." "0: Applies when PAD10FNCSEL = GPIO - Output disabled,1: Applies when PAD10FNCSEL = GPIO - Output is..,2: Applies when PAD10FNCSEL = GPIO - Output is open..,3: Applies when PAD10FNCSEL = GPIO - Output is.."
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bitfld.long 0x1C 8. "GPIO10INCFG,GPIO10 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x1C 7. "GPIO9INTD,GPIO9 interrupt direction nCE polarity." "0: Applies when PAD9FNCSEL = NCE9 - nCE polarity..,1: Applies when PAD9FNCSEL = NCE9 - nCE polarity.."
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bitfld.long 0x1C 5.--6. "GPIO9OUTCFG,GPIO9 output configuration." "0: Applies when PAD9FNCSEL = GPIO - Output disabled,1: Applies when PAD9FNCSEL = GPIO - Output is..,2: Applies when PAD9FNCSEL = GPIO - Output is open..,3: Applies when PAD9FNCSEL = GPIO - Output is.."
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bitfld.long 0x1C 4. "GPIO9INCFG,GPIO9 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x1C 3. "GPIO8INTD,GPIO8 interrupt direction nCE polarity." "0: Applies when PAD8FNCSEL = NCE8 - nCE polarity..,1: Applies when PAD8FNCSEL = NCE8 - nCE polarity.."
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bitfld.long 0x1C 1.--2. "GPIO8OUTCFG,GPIO8 output configuration." "0: Applies when PAD8FNCSEL = GPIO - Output disabled,1: Applies when PAD8FNCSEL = GPIO - Output is..,2: Applies when PAD8FNCSEL = GPIO - Output is open..,3: Applies when PAD8FNCSEL = GPIO - Output is.."
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bitfld.long 0x1C 0. "GPIO8INCFG,GPIO8 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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line.long 0x20 "CFGC,GPIO configuration controls for GPIO[23:16]. Writes to this register must be unlocked by the PADKEY register."
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bitfld.long 0x20 31. "GPIO23INTD,GPIO23 interrupt direction nCE polarity." "0: Applies when PAD23FNCSEL = NCE23 - nCE polarity..,1: Applies when PAD23FNCSEL = NCE23 - nCE polarity.."
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bitfld.long 0x20 29.--30. "GPIO23OUTCFG,GPIO23 output configuration." "0: Applies when PAD23FNCSEL = GPIO - Output disabled,1: Applies when PAD23FNCSEL = GPIO - Output is..,2: Applies when PAD23FNCSEL = GPIO - Output is open..,3: Applies when PAD23FNCSEL = GPIO - Output is.."
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bitfld.long 0x20 28. "GPIO23INCFG,GPIO23 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x20 27. "GPIO22INTD,GPIO22 interrupt direction nCE polarity." "0: Applies when PAD22FNCSEL = NCE22 - nCE polarity..,1: Applies when PAD22FNCSEL = NCE22 - nCE polarity.."
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bitfld.long 0x20 25.--26. "GPIO22OUTCFG,GPIO22 output configuration." "0: Applies when PAD22FNCSEL = GPIO - Output disabled,1: Applies when PAD22FNCSEL = GPIO - Output is..,2: Applies when PAD22FNCSEL = GPIO - Output is open..,3: Applies when PAD22FNCSEL = GPIO - Output is.."
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bitfld.long 0x20 24. "GPIO22INCFG,GPIO22 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x20 23. "GPIO21INTD,GPIO21 interrupt direction nCE polarity." "0: Applies when PAD21FNCSEL = NCE21 - nCE polarity..,1: Applies when PAD21FNCSEL = NCE21 - nCE polarity.."
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bitfld.long 0x20 21.--22. "GPIO21OUTCFG,GPIO21 output configuration." "0: Applies when PAD21FNCSEL = GPIO - Output disabled,1: Applies when PAD21FNCSEL = GPIO - Output is..,2: Applies when PAD21FNCSEL = GPIO - Output is open..,3: Applies when PAD21FNCSEL = GPIO - Output is.."
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bitfld.long 0x20 20. "GPIO21INCFG,GPIO21 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x20 19. "GPIO20INTD,GPIO20 interrupt direction nCE polarity." "0: Applies when PAD20FNCSEL = NCE20 - nCE polarity..,1: Applies when PAD20FNCSEL = NCE20 - nCE polarity.."
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bitfld.long 0x20 17.--18. "GPIO20OUTCFG,GPIO20 output configuration." "0: Applies when PAD20FNCSEL = GPIO - Output disabled,1: Applies when PAD20FNCSEL = GPIO - Output is..,2: Applies when PAD20FNCSEL = GPIO - Output is open..,3: Applies when PAD20FNCSEL = GPIO - Output is.."
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bitfld.long 0x20 16. "GPIO20INCFG,GPIO20 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x20 15. "GPIO19INTD,GPIO19 interrupt direction nCE polarity." "0: Applies when PAD19FNCSEL = NCE19 - nCE polarity..,1: Applies when PAD19FNCSEL = NCE19 - nCE polarity.."
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bitfld.long 0x20 13.--14. "GPIO19OUTCFG,GPIO19 output configuration." "0: Applies when PAD19FNCSEL = GPIO - Output disabled,1: Applies when PAD19FNCSEL = GPIO - Output is..,2: Applies when PAD19FNCSEL = GPIO - Output is open..,3: Applies when PAD19FNCSEL = GPIO - Output is.."
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bitfld.long 0x20 12. "GPIO19INCFG,GPIO19 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x20 11. "GPIO18INTD,GPIO18 interrupt direction nCE polarity." "0: Applies when PAD18FNCSEL = NCE18 - nCE polarity..,1: Applies when PAD18FNCSEL = NCE18 - nCE polarity.."
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bitfld.long 0x20 9.--10. "GPIO18OUTCFG,GPIO18 output configuration." "0: Applies when PAD18FNCSEL = GPIO - Output disabled,1: Applies when PAD18FNCSEL = GPIO - Output is..,2: Applies when PAD18FNCSEL = GPIO - Output is open..,3: Applies when PAD18FNCSEL = GPIO - Output is.."
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bitfld.long 0x20 8. "GPIO18INCFG,GPIO18 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x20 7. "GPIO17INTD,GPIO17 interrupt direction nCE polarity." "0: Applies when PAD17FNCSEL = NCE17 - nCE polarity..,1: Applies when PAD17FNCSEL = NCE17 - nCE polarity.."
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bitfld.long 0x20 5.--6. "GPIO17OUTCFG,GPIO17 output configuration." "0: Applies when PAD17FNCSEL = GPIO - Output disabled,1: Applies when PAD17FNCSEL = GPIO - Output is..,2: Applies when PAD17FNCSEL = GPIO - Output is open..,3: Applies when PAD17FNCSEL = GPIO - Output is.."
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bitfld.long 0x20 4. "GPIO17INCFG,GPIO17 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x20 3. "GPIO16INTD,GPIO16 interrupt direction nCE polarity." "0: Applies when PAD16FNCSEL = NCE16 - nCE polarity..,1: Applies when PAD16FNCSEL = NCE16 - nCE polarity.."
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bitfld.long 0x20 1.--2. "GPIO16OUTCFG,GPIO16 output configuration." "0: Applies when PAD16FNCSEL = GPIO - Output disabled,1: Applies when PAD16FNCSEL = GPIO - Output is..,2: Applies when PAD16FNCSEL = GPIO - Output is open..,3: Applies when PAD16FNCSEL = GPIO - Output is.."
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bitfld.long 0x20 0. "GPIO16INCFG,GPIO16 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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line.long 0x24 "CFGD,GPIO configuration controls for GPIO[31:24]. Writes to this register must be unlocked by the PADKEY register."
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bitfld.long 0x24 31. "GPIO31INTD,GPIO31 interrupt direction nCE polarity." "0: Applies when PAD31FNCSEL = NCE31 - nCE polarity..,1: Applies when PAD31FNCSEL = NCE31 - nCE polarity.."
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bitfld.long 0x24 29.--30. "GPIO31OUTCFG,GPIO31 output configuration." "0: Applies when PAD31FNCSEL = GPIO - Output disabled,1: Applies when PAD31FNCSEL = GPIO - Output is..,2: Applies when PAD31FNCSEL = GPIO - Output is open..,3: Applies when PAD31FNCSEL = GPIO - Output is.."
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bitfld.long 0x24 28. "GPIO31INCFG,GPIO31 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x24 27. "GPIO30INTD,GPIO30 interrupt direction nCE polarity." "0: Applies when PAD30FNCSEL = NCE30 - nCE polarity..,1: Applies when PAD30FNCSEL = NCE30 - nCE polarity.."
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bitfld.long 0x24 25.--26. "GPIO30OUTCFG,GPIO30 output configuration." "0: Applies when PAD30FNCSEL = GPIO - Output disabled,1: Applies when PAD30FNCSEL = GPIO - Output is..,2: Applies when PAD30FNCSEL = GPIO - Output is open..,3: Applies when PAD30FNCSEL = GPIO - Output is.."
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bitfld.long 0x24 24. "GPIO30INCFG,GPIO30 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x24 23. "GPIO29INTD,GPIO29 interrupt direction nCE polarity." "0: Applies when PAD29FNCSEL = NCE29 - nCE polarity..,1: Applies when PAD29FNCSEL = NCE29 - nCE polarity.."
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bitfld.long 0x24 21.--22. "GPIO29OUTCFG,GPIO29 output configuration." "0: Applies when PAD29FNCSEL = GPIO - Output disabled,1: Applies when PAD29FNCSEL = GPIO - Output is..,2: Applies when PAD29FNCSEL = GPIO - Output is open..,3: Applies when PAD29FNCSEL = GPIO - Output is.."
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bitfld.long 0x24 20. "GPIO29INCFG,GPIO29 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x24 19. "GPIO28INTD,GPIO28 interrupt direction nCE polarity." "0: Applies when PAD28FNCSEL = NCE28 - nCE polarity..,1: Applies when PAD28FNCSEL = NCE28 - nCE polarity.."
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bitfld.long 0x24 17.--18. "GPIO28OUTCFG,GPIO28 output configuration." "0: Applies when PAD28FNCSEL = GPIO - Output disabled,1: Applies when PAD28FNCSEL = GPIO - Output is..,2: Applies when PAD28FNCSEL = GPIO - Output is open..,3: Applies when PAD28FNCSEL = GPIO - Output is.."
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bitfld.long 0x24 16. "GPIO28INCFG,GPIO28 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x24 15. "GPIO27INTD,GPIO27 interrupt direction nCE polarity." "0: Applies when PAD27FNCSEL = NCE27 - nCE polarity..,1: Applies when PAD27FNCSEL = NCE27 - nCE polarity.."
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bitfld.long 0x24 13.--14. "GPIO27OUTCFG,GPIO27 output configuration." "0: Applies when PAD27FNCSEL = GPIO - Output disabled,1: Applies when PAD27FNCSEL = GPIO - Output is..,2: Applies when PAD27FNCSEL = GPIO - Output is open..,3: Applies when PAD27FNCSEL = GPIO - Output is.."
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bitfld.long 0x24 12. "GPIO27INCFG,GPIO27 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x24 11. "GPIO26INTD,GPIO26 interrupt direction nCE polarity." "0: Applies when PAD26FNCSEL = NCE26 - nCE polarity..,1: Applies when PAD26FNCSEL = NCE26 - nCE polarity.."
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bitfld.long 0x24 9.--10. "GPIO26OUTCFG,GPIO26 output configuration." "0: Applies when PAD26FNCSEL = GPIO - Output disabled,1: Applies when PAD26FNCSEL = GPIO - Output is..,2: Applies when PAD26FNCSEL = GPIO - Output is open..,3: Applies when PAD26FNCSEL = GPIO - Output is.."
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bitfld.long 0x24 8. "GPIO26INCFG,GPIO26 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x24 7. "GPIO25INTD,GPIO25 interrupt direction nCE polarity." "0: Applies when PAD25FNCSEL = NCE25 - nCE polarity..,1: Applies when PAD25FNCSEL = NCE25 - nCE polarity.."
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bitfld.long 0x24 5.--6. "GPIO25OUTCFG,GPIO25 output configuration." "0: Applies when PAD25FNCSEL = GPIO - Output disabled,1: Applies when PAD25FNCSEL = GPIO - Output is..,2: Applies when PAD25FNCSEL = GPIO - Output is open..,3: Applies when PAD25FNCSEL = GPIO - Output is.."
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bitfld.long 0x24 4. "GPIO25INCFG,GPIO25 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x24 3. "GPIO24INTD,GPIO24 interrupt direction nCE polarity." "0: Applies when PAD24FNCSEL = NCE24 - nCE polarity..,1: Applies when PAD24FNCSEL = NCE24 - nCE polarity.."
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bitfld.long 0x24 1.--2. "GPIO24OUTCFG,GPIO24 output configuration." "0: Applies when PAD24FNCSEL = GPIO - Output disabled,1: Applies when PAD24FNCSEL = GPIO - Output is..,2: Applies when PAD24FNCSEL = GPIO - Output is open..,3: Applies when PAD24FNCSEL = GPIO - Output is.."
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bitfld.long 0x24 0. "GPIO24INCFG,GPIO24 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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line.long 0x28 "CFGE,GPIO configuration controls for GPIO[39:32]. Writes to this register must be unlocked by the PADKEY register."
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bitfld.long 0x28 31. "GPIO39INTD,GPIO39 interrupt direction nCE polarity." "0: Applies when GPIO39INCFG = 1 - No interrupt on..,1: Applies when GPIO39INCFG = 1 - Interrupt on.."
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bitfld.long 0x28 29.--30. "GPIO39OUTCFG,GPIO39 output configuration." "0: Applies when PAD39FNCSEL = GPIO - Output disabled,1: Applies when PAD39FNCSEL = GPIO - Output is..,2: Applies when PAD39FNCSEL = GPIO - Output is open..,3: Applies when PAD39FNCSEL = GPIO - Output is.."
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bitfld.long 0x28 28. "GPIO39INCFG,GPIO39 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x28 27. "GPIO38INTD,GPIO38 interrupt direction nCE polarity." "0: Applies when PAD38FNCSEL = NCE38 - nCE polarity..,1: Applies when PAD38FNCSEL = NCE38 - nCE polarity.."
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bitfld.long 0x28 25.--26. "GPIO38OUTCFG,GPIO38 output configuration." "0: Applies when PAD38FNCSEL = GPIO - Output disabled,1: Applies when PAD38FNCSEL = GPIO - Output is..,2: Applies when PAD38FNCSEL = GPIO - Output is open..,3: Applies when PAD38FNCSEL = GPIO - Output is.."
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bitfld.long 0x28 24. "GPIO38INCFG,GPIO38 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x28 23. "GPIO37INTD,GPIO37 interrupt direction nCE polarity." "0: Applies when PAD37FNCSEL = NCE37 - nCE polarity..,1: Applies when PAD37FNCSEL = NCE37 - nCE polarity.."
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bitfld.long 0x28 21.--22. "GPIO37OUTCFG,GPIO37 output configuration." "0: Applies when PAD37FNCSEL = GPIO - Output disabled,1: Applies when PAD37FNCSEL = GPIO - Output is..,2: Applies when PAD37FNCSEL = GPIO - Output is open..,3: Applies when PAD37FNCSEL = GPIO - Output is.."
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bitfld.long 0x28 20. "GPIO37INCFG,GPIO37 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x28 19. "GPIO36INTD,GPIO36 interrupt direction nCE polarity." "0: Applies when PAD36FNCSEL = NCE36 - nCE polarity..,1: Applies when PAD36FNCSEL = NCE36 - nCE polarity.."
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bitfld.long 0x28 17.--18. "GPIO36OUTCFG,GPIO36 output configuration." "0: Applies when PAD36FNCSEL = GPIO - Output disabled,1: Applies when PAD36FNCSEL = GPIO - Output is..,2: Applies when PAD36FNCSEL = GPIO - Output is open..,3: Applies when PAD36FNCSEL = GPIO - Output is.."
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bitfld.long 0x28 16. "GPIO36INCFG,GPIO36 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x28 15. "GPIO35INTD,GPIO35 interrupt direction nCE polarity." "0: Applies when PAD35FNCSEL = NCE35 - nCE polarity..,1: Applies when PAD35FNCSEL = NCE35 - nCE polarity.."
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bitfld.long 0x28 13.--14. "GPIO35OUTCFG,GPIO35 output configuration." "0: Applies when PAD35FNCSEL = GPIO - Output disabled,1: Applies when PAD35FNCSEL = GPIO - Output is..,2: Applies when PAD35FNCSEL = GPIO - Output is open..,3: Applies when PAD35FNCSEL = GPIO - Output is.."
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bitfld.long 0x28 12. "GPIO35INCFG,GPIO35 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x28 11. "GPIO34INTD,GPIO34 interrupt direction nCE polarity." "0: Applies when PAD34FNCSEL = NCE34 - nCE polarity..,1: Applies when PAD34FNCSEL = NCE34 - nCE polarity.."
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bitfld.long 0x28 9.--10. "GPIO34OUTCFG,GPIO34 output configuration." "0: Applies when PAD34FNCSEL = GPIO - Output disabled,1: Applies when PAD34FNCSEL = GPIO - Output is..,2: Applies when PAD34FNCSEL = GPIO - Output is open..,3: Applies when PAD34FNCSEL = GPIO - Output is.."
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bitfld.long 0x28 8. "GPIO34INCFG,GPIO34 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x28 7. "GPIO33INTD,GPIO33 interrupt direction nCE polarity." "0: Applies when PAD33FNCSEL = NCE33 - nCE polarity..,1: Applies when PAD33FNCSEL = NCE33 - nCE polarity.."
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bitfld.long 0x28 5.--6. "GPIO33OUTCFG,GPIO33 output configuration." "0: Applies when PAD33FNCSEL = GPIO - Output disabled,1: Applies when PAD33FNCSEL = GPIO - Output is..,2: Applies when PAD33FNCSEL = GPIO - Output is open..,3: Applies when PAD33FNCSEL = GPIO - Output is.."
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bitfld.long 0x28 4. "GPIO33INCFG,GPIO33 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x28 3. "GPIO32INTD,GPIO32 interrupt direction nCE polarity." "0: Applies when PAD32FNCSEL = NCE32 - nCE polarity..,1: Applies when PAD32FNCSEL = NCE32 - nCE polarity.."
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bitfld.long 0x28 1.--2. "GPIO32OUTCFG,GPIO32 output configuration." "0: Applies when PAD32FNCSEL = GPIO - Output disabled,1: Applies when PAD32FNCSEL = GPIO - Output is..,2: Applies when PAD32FNCSEL = GPIO - Output is open..,3: Applies when PAD32FNCSEL = GPIO - Output is.."
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bitfld.long 0x28 0. "GPIO32INCFG,GPIO32 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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line.long 0x2C "CFGF,GPIO configuration controls for GPIO[47:40]. Writes to this register must be unlocked by the PADKEY register."
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bitfld.long 0x2C 31. "GPIO47INTD,GPIO47 interrupt direction nCE polarity." "0: Applies when PAD47FNCSEL = NCE47 - nCE polarity..,1: Applies when PAD47FNCSEL = NCE47 - nCE polarity.."
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bitfld.long 0x2C 29.--30. "GPIO47OUTCFG,GPIO47 output configuration." "0: Applies when PAD47FNCSEL = GPIO - Output disabled,1: Applies when PAD47FNCSEL = GPIO - Output is..,2: Applies when PAD47FNCSEL = GPIO - Output is open..,3: Applies when PAD47FNCSEL = GPIO - Output is.."
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bitfld.long 0x2C 28. "GPIO47INCFG,GPIO47 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x2C 27. "GPIO46INTD,GPIO46 interrupt direction nCE polarity." "0: Applies when PAD46FNCSEL = NCE46 - nCE polarity..,1: Applies when PAD46FNCSEL = NCE46 - nCE polarity.."
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bitfld.long 0x2C 25.--26. "GPIO46OUTCFG,GPIO46 output configuration." "0: Applies when PAD46FNCSEL = GPIO - Output disabled,1: Applies when PAD46FNCSEL = GPIO - Output is..,2: Applies when PAD46FNCSEL = GPIO - Output is open..,3: Applies when PAD46FNCSEL = GPIO - Output is.."
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bitfld.long 0x2C 24. "GPIO46INCFG,GPIO46 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x2C 23. "GPIO45INTD,GPIO45 interrupt direction nCE polarity." "0: Applies when PAD45FNCSEL = NCE45 - nCE polarity..,1: Applies when PAD45FNCSEL = NCE45 - nCE polarity.."
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bitfld.long 0x2C 21.--22. "GPIO45OUTCFG,GPIO45 output configuration." "0: Applies when PAD45FNCSEL = GPIO - Output disabled,1: Applies when PAD45FNCSEL = GPIO - Output is..,2: Applies when PAD45FNCSEL = GPIO - Output is open..,3: Applies when PAD45FNCSEL = GPIO - Output is.."
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bitfld.long 0x2C 20. "GPIO45INCFG,GPIO45 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x2C 19. "GPIO44INTD,GPIO44 interrupt direction nCE polarity." "0: Applies when PAD44FNCSEL = NCE44 - nCE polarity..,1: Applies when PAD44FNCSEL = NCE44 - nCE polarity.."
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bitfld.long 0x2C 17.--18. "GPIO44OUTCFG,GPIO44 output configuration." "0: Applies when PAD44FNCSEL = GPIO - Output disabled,1: Applies when PAD44FNCSEL = GPIO - Output is..,2: Applies when PAD44FNCSEL = GPIO - Output is open..,3: Applies when PAD44FNCSEL = GPIO - Output is.."
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bitfld.long 0x2C 16. "GPIO44INCFG,GPIO44 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x2C 15. "GPIO43INTD,GPIO43 interrupt direction nCE polarity." "0: Applies when PAD43FNCSEL = NCE43 - nCE polarity..,1: Applies when PAD43FNCSEL = NCE43 - nCE polarity.."
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bitfld.long 0x2C 13.--14. "GPIO43OUTCFG,GPIO43 output configuration." "0: Applies when PAD43FNCSEL = GPIO - Output disabled,1: Applies when PAD43FNCSEL = GPIO - Output is..,2: Applies when PAD43FNCSEL = GPIO - Output is open..,3: Applies when PAD43FNCSEL = GPIO - Output is.."
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bitfld.long 0x2C 12. "GPIO43INCFG,GPIO43 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x2C 11. "GPIO42INTD,GPIO42 interrupt direction nCE polarity." "0: Applies when PAD42FNCSEL = NCE42 - nCE polarity..,1: Applies when PAD42FNCSEL = NCE42 - nCE polarity.."
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bitfld.long 0x2C 9.--10. "GPIO42OUTCFG,GPIO42 output configuration." "0: Applies when PAD42FNCSEL = GPIO - Output disabled,1: Applies when PAD42FNCSEL = GPIO - Output is..,2: Applies when PAD42FNCSEL = GPIO - Output is open..,3: Applies when PAD42FNCSEL = GPIO - Output is.."
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bitfld.long 0x2C 8. "GPIO42INCFG,GPIO42 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x2C 7. "GPIO41INTD,GPIO41 interrupt direction nCE polarity." "0: Applies when PAD41FNCSEL = NCE41 - nCE polarity..,1: Applies when PAD41FNCSEL = NCE41 - nCE polarity.."
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bitfld.long 0x2C 5.--6. "GPIO41OUTCFG,GPIO41 output configuration." "0: Applies when PAD41FNCSEL = GPIO - Output disabled,1: Applies when PAD41FNCSEL = GPIO - Output is..,2: Applies when PAD41FNCSEL = GPIO - Output is open..,3: Applies when PAD41FNCSEL = GPIO - Output is.."
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bitfld.long 0x2C 4. "GPIO41INCFG,GPIO41 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x2C 3. "GPIO40INTD,GPIO40 interrupt direction nCE polarity." "0: Applies when GPIO40INCFG = 1 - No interrupt on..,1: Applies when GPIO40INCFG = 1 - Interrupt on.."
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bitfld.long 0x2C 1.--2. "GPIO40OUTCFG,GPIO40 output configuration." "0: Applies when PAD40FNCSEL = GPIO - Output disabled,1: Applies when PAD40FNCSEL = GPIO - Output is..,2: Applies when PAD40FNCSEL = GPIO - Output is open..,3: Applies when PAD40FNCSEL = GPIO - Output is.."
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bitfld.long 0x2C 0. "GPIO40INCFG,GPIO40 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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line.long 0x30 "CFGG,GPIO configuration controls for GPIO[55:48]. Writes to this register must be unlocked by the PADKEY register."
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bitfld.long 0x30 31. "GPIO55INTD,GPIO55 interrupt direction nCE polarity." "0: Applies when PAD55FNCSEL = NCE55 - nCE polarity..,1: Applies when PAD55FNCSEL = NCE55 - nCE polarity.."
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bitfld.long 0x30 29.--30. "GPIO55OUTCFG,GPIO55 output configuration." "0: Applies when PAD55FNCSEL = GPIO - Output disabled,1: Applies when PAD55FNCSEL = GPIO - Output is..,2: Applies when PAD55FNCSEL = GPIO - Output is open..,3: Applies when PAD55FNCSEL = GPIO - Output is.."
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bitfld.long 0x30 28. "GPIO55INCFG,GPIO55 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x30 27. "GPIO54INTD,GPIO54 interrupt direction nCE polarity." "0: Applies when PAD54FNCSEL = NCE54 - nCE polarity..,1: Applies when PAD54FNCSEL = NCE54 - nCE polarity.."
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bitfld.long 0x30 25.--26. "GPIO54OUTCFG,GPIO54 output configuration." "0: Applies when PAD54FNCSEL = GPIO - Output disabled,1: Applies when PAD54FNCSEL = GPIO - Output is..,2: Applies when PAD54FNCSEL = GPIO - Output is open..,3: Applies when PAD54FNCSEL = GPIO - Output is.."
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bitfld.long 0x30 24. "GPIO54INCFG,GPIO54 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x30 23. "GPIO53INTD,GPIO53 interrupt direction nCE polarity." "0: Applies when PAD53FNCSEL = NCE53 - nCE polarity..,1: Applies when PAD53FNCSEL = NCE53 - nCE polarity.."
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bitfld.long 0x30 21.--22. "GPIO53OUTCFG,GPIO53 output configuration." "0: Applies when PAD53FNCSEL = GPIO - Output disabled,1: Applies when PAD53FNCSEL = GPIO - Output is..,2: Applies when PAD53FNCSEL = GPIO - Output is open..,3: Applies when PAD53FNCSEL = GPIO - Output is.."
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bitfld.long 0x30 20. "GPIO53INCFG,GPIO53 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x30 19. "GPIO52INTD,GPIO52 interrupt direction nCE polarity." "0: Applies when PAD52FNCSEL = NCE52 - nCE polarity..,1: Applies when PAD52FNCSEL = NCE52 - nCE polarity.."
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bitfld.long 0x30 17.--18. "GPIO52OUTCFG,GPIO52 output configuration." "0: Applies when PAD52FNCSEL = GPIO - Output disabled,1: Applies when PAD52FNCSEL = GPIO - Output is..,2: Applies when PAD52FNCSEL = GPIO - Output is open..,3: Applies when PAD52FNCSEL = GPIO - Output is.."
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bitfld.long 0x30 16. "GPIO52INCFG,GPIO52 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x30 15. "GPIO51INTD,GPIO51 interrupt direction nCE polarity." "0: Applies when PAD51FNCSEL = NCE51 - nCE polarity..,1: Applies when PAD51FNCSEL = NCE51 - nCE polarity.."
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bitfld.long 0x30 13.--14. "GPIO51OUTCFG,GPIO51 output configuration." "0: Applies when PAD51FNCSEL = GPIO - Output disabled,1: Applies when PAD51FNCSEL = GPIO - Output is..,2: Applies when PAD51FNCSEL = GPIO - Output is open..,3: Applies when PAD51FNCSEL = GPIO - Output is.."
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bitfld.long 0x30 12. "GPIO51INCFG,GPIO51 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x30 11. "GPIO50INTD,GPIO50 interrupt direction nCE polarity." "0: Applies when PAD50FNCSEL = NCE50 - nCE polarity..,1: Applies when PAD50FNCSEL = NCE50 - nCE polarity.."
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bitfld.long 0x30 9.--10. "GPIO50OUTCFG,GPIO50 output configuration." "0: Applies when PAD50FNCSEL = GPIO - Output disabled,1: Applies when PAD50FNCSEL = GPIO - Output is..,2: Applies when PAD50FNCSEL = GPIO - Output is open..,3: Applies when PAD50FNCSEL = GPIO - Output is.."
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bitfld.long 0x30 8. "GPIO50INCFG,GPIO50 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x30 7. "GPIO49INTD,GPIO49 interrupt direction nCE polarity." "0: Applies when PAD49FNCSEL = NCE49 - nCE polarity..,1: Applies when PAD49FNCSEL = NCE49 - nCE polarity.."
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bitfld.long 0x30 5.--6. "GPIO49OUTCFG,GPIO49 output configuration." "0: Applies when PAD49FNCSEL = GPIO - Output disabled,1: Applies when PAD49FNCSEL = GPIO - Output is..,2: Applies when PAD49FNCSEL = GPIO - Output is open..,3: Applies when PAD49FNCSEL = GPIO - Output is.."
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bitfld.long 0x30 4. "GPIO49INCFG,GPIO49 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x30 3. "GPIO48INTD,GPIO48 interrupt direction nCE polarity." "0: Applies when PAD48FNCSEL = NCE48 - nCE polarity..,1: Applies when PAD48FNCSEL = NCE48 - nCE polarity.."
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bitfld.long 0x30 1.--2. "GPIO48OUTCFG,GPIO48 output configuration." "0: Applies when PAD48FNCSEL = GPIO - Output disabled,1: Applies when PAD48FNCSEL = GPIO - Output is..,2: Applies when PAD48FNCSEL = GPIO - Output is open..,3: Applies when PAD48FNCSEL = GPIO - Output is.."
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bitfld.long 0x30 0. "GPIO48INCFG,GPIO48 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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line.long 0x34 "CFGH,GPIO configuration controls for GPIO[63:56]. Writes to this register must be unlocked by the PADKEY register."
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bitfld.long 0x34 31. "GPIO63INTD,GPIO63 interrupt direction nCE polarity." "0: Applies when PAD63FNCSEL = NCE63 - nCE polarity..,1: Applies when PAD63FNCSEL = NCE63 - nCE polarity.."
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bitfld.long 0x34 29.--30. "GPIO63OUTCFG,GPIO63 output configuration." "0: Applies when PAD63FNCSEL = GPIO - Output disabled,1: Applies when PAD63FNCSEL = GPIO - Output is..,2: Applies when PAD63FNCSEL = GPIO - Output is open..,3: Applies when PAD63FNCSEL = GPIO - Output is.."
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bitfld.long 0x34 28. "GPIO63INCFG,GPIO63 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x34 27. "GPIO62INTD,GPIO62 interrupt direction nCE polarity." "0: Applies when PAD62FNCSEL = NCE62 - nCE polarity..,1: Applies when PAD62FNCSEL = NCE62 - nCE polarity.."
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bitfld.long 0x34 25.--26. "GPIO62OUTCFG,GPIO62 output configuration." "0: Applies when PAD62FNCSEL = GPIO - Output disabled,1: Applies when PAD62FNCSEL = GPIO - Output is..,2: Applies when PAD62FNCSEL = GPIO - Output is open..,3: Applies when PAD62FNCSEL = GPIO - Output is.."
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bitfld.long 0x34 24. "GPIO62INCFG,GPIO62 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x34 23. "GPIO61INTD,GPIO61 interrupt direction nCE polarity." "0: Applies when PAD61FNCSEL = NCE61 - nCE polarity..,1: Applies when PAD61FNCSEL = NCE61 - nCE polarity.."
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bitfld.long 0x34 21.--22. "GPIO61OUTCFG,GPIO61 output configuration." "0: Applies when PAD61FNCSEL = GPIO - Output disabled,1: Applies when PAD61FNCSEL = GPIO - Output is..,2: Applies when PAD61FNCSEL = GPIO - Output is open..,3: Applies when PAD61FNCSEL = GPIO - Output is.."
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bitfld.long 0x34 20. "GPIO61INCFG,GPIO61 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x34 19. "GPIO60INTD,GPIO60 interrupt direction nCE polarity." "0: Applies when PAD60FNCSEL = NCE60 - nCE polarity..,1: Applies when PAD60FNCSEL = NCE60 - nCE polarity.."
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bitfld.long 0x34 17.--18. "GPIO60OUTCFG,GPIO60 output configuration." "0: Applies when PAD60FNCSEL = GPIO - Output disabled,1: Applies when PAD60FNCSEL = GPIO - Output is..,2: Applies when PAD60FNCSEL = GPIO - Output is open..,3: Applies when PAD60FNCSEL = GPIO - Output is.."
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bitfld.long 0x34 16. "GPIO60INCFG,GPIO60 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x34 15. "GPIO59INTD,GPIO59 interrupt direction nCE polarity." "0: Applies when PAD59FNCSEL = NCE59 - nCE polarity..,1: Applies when PAD59FNCSEL = NCE59 - nCE polarity.."
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bitfld.long 0x34 13.--14. "GPIO59OUTCFG,GPIO59 output configuration." "0: Applies when PAD59FNCSEL = GPIO - Output disabled,1: Applies when PAD59FNCSEL = GPIO - Output is..,2: Applies when PAD59FNCSEL = GPIO - Output is open..,3: Applies when PAD59FNCSEL = GPIO - Output is.."
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bitfld.long 0x34 12. "GPIO59INCFG,GPIO59 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x34 11. "GPIO58INTD,GPIO58 interrupt direction nCE polarity." "0: Applies when PAD58FNCSEL = NCE58 - nCE polarity..,1: Applies when PAD58FNCSEL = NCE58 - nCE polarity.."
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bitfld.long 0x34 9.--10. "GPIO58OUTCFG,GPIO58 output configuration." "0: Applies when PAD58FNCSEL = GPIO - Output disabled,1: Applies when PAD58FNCSEL = GPIO - Output is..,2: Applies when PAD58FNCSEL = GPIO - Output is open..,3: Applies when PAD58FNCSEL = GPIO - Output is.."
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bitfld.long 0x34 8. "GPIO58INCFG,GPIO58 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x34 7. "GPIO57INTD,GPIO57 interrupt direction nCE polarity." "0: Applies when PAD57FNCSEL = NCE57 - nCE polarity..,1: Applies when PAD57FNCSEL = NCE57 - nCE polarity.."
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bitfld.long 0x34 5.--6. "GPIO57OUTCFG,GPIO57 output configuration." "0: Applies when PAD57FNCSEL = GPIO - Output disabled,1: Applies when PAD57FNCSEL = GPIO - Output is..,2: Applies when PAD57FNCSEL = GPIO - Output is open..,3: Applies when PAD57FNCSEL = GPIO - Output is.."
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bitfld.long 0x34 4. "GPIO57INCFG,GPIO57 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x34 3. "GPIO56INTD,GPIO56 interrupt direction nCE polarity." "0: Applies when PAD56FNCSEL = NCE56 - nCE polarity..,1: Applies when PAD56FNCSEL = NCE56 - nCE polarity.."
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bitfld.long 0x34 1.--2. "GPIO56OUTCFG,GPIO56 output configuration." "0: Applies when PAD56FNCSEL = GPIO - Output disabled,1: Applies when PAD56FNCSEL = GPIO - Output is..,2: Applies when PAD56FNCSEL = GPIO - Output is open..,3: Applies when PAD56FNCSEL = GPIO - Output is.."
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bitfld.long 0x34 0. "GPIO56INCFG,GPIO56 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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line.long 0x38 "CFGI,GPIO configuration controls for GPIO[71:64]. Writes to this register must be unlocked by the PADKEY register."
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bitfld.long 0x38 31. "GPIO71INTD,GPIO71 interrupt direction nCE polarity." "0: Applies when PAD71FNCSEL = NCE71 - nCE polarity..,1: Applies when PAD71FNCSEL = NCE71 - nCE polarity.."
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bitfld.long 0x38 29.--30. "GPIO71OUTCFG,GPIO71 output configuration." "0: Applies when PAD71FNCSEL = GPIO - Output disabled,1: Applies when PAD71FNCSEL = GPIO - Output is..,2: Applies when PAD71FNCSEL = GPIO - Output is open..,3: Applies when PAD71FNCSEL = GPIO - Output is.."
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bitfld.long 0x38 28. "GPIO71INCFG,GPIO71 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x38 27. "GPIO70INTD,GPIO70 interrupt direction nCE polarity." "0: Applies when PAD70FNCSEL = NCE70 - nCE polarity..,1: Applies when PAD70FNCSEL = NCE70 - nCE polarity.."
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bitfld.long 0x38 25.--26. "GPIO70OUTCFG,GPIO70 output configuration." "0: Applies when PAD70FNCSEL = GPIO - Output disabled,1: Applies when PAD70FNCSEL = GPIO - Output is..,2: Applies when PAD70FNCSEL = GPIO - Output is open..,3: Applies when PAD70FNCSEL = GPIO - Output is.."
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bitfld.long 0x38 24. "GPIO70INCFG,GPIO70 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x38 23. "GPIO69INTD,GPIO69 interrupt direction nCE polarity." "0: Applies when PAD69FNCSEL = NCE69 - nCE polarity..,1: Applies when PAD69FNCSEL = NCE69 - nCE polarity.."
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bitfld.long 0x38 21.--22. "GPIO69OUTCFG,GPIO69 output configuration." "0: Applies when PAD69FNCSEL = GPIO - Output disabled,1: Applies when PAD69FNCSEL = GPIO - Output is..,2: Applies when PAD69FNCSEL = GPIO - Output is open..,3: Applies when PAD69FNCSEL = GPIO - Output is.."
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bitfld.long 0x38 20. "GPIO69INCFG,GPIO69 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x38 19. "GPIO68INTD,GPIO68 interrupt direction nCE polarity." "0: Applies when PAD68FNCSEL = NCE68 - nCE polarity..,1: Applies when PAD68FNCSEL = NCE68 - nCE polarity.."
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bitfld.long 0x38 17.--18. "GPIO68OUTCFG,GPIO68 output configuration." "0: Applies when PAD68FNCSEL = GPIO - Output disabled,1: Applies when PAD68FNCSEL = GPIO - Output is..,2: Applies when PAD68FNCSEL = GPIO - Output is open..,3: Applies when PAD68FNCSEL = GPIO - Output is.."
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bitfld.long 0x38 16. "GPIO68INCFG,GPIO68 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x38 15. "GPIO67INTD,GPIO67 interrupt direction nCE polarity." "0: Applies when PAD67FNCSEL = NCE67 - nCE polarity..,1: Applies when PAD67FNCSEL = NCE67 - nCE polarity.."
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bitfld.long 0x38 13.--14. "GPIO67OUTCFG,GPIO67 output configuration." "0: Applies when PAD67FNCSEL = GPIO - Output disabled,1: Applies when PAD67FNCSEL = GPIO - Output is..,2: Applies when PAD67FNCSEL = GPIO - Output is open..,3: Applies when PAD67FNCSEL = GPIO - Output is.."
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bitfld.long 0x38 12. "GPIO67INCFG,GPIO67 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x38 11. "GPIO66INTD,GPIO66 interrupt direction nCE polarity." "0: Applies when PAD66FNCSEL = NCE66 - nCE polarity..,1: Applies when PAD66FNCSEL = NCE66 - nCE polarity.."
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bitfld.long 0x38 9.--10. "GPIO66OUTCFG,GPIO66 output configuration." "0: Applies when PAD66FNCSEL = GPIO - Output disabled,1: Applies when PAD66FNCSEL = GPIO - Output is..,2: Applies when PAD66FNCSEL = GPIO - Output is open..,3: Applies when PAD66FNCSEL = GPIO - Output is.."
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bitfld.long 0x38 8. "GPIO66INCFG,GPIO66 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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newline
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bitfld.long 0x38 7. "GPIO65INTD,GPIO65 interrupt direction nCE polarity." "0: Applies when PAD65FNCSEL = NCE65 - nCE polarity..,1: Applies when PAD65FNCSEL = NCE65 - nCE polarity.."
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bitfld.long 0x38 5.--6. "GPIO65OUTCFG,GPIO65 output configuration." "0: Applies when PAD65FNCSEL = GPIO - Output disabled,1: Applies when PAD65FNCSEL = GPIO - Output is..,2: Applies when PAD65FNCSEL = GPIO - Output is open..,3: Applies when PAD65FNCSEL = GPIO - Output is.."
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bitfld.long 0x38 4. "GPIO65INCFG,GPIO65 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x38 3. "GPIO64INTD,GPIO64 interrupt direction nCE polarity." "0: Applies when PAD64FNCSEL = NCE64 - nCE polarity..,1: Applies when PAD64FNCSEL = NCE64 - nCE polarity.."
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newline
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bitfld.long 0x38 1.--2. "GPIO64OUTCFG,GPIO64 output configuration." "0: Applies when PAD64FNCSEL = GPIO - Output disabled,1: Applies when PAD64FNCSEL = GPIO - Output is..,2: Applies when PAD64FNCSEL = GPIO - Output is open..,3: Applies when PAD64FNCSEL = GPIO - Output is.."
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bitfld.long 0x38 0. "GPIO64INCFG,GPIO64 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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line.long 0x3C "CFGJ,GPIO configuration controls for GPIO[73:72]. Writes to this register must be unlocked by the PADKEY register."
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bitfld.long 0x3C 7. "GPIO73INTD,GPIO73 interrupt direction nCE polarity." "0: Applies when PAD73FNCSEL = NCE73 - nCE polarity..,1: Applies when PAD73FNCSEL = NCE73 - nCE polarity.."
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bitfld.long 0x3C 5.--6. "GPIO73OUTCFG,GPIO73 output configuration." "0: Applies when PAD73FNCSEL = GPIO - Output disabled,1: Applies when PAD73FNCSEL = GPIO - Output is..,2: Applies when PAD73FNCSEL = GPIO - Output is open..,3: Applies when PAD73FNCSEL = GPIO - Output is.."
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bitfld.long 0x3C 4. "GPIO73INCFG,GPIO73 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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bitfld.long 0x3C 3. "GPIO72INTD,GPIO72 interrupt direction nCE polarity." "0: Applies when PAD72FNCSEL = NCE72 - nCE polarity..,1: Applies when PAD72FNCSEL = NCE72 - nCE polarity.."
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newline
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bitfld.long 0x3C 1.--2. "GPIO72OUTCFG,GPIO72 output configuration." "0: Applies when PAD72FNCSEL = GPIO - Output disabled,1: Applies when PAD72FNCSEL = GPIO - Output is..,2: Applies when PAD72FNCSEL = GPIO - Output is open..,3: Applies when PAD72FNCSEL = GPIO - Output is.."
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bitfld.long 0x3C 0. "GPIO72INCFG,GPIO72 input enable." "0: Read the GPIO pin data,1: INTD = 0 - Read-back will always be zero"
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line.long 0x40 "PADKEY,Lock state of the PINCFG and GPIO configuration registers. Write a value of 0x73 to unlock write access to the PAD and GPIO configuration registers. Write any other value to lock access to PAD and GPIO registers. This register also indicates lock.."
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hexmask.long 0x40 0.--31. 1. "PADKEY,Key register value."
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group.long 0x88++0xC3
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line.long 0x0 "RDC,GPIO Input C (73-64)"
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hexmask.long.word 0x0 0.--9. 1. "RDC,GPIO73-64 read data."
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line.long 0x4 "WTA,GPIO Output A (31-0)"
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hexmask.long 0x4 0.--31. 1. "WTA,GPIO31-0 write data."
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line.long 0x8 "WTB,GPIO Output B (63-32)"
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hexmask.long 0x8 0.--31. 1. "WTB,GPIO63-32 write data."
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line.long 0xC "WTC,GPIO Output C (73-64)"
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hexmask.long.word 0xC 0.--9. 1. "WTC,GPIO73-64 write data."
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line.long 0x10 "WTSA,GPIO Output A Set (31-0)"
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hexmask.long 0x10 0.--31. 1. "WTSA,Set the GPIO31-0 write data."
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line.long 0x14 "WTSB,GPIO Output B Set (63-32)"
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hexmask.long 0x14 0.--31. 1. "WTSB,Set the GPIO63-32 write data."
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line.long 0x18 "WTSC,GPIO Output C Set (73-64)"
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hexmask.long.word 0x18 0.--9. 1. "WTSC,Set the GPIO73-64 write data."
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line.long 0x1C "WTCA,GPIO Output A Clear (31-0)"
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hexmask.long 0x1C 0.--31. 1. "WTCA,Clear the GPIO31-0 write data."
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line.long 0x20 "WTCB,GPIO Output B Clear (63-32)"
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hexmask.long 0x20 0.--31. 1. "WTCB,Clear the GPIO63-32 write data."
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line.long 0x24 "WTCC,GPIO Output C Clear (73-64)"
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hexmask.long.word 0x24 0.--9. 1. "WTCB,Clear the GPIO73-64 write data."
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line.long 0x28 "ENA,GPIO Enable A (31-0)"
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hexmask.long 0x28 0.--31. 1. "ENA,GPIO31-0 output enables"
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line.long 0x2C "ENB,GPIO Enable B (63-32)"
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hexmask.long 0x2C 0.--31. 1. "ENB,GPIO63-32 output enables"
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line.long 0x30 "ENC,GPIO Enable C (73-64)"
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hexmask.long.word 0x30 0.--9. 1. "ENC,GPIO73-64 output enables"
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line.long 0x34 "ENSA,GPIO Enable A Set (31-0)"
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hexmask.long 0x34 0.--31. 1. "ENSA,Set the GPIO31-0 output enables"
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line.long 0x38 "ENSB,GPIO Enable B Set (63-32)"
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hexmask.long 0x38 0.--31. 1. "ENSB,Set the GPIO63-32 output enables"
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line.long 0x3C "ENSC,GPIO Enable C Set (73-64)"
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hexmask.long.word 0x3C 0.--9. 1. "ENSC,Set the GPIO73-64 output enables"
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line.long 0x40 "ENCA,GPIO Enable A Clear (31-0)"
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hexmask.long 0x40 0.--31. 1. "ENCA,Clear the GPIO31-0 output enables"
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line.long 0x44 "ENCB,GPIO Enable B Clear (63-32)"
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hexmask.long 0x44 0.--31. 1. "ENCB,Clear the GPIO49-32 output enables"
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line.long 0x48 "ENCC,GPIO Enable C Clear (73-64)"
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hexmask.long.word 0x48 0.--9. 1. "ENCC,Clear the GPIO73-64 output enables"
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line.long 0x4C "STMRCAP,STIMER Capture trigger select and enable."
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bitfld.long 0x4C 31. "STPOL3,STIMER Capture 3 Polarity." "0: Capture on low to high GPIO transition,1: Capture on high to low GPIO transition"
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hexmask.long.byte 0x4C 24.--30. 1. "STSEL3,STIMER Capture 3 Select."
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newline
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bitfld.long 0x4C 23. "STPOL2,STIMER Capture 2 Polarity." "0: Capture on low to high GPIO transition,1: Capture on high to low GPIO transition"
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hexmask.long.byte 0x4C 16.--22. 1. "STSEL2,STIMER Capture 2 Select."
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newline
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bitfld.long 0x4C 15. "STPOL1,STIMER Capture 1 Polarity." "0: Capture on low to high GPIO transition,1: Capture on high to low GPIO transition"
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hexmask.long.byte 0x4C 8.--14. 1. "STSEL1,STIMER Capture 1 Select."
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newline
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bitfld.long 0x4C 7. "STPOL0,STIMER Capture 0 Polarity." "0: Capture on low to high GPIO transition,1: Capture on high to low GPIO transition"
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hexmask.long.byte 0x4C 0.--6. 1. "STSEL0,STIMER Capture 0 Select."
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line.long 0x50 "IOM0IRQ,IOMSTR0 IRQ select for flow control."
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hexmask.long.byte 0x50 0.--6. 1. "IOM0IRQ,IOMSTR0 IRQ pad select."
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line.long 0x54 "IOM1IRQ,IOMSTR1 IRQ select for flow control."
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hexmask.long.byte 0x54 0.--6. 1. "IOM1IRQ,IOMSTR1 IRQ pad select."
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line.long 0x58 "IOM2IRQ,IOMSTR2 IRQ select for flow control."
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hexmask.long.byte 0x58 0.--6. 1. "IOM2IRQ,IOMSTR2 IRQ pad select."
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line.long 0x5C "IOM3IRQ,IOMSTR3 IRQ select for flow control."
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hexmask.long.byte 0x5C 0.--6. 1. "IOM3IRQ,IOMSTR3 IRQ pad select."
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line.long 0x60 "IOM4IRQ,IOMSTR4 IRQ select for flow control."
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hexmask.long.byte 0x60 0.--6. 1. "IOM4IRQ,IOMSTR4 IRQ pad select."
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line.long 0x64 "IOM5IRQ,IOMSTR5 IRQ select for flow control."
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hexmask.long.byte 0x64 0.--6. 1. "IOM5IRQ,IOMSTR5 IRQ pad select."
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line.long 0x68 "BLEIFIRQ,BLE IF IRQ select for flow control."
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hexmask.long.byte 0x68 0.--6. 1. "BLEIFIRQ,BLEIF IRQ pad select."
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line.long 0x6C "GPIOOBS,GPIO Observation mode sample register"
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hexmask.long.word 0x6C 0.--15. 1. "OBS_DATA,Sample of the data output on the GPIO observation port. May have sampling non-synchronization issues as the data is not synchronized to the read operation. Intended for debug purposes only"
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line.long 0x70 "ALTPADCFGA,This register has additional configuration control for pads [3:0]"
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bitfld.long 0x70 28. "PAD3_SR,Pad 3 slew rate selection." "?,1: Enables Slew rate control on pad"
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bitfld.long 0x70 24. "PAD3_DS1,Pad 3 high order drive strength selection. Used in conjunction with PAD3STRNG field to set the pad drive strength." "0,1"
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newline
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bitfld.long 0x70 20. "PAD2_SR,Pad 3 slew rate selection." "?,1: Enables Slew rate control on pad"
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bitfld.long 0x70 16. "PAD2_DS1,Pad 2 high order drive strength selection. Used in conjunction with PAD2STRNG field to set the pad drive strength." "0,1"
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newline
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bitfld.long 0x70 12. "PAD1_SR,Pad 3 slew rate selection." "?,1: Enables Slew rate control on pad"
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bitfld.long 0x70 8. "PAD1_DS1,Pad 1 high order drive strength selection. Used in conjunction with PAD1STRNG field to set the pad drive strength." "0,1"
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newline
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bitfld.long 0x70 4. "PAD0_SR,Pad 3 slew rate selection." "?,1: Enables Slew rate control on pad"
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bitfld.long 0x70 0. "PAD0_DS1,Pad 0 high order drive strength selection. Used in conjunction with PAD0STRNG field to set the pad drive strength." "0,1"
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line.long 0x74 "ALTPADCFGB,This register has additional configuration control for pads [7:4]"
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bitfld.long 0x74 28. "PAD7_SR,Pad 7 slew rate selection." "?,1: Enables Slew rate control on pad"
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bitfld.long 0x74 24. "PAD7_DS1,Pad 7 high order drive strength selection. Used in conjunction with PAD7STRNG field to set the pad drive strength." "0,1"
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newline
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bitfld.long 0x74 20. "PAD6_SR,Pad 7 slew rate selection." "?,1: Enables Slew rate control on pad"
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bitfld.long 0x74 16. "PAD6_DS1,Pad 6 high order drive strength selection. Used in conjunction with PAD6STRNG field to set the pad drive strength." "0,1"
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newline
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bitfld.long 0x74 12. "PAD5_SR,Pad 7 slew rate selection." "?,1: Enables Slew rate control on pad"
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bitfld.long 0x74 8. "PAD5_DS1,Pad 5 high order drive strength selection. Used in conjunction with PAD5STRNG field to set the pad drive strength." "0,1"
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newline
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bitfld.long 0x74 4. "PAD4_SR,Pad 7 slew rate selection." "?,1: Enables Slew rate control on pad"
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bitfld.long 0x74 0. "PAD4_DS1,Pad 4 high order drive strength selection. Used in conjunction with PAD4STRNG field to set the pad drive strength." "0,1"
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line.long 0x78 "ALTPADCFGC,This register has additional configuration control for pads [11:8]"
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bitfld.long 0x78 28. "PAD11_SR,Pad 11 slew rate selection." "?,1: Enables Slew rate control on pad"
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bitfld.long 0x78 24. "PAD11_DS1,Pad 11 high order drive strength selection. Used in conjunction with PAD11STRNG field to set the pad drive strength." "0,1"
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newline
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bitfld.long 0x78 20. "PAD10_SR,Pad 11 slew rate selection." "?,1: Enables Slew rate control on pad"
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bitfld.long 0x78 16. "PAD10_DS1,Pad 10 high order drive strength selection. Used in conjunction with PAD10STRNG field to set the pad drive strength." "0,1"
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newline
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bitfld.long 0x78 12. "PAD9_SR,Pad 11 slew rate selection." "?,1: Enables Slew rate control on pad"
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bitfld.long 0x78 8. "PAD9_DS1,Pad 9 high order drive strength selection. Used in conjunction with PAD9STRNG field to set the pad drive strength." "0,1"
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newline
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bitfld.long 0x78 4. "PAD8_SR,Pad 11 slew rate selection." "?,1: Enables Slew rate control on pad"
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bitfld.long 0x78 0. "PAD8_DS1,Pad 8 high order drive strength selection. Used in conjunction with PAD8STRNG field to set the pad drive strength." "0,1"
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line.long 0x7C "ALTPADCFGD,This register has additional configuration control for pads [15:12]"
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bitfld.long 0x7C 28. "PAD15_SR,Pad 15 slew rate selection." "?,1: Enables Slew rate control on pad"
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bitfld.long 0x7C 24. "PAD15_DS1,Pad 15 high order drive strength selection. Used in conjunction with PAD15STRNG field to set the pad drive strength." "0,1"
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newline
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bitfld.long 0x7C 20. "PAD14_SR,Pad 15 slew rate selection." "?,1: Enables Slew rate control on pad"
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bitfld.long 0x7C 16. "PAD14_DS1,Pad 14 high order drive strength selection. Used in conjunction with PAD14STRNG field to set the pad drive strength." "0,1"
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newline
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bitfld.long 0x7C 12. "PAD13_SR,Pad 15 slew rate selection." "?,1: Enables Slew rate control on pad"
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bitfld.long 0x7C 8. "PAD13_DS1,Pad 13 high order drive strength selection. Used in conjunction with PAD13STRNG field to set the pad drive strength." "0,1"
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newline
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bitfld.long 0x7C 4. "PAD12_SR,Pad 15 slew rate selection." "?,1: Enables Slew rate control on pad"
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bitfld.long 0x7C 0. "PAD12_DS1,Pad 12 high order drive strength selection. Used in conjunction with PAD12STRNG field to set the pad drive strength." "0,1"
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line.long 0x80 "ALTPADCFGE,This register has additional configuration control for pads [19:16]"
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bitfld.long 0x80 28. "PAD19_SR,Pad 19 slew rate selection." "?,1: Enables Slew rate control on pad"
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bitfld.long 0x80 24. "PAD19_DS1,Pad 19 high order drive strength selection. Used in conjunction with PAD19STRNG field to set the pad drive strength." "0,1"
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newline
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bitfld.long 0x80 20. "PAD18_SR,Pad 19 slew rate selection." "?,1: Enables Slew rate control on pad"
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bitfld.long 0x80 16. "PAD18_DS1,Pad 18 high order drive strength selection. Used in conjunction with PAD18STRNG field to set the pad drive strength." "0,1"
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newline
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bitfld.long 0x80 12. "PAD17_SR,Pad 19 slew rate selection." "?,1: Enables Slew rate control on pad"
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bitfld.long 0x80 8. "PAD17_DS1,Pad 17 high order drive strength selection. Used in conjunction with PAD17STRNG field to set the pad drive strength." "0,1"
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newline
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|
bitfld.long 0x80 4. "PAD16_SR,Pad 19 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x80 0. "PAD16_DS1,Pad 16 high order drive strength selection. Used in conjunction with PAD16STRNG field to set the pad drive strength." "0,1"
|
|
line.long 0x84 "ALTPADCFGF,This register has additional configuration control for pads [23:20]"
|
|
bitfld.long 0x84 28. "PAD23_SR,Pad 23 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x84 24. "PAD23_DS1,Pad 23 high order drive strength selection. Used in conjunction with PAD23STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x84 20. "PAD22_SR,Pad 23 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x84 16. "PAD22_DS1,Pad 22 high order drive strength selection. Used in conjunction with PAD22STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x84 12. "PAD21_SR,Pad 23 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x84 8. "PAD21_DS1,Pad 21 high order drive strength selection. Used in conjunction with PAD21STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x84 4. "PAD20_SR,Pad 23 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x84 0. "PAD20_DS1,Pad 20 high order drive strength selection. Used in conjunction with PAD20STRNG field to set the pad drive strength." "0,1"
|
|
line.long 0x88 "ALTPADCFGG,This register has additional configuration control for pads [27:24]"
|
|
bitfld.long 0x88 28. "PAD27_SR,Pad 27 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x88 24. "PAD27_DS1,Pad 27 high order drive strength selection. Used in conjunction with PAD27STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x88 20. "PAD26_SR,Pad 27 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x88 16. "PAD26_DS1,Pad 26 high order drive strength selection. Used in conjunction with PAD26STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x88 12. "PAD25_SR,Pad 27 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x88 8. "PAD25_DS1,Pad 25 high order drive strength selection. Used in conjunction with PAD25STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x88 4. "PAD24_SR,Pad 27 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x88 0. "PAD24_DS1,Pad 24 high order drive strength selection. Used in conjunction with PAD24STRNG field to set the pad drive strength." "0,1"
|
|
line.long 0x8C "ALTPADCFGH,This register has additional configuration control for pads [31:28]"
|
|
bitfld.long 0x8C 28. "PAD31_SR,Pad 31 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x8C 24. "PAD31_DS1,Pad 31 high order drive strength selection. Used in conjunction with PAD31STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x8C 20. "PAD30_SR,Pad 31 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x8C 16. "PAD30_DS1,Pad 30 high order drive strength selection. Used in conjunction with PAD30STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x8C 12. "PAD29_SR,Pad 31 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x8C 8. "PAD29_DS1,Pad 29 high order drive strength selection. Used in conjunction with PAD29STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x8C 4. "PAD28_SR,Pad 31 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x8C 0. "PAD28_DS1,Pad 28 high order drive strength selection. Used in conjunction with PAD28STRNG field to set the pad drive strength." "0,1"
|
|
line.long 0x90 "ALTPADCFGI,This register has additional configuration control for pads [35:32]"
|
|
bitfld.long 0x90 28. "PAD35_SR,Pad 35 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x90 24. "PAD35_DS1,Pad 35 high order drive strength selection. Used in conjunction with PAD35STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x90 20. "PAD34_SR,Pad 35 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x90 16. "PAD34_DS1,Pad 34 high order drive strength selection. Used in conjunction with PAD34STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x90 12. "PAD33_SR,Pad 35 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x90 8. "PAD33_DS1,Pad 33 high order drive strength selection. Used in conjunction with PAD33STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x90 4. "PAD32_SR,Pad 35 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x90 0. "PAD32_DS1,Pad 32 high order drive strength selection. Used in conjunction with PAD32STRNG field to set the pad drive strength." "0,1"
|
|
line.long 0x94 "ALTPADCFGJ,This register has additional configuration control for pads [39:36]"
|
|
bitfld.long 0x94 28. "PAD39_SR,Pad 39 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x94 24. "PAD39_DS1,Pad 39 high order drive strength selection. Used in conjunction with PAD39STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x94 20. "PAD38_SR,Pad 39 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x94 16. "PAD38_DS1,Pad 38 high order drive strength selection. Used in conjunction with PAD38STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x94 12. "PAD37_SR,Pad 39 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x94 8. "PAD37_DS1,Pad 37 high order drive strength selection. Used in conjunction with PAD37STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x94 4. "PAD36_SR,Pad 39 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x94 0. "PAD36_DS1,Pad 36 high order drive strength selection. Used in conjunction with PAD36STRNG field to set the pad drive strength." "0,1"
|
|
line.long 0x98 "ALTPADCFGK,This register has additional configuration control for pads [43:40]"
|
|
bitfld.long 0x98 28. "PAD43_SR,Pad 43 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x98 24. "PAD43_DS1,Pad 43 high order drive strength selection. Used in conjunction with PAD43STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x98 20. "PAD42_SR,Pad 43 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x98 16. "PAD42_DS1,Pad 42 high order drive strength selection. Used in conjunction with PAD42STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x98 12. "PAD41_SR,Pad 43 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x98 8. "PAD41_DS1,Pad 41 high order drive strength selection. Used in conjunction with PAD41STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x98 4. "PAD40_SR,Pad 43 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x98 0. "PAD40_DS1,Pad 40 high order drive strength selection. Used in conjunction with PAD40STRNG field to set the pad drive strength." "0,1"
|
|
line.long 0x9C "ALTPADCFGL,This register has additional configuration control for pads [47:44]"
|
|
bitfld.long 0x9C 28. "PAD47_SR,Pad 47 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x9C 24. "PAD47_DS1,Pad 47 high order drive strength selection. Used in conjunction with PAD47STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x9C 20. "PAD46_SR,Pad 47 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x9C 16. "PAD46_DS1,Pad 46 high order drive strength selection. Used in conjunction with PAD46STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x9C 12. "PAD45_SR,Pad 47 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x9C 8. "PAD45_DS1,Pad 45 high order drive strength selection. Used in conjunction with PAD45STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0x9C 4. "PAD44_SR,Pad 47 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0x9C 0. "PAD44_DS1,Pad 44 high order drive strength selection. Used in conjunction with PAD44STRNG field to set the pad drive strength." "0,1"
|
|
line.long 0xA0 "ALTPADCFGM,This register has additional configuration control for pads [51:48]"
|
|
bitfld.long 0xA0 28. "PAD51_SR,Pad 51 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0xA0 24. "PAD51_DS1,Pad 51 high order drive strength selection. Used in conjunction with PAD51STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0xA0 20. "PAD50_SR,Pad 51 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0xA0 16. "PAD50_DS1,Pad 50 high order drive strength selection. Used in conjunction with PAD50STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0xA0 12. "PAD49_SR,Pad 51 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0xA0 8. "PAD49_DS1,Pad 49 high order drive strength selection. Used in conjunction with PAD49STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0xA0 4. "PAD48_SR,Pad 51 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0xA0 0. "PAD48_DS1,Pad 48 high order drive strength selection. Used in conjunction with PAD48STRNG field to set the pad drive strength." "0,1"
|
|
line.long 0xA4 "ALTPADCFGN,This register has additional configuration control for pads [55:52]"
|
|
bitfld.long 0xA4 28. "PAD55_SR,Pad 55 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0xA4 24. "PAD55_DS1,Pad 55 high order drive strength selection. Used in conjunction with PAD55STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0xA4 20. "PAD54_SR,Pad 55 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0xA4 16. "PAD54_DS1,Pad 54 high order drive strength selection. Used in conjunction with PAD54STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0xA4 12. "PAD53_SR,Pad 55 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0xA4 8. "PAD53_DS1,Pad 53 high order drive strength selection. Used in conjunction with PAD53STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0xA4 4. "PAD52_SR,Pad 55 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0xA4 0. "PAD52_DS1,Pad 52 high order drive strength selection. Used in conjunction with PAD52STRNG field to set the pad drive strength." "0,1"
|
|
line.long 0xA8 "ALTPADCFGO,This register has additional configuration control for pads [59:56]"
|
|
bitfld.long 0xA8 28. "PAD59_SR,Pad 59 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0xA8 24. "PAD59_DS1,Pad 59 high order drive strength selection. Used in conjunction with PAD59STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0xA8 20. "PAD58_SR,Pad 59 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0xA8 16. "PAD58_DS1,Pad 58 high order drive strength selection. Used in conjunction with PAD58STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0xA8 12. "PAD57_SR,Pad 59 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0xA8 8. "PAD57_DS1,Pad 57 high order drive strength selection. Used in conjunction with PAD57STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0xA8 4. "PAD56_SR,Pad 59 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0xA8 0. "PAD56_DS1,Pad 56 high order drive strength selection. Used in conjunction with PAD56STRNG field to set the pad drive strength." "0,1"
|
|
line.long 0xAC "ALTPADCFGP,This register has additional configuration control for pads [63:60]"
|
|
bitfld.long 0xAC 28. "PAD63_SR,Pad 63 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0xAC 24. "PAD63_DS1,Pad 63 high order drive strength selection. Used in conjunction with PAD63STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0xAC 20. "PAD62_SR,Pad 63 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0xAC 16. "PAD62_DS1,Pad 62 high order drive strength selection. Used in conjunction with PAD62STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0xAC 12. "PAD61_SR,Pad 63 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0xAC 8. "PAD61_DS1,Pad 61 high order drive strength selection. Used in conjunction with PAD61STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0xAC 4. "PAD60_SR,Pad 63 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0xAC 0. "PAD60_DS1,Pad 60 high order drive strength selection. Used in conjunction with PAD60STRNG field to set the pad drive strength." "0,1"
|
|
line.long 0xB0 "ALTPADCFGQ,This register has additional configuration control for pads [67:64]"
|
|
bitfld.long 0xB0 28. "PAD67_SR,Pad 67 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0xB0 24. "PAD67_DS1,Pad 67 high order drive strength selection. Used in conjunction with PAD67STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0xB0 20. "PAD66_SR,Pad 67 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0xB0 16. "PAD66_DS1,Pad 66 high order drive strength selection. Used in conjunction with PAD66STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0xB0 12. "PAD65_SR,Pad 67 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0xB0 8. "PAD65_DS1,Pad 65 high order drive strength selection. Used in conjunction with PAD65STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0xB0 4. "PAD64_SR,Pad 67 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0xB0 0. "PAD64_DS1,Pad 64 high order drive strength selection. Used in conjunction with PAD64STRNG field to set the pad drive strength." "0,1"
|
|
line.long 0xB4 "ALTPADCFGR,This register has additional configuration control for pads [71:68]"
|
|
bitfld.long 0xB4 28. "PAD71_SR,Pad 71 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0xB4 24. "PAD71_DS1,Pad 71 high order drive strength selection. Used in conjunction with PAD71STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0xB4 20. "PAD70_SR,Pad 71 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0xB4 16. "PAD70_DS1,Pad 70 high order drive strength selection. Used in conjunction with PAD70STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0xB4 12. "PAD69_SR,Pad 71 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0xB4 8. "PAD69_DS1,Pad 69 high order drive strength selection. Used in conjunction with PAD69STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0xB4 4. "PAD68_SR,Pad 71 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0xB4 0. "PAD68_DS1,Pad 68 high order drive strength selection. Used in conjunction with PAD68STRNG field to set the pad drive strength." "0,1"
|
|
line.long 0xB8 "ALTPADCFGS,This register has additional configuration control for pads [73:72]"
|
|
bitfld.long 0xB8 12. "PAD73_SR,Pad 73 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0xB8 8. "PAD73_DS1,Pad 73 high order drive strength selection. Used in conjunction with PAD73STRNG field to set the pad drive strength." "0,1"
|
|
newline
|
|
bitfld.long 0xB8 4. "PAD72_SR,Pad 72 slew rate selection." "?,1: Enables Slew rate control on pad"
|
|
bitfld.long 0xB8 0. "PAD72_DS1,Pad 72 high order drive strength selection. Used in conjunction with PAD72STRNG field to set the pad drive strength." "0,1"
|
|
line.long 0xBC "SCDET,SCARD card detect select."
|
|
hexmask.long.byte 0xBC 0.--6. 1. "SCDET,SCARD card detect pad select."
|
|
line.long 0xC0 "CTENCFG,Pad enable configuration."
|
|
bitfld.long 0xC0 31. "EN31,CT31 Enable" "0: Enable CT31 for output,1: Disable CT31 for output"
|
|
bitfld.long 0xC0 30. "EN30,CT30 Enable" "0: Enable CT30 for output,1: Disable CT30 for output"
|
|
newline
|
|
bitfld.long 0xC0 29. "EN29,CT29 Enable" "0: Enable CT29 for output,1: Disable CT29 for output"
|
|
bitfld.long 0xC0 28. "EN28,CT28 Enable" "0: Enable CT28 for output,1: Disable CT28 for output"
|
|
newline
|
|
bitfld.long 0xC0 27. "EN27,CT27 Enable" "0: Enable CT27 for output,1: Disable CT27 for output"
|
|
bitfld.long 0xC0 26. "EN26,CT26 Enable" "0: Enable CT26 for output,1: Disable CT26 for output"
|
|
newline
|
|
bitfld.long 0xC0 25. "EN25,CT25 Enable" "0: Enable CT25 for output,1: Disable CT25 for output"
|
|
bitfld.long 0xC0 24. "EN24,CT24 Enable" "0: Enable CT24 for output,1: Disable CT24 for output"
|
|
newline
|
|
bitfld.long 0xC0 23. "EN23,CT23 Enable" "0: Enable CT23 for output,1: Disable CT23 for output"
|
|
bitfld.long 0xC0 22. "EN22,CT22 Enable" "0: Enable CT22 for output,1: Disable CT22 for output"
|
|
newline
|
|
bitfld.long 0xC0 21. "EN21,CT21 Enable" "0: Enable CT21 for output,1: Disable CT21 for output"
|
|
bitfld.long 0xC0 20. "EN20,CT20 Enable" "0: Enable CT20 for output,1: Disable CT20 for output"
|
|
newline
|
|
bitfld.long 0xC0 19. "EN19,CT19 Enable" "0: Enable CT19 for output,1: Disable CT19 for output"
|
|
bitfld.long 0xC0 18. "EN18,CT18 Enable" "0: Enable CT18 for output,1: Disable CT18 for output"
|
|
newline
|
|
bitfld.long 0xC0 17. "EN17,CT17 Enable" "0: Enable CT17 for output,1: Disable CT17 for output"
|
|
bitfld.long 0xC0 16. "EN16,CT16 Enable" "0: Enable CT16 for output,1: Disable CT16 for output"
|
|
newline
|
|
bitfld.long 0xC0 15. "EN15,CT15 Enable" "0: Enable CT15 for output,1: Disable CT15 for output"
|
|
bitfld.long 0xC0 14. "EN14,CT14 Enable" "0: Enable CT14 for output,1: Disable CT14 for output"
|
|
newline
|
|
bitfld.long 0xC0 13. "EN13,CT13 Enable" "0: Enable CT13 for output,1: Disable CT13 for output"
|
|
bitfld.long 0xC0 12. "EN12,CT12 Enable" "0: Enable CT12 for output,1: Disable CT12 for output"
|
|
newline
|
|
bitfld.long 0xC0 11. "EN11,CT11 Enable" "0: Enable CT11 for output,1: Disable CT11 for output"
|
|
bitfld.long 0xC0 10. "EN10,CT10 Enable" "0: Enable CT10 for output,1: Disable CT10 for output"
|
|
newline
|
|
bitfld.long 0xC0 9. "EN9,CT9 Enable" "0: Disable CT9 for output,?"
|
|
bitfld.long 0xC0 8. "EN8,CT8 Enable" "0: Enable CT8 for output,1: Disable CT8 for output"
|
|
newline
|
|
bitfld.long 0xC0 7. "EN7,CT7 Enable" "0: Enable CT7 for output,1: Disable CT7 for output"
|
|
bitfld.long 0xC0 6. "EN6,CT6 Enable" "0: Enable CT6 for output,1: Disable CT6 for output"
|
|
newline
|
|
bitfld.long 0xC0 5. "EN5,CT5 Enable" "0: Enable CT5 for output,1: Disable CT5 for output"
|
|
bitfld.long 0xC0 4. "EN4,CT4 Enable" "0: Enable CT4 for output,1: Disable CT4 for output"
|
|
newline
|
|
bitfld.long 0xC0 3. "EN3,CT3 Enable" "0: Enable CT3 for output,1: Disable CT3 for output"
|
|
bitfld.long 0xC0 2. "EN2,CT2 Enable" "0: Enable CT2 for output,1: Disable CT2 for output"
|
|
newline
|
|
bitfld.long 0xC0 1. "EN1,CT1 Enable" "0: Enable CT1 for output,1: Disable CT1 for output"
|
|
bitfld.long 0xC0 0. "EN0,CT0 Enable" "0: Enable CT0 for output,1: Disable CT0 for output"
|
|
endif
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "RDA,GPIO Input Register A (31-0)"
|
|
hexmask.long 0x0 0.--31. 1. "RDA,GPIO31-0 read data."
|
|
line.long 0x4 "RDB,GPIO Input Register B (49-32)"
|
|
sif (cpuis("AMA3B1KK")||cpuis("AMAP31KK"))
|
|
hexmask.long.tbyte 0x4 0.--17. 1. "RDB,GPIO49-32 read data."
|
|
endif
|
|
sif (cpuis("AMA3B2KK"))
|
|
hexmask.long 0x4 0.--31. 1. "RDB,GPIO63-32 read data."
|
|
endif
|
|
group.long 0x200++0xF
|
|
line.long 0x0 "INT0EN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 31. "GPIO31,GPIO31 interrupt." "0,1"
|
|
bitfld.long 0x0 30. "GPIO30,GPIO30 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "GPIO29,GPIO29 interrupt." "0,1"
|
|
bitfld.long 0x0 28. "GPIO28,GPIO28 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "GPIO27,GPIO27 interrupt." "0,1"
|
|
bitfld.long 0x0 26. "GPIO26,GPIO26 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "GPIO25,GPIO25 interrupt." "0,1"
|
|
bitfld.long 0x0 24. "GPIO24,GPIO24 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "GPIO23,GPIO23 interrupt." "0,1"
|
|
bitfld.long 0x0 22. "GPIO22,GPIO22 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "GPIO21,GPIO21 interrupt." "0,1"
|
|
bitfld.long 0x0 20. "GPIO20,GPIO20 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "GPIO19,GPIO19 interrupt." "0,1"
|
|
bitfld.long 0x0 18. "GPIO18,GPIO18interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "GPIO17,GPIO17 interrupt." "0,1"
|
|
bitfld.long 0x0 16. "GPIO16,GPIO16 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "GPIO15,GPIO15 interrupt." "0,1"
|
|
bitfld.long 0x0 14. "GPIO14,GPIO14 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "GPIO13,GPIO13 interrupt." "0,1"
|
|
bitfld.long 0x0 12. "GPIO12,GPIO12 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "GPIO11,GPIO11 interrupt." "0,1"
|
|
bitfld.long 0x0 10. "GPIO10,GPIO10 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "GPIO9,GPIO9 interrupt." "0,1"
|
|
bitfld.long 0x0 8. "GPIO8,GPIO8 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "GPIO7,GPIO7 interrupt." "0,1"
|
|
bitfld.long 0x0 6. "GPIO6,GPIO6 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GPIO5,GPIO5 interrupt." "0,1"
|
|
bitfld.long 0x0 4. "GPIO4,GPIO4 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "GPIO3,GPIO3 interrupt." "0,1"
|
|
bitfld.long 0x0 2. "GPIO2,GPIO2 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "GPIO1,GPIO1 interrupt." "0,1"
|
|
bitfld.long 0x0 0. "GPIO0,GPIO0 interrupt." "0,1"
|
|
line.long 0x4 "INT0STAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 31. "GPIO31,GPIO31 interrupt." "0,1"
|
|
bitfld.long 0x4 30. "GPIO30,GPIO30 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "GPIO29,GPIO29 interrupt." "0,1"
|
|
bitfld.long 0x4 28. "GPIO28,GPIO28 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "GPIO27,GPIO27 interrupt." "0,1"
|
|
bitfld.long 0x4 26. "GPIO26,GPIO26 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "GPIO25,GPIO25 interrupt." "0,1"
|
|
bitfld.long 0x4 24. "GPIO24,GPIO24 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "GPIO23,GPIO23 interrupt." "0,1"
|
|
bitfld.long 0x4 22. "GPIO22,GPIO22 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "GPIO21,GPIO21 interrupt." "0,1"
|
|
bitfld.long 0x4 20. "GPIO20,GPIO20 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "GPIO19,GPIO19 interrupt." "0,1"
|
|
bitfld.long 0x4 18. "GPIO18,GPIO18interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "GPIO17,GPIO17 interrupt." "0,1"
|
|
bitfld.long 0x4 16. "GPIO16,GPIO16 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "GPIO15,GPIO15 interrupt." "0,1"
|
|
bitfld.long 0x4 14. "GPIO14,GPIO14 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "GPIO13,GPIO13 interrupt." "0,1"
|
|
bitfld.long 0x4 12. "GPIO12,GPIO12 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "GPIO11,GPIO11 interrupt." "0,1"
|
|
bitfld.long 0x4 10. "GPIO10,GPIO10 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "GPIO9,GPIO9 interrupt." "0,1"
|
|
bitfld.long 0x4 8. "GPIO8,GPIO8 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "GPIO7,GPIO7 interrupt." "0,1"
|
|
bitfld.long 0x4 6. "GPIO6,GPIO6 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "GPIO5,GPIO5 interrupt." "0,1"
|
|
bitfld.long 0x4 4. "GPIO4,GPIO4 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "GPIO3,GPIO3 interrupt." "0,1"
|
|
bitfld.long 0x4 2. "GPIO2,GPIO2 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "GPIO1,GPIO1 interrupt." "0,1"
|
|
bitfld.long 0x4 0. "GPIO0,GPIO0 interrupt." "0,1"
|
|
line.long 0x8 "INT0CLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 31. "GPIO31,GPIO31 interrupt." "0,1"
|
|
bitfld.long 0x8 30. "GPIO30,GPIO30 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "GPIO29,GPIO29 interrupt." "0,1"
|
|
bitfld.long 0x8 28. "GPIO28,GPIO28 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "GPIO27,GPIO27 interrupt." "0,1"
|
|
bitfld.long 0x8 26. "GPIO26,GPIO26 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "GPIO25,GPIO25 interrupt." "0,1"
|
|
bitfld.long 0x8 24. "GPIO24,GPIO24 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "GPIO23,GPIO23 interrupt." "0,1"
|
|
bitfld.long 0x8 22. "GPIO22,GPIO22 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "GPIO21,GPIO21 interrupt." "0,1"
|
|
bitfld.long 0x8 20. "GPIO20,GPIO20 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "GPIO19,GPIO19 interrupt." "0,1"
|
|
bitfld.long 0x8 18. "GPIO18,GPIO18interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "GPIO17,GPIO17 interrupt." "0,1"
|
|
bitfld.long 0x8 16. "GPIO16,GPIO16 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "GPIO15,GPIO15 interrupt." "0,1"
|
|
bitfld.long 0x8 14. "GPIO14,GPIO14 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "GPIO13,GPIO13 interrupt." "0,1"
|
|
bitfld.long 0x8 12. "GPIO12,GPIO12 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "GPIO11,GPIO11 interrupt." "0,1"
|
|
bitfld.long 0x8 10. "GPIO10,GPIO10 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "GPIO9,GPIO9 interrupt." "0,1"
|
|
bitfld.long 0x8 8. "GPIO8,GPIO8 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "GPIO7,GPIO7 interrupt." "0,1"
|
|
bitfld.long 0x8 6. "GPIO6,GPIO6 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "GPIO5,GPIO5 interrupt." "0,1"
|
|
bitfld.long 0x8 4. "GPIO4,GPIO4 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "GPIO3,GPIO3 interrupt." "0,1"
|
|
bitfld.long 0x8 2. "GPIO2,GPIO2 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "GPIO1,GPIO1 interrupt." "0,1"
|
|
bitfld.long 0x8 0. "GPIO0,GPIO0 interrupt." "0,1"
|
|
line.long 0xC "INT0SET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 31. "GPIO31,GPIO31 interrupt." "0,1"
|
|
bitfld.long 0xC 30. "GPIO30,GPIO30 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "GPIO29,GPIO29 interrupt." "0,1"
|
|
bitfld.long 0xC 28. "GPIO28,GPIO28 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "GPIO27,GPIO27 interrupt." "0,1"
|
|
bitfld.long 0xC 26. "GPIO26,GPIO26 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "GPIO25,GPIO25 interrupt." "0,1"
|
|
bitfld.long 0xC 24. "GPIO24,GPIO24 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "GPIO23,GPIO23 interrupt." "0,1"
|
|
bitfld.long 0xC 22. "GPIO22,GPIO22 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "GPIO21,GPIO21 interrupt." "0,1"
|
|
bitfld.long 0xC 20. "GPIO20,GPIO20 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "GPIO19,GPIO19 interrupt." "0,1"
|
|
bitfld.long 0xC 18. "GPIO18,GPIO18interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "GPIO17,GPIO17 interrupt." "0,1"
|
|
bitfld.long 0xC 16. "GPIO16,GPIO16 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "GPIO15,GPIO15 interrupt." "0,1"
|
|
bitfld.long 0xC 14. "GPIO14,GPIO14 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "GPIO13,GPIO13 interrupt." "0,1"
|
|
bitfld.long 0xC 12. "GPIO12,GPIO12 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "GPIO11,GPIO11 interrupt." "0,1"
|
|
bitfld.long 0xC 10. "GPIO10,GPIO10 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "GPIO9,GPIO9 interrupt." "0,1"
|
|
bitfld.long 0xC 8. "GPIO8,GPIO8 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "GPIO7,GPIO7 interrupt." "0,1"
|
|
bitfld.long 0xC 6. "GPIO6,GPIO6 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "GPIO5,GPIO5 interrupt." "0,1"
|
|
bitfld.long 0xC 4. "GPIO4,GPIO4 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "GPIO3,GPIO3 interrupt." "0,1"
|
|
bitfld.long 0xC 2. "GPIO2,GPIO2 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "GPIO1,GPIO1 interrupt." "0,1"
|
|
bitfld.long 0xC 0. "GPIO0,GPIO0 interrupt." "0,1"
|
|
sif (cpuis("AMA3B2KK"))
|
|
group.long 0x220++0xF
|
|
line.long 0x0 "INT1EN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 31. "GPIO63,GPIO63 interrupt." "0,1"
|
|
bitfld.long 0x0 30. "GPIO62,GPIO62 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "GPIO61,GPIO61 interrupt." "0,1"
|
|
bitfld.long 0x0 28. "GPIO60,GPIO60 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "GPIO59,GPIO59 interrupt." "0,1"
|
|
bitfld.long 0x0 26. "GPIO58,GPIO58 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "GPIO57,GPIO57 interrupt." "0,1"
|
|
bitfld.long 0x0 24. "GPIO56,GPIO56 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "GPIO55,GPIO55 interrupt." "0,1"
|
|
bitfld.long 0x0 22. "GPIO54,GPIO54 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "GPIO53,GPIO53 interrupt." "0,1"
|
|
bitfld.long 0x0 20. "GPIO52,GPIO52 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "GPIO51,GPIO51 interrupt." "0,1"
|
|
bitfld.long 0x0 18. "GPIO50,GPIO50 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "GPIO49,GPIO49 interrupt." "0,1"
|
|
bitfld.long 0x0 16. "GPIO48,GPIO48 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "GPIO47,GPIO47 interrupt." "0,1"
|
|
bitfld.long 0x0 14. "GPIO46,GPIO46 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "GPIO45,GPIO45 interrupt." "0,1"
|
|
bitfld.long 0x0 12. "GPIO44,GPIO44 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "GPIO43,GPIO43 interrupt." "0,1"
|
|
bitfld.long 0x0 10. "GPIO42,GPIO42 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "GPIO41,GPIO41 interrupt." "0,1"
|
|
bitfld.long 0x0 8. "GPIO40,GPIO40 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "GPIO39,GPIO39 interrupt." "0,1"
|
|
bitfld.long 0x0 6. "GPIO38,GPIO38 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GPIO37,GPIO37 interrupt." "0,1"
|
|
bitfld.long 0x0 4. "GPIO36,GPIO36 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "GPIO35,GPIO35 interrupt." "0,1"
|
|
bitfld.long 0x0 2. "GPIO34,GPIO34 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "GPIO33,GPIO33 interrupt." "0,1"
|
|
bitfld.long 0x0 0. "GPIO32,GPIO32 interrupt." "0,1"
|
|
line.long 0x4 "INT1STAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 31. "GPIO63,GPIO63 interrupt." "0,1"
|
|
bitfld.long 0x4 30. "GPIO62,GPIO62 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "GPIO61,GPIO61 interrupt." "0,1"
|
|
bitfld.long 0x4 28. "GPIO60,GPIO60 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "GPIO59,GPIO59 interrupt." "0,1"
|
|
bitfld.long 0x4 26. "GPIO58,GPIO58 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "GPIO57,GPIO57 interrupt." "0,1"
|
|
bitfld.long 0x4 24. "GPIO56,GPIO56 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "GPIO55,GPIO55 interrupt." "0,1"
|
|
bitfld.long 0x4 22. "GPIO54,GPIO54 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "GPIO53,GPIO53 interrupt." "0,1"
|
|
bitfld.long 0x4 20. "GPIO52,GPIO52 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "GPIO51,GPIO51 interrupt." "0,1"
|
|
bitfld.long 0x4 18. "GPIO50,GPIO50 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "GPIO49,GPIO49 interrupt." "0,1"
|
|
bitfld.long 0x4 16. "GPIO48,GPIO48 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "GPIO47,GPIO47 interrupt." "0,1"
|
|
bitfld.long 0x4 14. "GPIO46,GPIO46 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "GPIO45,GPIO45 interrupt." "0,1"
|
|
bitfld.long 0x4 12. "GPIO44,GPIO44 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "GPIO43,GPIO43 interrupt." "0,1"
|
|
bitfld.long 0x4 10. "GPIO42,GPIO42 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "GPIO41,GPIO41 interrupt." "0,1"
|
|
bitfld.long 0x4 8. "GPIO40,GPIO40 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "GPIO39,GPIO39 interrupt." "0,1"
|
|
bitfld.long 0x4 6. "GPIO38,GPIO38 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "GPIO37,GPIO37 interrupt." "0,1"
|
|
bitfld.long 0x4 4. "GPIO36,GPIO36 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "GPIO35,GPIO35 interrupt." "0,1"
|
|
bitfld.long 0x4 2. "GPIO34,GPIO34 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "GPIO33,GPIO33 interrupt." "0,1"
|
|
bitfld.long 0x4 0. "GPIO32,GPIO32 interrupt." "0,1"
|
|
line.long 0x8 "INT1CLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 31. "GPIO63,GPIO63 interrupt." "0,1"
|
|
bitfld.long 0x8 30. "GPIO62,GPIO62 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "GPIO61,GPIO61 interrupt." "0,1"
|
|
bitfld.long 0x8 28. "GPIO60,GPIO60 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "GPIO59,GPIO59 interrupt." "0,1"
|
|
bitfld.long 0x8 26. "GPIO58,GPIO58 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "GPIO57,GPIO57 interrupt." "0,1"
|
|
bitfld.long 0x8 24. "GPIO56,GPIO56 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "GPIO55,GPIO55 interrupt." "0,1"
|
|
bitfld.long 0x8 22. "GPIO54,GPIO54 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "GPIO53,GPIO53 interrupt." "0,1"
|
|
bitfld.long 0x8 20. "GPIO52,GPIO52 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "GPIO51,GPIO51 interrupt." "0,1"
|
|
bitfld.long 0x8 18. "GPIO50,GPIO50 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "GPIO49,GPIO49 interrupt." "0,1"
|
|
bitfld.long 0x8 16. "GPIO48,GPIO48 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "GPIO47,GPIO47 interrupt." "0,1"
|
|
bitfld.long 0x8 14. "GPIO46,GPIO46 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "GPIO45,GPIO45 interrupt." "0,1"
|
|
bitfld.long 0x8 12. "GPIO44,GPIO44 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "GPIO43,GPIO43 interrupt." "0,1"
|
|
bitfld.long 0x8 10. "GPIO42,GPIO42 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "GPIO41,GPIO41 interrupt." "0,1"
|
|
bitfld.long 0x8 8. "GPIO40,GPIO40 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "GPIO39,GPIO39 interrupt." "0,1"
|
|
bitfld.long 0x8 6. "GPIO38,GPIO38 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "GPIO37,GPIO37 interrupt." "0,1"
|
|
bitfld.long 0x8 4. "GPIO36,GPIO36 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "GPIO35,GPIO35 interrupt." "0,1"
|
|
bitfld.long 0x8 2. "GPIO34,GPIO34 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "GPIO33,GPIO33 interrupt." "0,1"
|
|
bitfld.long 0x8 0. "GPIO32,GPIO32 interrupt." "0,1"
|
|
line.long 0xC "INT1SET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 31. "GPIO63,GPIO63 interrupt." "0,1"
|
|
bitfld.long 0xC 30. "GPIO62,GPIO62 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "GPIO61,GPIO61 interrupt." "0,1"
|
|
bitfld.long 0xC 28. "GPIO60,GPIO60 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "GPIO59,GPIO59 interrupt." "0,1"
|
|
bitfld.long 0xC 26. "GPIO58,GPIO58 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "GPIO57,GPIO57 interrupt." "0,1"
|
|
bitfld.long 0xC 24. "GPIO56,GPIO56 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "GPIO55,GPIO55 interrupt." "0,1"
|
|
bitfld.long 0xC 22. "GPIO54,GPIO54 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "GPIO53,GPIO53 interrupt." "0,1"
|
|
bitfld.long 0xC 20. "GPIO52,GPIO52 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "GPIO51,GPIO51 interrupt." "0,1"
|
|
bitfld.long 0xC 18. "GPIO50,GPIO50 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "GPIO49,GPIO49 interrupt." "0,1"
|
|
bitfld.long 0xC 16. "GPIO48,GPIO48 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "GPIO47,GPIO47 interrupt." "0,1"
|
|
bitfld.long 0xC 14. "GPIO46,GPIO46 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "GPIO45,GPIO45 interrupt." "0,1"
|
|
bitfld.long 0xC 12. "GPIO44,GPIO44 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "GPIO43,GPIO43 interrupt." "0,1"
|
|
bitfld.long 0xC 10. "GPIO42,GPIO42 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "GPIO41,GPIO41 interrupt." "0,1"
|
|
bitfld.long 0xC 8. "GPIO40,GPIO40 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "GPIO39,GPIO39 interrupt." "0,1"
|
|
bitfld.long 0xC 6. "GPIO38,GPIO38 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "GPIO37,GPIO37 interrupt." "0,1"
|
|
bitfld.long 0xC 4. "GPIO36,GPIO36 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "GPIO35,GPIO35 interrupt." "0,1"
|
|
bitfld.long 0xC 2. "GPIO34,GPIO34 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "GPIO33,GPIO33 interrupt." "0,1"
|
|
bitfld.long 0xC 0. "GPIO32,GPIO32 interrupt." "0,1"
|
|
group.long 0x240++0x13
|
|
line.long 0x0 "INT2EN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 9. "GPIO73,GPIO73 interrupt." "0,1"
|
|
bitfld.long 0x0 8. "GPIO72,GPIO72 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "GPIO71,GPIO71 interrupt." "0,1"
|
|
bitfld.long 0x0 6. "GPIO70,GPIO70 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GPIO69,GPIO69 interrupt." "0,1"
|
|
bitfld.long 0x0 4. "GPIO68,GPIO68 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "GPIO67,GPIO67 interrupt." "0,1"
|
|
bitfld.long 0x0 2. "GPIO66,GPIO66 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "GPIO65,GPIO65 interrupt." "0,1"
|
|
bitfld.long 0x0 0. "GPIO64,GPIO64 interrupt." "0,1"
|
|
line.long 0x4 "INT2STAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 9. "GPIO73,GPIO73 interrupt." "0,1"
|
|
bitfld.long 0x4 8. "GPIO72,GPIO72 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "GPIO71,GPIO71 interrupt." "0,1"
|
|
bitfld.long 0x4 6. "GPIO70,GPIO70 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "GPIO69,GPIO69 interrupt." "0,1"
|
|
bitfld.long 0x4 4. "GPIO68,GPIO68 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "GPIO67,GPIO67 interrupt." "0,1"
|
|
bitfld.long 0x4 2. "GPIO66,GPIO66 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "GPIO65,GPIO65 interrupt." "0,1"
|
|
bitfld.long 0x4 0. "GPIO64,GPIO64 interrupt." "0,1"
|
|
line.long 0x8 "INT2CLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 9. "GPIO73,GPIO73 interrupt." "0,1"
|
|
bitfld.long 0x8 8. "GPIO72,GPIO72 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "GPIO71,GPIO71 interrupt." "0,1"
|
|
bitfld.long 0x8 6. "GPIO70,GPIO70 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "GPIO69,GPIO69 interrupt." "0,1"
|
|
bitfld.long 0x8 4. "GPIO68,GPIO68 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "GPIO67,GPIO67 interrupt." "0,1"
|
|
bitfld.long 0x8 2. "GPIO66,GPIO66 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "GPIO65,GPIO65 interrupt." "0,1"
|
|
bitfld.long 0x8 0. "GPIO64,GPIO64 interrupt." "0,1"
|
|
line.long 0xC "INT2SET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 9. "GPIO73,GPIO73 interrupt." "0,1"
|
|
bitfld.long 0xC 8. "GPIO72,GPIO72 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "GPIO71,GPIO71 interrupt." "0,1"
|
|
bitfld.long 0xC 6. "GPIO70,GPIO70 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "GPIO69,GPIO69 interrupt." "0,1"
|
|
bitfld.long 0xC 4. "GPIO68,GPIO68 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "GPIO67,GPIO67 interrupt." "0,1"
|
|
bitfld.long 0xC 2. "GPIO66,GPIO66 interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "GPIO65,GPIO65 interrupt." "0,1"
|
|
bitfld.long 0xC 0. "GPIO64,GPIO64 interrupt." "0,1"
|
|
line.long 0x10 "DBGCTRL,Debug control for test purposes only"
|
|
bitfld.long 0x10 5. "GCLK5,Gate IOM5 CLK in SPI mode allowing external input clock" "0,1"
|
|
bitfld.long 0x10 4. "GCLK4,Gate IOM4 CLK in SPI mode allowing external input clock" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "GCLK3,Gate IOM3 CLK in SPI mode allowing external input clock" "0,1"
|
|
bitfld.long 0x10 2. "GCLK2,Gate IOM2 CLK in SPI mode allowing external input clock" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "GCLK1,Gate IOM1 CLK in SPI mode allowing external input clock" "0,1"
|
|
bitfld.long 0x10 0. "GCLK0,Gate IOM0 CLK in SPI mode allowing external input clock" "0,1"
|
|
endif
|
|
tree.end
|
|
tree "IOM (IO Peripheral Master)"
|
|
base ad:0x0
|
|
sif (cpuis("AMA3B1KK")||cpuis("AMAP31KK"))
|
|
tree "IOM0"
|
|
base ad:0x50004000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FIFO,Provides direct random access to both output and input FIFOs. The state of the FIFO is not disturbed by reading these locations (i.e.. no POP will be done). FIFO0 is accessible from addresses 0x0 - 0x1C. and is used for data output from the IOM to.."
|
|
hexmask.long 0x0 0.--31. 1. "FIFO,FIFO direct access. Only locations 0 - 3F will return valid information."
|
|
group.long 0x100++0x17
|
|
line.long 0x0 "FIFOPTR,Provides the current valid byte count of data within the FIFO as seen from the internal state machines. FIFO0 is dedicated to outgoing transactions and FIFO1 is dedicated to incoming transactions. All counts are specified in units of bytes."
|
|
hexmask.long.byte 0x0 24.--31. 1. "FIFO1REM,The number of remaining data bytes slots currently in FIFO 1 (written by interface read by MCU)"
|
|
hexmask.long.byte 0x0 16.--23. 1. "FIFO1SIZ,The number of valid data bytes currently in FIFO 1 (written by interface read by MCU)"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "FIFO0REM,The number of remaining data bytes slots currently in FIFO 0 (written by MCU read by interface)"
|
|
hexmask.long.byte 0x0 0.--7. 1. "FIFO0SIZ,The number of valid data bytes currently in the FIFO 0 (written by MCU read by interface)"
|
|
line.long 0x4 "FIFOTHR,Sets the threshold values for incoming and outgoing transactions. The threshold values are used to assert the interrupt if enabled. and also used during DMA to set the transfer size as a result of DMATHR trigger."
|
|
hexmask.long.byte 0x4 8.--13. 1. "FIFOWTHR,FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the write FIFO contains FIFOWTHR free bytes as.."
|
|
hexmask.long.byte 0x4 0.--5. 1. "FIFORTHR,FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the read FIFO contains FIFORTHR valid bytes of data as.."
|
|
line.long 0x8 "FIFOPOP,Will advance the internal read pointer of the incoming FIFO (FIFO1) when read. if POPWR is not active. If POPWR is active. a write to this register is needed to advance the internal FIFO pointer."
|
|
hexmask.long 0x8 0.--31. 1. "FIFODOUT,This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0) the FIFO read pointer will be advanced by one word as a result of the read."
|
|
line.long 0xC "FIFOPUSH,Will write new data into the outgoing FIFO and advance the internal write pointer."
|
|
hexmask.long 0xC 0.--31. 1. "FIFODIN,This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes)."
|
|
line.long 0x10 "FIFOCTRL,Provides controls for the operation of the internal FIFOs. Contains fields used to control the operation of the POP register. and also controls to reset the internal pointers of the FIFOs."
|
|
bitfld.long 0x10 1. "FIFORSTN,Active low manual reset of the FIFO. Write to 0 to reset FIFO and then write to 1 to remove the reset." "0,1"
|
|
bitfld.long 0x10 0. "POPWR,Selects the mode in which 'pop' events are done for the FIFO read operations. A value of '1' will prevent a pop event on a read operation and will require a write to the FIFOPOP register to create a pop event." "0,1"
|
|
line.long 0x14 "FIFOLOC,Provides a read only value of the current read and write pointers. This register is read only and can be used along with the FIFO direct access method to determine the next data to be used for input and output functions."
|
|
hexmask.long.byte 0x14 8.--11. 1. "FIFORPTR,Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1) which is used to store read data returned from external devices during a read operation."
|
|
hexmask.long.byte 0x14 0.--3. 1. "FIFOWPTR,Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0) which is used during write operations to external devices."
|
|
group.long 0x200++0x27
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 14. "CQERR,Error during command queue operations" "0,1"
|
|
bitfld.long 0x0 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
|
|
bitfld.long 0x0 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0x0 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x0 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x0 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0x0 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
|
|
bitfld.long 0x0 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 14. "CQERR,Error during command queue operations" "0,1"
|
|
bitfld.long 0x4 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
|
|
bitfld.long 0x4 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0x4 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x4 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x4 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0x4 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
|
|
bitfld.long 0x4 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 14. "CQERR,Error during command queue operations" "0,1"
|
|
bitfld.long 0x8 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
|
|
bitfld.long 0x8 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0x8 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x8 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x8 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0x8 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
|
|
bitfld.long 0x8 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 14. "CQERR,Error during command queue operations" "0,1"
|
|
bitfld.long 0xC 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
|
|
bitfld.long 0xC 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0xC 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0xC 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0xC 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0xC 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
|
|
bitfld.long 0xC 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
|
|
line.long 0x10 "CLKCFG,Provides clock related controls used internal to the BLEIF module. and enablement of 32KHz clock to the BLE Core module. The internal clock sourced is selected via the FSEL and can be further divided by 3 using the DIV3 control."
|
|
hexmask.long.byte 0x10 24.--31. 1. "TOTPER,Clock total clock count minus 1. This provides the total period of the divided clock -1 when the DIVEN is active. The"
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hexmask.long.byte 0x10 16.--23. 1. "LOWPER,Clock low clock count minus 1. This provides the number of clocks the divided clock will be low when the DIVEN = 1."
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bitfld.long 0x10 12. "DIVEN,Enable clock division by TOTPER and LOWPER" "0: Disable TOTPER division.,1: Enable TOTPER division."
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bitfld.long 0x10 11. "DIV3,Enable divide by 3 of the source IOCLK. Division by 3 is done before the DIVEN programmable divider and if enabled" "0: Select divide by 1.,1: Select divide by 3."
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bitfld.long 0x10 8.--10. "FSEL,Select the input clock frequency." "0: Selects the minimum power clock. This setting..,1: Selects the HFRC as the input clock.,2: Selects the HFRC / 2 as the input clock.,3: Selects the HFRC / 4 as the input clock.,4: Selects the HFRC / 8 as the input clock.,5: Selects the HFRC / 16 as the input clock.,6: Selects the HFRC / 32 as the input clock.,7: Selects the HFRC / 64 as the input clock."
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bitfld.long 0x10 0. "IOCLKEN,Enable for the interface clock. Must be enabled prior to executing any IO operations." "0,1"
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|
line.long 0x14 "SUBMODCTRL,Provides enable for each submodule. Only a single submodule can be enabled at one time."
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bitfld.long 0x14 5.--7. "SMOD1TYPE,Submodule 0 module type. This is the I2C Master interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,?,?,?,7: NOT INSTALLED"
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bitfld.long 0x14 4. "SMOD1EN,Submodule 1 enable (1) or disable (0)" "0,1"
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bitfld.long 0x14 1.--3. "SMOD0TYPE,Submodule 0 module type. This is the SPI Master interface." "0: MSPI submodule,1: I2C Master submodule,2: SPI Slave submodule,3: I2C Slave submodule,?,?,?,7: NOT INSTALLED"
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bitfld.long 0x14 0. "SMOD0EN,Submodule 0 enable (1) or disable (0)" "0,1"
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line.long 0x18 "CMD,Writes to this register will start an IO transaction. as well as set various parameters for the command itself. Reads will return the command value written to the CMD register."
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hexmask.long.byte 0x18 24.--31. 1. "OFFSETLO,This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command."
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bitfld.long 0x18 20.--21. "CMDSEL,Command Specific selection information. Not used in Master I2C. Used as CEn select for Master SPI transactions" "0,1,2,3"
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hexmask.long.word 0x18 8.--19. 1. "TSIZE,Defines the transaction size in bytes. The offset transfer is not included in this size."
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bitfld.long 0x18 7. "CONT,Continue to hold the bus after the current transaction if set to a 1 with a new command issued." "0,1"
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bitfld.long 0x18 5.--6. "OFFSETCNT,Number of offset bytes to use for the command - 0 1 2 3 are valid selections. The second (byte 1) and third byte (byte 2) are read from the OFFSETHI register and the low order byte is pulled from this register in the OFFSETLO field." "0,1,2,3"
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hexmask.long.byte 0x18 0.--4. 1. "CMD,Command for submodule."
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line.long 0x1C "DCX,Enables use of CE signals to transmit DCX level for SPI transactions. Only used in Apollo3 Revision B. For Revision A. this register MUST NOT be programmed!"
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bitfld.long 0x1C 4. "DCXEN,Revision A: MUST NOT be programmed! Revision B: Bit 4: DCX Signaling Enable via other CE signals. The selected DCX signal (unused CE pin) will be driven low during write of offset byte and high during transmission of data bytes." "0: Disable DCX.,1: Enable DCX."
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bitfld.long 0x1C 3. "CE3OUT,Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE3 output." "0,1"
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bitfld.long 0x1C 2. "CE2OUT,Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE2 output." "0,1"
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bitfld.long 0x1C 1. "CE1OUT,Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE1 output." "0,1"
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bitfld.long 0x1C 0. "CE0OUT,Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE0 output." "0,1"
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line.long 0x20 "OFFSETHI,High order 2 bytes of 3 byte offset for IO transaction"
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hexmask.long.word 0x20 0.--15. 1. "OFFSETHI,Holds the high order 2 bytes of the 3 byte addressing/offset field to use with IO commands. The number of offset bytes to use is specified in the command register"
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line.long 0x24 "CMDSTAT,Provides status on the execution of the command currently in progress. The fields in this register will reflect the real time status of the internal state machines and data transfers within the IOM."
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hexmask.long.word 0x24 8.--19. 1. "CTSIZE,The current number of bytes still to be transferred with this command. This field will count down to zero."
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bitfld.long 0x24 5.--7. "CMDSTAT,The current status of the command execution." "?,1: Error encountered with command,2: Actively processing command,?,4: Idle state no active command no error,?,6: Command in progress but waiting on data from host,?"
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hexmask.long.byte 0x24 0.--4. 1. "CCMD,current command that is being executed"
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|
group.long 0x240++0x7
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line.long 0x0 "DMATRIGEN,Provides control on which event will trigger the DMA transfer after the DMA operation is setup and enabled. The trigger event will cause a number of bytes (depending on trigger event) to be"
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bitfld.long 0x0 1. "DTHREN,Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes) the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO and will transfer (WTHR/4) number of words" "0,1"
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bitfld.long 0x0 0. "DCMDCMPEN,Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered the number of words transferred will be the lesser of the remaining TOTCOUNT bytes or" "0,1"
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line.long 0x4 "DMATRIGSTAT,Provides the status of trigger events that have occurred for the transaction. Some of the bits are read only and some can be reset via a write of 0."
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bitfld.long 0x4 2. "DTOTCMP,DMA triggered when DCMDCMP = 0 and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is" "0,1"
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bitfld.long 0x4 1. "DTHR,Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA." "0,1"
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bitfld.long 0x4 0. "DCMDCMP,Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA." "0,1"
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group.long 0x280++0x3
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line.long 0x0 "DMACFG,Configuration control of the DMA process. including the direction of DMA. and enablement of DMA"
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bitfld.long 0x0 9. "DPWROFF,Power off module after DMA is complete. If this bit is active the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain power down will not be performed." "0: Power off disabled,1: Power off enabled"
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bitfld.long 0x0 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x0 1. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction. To be..,1: Memory to Peripheral transaction. To be set when.."
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bitfld.long 0x0 0. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable DMA Function,1: Enable DMA Function"
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group.long 0x288++0x2F
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line.long 0x0 "DMATOTCOUNT,Contains the number of bytes to be transferred for this DMA transaction. This register is decremented as the data is transferred. and will be 0 at the completion of the DMA operation."
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hexmask.long.word 0x0 0.--11. 1. "TOTCOUNT,Triggered DMA from Command complete event occurred. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."
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line.long 0x4 "DMATARGADDR,The source or destination address internal the SRAM for the DMA data. For write operations. this can only be SRAM data (ADDR bit 28 = 1); For read operations. this can be either SRAM or FLASH (ADDR bit 28 = 0)"
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bitfld.long 0x4 28. "TARGADDR28,Bit 28 of the target byte address for source of DMA (either read or write). In cases of non-word aligned addresses the DMA logic will take care for ensuring only the target bytes are read/written." "0,1"
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hexmask.long.tbyte 0x4 0.--19. 1. "TARGADDR,Bits [19:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment and does not have to be word aligned. In cases of non-word aligned addresses the DMA logic will take care for ensuring only.."
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line.long 0x8 "DMASTAT,Status of the DMA operation currently in progress."
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bitfld.long 0x8 2. "DMAERR,DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set this bit will remain set until cleared by software." "0,1"
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bitfld.long 0x8 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0 and will also be cleared when a new DMA is started." "0,1"
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bitfld.long 0x8 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
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line.long 0xC "CQCFG,Controls parameters and options for execution of the command queue operation. To enable command queue. create this in memory. set the address. and enable it with a write to CQEN"
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bitfld.long 0xC 1. "CQPRI,Sets the Priority of the command queue DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0xC 0. "CQEN,Command queue enable. When set will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled using a CQ executed write to this bit as well." "0: Disable CQ Function,1: Enable CQ Function"
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line.long 0x10 "CQADDR,The SRAM address which will be fetched next execution of the CQ operation. This register is updated as the CQ operation progresses. and is the live version of the register. The register can also be written by the Command Queue operation itself..."
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bitfld.long 0x10 28. "CQADDR28,Bit 28 of target byte address for source of CQ. Used to denote Flash (0) or SRAM (1) access" "0,1"
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hexmask.long.tbyte 0x10 2.--19. 1. "CQADDR,Bits 19:2 of target byte address for source of CQ. The buffer must be aligned on a word boundary"
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line.long 0x14 "CQSTAT,Provides the status of the command queue operation. If the command queue is disabled. these bits will be cleared. The bits are read only"
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bitfld.long 0x14 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
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bitfld.long 0x14 1. "CQPAUSED,Command queue operation is currently paused." "0,1"
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bitfld.long 0x14 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
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line.long 0x18 "CQFLAGS,Command Queue Flag"
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hexmask.long.word 0x18 16.--31. 1. "CQIRQMASK,Mask the bits used to generate the command queue interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE"
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hexmask.long.word 0x18 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
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line.long 0x1C "CQSETCLEAR,Set/Clear the command queue software pause flags on a per-bit basis. Contains 3 fields. allowing for setting. clearing or toggling the value in the software flags. Priority when the same bit"
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hexmask.long.byte 0x1C 16.--23. 1. "CQFCLR,Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x1C 8.--15. 1. "CQFTGL,Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x1C 0.--7. 1. "CQFSET,Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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line.long 0x20 "CQPAUSEEN,Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the CQFLAG register is '1'. CQ processing will halt until either value is changed to '0'."
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hexmask.long.word 0x20 0.--15. 1. "CQPEN,Enables the specified event to pause command processing when active"
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line.long 0x24 "CQCURIDX,Current index value. targeted to be written by register write operations within the command queue. This is compared to the CQENDIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and"
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hexmask.long.byte 0x24 0.--7. 1. "CQCURIDX,Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x28 "CQENDIDX,End index value. targeted to be written by software to indicate the last valid register pair contained within the command queue for a register write operations within the command queue."
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hexmask.long.byte 0x28 0.--7. 1. "CQENDIDX,Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x2C "STATUS,IOM Module Status"
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bitfld.long 0x2C 2. "IDLEST,indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to hold-offs from data availability or as the command gets propagated into the logic from the registers." "?,1: The I/O state machine is in the idle state."
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bitfld.long 0x2C 1. "CMDACT,Indicates if the active I/O Command is currently processing a transaction or command is complete but the FIFO pointers are still synchronizing internally. This bit will go high at" "?,1: An I/O command is active. Indicates the active.."
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bitfld.long 0x2C 0. "ERR,Bit has been deprecated. Please refer to the other error indicators. This will always return 0." "?,1: Bit has been deprecated and will always return 0."
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group.long 0x300++0x3
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line.long 0x0 "MSPICFG,Controls the configuration of the SPI master module. including POL/PHA. LSB. flow control. and delays for MISO and MOSI"
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bitfld.long 0x0 30. "MSPIRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 27.--29. "DOUTDLY,Delay tap to use for the output signal (MOSI). This give more hold time on the output data" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 24.--26. "DINDLY,Delay tap to use for the input signal (MISO). This gives more hold time on the input data." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "SPILSB,Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first." "0: Send and receive MSB bit first,1: Send and receive LSB bit first"
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bitfld.long 0x0 22. "RDFCPOL,selects the read flow control signal polarity." "0: Flow control signal high creates flow control.,1: Flow control signal low creates flow control."
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bitfld.long 0x0 21. "WTFCPOL,selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 will allow a IRQ=1 to pause transfers)." "0: Flow control signal high(1) creates flow control..,1: Flow control signal low(0) creates flow control.."
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bitfld.long 0x0 20. "WTFCIRQ,selects the write mode flow control signal." "0: MISO is used as the write mode flow control..,1: IRQ is used as the write mode flow control signal."
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bitfld.long 0x0 18. "MOSIINV,inverts MOSI when flow control is enabled." "0: MOSI is set to 0 in read mode and 1 in write mode.,1: MOSI is set to 1 in read mode and 0 in write mode."
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bitfld.long 0x0 17. "RDFC,enables read mode flow control." "0: Read mode flow control disabled.,1: Read mode flow control enabled."
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bitfld.long 0x0 16. "WTFC,enables write mode flow control." "0: Write mode flow control disabled.,1: Write mode flow control enabled."
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bitfld.long 0x0 2. "FULLDUP,Enables full duplex mode for Master SPI write operations. Data will be captured simultaneously into the read FIFO" "0,1"
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|
bitfld.long 0x0 1. "SPHA,selects SPI phase." "0: Sample on the leading (first) clock edge.,1: Sample on the trailing (second) clock edge."
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bitfld.long 0x0 0. "SPOL,selects SPI polarity." "0: The base value of the clock is 0.,1: The base value of the clock is 1."
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group.long 0x400++0x7
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line.long 0x0 "MI2CCFG,Controls the configuration of the I2C bus master."
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bitfld.long 0x0 24. "STRDIS,Disable detection of clock stretch events smaller than 1 cycle" "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "SMPCNT,Number of Base clock cycles to wait before sampling the SCL clock to determine if a clock stretch event has occurred"
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hexmask.long.byte 0x0 12.--15. 1. "SDAENDLY,Number of IOCLK cycles to delay the SDA output en (all transitions affected). Used to delay data relative to clock"
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hexmask.long.byte 0x0 8.--11. 1. "SCLENDLY,Number of IOCLK cycles to delay the rising edge of the SCL output en (clock will go low on this edge). Used to allow clock shaping."
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bitfld.long 0x0 6. "MI2CRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
|
|
bitfld.long 0x0 4.--5. "SDADLY,Delay to enable on the SDA output. Values are 0x0-0x3." "0,1,2,3"
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bitfld.long 0x0 2. "ARBEN,Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master this function can be disabled to save clock cycles on I2C transactions" "0: Disable multi-master bus arbitration support for..,1: Enable multi-master bus arbitration support for.."
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bitfld.long 0x0 1. "I2CLSB,Direction of data transmit and receive MSB(0) or LSB(1) first. Default per I2C specification is MSB first. This applies to both read and write data and read data will be bit" "0: Byte data is transmitted MSB first onto the..,1: Byte data is transmitted LSB first onto the.."
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bitfld.long 0x0 0. "ADDRSZ,Sets the I2C master device address size to either 7 bits (0) or 10 bits (1)." "0: Use 7-bit addressing for I2C master transactions,1: Use 10-bit addressing for I2C master transactions"
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line.long 0x4 "DEVCFG,Contains the I2C device address."
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hexmask.long.word 0x4 0.--9. 1. "DEVADDR,I2C address of the device that the Master will use to target for read/write operations. This can be either a 7-bit or 10-bit address."
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group.long 0x410++0x3
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line.long 0x0 "IOMDBG,Debug control"
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hexmask.long 0x0 3.--31. 1. "DBGDATA,Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers."
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bitfld.long 0x0 2. "APBCLKON,APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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newline
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bitfld.long 0x0 1. "IOCLKON,IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
|
|
bitfld.long 0x0 0. "DBGEN,Debug Enable. Setting bit will enable the update of data within this register otherwise it is clock gated for power savings" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("AMA3B1KK")||cpuis("AMAP31KK"))
|
|
tree "IOM1"
|
|
base ad:0x50005000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FIFO,Provides direct random access to both output and input FIFOs. The state of the FIFO is not disturbed by reading these locations (i.e.. no POP will be done). FIFO0 is accessible from addresses 0x0 - 0x1C. and is used for data output from the IOM to.."
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hexmask.long 0x0 0.--31. 1. "FIFO,FIFO direct access. Only locations 0 - 3F will return valid information."
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group.long 0x100++0x17
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line.long 0x0 "FIFOPTR,Provides the current valid byte count of data within the FIFO as seen from the internal state machines. FIFO0 is dedicated to outgoing transactions and FIFO1 is dedicated to incoming transactions. All counts are specified in units of bytes."
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hexmask.long.byte 0x0 24.--31. 1. "FIFO1REM,The number of remaining data bytes slots currently in FIFO 1 (written by interface read by MCU)"
|
|
hexmask.long.byte 0x0 16.--23. 1. "FIFO1SIZ,The number of valid data bytes currently in FIFO 1 (written by interface read by MCU)"
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|
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hexmask.long.byte 0x0 8.--15. 1. "FIFO0REM,The number of remaining data bytes slots currently in FIFO 0 (written by MCU read by interface)"
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|
hexmask.long.byte 0x0 0.--7. 1. "FIFO0SIZ,The number of valid data bytes currently in the FIFO 0 (written by MCU read by interface)"
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line.long 0x4 "FIFOTHR,Sets the threshold values for incoming and outgoing transactions. The threshold values are used to assert the interrupt if enabled. and also used during DMA to set the transfer size as a result of DMATHR trigger."
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hexmask.long.byte 0x4 8.--13. 1. "FIFOWTHR,FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the write FIFO contains FIFOWTHR free bytes as.."
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|
hexmask.long.byte 0x4 0.--5. 1. "FIFORTHR,FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the read FIFO contains FIFORTHR valid bytes of data as.."
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|
line.long 0x8 "FIFOPOP,Will advance the internal read pointer of the incoming FIFO (FIFO1) when read. if POPWR is not active. If POPWR is active. a write to this register is needed to advance the internal FIFO pointer."
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hexmask.long 0x8 0.--31. 1. "FIFODOUT,This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0) the FIFO read pointer will be advanced by one word as a result of the read."
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|
line.long 0xC "FIFOPUSH,Will write new data into the outgoing FIFO and advance the internal write pointer."
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|
hexmask.long 0xC 0.--31. 1. "FIFODIN,This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes)."
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line.long 0x10 "FIFOCTRL,Provides controls for the operation of the internal FIFOs. Contains fields used to control the operation of the POP register. and also controls to reset the internal pointers of the FIFOs."
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bitfld.long 0x10 1. "FIFORSTN,Active low manual reset of the FIFO. Write to 0 to reset FIFO and then write to 1 to remove the reset." "0,1"
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|
bitfld.long 0x10 0. "POPWR,Selects the mode in which 'pop' events are done for the FIFO read operations. A value of '1' will prevent a pop event on a read operation and will require a write to the FIFOPOP register to create a pop event." "0,1"
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|
line.long 0x14 "FIFOLOC,Provides a read only value of the current read and write pointers. This register is read only and can be used along with the FIFO direct access method to determine the next data to be used for input and output functions."
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hexmask.long.byte 0x14 8.--11. 1. "FIFORPTR,Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1) which is used to store read data returned from external devices during a read operation."
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|
hexmask.long.byte 0x14 0.--3. 1. "FIFOWPTR,Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0) which is used during write operations to external devices."
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|
group.long 0x200++0x27
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line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
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bitfld.long 0x0 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x0 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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newline
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bitfld.long 0x0 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x0 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x0 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x0 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0x0 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x0 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x0 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x0 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x0 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x0 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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bitfld.long 0x0 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
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bitfld.long 0x0 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x0 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
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bitfld.long 0x4 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x4 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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newline
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bitfld.long 0x4 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x4 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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newline
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bitfld.long 0x4 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x4 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0x4 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x4 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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newline
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bitfld.long 0x4 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x4 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x4 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x4 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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bitfld.long 0x4 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
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bitfld.long 0x4 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x4 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
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bitfld.long 0x8 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x8 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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newline
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bitfld.long 0x8 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x8 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x8 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x8 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0x8 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x8 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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newline
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bitfld.long 0x8 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x8 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x8 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x8 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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bitfld.long 0x8 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
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bitfld.long 0x8 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x8 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
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bitfld.long 0xC 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0xC 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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newline
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bitfld.long 0xC 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0xC 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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newline
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bitfld.long 0xC 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0xC 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0xC 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0xC 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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newline
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bitfld.long 0xC 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0xC 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0xC 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0xC 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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newline
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bitfld.long 0xC 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
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bitfld.long 0xC 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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newline
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bitfld.long 0xC 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x10 "CLKCFG,Provides clock related controls used internal to the BLEIF module. and enablement of 32KHz clock to the BLE Core module. The internal clock sourced is selected via the FSEL and can be further divided by 3 using the DIV3 control."
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hexmask.long.byte 0x10 24.--31. 1. "TOTPER,Clock total clock count minus 1. This provides the total period of the divided clock -1 when the DIVEN is active. The"
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hexmask.long.byte 0x10 16.--23. 1. "LOWPER,Clock low clock count minus 1. This provides the number of clocks the divided clock will be low when the DIVEN = 1."
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newline
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bitfld.long 0x10 12. "DIVEN,Enable clock division by TOTPER and LOWPER" "0: Disable TOTPER division.,1: Enable TOTPER division."
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bitfld.long 0x10 11. "DIV3,Enable divide by 3 of the source IOCLK. Division by 3 is done before the DIVEN programmable divider and if enabled" "0: Select divide by 1.,1: Select divide by 3."
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newline
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bitfld.long 0x10 8.--10. "FSEL,Select the input clock frequency." "0: Selects the minimum power clock. This setting..,1: Selects the HFRC as the input clock.,2: Selects the HFRC / 2 as the input clock.,3: Selects the HFRC / 4 as the input clock.,4: Selects the HFRC / 8 as the input clock.,5: Selects the HFRC / 16 as the input clock.,6: Selects the HFRC / 32 as the input clock.,7: Selects the HFRC / 64 as the input clock."
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bitfld.long 0x10 0. "IOCLKEN,Enable for the interface clock. Must be enabled prior to executing any IO operations." "0,1"
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line.long 0x14 "SUBMODCTRL,Provides enable for each submodule. Only a single submodule can be enabled at one time."
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bitfld.long 0x14 5.--7. "SMOD1TYPE,Submodule 0 module type. This is the I2C Master interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,?,?,?,7: NOT INSTALLED"
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bitfld.long 0x14 4. "SMOD1EN,Submodule 1 enable (1) or disable (0)" "0,1"
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newline
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bitfld.long 0x14 1.--3. "SMOD0TYPE,Submodule 0 module type. This is the SPI Master interface." "0: MSPI submodule,1: I2C Master submodule,2: SPI Slave submodule,3: I2C Slave submodule,?,?,?,7: NOT INSTALLED"
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bitfld.long 0x14 0. "SMOD0EN,Submodule 0 enable (1) or disable (0)" "0,1"
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line.long 0x18 "CMD,Writes to this register will start an IO transaction. as well as set various parameters for the command itself. Reads will return the command value written to the CMD register."
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hexmask.long.byte 0x18 24.--31. 1. "OFFSETLO,This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command."
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bitfld.long 0x18 20.--21. "CMDSEL,Command Specific selection information. Not used in Master I2C. Used as CEn select for Master SPI transactions" "0,1,2,3"
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hexmask.long.word 0x18 8.--19. 1. "TSIZE,Defines the transaction size in bytes. The offset transfer is not included in this size."
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bitfld.long 0x18 7. "CONT,Continue to hold the bus after the current transaction if set to a 1 with a new command issued." "0,1"
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newline
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bitfld.long 0x18 5.--6. "OFFSETCNT,Number of offset bytes to use for the command - 0 1 2 3 are valid selections. The second (byte 1) and third byte (byte 2) are read from the OFFSETHI register and the low order byte is pulled from this register in the OFFSETLO field." "0,1,2,3"
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hexmask.long.byte 0x18 0.--4. 1. "CMD,Command for submodule."
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line.long 0x1C "DCX,Enables use of CE signals to transmit DCX level for SPI transactions. Only used in Apollo3 Revision B. For Revision A. this register MUST NOT be programmed!"
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bitfld.long 0x1C 4. "DCXEN,Revision A: MUST NOT be programmed! Revision B: Bit 4: DCX Signaling Enable via other CE signals. The selected DCX signal (unused CE pin) will be driven low during write of offset byte and high during transmission of data bytes." "0: Disable DCX.,1: Enable DCX."
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bitfld.long 0x1C 3. "CE3OUT,Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE3 output." "0,1"
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newline
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bitfld.long 0x1C 2. "CE2OUT,Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE2 output." "0,1"
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bitfld.long 0x1C 1. "CE1OUT,Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE1 output." "0,1"
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newline
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bitfld.long 0x1C 0. "CE0OUT,Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE0 output." "0,1"
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line.long 0x20 "OFFSETHI,High order 2 bytes of 3 byte offset for IO transaction"
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hexmask.long.word 0x20 0.--15. 1. "OFFSETHI,Holds the high order 2 bytes of the 3 byte addressing/offset field to use with IO commands. The number of offset bytes to use is specified in the command register"
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line.long 0x24 "CMDSTAT,Provides status on the execution of the command currently in progress. The fields in this register will reflect the real time status of the internal state machines and data transfers within the IOM."
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hexmask.long.word 0x24 8.--19. 1. "CTSIZE,The current number of bytes still to be transferred with this command. This field will count down to zero."
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bitfld.long 0x24 5.--7. "CMDSTAT,The current status of the command execution." "?,1: Error encountered with command,2: Actively processing command,?,4: Idle state no active command no error,?,6: Command in progress but waiting on data from host,?"
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newline
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hexmask.long.byte 0x24 0.--4. 1. "CCMD,current command that is being executed"
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group.long 0x240++0x7
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line.long 0x0 "DMATRIGEN,Provides control on which event will trigger the DMA transfer after the DMA operation is setup and enabled. The trigger event will cause a number of bytes (depending on trigger event) to be"
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bitfld.long 0x0 1. "DTHREN,Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes) the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO and will transfer (WTHR/4) number of words" "0,1"
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bitfld.long 0x0 0. "DCMDCMPEN,Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered the number of words transferred will be the lesser of the remaining TOTCOUNT bytes or" "0,1"
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line.long 0x4 "DMATRIGSTAT,Provides the status of trigger events that have occurred for the transaction. Some of the bits are read only and some can be reset via a write of 0."
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bitfld.long 0x4 2. "DTOTCMP,DMA triggered when DCMDCMP = 0 and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is" "0,1"
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bitfld.long 0x4 1. "DTHR,Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA." "0,1"
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newline
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bitfld.long 0x4 0. "DCMDCMP,Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA." "0,1"
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group.long 0x280++0x3
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line.long 0x0 "DMACFG,Configuration control of the DMA process. including the direction of DMA. and enablement of DMA"
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bitfld.long 0x0 9. "DPWROFF,Power off module after DMA is complete. If this bit is active the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain power down will not be performed." "0: Power off disabled,1: Power off enabled"
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bitfld.long 0x0 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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newline
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bitfld.long 0x0 1. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction. To be..,1: Memory to Peripheral transaction. To be set when.."
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bitfld.long 0x0 0. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable DMA Function,1: Enable DMA Function"
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group.long 0x288++0x2F
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line.long 0x0 "DMATOTCOUNT,Contains the number of bytes to be transferred for this DMA transaction. This register is decremented as the data is transferred. and will be 0 at the completion of the DMA operation."
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hexmask.long.word 0x0 0.--11. 1. "TOTCOUNT,Triggered DMA from Command complete event occurred. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."
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line.long 0x4 "DMATARGADDR,The source or destination address internal the SRAM for the DMA data. For write operations. this can only be SRAM data (ADDR bit 28 = 1); For read operations. this can be either SRAM or FLASH (ADDR bit 28 = 0)"
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bitfld.long 0x4 28. "TARGADDR28,Bit 28 of the target byte address for source of DMA (either read or write). In cases of non-word aligned addresses the DMA logic will take care for ensuring only the target bytes are read/written." "0,1"
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hexmask.long.tbyte 0x4 0.--19. 1. "TARGADDR,Bits [19:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment and does not have to be word aligned. In cases of non-word aligned addresses the DMA logic will take care for ensuring only.."
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line.long 0x8 "DMASTAT,Status of the DMA operation currently in progress."
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bitfld.long 0x8 2. "DMAERR,DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set this bit will remain set until cleared by software." "0,1"
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bitfld.long 0x8 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0 and will also be cleared when a new DMA is started." "0,1"
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newline
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bitfld.long 0x8 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
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line.long 0xC "CQCFG,Controls parameters and options for execution of the command queue operation. To enable command queue. create this in memory. set the address. and enable it with a write to CQEN"
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bitfld.long 0xC 1. "CQPRI,Sets the Priority of the command queue DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0xC 0. "CQEN,Command queue enable. When set will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled using a CQ executed write to this bit as well." "0: Disable CQ Function,1: Enable CQ Function"
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line.long 0x10 "CQADDR,The SRAM address which will be fetched next execution of the CQ operation. This register is updated as the CQ operation progresses. and is the live version of the register. The register can also be written by the Command Queue operation itself..."
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bitfld.long 0x10 28. "CQADDR28,Bit 28 of target byte address for source of CQ. Used to denote Flash (0) or SRAM (1) access" "0,1"
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hexmask.long.tbyte 0x10 2.--19. 1. "CQADDR,Bits 19:2 of target byte address for source of CQ. The buffer must be aligned on a word boundary"
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line.long 0x14 "CQSTAT,Provides the status of the command queue operation. If the command queue is disabled. these bits will be cleared. The bits are read only"
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bitfld.long 0x14 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
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bitfld.long 0x14 1. "CQPAUSED,Command queue operation is currently paused." "0,1"
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bitfld.long 0x14 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
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line.long 0x18 "CQFLAGS,Command Queue Flag"
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hexmask.long.word 0x18 16.--31. 1. "CQIRQMASK,Mask the bits used to generate the command queue interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE"
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hexmask.long.word 0x18 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
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line.long 0x1C "CQSETCLEAR,Set/Clear the command queue software pause flags on a per-bit basis. Contains 3 fields. allowing for setting. clearing or toggling the value in the software flags. Priority when the same bit"
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hexmask.long.byte 0x1C 16.--23. 1. "CQFCLR,Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x1C 8.--15. 1. "CQFTGL,Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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newline
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hexmask.long.byte 0x1C 0.--7. 1. "CQFSET,Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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line.long 0x20 "CQPAUSEEN,Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the CQFLAG register is '1'. CQ processing will halt until either value is changed to '0'."
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hexmask.long.word 0x20 0.--15. 1. "CQPEN,Enables the specified event to pause command processing when active"
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line.long 0x24 "CQCURIDX,Current index value. targeted to be written by register write operations within the command queue. This is compared to the CQENDIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and"
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hexmask.long.byte 0x24 0.--7. 1. "CQCURIDX,Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x28 "CQENDIDX,End index value. targeted to be written by software to indicate the last valid register pair contained within the command queue for a register write operations within the command queue."
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|
hexmask.long.byte 0x28 0.--7. 1. "CQENDIDX,Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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|
line.long 0x2C "STATUS,IOM Module Status"
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|
bitfld.long 0x2C 2. "IDLEST,indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to hold-offs from data availability or as the command gets propagated into the logic from the registers." "?,1: The I/O state machine is in the idle state."
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bitfld.long 0x2C 1. "CMDACT,Indicates if the active I/O Command is currently processing a transaction or command is complete but the FIFO pointers are still synchronizing internally. This bit will go high at" "?,1: An I/O command is active. Indicates the active.."
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|
newline
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bitfld.long 0x2C 0. "ERR,Bit has been deprecated. Please refer to the other error indicators. This will always return 0." "?,1: Bit has been deprecated and will always return 0."
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|
group.long 0x300++0x3
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|
line.long 0x0 "MSPICFG,Controls the configuration of the SPI master module. including POL/PHA. LSB. flow control. and delays for MISO and MOSI"
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|
bitfld.long 0x0 30. "MSPIRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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|
bitfld.long 0x0 27.--29. "DOUTDLY,Delay tap to use for the output signal (MOSI). This give more hold time on the output data" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x0 24.--26. "DINDLY,Delay tap to use for the input signal (MISO). This gives more hold time on the input data." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "SPILSB,Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first." "0: Send and receive MSB bit first,1: Send and receive LSB bit first"
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newline
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bitfld.long 0x0 22. "RDFCPOL,selects the read flow control signal polarity." "0: Flow control signal high creates flow control.,1: Flow control signal low creates flow control."
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bitfld.long 0x0 21. "WTFCPOL,selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 will allow a IRQ=1 to pause transfers)." "0: Flow control signal high(1) creates flow control..,1: Flow control signal low(0) creates flow control.."
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newline
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bitfld.long 0x0 20. "WTFCIRQ,selects the write mode flow control signal." "0: MISO is used as the write mode flow control..,1: IRQ is used as the write mode flow control signal."
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bitfld.long 0x0 18. "MOSIINV,inverts MOSI when flow control is enabled." "0: MOSI is set to 0 in read mode and 1 in write mode.,1: MOSI is set to 1 in read mode and 0 in write mode."
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newline
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bitfld.long 0x0 17. "RDFC,enables read mode flow control." "0: Read mode flow control disabled.,1: Read mode flow control enabled."
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bitfld.long 0x0 16. "WTFC,enables write mode flow control." "0: Write mode flow control disabled.,1: Write mode flow control enabled."
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newline
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bitfld.long 0x0 2. "FULLDUP,Enables full duplex mode for Master SPI write operations. Data will be captured simultaneously into the read FIFO" "0,1"
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bitfld.long 0x0 1. "SPHA,selects SPI phase." "0: Sample on the leading (first) clock edge.,1: Sample on the trailing (second) clock edge."
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newline
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bitfld.long 0x0 0. "SPOL,selects SPI polarity." "0: The base value of the clock is 0.,1: The base value of the clock is 1."
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group.long 0x400++0x7
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line.long 0x0 "MI2CCFG,Controls the configuration of the I2C bus master."
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bitfld.long 0x0 24. "STRDIS,Disable detection of clock stretch events smaller than 1 cycle" "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "SMPCNT,Number of Base clock cycles to wait before sampling the SCL clock to determine if a clock stretch event has occurred"
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|
newline
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hexmask.long.byte 0x0 12.--15. 1. "SDAENDLY,Number of IOCLK cycles to delay the SDA output en (all transitions affected). Used to delay data relative to clock"
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|
hexmask.long.byte 0x0 8.--11. 1. "SCLENDLY,Number of IOCLK cycles to delay the rising edge of the SCL output en (clock will go low on this edge). Used to allow clock shaping."
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newline
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bitfld.long 0x0 6. "MI2CRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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|
bitfld.long 0x0 4.--5. "SDADLY,Delay to enable on the SDA output. Values are 0x0-0x3." "0,1,2,3"
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newline
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bitfld.long 0x0 2. "ARBEN,Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master this function can be disabled to save clock cycles on I2C transactions" "0: Disable multi-master bus arbitration support for..,1: Enable multi-master bus arbitration support for.."
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|
bitfld.long 0x0 1. "I2CLSB,Direction of data transmit and receive MSB(0) or LSB(1) first. Default per I2C specification is MSB first. This applies to both read and write data and read data will be bit" "0: Byte data is transmitted MSB first onto the..,1: Byte data is transmitted LSB first onto the.."
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newline
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bitfld.long 0x0 0. "ADDRSZ,Sets the I2C master device address size to either 7 bits (0) or 10 bits (1)." "0: Use 7-bit addressing for I2C master transactions,1: Use 10-bit addressing for I2C master transactions"
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|
line.long 0x4 "DEVCFG,Contains the I2C device address."
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hexmask.long.word 0x4 0.--9. 1. "DEVADDR,I2C address of the device that the Master will use to target for read/write operations. This can be either a 7-bit or 10-bit address."
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group.long 0x410++0x3
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line.long 0x0 "IOMDBG,Debug control"
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hexmask.long 0x0 3.--31. 1. "DBGDATA,Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers."
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bitfld.long 0x0 2. "APBCLKON,APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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|
newline
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bitfld.long 0x0 1. "IOCLKON,IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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bitfld.long 0x0 0. "DBGEN,Debug Enable. Setting bit will enable the update of data within this register otherwise it is clock gated for power savings" "0,1"
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|
tree.end
|
|
endif
|
|
sif (cpuis("AMA3B1KK")||cpuis("AMAP31KK"))
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tree "IOM2"
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base ad:0x50006000
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group.long 0x0++0x3
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line.long 0x0 "FIFO,Provides direct random access to both output and input FIFOs. The state of the FIFO is not disturbed by reading these locations (i.e.. no POP will be done). FIFO0 is accessible from addresses 0x0 - 0x1C. and is used for data output from the IOM to.."
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|
hexmask.long 0x0 0.--31. 1. "FIFO,FIFO direct access. Only locations 0 - 3F will return valid information."
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group.long 0x100++0x17
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line.long 0x0 "FIFOPTR,Provides the current valid byte count of data within the FIFO as seen from the internal state machines. FIFO0 is dedicated to outgoing transactions and FIFO1 is dedicated to incoming transactions. All counts are specified in units of bytes."
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hexmask.long.byte 0x0 24.--31. 1. "FIFO1REM,The number of remaining data bytes slots currently in FIFO 1 (written by interface read by MCU)"
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hexmask.long.byte 0x0 16.--23. 1. "FIFO1SIZ,The number of valid data bytes currently in FIFO 1 (written by interface read by MCU)"
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|
newline
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hexmask.long.byte 0x0 8.--15. 1. "FIFO0REM,The number of remaining data bytes slots currently in FIFO 0 (written by MCU read by interface)"
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hexmask.long.byte 0x0 0.--7. 1. "FIFO0SIZ,The number of valid data bytes currently in the FIFO 0 (written by MCU read by interface)"
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line.long 0x4 "FIFOTHR,Sets the threshold values for incoming and outgoing transactions. The threshold values are used to assert the interrupt if enabled. and also used during DMA to set the transfer size as a result of DMATHR trigger."
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hexmask.long.byte 0x4 8.--13. 1. "FIFOWTHR,FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the write FIFO contains FIFOWTHR free bytes as.."
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|
hexmask.long.byte 0x4 0.--5. 1. "FIFORTHR,FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the read FIFO contains FIFORTHR valid bytes of data as.."
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|
line.long 0x8 "FIFOPOP,Will advance the internal read pointer of the incoming FIFO (FIFO1) when read. if POPWR is not active. If POPWR is active. a write to this register is needed to advance the internal FIFO pointer."
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hexmask.long 0x8 0.--31. 1. "FIFODOUT,This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0) the FIFO read pointer will be advanced by one word as a result of the read."
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line.long 0xC "FIFOPUSH,Will write new data into the outgoing FIFO and advance the internal write pointer."
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|
hexmask.long 0xC 0.--31. 1. "FIFODIN,This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes)."
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line.long 0x10 "FIFOCTRL,Provides controls for the operation of the internal FIFOs. Contains fields used to control the operation of the POP register. and also controls to reset the internal pointers of the FIFOs."
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bitfld.long 0x10 1. "FIFORSTN,Active low manual reset of the FIFO. Write to 0 to reset FIFO and then write to 1 to remove the reset." "0,1"
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|
bitfld.long 0x10 0. "POPWR,Selects the mode in which 'pop' events are done for the FIFO read operations. A value of '1' will prevent a pop event on a read operation and will require a write to the FIFOPOP register to create a pop event." "0,1"
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line.long 0x14 "FIFOLOC,Provides a read only value of the current read and write pointers. This register is read only and can be used along with the FIFO direct access method to determine the next data to be used for input and output functions."
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hexmask.long.byte 0x14 8.--11. 1. "FIFORPTR,Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1) which is used to store read data returned from external devices during a read operation."
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hexmask.long.byte 0x14 0.--3. 1. "FIFOWPTR,Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0) which is used during write operations to external devices."
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group.long 0x200++0x27
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line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
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bitfld.long 0x0 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x0 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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newline
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bitfld.long 0x0 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x0 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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newline
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bitfld.long 0x0 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x0 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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newline
|
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bitfld.long 0x0 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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|
bitfld.long 0x0 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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newline
|
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bitfld.long 0x0 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x0 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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|
newline
|
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bitfld.long 0x0 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x0 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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newline
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bitfld.long 0x0 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
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bitfld.long 0x0 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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|
newline
|
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bitfld.long 0x0 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
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bitfld.long 0x4 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x4 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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newline
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bitfld.long 0x4 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x4 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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|
newline
|
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bitfld.long 0x4 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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|
bitfld.long 0x4 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x4 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x4 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0x4 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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|
newline
|
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bitfld.long 0x4 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
|
|
bitfld.long 0x4 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 14. "CQERR,Error during command queue operations" "0,1"
|
|
bitfld.long 0x8 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
|
|
newline
|
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bitfld.long 0x8 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
|
|
bitfld.long 0x8 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
newline
|
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bitfld.long 0x8 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0x8 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x8 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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|
newline
|
|
bitfld.long 0x8 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
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bitfld.long 0x8 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
|
|
newline
|
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bitfld.long 0x8 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0x8 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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newline
|
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bitfld.long 0x8 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
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|
bitfld.long 0x8 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
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bitfld.long 0x8 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 14. "CQERR,Error during command queue operations" "0,1"
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|
bitfld.long 0xC 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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newline
|
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bitfld.long 0xC 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
|
|
bitfld.long 0xC 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
newline
|
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bitfld.long 0xC 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0xC 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0xC 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0xC 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0xC 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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|
newline
|
|
bitfld.long 0xC 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
|
|
bitfld.long 0xC 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
|
|
line.long 0x10 "CLKCFG,Provides clock related controls used internal to the BLEIF module. and enablement of 32KHz clock to the BLE Core module. The internal clock sourced is selected via the FSEL and can be further divided by 3 using the DIV3 control."
|
|
hexmask.long.byte 0x10 24.--31. 1. "TOTPER,Clock total clock count minus 1. This provides the total period of the divided clock -1 when the DIVEN is active. The"
|
|
hexmask.long.byte 0x10 16.--23. 1. "LOWPER,Clock low clock count minus 1. This provides the number of clocks the divided clock will be low when the DIVEN = 1."
|
|
newline
|
|
bitfld.long 0x10 12. "DIVEN,Enable clock division by TOTPER and LOWPER" "0: Disable TOTPER division.,1: Enable TOTPER division."
|
|
bitfld.long 0x10 11. "DIV3,Enable divide by 3 of the source IOCLK. Division by 3 is done before the DIVEN programmable divider and if enabled" "0: Select divide by 1.,1: Select divide by 3."
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|
newline
|
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bitfld.long 0x10 8.--10. "FSEL,Select the input clock frequency." "0: Selects the minimum power clock. This setting..,1: Selects the HFRC as the input clock.,2: Selects the HFRC / 2 as the input clock.,3: Selects the HFRC / 4 as the input clock.,4: Selects the HFRC / 8 as the input clock.,5: Selects the HFRC / 16 as the input clock.,6: Selects the HFRC / 32 as the input clock.,7: Selects the HFRC / 64 as the input clock."
|
|
bitfld.long 0x10 0. "IOCLKEN,Enable for the interface clock. Must be enabled prior to executing any IO operations." "0,1"
|
|
line.long 0x14 "SUBMODCTRL,Provides enable for each submodule. Only a single submodule can be enabled at one time."
|
|
bitfld.long 0x14 5.--7. "SMOD1TYPE,Submodule 0 module type. This is the I2C Master interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,?,?,?,7: NOT INSTALLED"
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|
bitfld.long 0x14 4. "SMOD1EN,Submodule 1 enable (1) or disable (0)" "0,1"
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|
newline
|
|
bitfld.long 0x14 1.--3. "SMOD0TYPE,Submodule 0 module type. This is the SPI Master interface." "0: MSPI submodule,1: I2C Master submodule,2: SPI Slave submodule,3: I2C Slave submodule,?,?,?,7: NOT INSTALLED"
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|
bitfld.long 0x14 0. "SMOD0EN,Submodule 0 enable (1) or disable (0)" "0,1"
|
|
line.long 0x18 "CMD,Writes to this register will start an IO transaction. as well as set various parameters for the command itself. Reads will return the command value written to the CMD register."
|
|
hexmask.long.byte 0x18 24.--31. 1. "OFFSETLO,This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command."
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|
bitfld.long 0x18 20.--21. "CMDSEL,Command Specific selection information. Not used in Master I2C. Used as CEn select for Master SPI transactions" "0,1,2,3"
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|
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hexmask.long.word 0x18 8.--19. 1. "TSIZE,Defines the transaction size in bytes. The offset transfer is not included in this size."
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|
bitfld.long 0x18 7. "CONT,Continue to hold the bus after the current transaction if set to a 1 with a new command issued." "0,1"
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|
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bitfld.long 0x18 5.--6. "OFFSETCNT,Number of offset bytes to use for the command - 0 1 2 3 are valid selections. The second (byte 1) and third byte (byte 2) are read from the OFFSETHI register and the low order byte is pulled from this register in the OFFSETLO field." "0,1,2,3"
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|
hexmask.long.byte 0x18 0.--4. 1. "CMD,Command for submodule."
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|
line.long 0x1C "DCX,Enables use of CE signals to transmit DCX level for SPI transactions. Only used in Apollo3 Revision B. For Revision A. this register MUST NOT be programmed!"
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|
bitfld.long 0x1C 4. "DCXEN,Revision A: MUST NOT be programmed! Revision B: Bit 4: DCX Signaling Enable via other CE signals. The selected DCX signal (unused CE pin) will be driven low during write of offset byte and high during transmission of data bytes." "0: Disable DCX.,1: Enable DCX."
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|
bitfld.long 0x1C 3. "CE3OUT,Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE3 output." "0,1"
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|
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bitfld.long 0x1C 2. "CE2OUT,Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE2 output." "0,1"
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|
bitfld.long 0x1C 1. "CE1OUT,Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE1 output." "0,1"
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|
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bitfld.long 0x1C 0. "CE0OUT,Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE0 output." "0,1"
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|
line.long 0x20 "OFFSETHI,High order 2 bytes of 3 byte offset for IO transaction"
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|
hexmask.long.word 0x20 0.--15. 1. "OFFSETHI,Holds the high order 2 bytes of the 3 byte addressing/offset field to use with IO commands. The number of offset bytes to use is specified in the command register"
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|
line.long 0x24 "CMDSTAT,Provides status on the execution of the command currently in progress. The fields in this register will reflect the real time status of the internal state machines and data transfers within the IOM."
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|
hexmask.long.word 0x24 8.--19. 1. "CTSIZE,The current number of bytes still to be transferred with this command. This field will count down to zero."
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|
bitfld.long 0x24 5.--7. "CMDSTAT,The current status of the command execution." "?,1: Error encountered with command,2: Actively processing command,?,4: Idle state no active command no error,?,6: Command in progress but waiting on data from host,?"
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newline
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hexmask.long.byte 0x24 0.--4. 1. "CCMD,current command that is being executed"
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|
group.long 0x240++0x7
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|
line.long 0x0 "DMATRIGEN,Provides control on which event will trigger the DMA transfer after the DMA operation is setup and enabled. The trigger event will cause a number of bytes (depending on trigger event) to be"
|
|
bitfld.long 0x0 1. "DTHREN,Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes) the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO and will transfer (WTHR/4) number of words" "0,1"
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bitfld.long 0x0 0. "DCMDCMPEN,Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered the number of words transferred will be the lesser of the remaining TOTCOUNT bytes or" "0,1"
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line.long 0x4 "DMATRIGSTAT,Provides the status of trigger events that have occurred for the transaction. Some of the bits are read only and some can be reset via a write of 0."
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bitfld.long 0x4 2. "DTOTCMP,DMA triggered when DCMDCMP = 0 and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is" "0,1"
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bitfld.long 0x4 1. "DTHR,Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA." "0,1"
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newline
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bitfld.long 0x4 0. "DCMDCMP,Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA." "0,1"
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|
group.long 0x280++0x3
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|
line.long 0x0 "DMACFG,Configuration control of the DMA process. including the direction of DMA. and enablement of DMA"
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|
bitfld.long 0x0 9. "DPWROFF,Power off module after DMA is complete. If this bit is active the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain power down will not be performed." "0: Power off disabled,1: Power off enabled"
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bitfld.long 0x0 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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newline
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bitfld.long 0x0 1. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction. To be..,1: Memory to Peripheral transaction. To be set when.."
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|
bitfld.long 0x0 0. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable DMA Function,1: Enable DMA Function"
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|
group.long 0x288++0x2F
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|
line.long 0x0 "DMATOTCOUNT,Contains the number of bytes to be transferred for this DMA transaction. This register is decremented as the data is transferred. and will be 0 at the completion of the DMA operation."
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hexmask.long.word 0x0 0.--11. 1. "TOTCOUNT,Triggered DMA from Command complete event occurred. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."
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line.long 0x4 "DMATARGADDR,The source or destination address internal the SRAM for the DMA data. For write operations. this can only be SRAM data (ADDR bit 28 = 1); For read operations. this can be either SRAM or FLASH (ADDR bit 28 = 0)"
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bitfld.long 0x4 28. "TARGADDR28,Bit 28 of the target byte address for source of DMA (either read or write). In cases of non-word aligned addresses the DMA logic will take care for ensuring only the target bytes are read/written." "0,1"
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hexmask.long.tbyte 0x4 0.--19. 1. "TARGADDR,Bits [19:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment and does not have to be word aligned. In cases of non-word aligned addresses the DMA logic will take care for ensuring only.."
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|
line.long 0x8 "DMASTAT,Status of the DMA operation currently in progress."
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bitfld.long 0x8 2. "DMAERR,DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set this bit will remain set until cleared by software." "0,1"
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bitfld.long 0x8 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0 and will also be cleared when a new DMA is started." "0,1"
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bitfld.long 0x8 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
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line.long 0xC "CQCFG,Controls parameters and options for execution of the command queue operation. To enable command queue. create this in memory. set the address. and enable it with a write to CQEN"
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bitfld.long 0xC 1. "CQPRI,Sets the Priority of the command queue DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0xC 0. "CQEN,Command queue enable. When set will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled using a CQ executed write to this bit as well." "0: Disable CQ Function,1: Enable CQ Function"
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line.long 0x10 "CQADDR,The SRAM address which will be fetched next execution of the CQ operation. This register is updated as the CQ operation progresses. and is the live version of the register. The register can also be written by the Command Queue operation itself..."
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bitfld.long 0x10 28. "CQADDR28,Bit 28 of target byte address for source of CQ. Used to denote Flash (0) or SRAM (1) access" "0,1"
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hexmask.long.tbyte 0x10 2.--19. 1. "CQADDR,Bits 19:2 of target byte address for source of CQ. The buffer must be aligned on a word boundary"
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line.long 0x14 "CQSTAT,Provides the status of the command queue operation. If the command queue is disabled. these bits will be cleared. The bits are read only"
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|
bitfld.long 0x14 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
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|
bitfld.long 0x14 1. "CQPAUSED,Command queue operation is currently paused." "0,1"
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bitfld.long 0x14 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
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line.long 0x18 "CQFLAGS,Command Queue Flag"
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hexmask.long.word 0x18 16.--31. 1. "CQIRQMASK,Mask the bits used to generate the command queue interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE"
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hexmask.long.word 0x18 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
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line.long 0x1C "CQSETCLEAR,Set/Clear the command queue software pause flags on a per-bit basis. Contains 3 fields. allowing for setting. clearing or toggling the value in the software flags. Priority when the same bit"
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hexmask.long.byte 0x1C 16.--23. 1. "CQFCLR,Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field"
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|
hexmask.long.byte 0x1C 8.--15. 1. "CQFTGL,Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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newline
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hexmask.long.byte 0x1C 0.--7. 1. "CQFSET,Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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line.long 0x20 "CQPAUSEEN,Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the CQFLAG register is '1'. CQ processing will halt until either value is changed to '0'."
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hexmask.long.word 0x20 0.--15. 1. "CQPEN,Enables the specified event to pause command processing when active"
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line.long 0x24 "CQCURIDX,Current index value. targeted to be written by register write operations within the command queue. This is compared to the CQENDIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and"
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hexmask.long.byte 0x24 0.--7. 1. "CQCURIDX,Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x28 "CQENDIDX,End index value. targeted to be written by software to indicate the last valid register pair contained within the command queue for a register write operations within the command queue."
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hexmask.long.byte 0x28 0.--7. 1. "CQENDIDX,Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x2C "STATUS,IOM Module Status"
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bitfld.long 0x2C 2. "IDLEST,indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to hold-offs from data availability or as the command gets propagated into the logic from the registers." "?,1: The I/O state machine is in the idle state."
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bitfld.long 0x2C 1. "CMDACT,Indicates if the active I/O Command is currently processing a transaction or command is complete but the FIFO pointers are still synchronizing internally. This bit will go high at" "?,1: An I/O command is active. Indicates the active.."
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newline
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bitfld.long 0x2C 0. "ERR,Bit has been deprecated. Please refer to the other error indicators. This will always return 0." "?,1: Bit has been deprecated and will always return 0."
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group.long 0x300++0x3
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line.long 0x0 "MSPICFG,Controls the configuration of the SPI master module. including POL/PHA. LSB. flow control. and delays for MISO and MOSI"
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bitfld.long 0x0 30. "MSPIRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 27.--29. "DOUTDLY,Delay tap to use for the output signal (MOSI). This give more hold time on the output data" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 24.--26. "DINDLY,Delay tap to use for the input signal (MISO). This gives more hold time on the input data." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "SPILSB,Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first." "0: Send and receive MSB bit first,1: Send and receive LSB bit first"
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bitfld.long 0x0 22. "RDFCPOL,selects the read flow control signal polarity." "0: Flow control signal high creates flow control.,1: Flow control signal low creates flow control."
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bitfld.long 0x0 21. "WTFCPOL,selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 will allow a IRQ=1 to pause transfers)." "0: Flow control signal high(1) creates flow control..,1: Flow control signal low(0) creates flow control.."
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newline
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bitfld.long 0x0 20. "WTFCIRQ,selects the write mode flow control signal." "0: MISO is used as the write mode flow control..,1: IRQ is used as the write mode flow control signal."
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bitfld.long 0x0 18. "MOSIINV,inverts MOSI when flow control is enabled." "0: MOSI is set to 0 in read mode and 1 in write mode.,1: MOSI is set to 1 in read mode and 0 in write mode."
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newline
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bitfld.long 0x0 17. "RDFC,enables read mode flow control." "0: Read mode flow control disabled.,1: Read mode flow control enabled."
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bitfld.long 0x0 16. "WTFC,enables write mode flow control." "0: Write mode flow control disabled.,1: Write mode flow control enabled."
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newline
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bitfld.long 0x0 2. "FULLDUP,Enables full duplex mode for Master SPI write operations. Data will be captured simultaneously into the read FIFO" "0,1"
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bitfld.long 0x0 1. "SPHA,selects SPI phase." "0: Sample on the leading (first) clock edge.,1: Sample on the trailing (second) clock edge."
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newline
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bitfld.long 0x0 0. "SPOL,selects SPI polarity." "0: The base value of the clock is 0.,1: The base value of the clock is 1."
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group.long 0x400++0x7
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line.long 0x0 "MI2CCFG,Controls the configuration of the I2C bus master."
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bitfld.long 0x0 24. "STRDIS,Disable detection of clock stretch events smaller than 1 cycle" "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "SMPCNT,Number of Base clock cycles to wait before sampling the SCL clock to determine if a clock stretch event has occurred"
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|
newline
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hexmask.long.byte 0x0 12.--15. 1. "SDAENDLY,Number of IOCLK cycles to delay the SDA output en (all transitions affected). Used to delay data relative to clock"
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hexmask.long.byte 0x0 8.--11. 1. "SCLENDLY,Number of IOCLK cycles to delay the rising edge of the SCL output en (clock will go low on this edge). Used to allow clock shaping."
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newline
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bitfld.long 0x0 6. "MI2CRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
|
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bitfld.long 0x0 4.--5. "SDADLY,Delay to enable on the SDA output. Values are 0x0-0x3." "0,1,2,3"
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newline
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bitfld.long 0x0 2. "ARBEN,Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master this function can be disabled to save clock cycles on I2C transactions" "0: Disable multi-master bus arbitration support for..,1: Enable multi-master bus arbitration support for.."
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bitfld.long 0x0 1. "I2CLSB,Direction of data transmit and receive MSB(0) or LSB(1) first. Default per I2C specification is MSB first. This applies to both read and write data and read data will be bit" "0: Byte data is transmitted MSB first onto the..,1: Byte data is transmitted LSB first onto the.."
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newline
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bitfld.long 0x0 0. "ADDRSZ,Sets the I2C master device address size to either 7 bits (0) or 10 bits (1)." "0: Use 7-bit addressing for I2C master transactions,1: Use 10-bit addressing for I2C master transactions"
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line.long 0x4 "DEVCFG,Contains the I2C device address."
|
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hexmask.long.word 0x4 0.--9. 1. "DEVADDR,I2C address of the device that the Master will use to target for read/write operations. This can be either a 7-bit or 10-bit address."
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group.long 0x410++0x3
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line.long 0x0 "IOMDBG,Debug control"
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hexmask.long 0x0 3.--31. 1. "DBGDATA,Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers."
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bitfld.long 0x0 2. "APBCLKON,APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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newline
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bitfld.long 0x0 1. "IOCLKON,IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
|
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bitfld.long 0x0 0. "DBGEN,Debug Enable. Setting bit will enable the update of data within this register otherwise it is clock gated for power savings" "0,1"
|
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tree.end
|
|
endif
|
|
sif (cpuis("AMA3B1KK")||cpuis("AMAP31KK"))
|
|
tree "IOM3"
|
|
base ad:0x50007000
|
|
group.long 0x0++0x3
|
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line.long 0x0 "FIFO,Provides direct random access to both output and input FIFOs. The state of the FIFO is not disturbed by reading these locations (i.e.. no POP will be done). FIFO0 is accessible from addresses 0x0 - 0x1C. and is used for data output from the IOM to.."
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hexmask.long 0x0 0.--31. 1. "FIFO,FIFO direct access. Only locations 0 - 3F will return valid information."
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group.long 0x100++0x17
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line.long 0x0 "FIFOPTR,Provides the current valid byte count of data within the FIFO as seen from the internal state machines. FIFO0 is dedicated to outgoing transactions and FIFO1 is dedicated to incoming transactions. All counts are specified in units of bytes."
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hexmask.long.byte 0x0 24.--31. 1. "FIFO1REM,The number of remaining data bytes slots currently in FIFO 1 (written by interface read by MCU)"
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hexmask.long.byte 0x0 16.--23. 1. "FIFO1SIZ,The number of valid data bytes currently in FIFO 1 (written by interface read by MCU)"
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "FIFO0REM,The number of remaining data bytes slots currently in FIFO 0 (written by MCU read by interface)"
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hexmask.long.byte 0x0 0.--7. 1. "FIFO0SIZ,The number of valid data bytes currently in the FIFO 0 (written by MCU read by interface)"
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line.long 0x4 "FIFOTHR,Sets the threshold values for incoming and outgoing transactions. The threshold values are used to assert the interrupt if enabled. and also used during DMA to set the transfer size as a result of DMATHR trigger."
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hexmask.long.byte 0x4 8.--13. 1. "FIFOWTHR,FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the write FIFO contains FIFOWTHR free bytes as.."
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hexmask.long.byte 0x4 0.--5. 1. "FIFORTHR,FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the read FIFO contains FIFORTHR valid bytes of data as.."
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line.long 0x8 "FIFOPOP,Will advance the internal read pointer of the incoming FIFO (FIFO1) when read. if POPWR is not active. If POPWR is active. a write to this register is needed to advance the internal FIFO pointer."
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hexmask.long 0x8 0.--31. 1. "FIFODOUT,This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0) the FIFO read pointer will be advanced by one word as a result of the read."
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line.long 0xC "FIFOPUSH,Will write new data into the outgoing FIFO and advance the internal write pointer."
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hexmask.long 0xC 0.--31. 1. "FIFODIN,This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes)."
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line.long 0x10 "FIFOCTRL,Provides controls for the operation of the internal FIFOs. Contains fields used to control the operation of the POP register. and also controls to reset the internal pointers of the FIFOs."
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bitfld.long 0x10 1. "FIFORSTN,Active low manual reset of the FIFO. Write to 0 to reset FIFO and then write to 1 to remove the reset." "0,1"
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bitfld.long 0x10 0. "POPWR,Selects the mode in which 'pop' events are done for the FIFO read operations. A value of '1' will prevent a pop event on a read operation and will require a write to the FIFOPOP register to create a pop event." "0,1"
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line.long 0x14 "FIFOLOC,Provides a read only value of the current read and write pointers. This register is read only and can be used along with the FIFO direct access method to determine the next data to be used for input and output functions."
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hexmask.long.byte 0x14 8.--11. 1. "FIFORPTR,Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1) which is used to store read data returned from external devices during a read operation."
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hexmask.long.byte 0x14 0.--3. 1. "FIFOWPTR,Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0) which is used during write operations to external devices."
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group.long 0x200++0x27
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line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
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bitfld.long 0x0 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x0 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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newline
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bitfld.long 0x0 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x0 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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newline
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bitfld.long 0x0 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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|
bitfld.long 0x0 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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|
newline
|
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bitfld.long 0x0 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x0 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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|
newline
|
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bitfld.long 0x0 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x0 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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|
newline
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bitfld.long 0x0 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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|
bitfld.long 0x0 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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newline
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bitfld.long 0x0 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
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bitfld.long 0x0 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x0 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
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bitfld.long 0x4 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x4 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x4 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x4 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x4 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x4 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0x4 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x4 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x4 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x4 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x4 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x4 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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bitfld.long 0x4 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
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bitfld.long 0x4 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x4 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
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bitfld.long 0x8 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x8 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x8 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x8 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x8 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x8 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0x8 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x8 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x8 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x8 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x8 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x8 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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bitfld.long 0x8 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
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bitfld.long 0x8 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x8 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
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bitfld.long 0xC 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0xC 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0xC 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0xC 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0xC 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0xC 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0xC 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0xC 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0xC 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0xC 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0xC 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0xC 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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bitfld.long 0xC 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
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bitfld.long 0xC 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0xC 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x10 "CLKCFG,Provides clock related controls used internal to the BLEIF module. and enablement of 32KHz clock to the BLE Core module. The internal clock sourced is selected via the FSEL and can be further divided by 3 using the DIV3 control."
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hexmask.long.byte 0x10 24.--31. 1. "TOTPER,Clock total clock count minus 1. This provides the total period of the divided clock -1 when the DIVEN is active. The"
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hexmask.long.byte 0x10 16.--23. 1. "LOWPER,Clock low clock count minus 1. This provides the number of clocks the divided clock will be low when the DIVEN = 1."
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bitfld.long 0x10 12. "DIVEN,Enable clock division by TOTPER and LOWPER" "0: Disable TOTPER division.,1: Enable TOTPER division."
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bitfld.long 0x10 11. "DIV3,Enable divide by 3 of the source IOCLK. Division by 3 is done before the DIVEN programmable divider and if enabled" "0: Select divide by 1.,1: Select divide by 3."
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bitfld.long 0x10 8.--10. "FSEL,Select the input clock frequency." "0: Selects the minimum power clock. This setting..,1: Selects the HFRC as the input clock.,2: Selects the HFRC / 2 as the input clock.,3: Selects the HFRC / 4 as the input clock.,4: Selects the HFRC / 8 as the input clock.,5: Selects the HFRC / 16 as the input clock.,6: Selects the HFRC / 32 as the input clock.,7: Selects the HFRC / 64 as the input clock."
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bitfld.long 0x10 0. "IOCLKEN,Enable for the interface clock. Must be enabled prior to executing any IO operations." "0,1"
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line.long 0x14 "SUBMODCTRL,Provides enable for each submodule. Only a single submodule can be enabled at one time."
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bitfld.long 0x14 5.--7. "SMOD1TYPE,Submodule 0 module type. This is the I2C Master interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,?,?,?,7: NOT INSTALLED"
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bitfld.long 0x14 4. "SMOD1EN,Submodule 1 enable (1) or disable (0)" "0,1"
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bitfld.long 0x14 1.--3. "SMOD0TYPE,Submodule 0 module type. This is the SPI Master interface." "0: MSPI submodule,1: I2C Master submodule,2: SPI Slave submodule,3: I2C Slave submodule,?,?,?,7: NOT INSTALLED"
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bitfld.long 0x14 0. "SMOD0EN,Submodule 0 enable (1) or disable (0)" "0,1"
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line.long 0x18 "CMD,Writes to this register will start an IO transaction. as well as set various parameters for the command itself. Reads will return the command value written to the CMD register."
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hexmask.long.byte 0x18 24.--31. 1. "OFFSETLO,This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command."
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bitfld.long 0x18 20.--21. "CMDSEL,Command Specific selection information. Not used in Master I2C. Used as CEn select for Master SPI transactions" "0,1,2,3"
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hexmask.long.word 0x18 8.--19. 1. "TSIZE,Defines the transaction size in bytes. The offset transfer is not included in this size."
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bitfld.long 0x18 7. "CONT,Continue to hold the bus after the current transaction if set to a 1 with a new command issued." "0,1"
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bitfld.long 0x18 5.--6. "OFFSETCNT,Number of offset bytes to use for the command - 0 1 2 3 are valid selections. The second (byte 1) and third byte (byte 2) are read from the OFFSETHI register and the low order byte is pulled from this register in the OFFSETLO field." "0,1,2,3"
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hexmask.long.byte 0x18 0.--4. 1. "CMD,Command for submodule."
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line.long 0x1C "DCX,Enables use of CE signals to transmit DCX level for SPI transactions. Only used in Apollo3 Revision B. For Revision A. this register MUST NOT be programmed!"
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bitfld.long 0x1C 4. "DCXEN,Revision A: MUST NOT be programmed! Revision B: Bit 4: DCX Signaling Enable via other CE signals. The selected DCX signal (unused CE pin) will be driven low during write of offset byte and high during transmission of data bytes." "0: Disable DCX.,1: Enable DCX."
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bitfld.long 0x1C 3. "CE3OUT,Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE3 output." "0,1"
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bitfld.long 0x1C 2. "CE2OUT,Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE2 output." "0,1"
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bitfld.long 0x1C 1. "CE1OUT,Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE1 output." "0,1"
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bitfld.long 0x1C 0. "CE0OUT,Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE0 output." "0,1"
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line.long 0x20 "OFFSETHI,High order 2 bytes of 3 byte offset for IO transaction"
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hexmask.long.word 0x20 0.--15. 1. "OFFSETHI,Holds the high order 2 bytes of the 3 byte addressing/offset field to use with IO commands. The number of offset bytes to use is specified in the command register"
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line.long 0x24 "CMDSTAT,Provides status on the execution of the command currently in progress. The fields in this register will reflect the real time status of the internal state machines and data transfers within the IOM."
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hexmask.long.word 0x24 8.--19. 1. "CTSIZE,The current number of bytes still to be transferred with this command. This field will count down to zero."
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bitfld.long 0x24 5.--7. "CMDSTAT,The current status of the command execution." "?,1: Error encountered with command,2: Actively processing command,?,4: Idle state no active command no error,?,6: Command in progress but waiting on data from host,?"
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hexmask.long.byte 0x24 0.--4. 1. "CCMD,current command that is being executed"
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group.long 0x240++0x7
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line.long 0x0 "DMATRIGEN,Provides control on which event will trigger the DMA transfer after the DMA operation is setup and enabled. The trigger event will cause a number of bytes (depending on trigger event) to be"
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bitfld.long 0x0 1. "DTHREN,Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes) the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO and will transfer (WTHR/4) number of words" "0,1"
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bitfld.long 0x0 0. "DCMDCMPEN,Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered the number of words transferred will be the lesser of the remaining TOTCOUNT bytes or" "0,1"
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line.long 0x4 "DMATRIGSTAT,Provides the status of trigger events that have occurred for the transaction. Some of the bits are read only and some can be reset via a write of 0."
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bitfld.long 0x4 2. "DTOTCMP,DMA triggered when DCMDCMP = 0 and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is" "0,1"
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bitfld.long 0x4 1. "DTHR,Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA." "0,1"
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bitfld.long 0x4 0. "DCMDCMP,Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA." "0,1"
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group.long 0x280++0x3
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line.long 0x0 "DMACFG,Configuration control of the DMA process. including the direction of DMA. and enablement of DMA"
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bitfld.long 0x0 9. "DPWROFF,Power off module after DMA is complete. If this bit is active the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain power down will not be performed." "0: Power off disabled,1: Power off enabled"
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bitfld.long 0x0 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x0 1. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction. To be..,1: Memory to Peripheral transaction. To be set when.."
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bitfld.long 0x0 0. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable DMA Function,1: Enable DMA Function"
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group.long 0x288++0x2F
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line.long 0x0 "DMATOTCOUNT,Contains the number of bytes to be transferred for this DMA transaction. This register is decremented as the data is transferred. and will be 0 at the completion of the DMA operation."
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hexmask.long.word 0x0 0.--11. 1. "TOTCOUNT,Triggered DMA from Command complete event occurred. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."
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line.long 0x4 "DMATARGADDR,The source or destination address internal the SRAM for the DMA data. For write operations. this can only be SRAM data (ADDR bit 28 = 1); For read operations. this can be either SRAM or FLASH (ADDR bit 28 = 0)"
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bitfld.long 0x4 28. "TARGADDR28,Bit 28 of the target byte address for source of DMA (either read or write). In cases of non-word aligned addresses the DMA logic will take care for ensuring only the target bytes are read/written." "0,1"
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hexmask.long.tbyte 0x4 0.--19. 1. "TARGADDR,Bits [19:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment and does not have to be word aligned. In cases of non-word aligned addresses the DMA logic will take care for ensuring only.."
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line.long 0x8 "DMASTAT,Status of the DMA operation currently in progress."
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bitfld.long 0x8 2. "DMAERR,DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set this bit will remain set until cleared by software." "0,1"
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bitfld.long 0x8 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0 and will also be cleared when a new DMA is started." "0,1"
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bitfld.long 0x8 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
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line.long 0xC "CQCFG,Controls parameters and options for execution of the command queue operation. To enable command queue. create this in memory. set the address. and enable it with a write to CQEN"
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bitfld.long 0xC 1. "CQPRI,Sets the Priority of the command queue DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0xC 0. "CQEN,Command queue enable. When set will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled using a CQ executed write to this bit as well." "0: Disable CQ Function,1: Enable CQ Function"
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line.long 0x10 "CQADDR,The SRAM address which will be fetched next execution of the CQ operation. This register is updated as the CQ operation progresses. and is the live version of the register. The register can also be written by the Command Queue operation itself..."
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bitfld.long 0x10 28. "CQADDR28,Bit 28 of target byte address for source of CQ. Used to denote Flash (0) or SRAM (1) access" "0,1"
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hexmask.long.tbyte 0x10 2.--19. 1. "CQADDR,Bits 19:2 of target byte address for source of CQ. The buffer must be aligned on a word boundary"
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line.long 0x14 "CQSTAT,Provides the status of the command queue operation. If the command queue is disabled. these bits will be cleared. The bits are read only"
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bitfld.long 0x14 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
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bitfld.long 0x14 1. "CQPAUSED,Command queue operation is currently paused." "0,1"
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bitfld.long 0x14 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
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line.long 0x18 "CQFLAGS,Command Queue Flag"
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hexmask.long.word 0x18 16.--31. 1. "CQIRQMASK,Mask the bits used to generate the command queue interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE"
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hexmask.long.word 0x18 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
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line.long 0x1C "CQSETCLEAR,Set/Clear the command queue software pause flags on a per-bit basis. Contains 3 fields. allowing for setting. clearing or toggling the value in the software flags. Priority when the same bit"
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hexmask.long.byte 0x1C 16.--23. 1. "CQFCLR,Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x1C 8.--15. 1. "CQFTGL,Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x1C 0.--7. 1. "CQFSET,Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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line.long 0x20 "CQPAUSEEN,Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the CQFLAG register is '1'. CQ processing will halt until either value is changed to '0'."
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hexmask.long.word 0x20 0.--15. 1. "CQPEN,Enables the specified event to pause command processing when active"
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line.long 0x24 "CQCURIDX,Current index value. targeted to be written by register write operations within the command queue. This is compared to the CQENDIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and"
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hexmask.long.byte 0x24 0.--7. 1. "CQCURIDX,Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x28 "CQENDIDX,End index value. targeted to be written by software to indicate the last valid register pair contained within the command queue for a register write operations within the command queue."
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hexmask.long.byte 0x28 0.--7. 1. "CQENDIDX,Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x2C "STATUS,IOM Module Status"
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bitfld.long 0x2C 2. "IDLEST,indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to hold-offs from data availability or as the command gets propagated into the logic from the registers." "?,1: The I/O state machine is in the idle state."
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bitfld.long 0x2C 1. "CMDACT,Indicates if the active I/O Command is currently processing a transaction or command is complete but the FIFO pointers are still synchronizing internally. This bit will go high at" "?,1: An I/O command is active. Indicates the active.."
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bitfld.long 0x2C 0. "ERR,Bit has been deprecated. Please refer to the other error indicators. This will always return 0." "?,1: Bit has been deprecated and will always return 0."
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group.long 0x300++0x3
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line.long 0x0 "MSPICFG,Controls the configuration of the SPI master module. including POL/PHA. LSB. flow control. and delays for MISO and MOSI"
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bitfld.long 0x0 30. "MSPIRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 27.--29. "DOUTDLY,Delay tap to use for the output signal (MOSI). This give more hold time on the output data" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 24.--26. "DINDLY,Delay tap to use for the input signal (MISO). This gives more hold time on the input data." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "SPILSB,Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first." "0: Send and receive MSB bit first,1: Send and receive LSB bit first"
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bitfld.long 0x0 22. "RDFCPOL,selects the read flow control signal polarity." "0: Flow control signal high creates flow control.,1: Flow control signal low creates flow control."
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bitfld.long 0x0 21. "WTFCPOL,selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 will allow a IRQ=1 to pause transfers)." "0: Flow control signal high(1) creates flow control..,1: Flow control signal low(0) creates flow control.."
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|
newline
|
|
bitfld.long 0x0 20. "WTFCIRQ,selects the write mode flow control signal." "0: MISO is used as the write mode flow control..,1: IRQ is used as the write mode flow control signal."
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|
bitfld.long 0x0 18. "MOSIINV,inverts MOSI when flow control is enabled." "0: MOSI is set to 0 in read mode and 1 in write mode.,1: MOSI is set to 1 in read mode and 0 in write mode."
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|
newline
|
|
bitfld.long 0x0 17. "RDFC,enables read mode flow control." "0: Read mode flow control disabled.,1: Read mode flow control enabled."
|
|
bitfld.long 0x0 16. "WTFC,enables write mode flow control." "0: Write mode flow control disabled.,1: Write mode flow control enabled."
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|
newline
|
|
bitfld.long 0x0 2. "FULLDUP,Enables full duplex mode for Master SPI write operations. Data will be captured simultaneously into the read FIFO" "0,1"
|
|
bitfld.long 0x0 1. "SPHA,selects SPI phase." "0: Sample on the leading (first) clock edge.,1: Sample on the trailing (second) clock edge."
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|
newline
|
|
bitfld.long 0x0 0. "SPOL,selects SPI polarity." "0: The base value of the clock is 0.,1: The base value of the clock is 1."
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|
group.long 0x400++0x7
|
|
line.long 0x0 "MI2CCFG,Controls the configuration of the I2C bus master."
|
|
bitfld.long 0x0 24. "STRDIS,Disable detection of clock stretch events smaller than 1 cycle" "0,1"
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|
hexmask.long.byte 0x0 16.--23. 1. "SMPCNT,Number of Base clock cycles to wait before sampling the SCL clock to determine if a clock stretch event has occurred"
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|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "SDAENDLY,Number of IOCLK cycles to delay the SDA output en (all transitions affected). Used to delay data relative to clock"
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|
hexmask.long.byte 0x0 8.--11. 1. "SCLENDLY,Number of IOCLK cycles to delay the rising edge of the SCL output en (clock will go low on this edge). Used to allow clock shaping."
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|
newline
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bitfld.long 0x0 6. "MI2CRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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|
bitfld.long 0x0 4.--5. "SDADLY,Delay to enable on the SDA output. Values are 0x0-0x3." "0,1,2,3"
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|
newline
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bitfld.long 0x0 2. "ARBEN,Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master this function can be disabled to save clock cycles on I2C transactions" "0: Disable multi-master bus arbitration support for..,1: Enable multi-master bus arbitration support for.."
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|
bitfld.long 0x0 1. "I2CLSB,Direction of data transmit and receive MSB(0) or LSB(1) first. Default per I2C specification is MSB first. This applies to both read and write data and read data will be bit" "0: Byte data is transmitted MSB first onto the..,1: Byte data is transmitted LSB first onto the.."
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|
newline
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bitfld.long 0x0 0. "ADDRSZ,Sets the I2C master device address size to either 7 bits (0) or 10 bits (1)." "0: Use 7-bit addressing for I2C master transactions,1: Use 10-bit addressing for I2C master transactions"
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|
line.long 0x4 "DEVCFG,Contains the I2C device address."
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|
hexmask.long.word 0x4 0.--9. 1. "DEVADDR,I2C address of the device that the Master will use to target for read/write operations. This can be either a 7-bit or 10-bit address."
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|
group.long 0x410++0x3
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|
line.long 0x0 "IOMDBG,Debug control"
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|
hexmask.long 0x0 3.--31. 1. "DBGDATA,Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers."
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bitfld.long 0x0 2. "APBCLKON,APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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newline
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bitfld.long 0x0 1. "IOCLKON,IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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|
bitfld.long 0x0 0. "DBGEN,Debug Enable. Setting bit will enable the update of data within this register otherwise it is clock gated for power savings" "0,1"
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|
tree.end
|
|
endif
|
|
sif (cpuis("AMA3B1KK")||cpuis("AMAP31KK"))
|
|
tree "IOM4"
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|
base ad:0x50008000
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|
group.long 0x0++0x3
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|
line.long 0x0 "FIFO,Provides direct random access to both output and input FIFOs. The state of the FIFO is not disturbed by reading these locations (i.e.. no POP will be done). FIFO0 is accessible from addresses 0x0 - 0x1C. and is used for data output from the IOM to.."
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|
hexmask.long 0x0 0.--31. 1. "FIFO,FIFO direct access. Only locations 0 - 3F will return valid information."
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|
group.long 0x100++0x17
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|
line.long 0x0 "FIFOPTR,Provides the current valid byte count of data within the FIFO as seen from the internal state machines. FIFO0 is dedicated to outgoing transactions and FIFO1 is dedicated to incoming transactions. All counts are specified in units of bytes."
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hexmask.long.byte 0x0 24.--31. 1. "FIFO1REM,The number of remaining data bytes slots currently in FIFO 1 (written by interface read by MCU)"
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|
hexmask.long.byte 0x0 16.--23. 1. "FIFO1SIZ,The number of valid data bytes currently in FIFO 1 (written by interface read by MCU)"
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|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "FIFO0REM,The number of remaining data bytes slots currently in FIFO 0 (written by MCU read by interface)"
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|
hexmask.long.byte 0x0 0.--7. 1. "FIFO0SIZ,The number of valid data bytes currently in the FIFO 0 (written by MCU read by interface)"
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|
line.long 0x4 "FIFOTHR,Sets the threshold values for incoming and outgoing transactions. The threshold values are used to assert the interrupt if enabled. and also used during DMA to set the transfer size as a result of DMATHR trigger."
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|
hexmask.long.byte 0x4 8.--13. 1. "FIFOWTHR,FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the write FIFO contains FIFOWTHR free bytes as.."
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|
hexmask.long.byte 0x4 0.--5. 1. "FIFORTHR,FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the read FIFO contains FIFORTHR valid bytes of data as.."
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|
line.long 0x8 "FIFOPOP,Will advance the internal read pointer of the incoming FIFO (FIFO1) when read. if POPWR is not active. If POPWR is active. a write to this register is needed to advance the internal FIFO pointer."
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hexmask.long 0x8 0.--31. 1. "FIFODOUT,This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0) the FIFO read pointer will be advanced by one word as a result of the read."
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|
line.long 0xC "FIFOPUSH,Will write new data into the outgoing FIFO and advance the internal write pointer."
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|
hexmask.long 0xC 0.--31. 1. "FIFODIN,This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes)."
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line.long 0x10 "FIFOCTRL,Provides controls for the operation of the internal FIFOs. Contains fields used to control the operation of the POP register. and also controls to reset the internal pointers of the FIFOs."
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|
bitfld.long 0x10 1. "FIFORSTN,Active low manual reset of the FIFO. Write to 0 to reset FIFO and then write to 1 to remove the reset." "0,1"
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|
bitfld.long 0x10 0. "POPWR,Selects the mode in which 'pop' events are done for the FIFO read operations. A value of '1' will prevent a pop event on a read operation and will require a write to the FIFOPOP register to create a pop event." "0,1"
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|
line.long 0x14 "FIFOLOC,Provides a read only value of the current read and write pointers. This register is read only and can be used along with the FIFO direct access method to determine the next data to be used for input and output functions."
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|
hexmask.long.byte 0x14 8.--11. 1. "FIFORPTR,Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1) which is used to store read data returned from external devices during a read operation."
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|
hexmask.long.byte 0x14 0.--3. 1. "FIFOWPTR,Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0) which is used during write operations to external devices."
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|
group.long 0x200++0x27
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|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
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|
bitfld.long 0x0 14. "CQERR,Error during command queue operations" "0,1"
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|
bitfld.long 0x0 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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newline
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bitfld.long 0x0 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x0 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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|
newline
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|
bitfld.long 0x0 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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|
bitfld.long 0x0 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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|
bitfld.long 0x0 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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|
newline
|
|
bitfld.long 0x0 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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|
bitfld.long 0x0 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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|
newline
|
|
bitfld.long 0x0 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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|
bitfld.long 0x0 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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|
newline
|
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bitfld.long 0x0 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
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|
bitfld.long 0x0 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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|
newline
|
|
bitfld.long 0x0 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
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|
bitfld.long 0x4 14. "CQERR,Error during command queue operations" "0,1"
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|
bitfld.long 0x4 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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newline
|
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bitfld.long 0x4 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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|
bitfld.long 0x4 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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|
newline
|
|
bitfld.long 0x4 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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|
bitfld.long 0x4 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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|
newline
|
|
bitfld.long 0x4 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x4 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x4 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0x4 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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|
newline
|
|
bitfld.long 0x4 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
|
|
bitfld.long 0x4 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 14. "CQERR,Error during command queue operations" "0,1"
|
|
bitfld.long 0x8 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
|
|
bitfld.long 0x8 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0x8 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x8 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x8 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0x8 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
|
|
bitfld.long 0x8 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 14. "CQERR,Error during command queue operations" "0,1"
|
|
bitfld.long 0xC 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
|
|
bitfld.long 0xC 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0xC 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0xC 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0xC 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0xC 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
|
|
bitfld.long 0xC 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
|
|
line.long 0x10 "CLKCFG,Provides clock related controls used internal to the BLEIF module. and enablement of 32KHz clock to the BLE Core module. The internal clock sourced is selected via the FSEL and can be further divided by 3 using the DIV3 control."
|
|
hexmask.long.byte 0x10 24.--31. 1. "TOTPER,Clock total clock count minus 1. This provides the total period of the divided clock -1 when the DIVEN is active. The"
|
|
hexmask.long.byte 0x10 16.--23. 1. "LOWPER,Clock low clock count minus 1. This provides the number of clocks the divided clock will be low when the DIVEN = 1."
|
|
newline
|
|
bitfld.long 0x10 12. "DIVEN,Enable clock division by TOTPER and LOWPER" "0: Disable TOTPER division.,1: Enable TOTPER division."
|
|
bitfld.long 0x10 11. "DIV3,Enable divide by 3 of the source IOCLK. Division by 3 is done before the DIVEN programmable divider and if enabled" "0: Select divide by 1.,1: Select divide by 3."
|
|
newline
|
|
bitfld.long 0x10 8.--10. "FSEL,Select the input clock frequency." "0: Selects the minimum power clock. This setting..,1: Selects the HFRC as the input clock.,2: Selects the HFRC / 2 as the input clock.,3: Selects the HFRC / 4 as the input clock.,4: Selects the HFRC / 8 as the input clock.,5: Selects the HFRC / 16 as the input clock.,6: Selects the HFRC / 32 as the input clock.,7: Selects the HFRC / 64 as the input clock."
|
|
bitfld.long 0x10 0. "IOCLKEN,Enable for the interface clock. Must be enabled prior to executing any IO operations." "0,1"
|
|
line.long 0x14 "SUBMODCTRL,Provides enable for each submodule. Only a single submodule can be enabled at one time."
|
|
bitfld.long 0x14 5.--7. "SMOD1TYPE,Submodule 0 module type. This is the I2C Master interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,?,?,?,7: NOT INSTALLED"
|
|
bitfld.long 0x14 4. "SMOD1EN,Submodule 1 enable (1) or disable (0)" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1.--3. "SMOD0TYPE,Submodule 0 module type. This is the SPI Master interface." "0: MSPI submodule,1: I2C Master submodule,2: SPI Slave submodule,3: I2C Slave submodule,?,?,?,7: NOT INSTALLED"
|
|
bitfld.long 0x14 0. "SMOD0EN,Submodule 0 enable (1) or disable (0)" "0,1"
|
|
line.long 0x18 "CMD,Writes to this register will start an IO transaction. as well as set various parameters for the command itself. Reads will return the command value written to the CMD register."
|
|
hexmask.long.byte 0x18 24.--31. 1. "OFFSETLO,This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command."
|
|
bitfld.long 0x18 20.--21. "CMDSEL,Command Specific selection information. Not used in Master I2C. Used as CEn select for Master SPI transactions" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x18 8.--19. 1. "TSIZE,Defines the transaction size in bytes. The offset transfer is not included in this size."
|
|
bitfld.long 0x18 7. "CONT,Continue to hold the bus after the current transaction if set to a 1 with a new command issued." "0,1"
|
|
newline
|
|
bitfld.long 0x18 5.--6. "OFFSETCNT,Number of offset bytes to use for the command - 0 1 2 3 are valid selections. The second (byte 1) and third byte (byte 2) are read from the OFFSETHI register and the low order byte is pulled from this register in the OFFSETLO field." "0,1,2,3"
|
|
hexmask.long.byte 0x18 0.--4. 1. "CMD,Command for submodule."
|
|
line.long 0x1C "DCX,Enables use of CE signals to transmit DCX level for SPI transactions. Only used in Apollo3 Revision B. For Revision A. this register MUST NOT be programmed!"
|
|
bitfld.long 0x1C 4. "DCXEN,Revision A: MUST NOT be programmed! Revision B: Bit 4: DCX Signaling Enable via other CE signals. The selected DCX signal (unused CE pin) will be driven low during write of offset byte and high during transmission of data bytes." "0: Disable DCX.,1: Enable DCX."
|
|
bitfld.long 0x1C 3. "CE3OUT,Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE3 output." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 2. "CE2OUT,Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE2 output." "0,1"
|
|
bitfld.long 0x1C 1. "CE1OUT,Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE1 output." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "CE0OUT,Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE0 output." "0,1"
|
|
line.long 0x20 "OFFSETHI,High order 2 bytes of 3 byte offset for IO transaction"
|
|
hexmask.long.word 0x20 0.--15. 1. "OFFSETHI,Holds the high order 2 bytes of the 3 byte addressing/offset field to use with IO commands. The number of offset bytes to use is specified in the command register"
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|
line.long 0x24 "CMDSTAT,Provides status on the execution of the command currently in progress. The fields in this register will reflect the real time status of the internal state machines and data transfers within the IOM."
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|
hexmask.long.word 0x24 8.--19. 1. "CTSIZE,The current number of bytes still to be transferred with this command. This field will count down to zero."
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|
bitfld.long 0x24 5.--7. "CMDSTAT,The current status of the command execution." "?,1: Error encountered with command,2: Actively processing command,?,4: Idle state no active command no error,?,6: Command in progress but waiting on data from host,?"
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|
newline
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hexmask.long.byte 0x24 0.--4. 1. "CCMD,current command that is being executed"
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|
group.long 0x240++0x7
|
|
line.long 0x0 "DMATRIGEN,Provides control on which event will trigger the DMA transfer after the DMA operation is setup and enabled. The trigger event will cause a number of bytes (depending on trigger event) to be"
|
|
bitfld.long 0x0 1. "DTHREN,Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes) the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO and will transfer (WTHR/4) number of words" "0,1"
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bitfld.long 0x0 0. "DCMDCMPEN,Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered the number of words transferred will be the lesser of the remaining TOTCOUNT bytes or" "0,1"
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|
line.long 0x4 "DMATRIGSTAT,Provides the status of trigger events that have occurred for the transaction. Some of the bits are read only and some can be reset via a write of 0."
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|
bitfld.long 0x4 2. "DTOTCMP,DMA triggered when DCMDCMP = 0 and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is" "0,1"
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|
bitfld.long 0x4 1. "DTHR,Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA." "0,1"
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|
newline
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bitfld.long 0x4 0. "DCMDCMP,Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA." "0,1"
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|
group.long 0x280++0x3
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|
line.long 0x0 "DMACFG,Configuration control of the DMA process. including the direction of DMA. and enablement of DMA"
|
|
bitfld.long 0x0 9. "DPWROFF,Power off module after DMA is complete. If this bit is active the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain power down will not be performed." "0: Power off disabled,1: Power off enabled"
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|
bitfld.long 0x0 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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|
newline
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bitfld.long 0x0 1. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction. To be..,1: Memory to Peripheral transaction. To be set when.."
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|
bitfld.long 0x0 0. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable DMA Function,1: Enable DMA Function"
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|
group.long 0x288++0x2F
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|
line.long 0x0 "DMATOTCOUNT,Contains the number of bytes to be transferred for this DMA transaction. This register is decremented as the data is transferred. and will be 0 at the completion of the DMA operation."
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|
hexmask.long.word 0x0 0.--11. 1. "TOTCOUNT,Triggered DMA from Command complete event occurred. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."
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|
line.long 0x4 "DMATARGADDR,The source or destination address internal the SRAM for the DMA data. For write operations. this can only be SRAM data (ADDR bit 28 = 1); For read operations. this can be either SRAM or FLASH (ADDR bit 28 = 0)"
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bitfld.long 0x4 28. "TARGADDR28,Bit 28 of the target byte address for source of DMA (either read or write). In cases of non-word aligned addresses the DMA logic will take care for ensuring only the target bytes are read/written." "0,1"
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|
hexmask.long.tbyte 0x4 0.--19. 1. "TARGADDR,Bits [19:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment and does not have to be word aligned. In cases of non-word aligned addresses the DMA logic will take care for ensuring only.."
|
|
line.long 0x8 "DMASTAT,Status of the DMA operation currently in progress."
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|
bitfld.long 0x8 2. "DMAERR,DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set this bit will remain set until cleared by software." "0,1"
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|
bitfld.long 0x8 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0 and will also be cleared when a new DMA is started." "0,1"
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newline
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bitfld.long 0x8 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
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|
line.long 0xC "CQCFG,Controls parameters and options for execution of the command queue operation. To enable command queue. create this in memory. set the address. and enable it with a write to CQEN"
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|
bitfld.long 0xC 1. "CQPRI,Sets the Priority of the command queue DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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|
bitfld.long 0xC 0. "CQEN,Command queue enable. When set will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled using a CQ executed write to this bit as well." "0: Disable CQ Function,1: Enable CQ Function"
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|
line.long 0x10 "CQADDR,The SRAM address which will be fetched next execution of the CQ operation. This register is updated as the CQ operation progresses. and is the live version of the register. The register can also be written by the Command Queue operation itself..."
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bitfld.long 0x10 28. "CQADDR28,Bit 28 of target byte address for source of CQ. Used to denote Flash (0) or SRAM (1) access" "0,1"
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hexmask.long.tbyte 0x10 2.--19. 1. "CQADDR,Bits 19:2 of target byte address for source of CQ. The buffer must be aligned on a word boundary"
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|
line.long 0x14 "CQSTAT,Provides the status of the command queue operation. If the command queue is disabled. these bits will be cleared. The bits are read only"
|
|
bitfld.long 0x14 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
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|
bitfld.long 0x14 1. "CQPAUSED,Command queue operation is currently paused." "0,1"
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bitfld.long 0x14 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
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line.long 0x18 "CQFLAGS,Command Queue Flag"
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hexmask.long.word 0x18 16.--31. 1. "CQIRQMASK,Mask the bits used to generate the command queue interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE"
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hexmask.long.word 0x18 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
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line.long 0x1C "CQSETCLEAR,Set/Clear the command queue software pause flags on a per-bit basis. Contains 3 fields. allowing for setting. clearing or toggling the value in the software flags. Priority when the same bit"
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|
hexmask.long.byte 0x1C 16.--23. 1. "CQFCLR,Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field"
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|
hexmask.long.byte 0x1C 8.--15. 1. "CQFTGL,Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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newline
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hexmask.long.byte 0x1C 0.--7. 1. "CQFSET,Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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line.long 0x20 "CQPAUSEEN,Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the CQFLAG register is '1'. CQ processing will halt until either value is changed to '0'."
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hexmask.long.word 0x20 0.--15. 1. "CQPEN,Enables the specified event to pause command processing when active"
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line.long 0x24 "CQCURIDX,Current index value. targeted to be written by register write operations within the command queue. This is compared to the CQENDIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and"
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|
hexmask.long.byte 0x24 0.--7. 1. "CQCURIDX,Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x28 "CQENDIDX,End index value. targeted to be written by software to indicate the last valid register pair contained within the command queue for a register write operations within the command queue."
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hexmask.long.byte 0x28 0.--7. 1. "CQENDIDX,Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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|
line.long 0x2C "STATUS,IOM Module Status"
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|
bitfld.long 0x2C 2. "IDLEST,indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to hold-offs from data availability or as the command gets propagated into the logic from the registers." "?,1: The I/O state machine is in the idle state."
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bitfld.long 0x2C 1. "CMDACT,Indicates if the active I/O Command is currently processing a transaction or command is complete but the FIFO pointers are still synchronizing internally. This bit will go high at" "?,1: An I/O command is active. Indicates the active.."
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|
newline
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bitfld.long 0x2C 0. "ERR,Bit has been deprecated. Please refer to the other error indicators. This will always return 0." "?,1: Bit has been deprecated and will always return 0."
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|
group.long 0x300++0x3
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|
line.long 0x0 "MSPICFG,Controls the configuration of the SPI master module. including POL/PHA. LSB. flow control. and delays for MISO and MOSI"
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bitfld.long 0x0 30. "MSPIRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 27.--29. "DOUTDLY,Delay tap to use for the output signal (MOSI). This give more hold time on the output data" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x0 24.--26. "DINDLY,Delay tap to use for the input signal (MISO). This gives more hold time on the input data." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "SPILSB,Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first." "0: Send and receive MSB bit first,1: Send and receive LSB bit first"
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newline
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bitfld.long 0x0 22. "RDFCPOL,selects the read flow control signal polarity." "0: Flow control signal high creates flow control.,1: Flow control signal low creates flow control."
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bitfld.long 0x0 21. "WTFCPOL,selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 will allow a IRQ=1 to pause transfers)." "0: Flow control signal high(1) creates flow control..,1: Flow control signal low(0) creates flow control.."
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newline
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bitfld.long 0x0 20. "WTFCIRQ,selects the write mode flow control signal." "0: MISO is used as the write mode flow control..,1: IRQ is used as the write mode flow control signal."
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bitfld.long 0x0 18. "MOSIINV,inverts MOSI when flow control is enabled." "0: MOSI is set to 0 in read mode and 1 in write mode.,1: MOSI is set to 1 in read mode and 0 in write mode."
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newline
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bitfld.long 0x0 17. "RDFC,enables read mode flow control." "0: Read mode flow control disabled.,1: Read mode flow control enabled."
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bitfld.long 0x0 16. "WTFC,enables write mode flow control." "0: Write mode flow control disabled.,1: Write mode flow control enabled."
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newline
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bitfld.long 0x0 2. "FULLDUP,Enables full duplex mode for Master SPI write operations. Data will be captured simultaneously into the read FIFO" "0,1"
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|
bitfld.long 0x0 1. "SPHA,selects SPI phase." "0: Sample on the leading (first) clock edge.,1: Sample on the trailing (second) clock edge."
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|
newline
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bitfld.long 0x0 0. "SPOL,selects SPI polarity." "0: The base value of the clock is 0.,1: The base value of the clock is 1."
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group.long 0x400++0x7
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line.long 0x0 "MI2CCFG,Controls the configuration of the I2C bus master."
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bitfld.long 0x0 24. "STRDIS,Disable detection of clock stretch events smaller than 1 cycle" "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "SMPCNT,Number of Base clock cycles to wait before sampling the SCL clock to determine if a clock stretch event has occurred"
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|
newline
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hexmask.long.byte 0x0 12.--15. 1. "SDAENDLY,Number of IOCLK cycles to delay the SDA output en (all transitions affected). Used to delay data relative to clock"
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hexmask.long.byte 0x0 8.--11. 1. "SCLENDLY,Number of IOCLK cycles to delay the rising edge of the SCL output en (clock will go low on this edge). Used to allow clock shaping."
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|
newline
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bitfld.long 0x0 6. "MI2CRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
|
|
bitfld.long 0x0 4.--5. "SDADLY,Delay to enable on the SDA output. Values are 0x0-0x3." "0,1,2,3"
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newline
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bitfld.long 0x0 2. "ARBEN,Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master this function can be disabled to save clock cycles on I2C transactions" "0: Disable multi-master bus arbitration support for..,1: Enable multi-master bus arbitration support for.."
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bitfld.long 0x0 1. "I2CLSB,Direction of data transmit and receive MSB(0) or LSB(1) first. Default per I2C specification is MSB first. This applies to both read and write data and read data will be bit" "0: Byte data is transmitted MSB first onto the..,1: Byte data is transmitted LSB first onto the.."
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newline
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bitfld.long 0x0 0. "ADDRSZ,Sets the I2C master device address size to either 7 bits (0) or 10 bits (1)." "0: Use 7-bit addressing for I2C master transactions,1: Use 10-bit addressing for I2C master transactions"
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line.long 0x4 "DEVCFG,Contains the I2C device address."
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hexmask.long.word 0x4 0.--9. 1. "DEVADDR,I2C address of the device that the Master will use to target for read/write operations. This can be either a 7-bit or 10-bit address."
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group.long 0x410++0x3
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line.long 0x0 "IOMDBG,Debug control"
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hexmask.long 0x0 3.--31. 1. "DBGDATA,Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers."
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bitfld.long 0x0 2. "APBCLKON,APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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newline
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bitfld.long 0x0 1. "IOCLKON,IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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bitfld.long 0x0 0. "DBGEN,Debug Enable. Setting bit will enable the update of data within this register otherwise it is clock gated for power savings" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("AMA3B1KK")||cpuis("AMAP31KK"))
|
|
tree "IOM5"
|
|
base ad:0x50009000
|
|
group.long 0x0++0x3
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|
line.long 0x0 "FIFO,Provides direct random access to both output and input FIFOs. The state of the FIFO is not disturbed by reading these locations (i.e.. no POP will be done). FIFO0 is accessible from addresses 0x0 - 0x1C. and is used for data output from the IOM to.."
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hexmask.long 0x0 0.--31. 1. "FIFO,FIFO direct access. Only locations 0 - 3F will return valid information."
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group.long 0x100++0x17
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line.long 0x0 "FIFOPTR,Provides the current valid byte count of data within the FIFO as seen from the internal state machines. FIFO0 is dedicated to outgoing transactions and FIFO1 is dedicated to incoming transactions. All counts are specified in units of bytes."
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hexmask.long.byte 0x0 24.--31. 1. "FIFO1REM,The number of remaining data bytes slots currently in FIFO 1 (written by interface read by MCU)"
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hexmask.long.byte 0x0 16.--23. 1. "FIFO1SIZ,The number of valid data bytes currently in FIFO 1 (written by interface read by MCU)"
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|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "FIFO0REM,The number of remaining data bytes slots currently in FIFO 0 (written by MCU read by interface)"
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hexmask.long.byte 0x0 0.--7. 1. "FIFO0SIZ,The number of valid data bytes currently in the FIFO 0 (written by MCU read by interface)"
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line.long 0x4 "FIFOTHR,Sets the threshold values for incoming and outgoing transactions. The threshold values are used to assert the interrupt if enabled. and also used during DMA to set the transfer size as a result of DMATHR trigger."
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hexmask.long.byte 0x4 8.--13. 1. "FIFOWTHR,FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the write FIFO contains FIFOWTHR free bytes as.."
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hexmask.long.byte 0x4 0.--5. 1. "FIFORTHR,FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the read FIFO contains FIFORTHR valid bytes of data as.."
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line.long 0x8 "FIFOPOP,Will advance the internal read pointer of the incoming FIFO (FIFO1) when read. if POPWR is not active. If POPWR is active. a write to this register is needed to advance the internal FIFO pointer."
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hexmask.long 0x8 0.--31. 1. "FIFODOUT,This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0) the FIFO read pointer will be advanced by one word as a result of the read."
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line.long 0xC "FIFOPUSH,Will write new data into the outgoing FIFO and advance the internal write pointer."
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hexmask.long 0xC 0.--31. 1. "FIFODIN,This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes)."
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line.long 0x10 "FIFOCTRL,Provides controls for the operation of the internal FIFOs. Contains fields used to control the operation of the POP register. and also controls to reset the internal pointers of the FIFOs."
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bitfld.long 0x10 1. "FIFORSTN,Active low manual reset of the FIFO. Write to 0 to reset FIFO and then write to 1 to remove the reset." "0,1"
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bitfld.long 0x10 0. "POPWR,Selects the mode in which 'pop' events are done for the FIFO read operations. A value of '1' will prevent a pop event on a read operation and will require a write to the FIFOPOP register to create a pop event." "0,1"
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line.long 0x14 "FIFOLOC,Provides a read only value of the current read and write pointers. This register is read only and can be used along with the FIFO direct access method to determine the next data to be used for input and output functions."
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hexmask.long.byte 0x14 8.--11. 1. "FIFORPTR,Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1) which is used to store read data returned from external devices during a read operation."
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hexmask.long.byte 0x14 0.--3. 1. "FIFOWPTR,Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0) which is used during write operations to external devices."
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group.long 0x200++0x27
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line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
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bitfld.long 0x0 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x0 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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newline
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bitfld.long 0x0 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x0 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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newline
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bitfld.long 0x0 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x0 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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newline
|
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bitfld.long 0x0 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x0 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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newline
|
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bitfld.long 0x0 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x0 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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newline
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bitfld.long 0x0 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0x0 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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newline
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bitfld.long 0x0 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
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|
bitfld.long 0x0 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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|
newline
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bitfld.long 0x0 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x4 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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newline
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bitfld.long 0x4 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x4 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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newline
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bitfld.long 0x4 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0x4 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x4 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x4 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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|
newline
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bitfld.long 0x4 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x4 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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bitfld.long 0x4 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
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bitfld.long 0x4 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x4 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
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bitfld.long 0x8 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x8 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x8 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x8 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x8 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x8 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0x8 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x8 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x8 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x8 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x8 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x8 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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bitfld.long 0x8 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
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bitfld.long 0x8 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x8 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
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bitfld.long 0xC 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0xC 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0xC 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0xC 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0xC 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0xC 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0xC 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0xC 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0xC 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0xC 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0xC 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0xC 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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bitfld.long 0xC 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
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bitfld.long 0xC 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0xC 0. "CMDCMP,Command Complete interrupt. Asserted when the current operation has completed. For repeated commands this will only be asserted when the final repeated command is completed." "0,1"
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line.long 0x10 "CLKCFG,Provides clock related controls used internal to the BLEIF module. and enablement of 32KHz clock to the BLE Core module. The internal clock sourced is selected via the FSEL and can be further divided by 3 using the DIV3 control."
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hexmask.long.byte 0x10 24.--31. 1. "TOTPER,Clock total clock count minus 1. This provides the total period of the divided clock -1 when the DIVEN is active. The"
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hexmask.long.byte 0x10 16.--23. 1. "LOWPER,Clock low clock count minus 1. This provides the number of clocks the divided clock will be low when the DIVEN = 1."
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bitfld.long 0x10 12. "DIVEN,Enable clock division by TOTPER and LOWPER" "0: Disable TOTPER division.,1: Enable TOTPER division."
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bitfld.long 0x10 11. "DIV3,Enable divide by 3 of the source IOCLK. Division by 3 is done before the DIVEN programmable divider and if enabled" "0: Select divide by 1.,1: Select divide by 3."
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bitfld.long 0x10 8.--10. "FSEL,Select the input clock frequency." "0: Selects the minimum power clock. This setting..,1: Selects the HFRC as the input clock.,2: Selects the HFRC / 2 as the input clock.,3: Selects the HFRC / 4 as the input clock.,4: Selects the HFRC / 8 as the input clock.,5: Selects the HFRC / 16 as the input clock.,6: Selects the HFRC / 32 as the input clock.,7: Selects the HFRC / 64 as the input clock."
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bitfld.long 0x10 0. "IOCLKEN,Enable for the interface clock. Must be enabled prior to executing any IO operations." "0,1"
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line.long 0x14 "SUBMODCTRL,Provides enable for each submodule. Only a single submodule can be enabled at one time."
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bitfld.long 0x14 5.--7. "SMOD1TYPE,Submodule 0 module type. This is the I2C Master interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,?,?,?,7: NOT INSTALLED"
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bitfld.long 0x14 4. "SMOD1EN,Submodule 1 enable (1) or disable (0)" "0,1"
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bitfld.long 0x14 1.--3. "SMOD0TYPE,Submodule 0 module type. This is the SPI Master interface." "0: MSPI submodule,1: I2C Master submodule,2: SPI Slave submodule,3: I2C Slave submodule,?,?,?,7: NOT INSTALLED"
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bitfld.long 0x14 0. "SMOD0EN,Submodule 0 enable (1) or disable (0)" "0,1"
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line.long 0x18 "CMD,Writes to this register will start an IO transaction. as well as set various parameters for the command itself. Reads will return the command value written to the CMD register."
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hexmask.long.byte 0x18 24.--31. 1. "OFFSETLO,This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command."
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bitfld.long 0x18 20.--21. "CMDSEL,Command Specific selection information. Not used in Master I2C. Used as CEn select for Master SPI transactions" "0,1,2,3"
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hexmask.long.word 0x18 8.--19. 1. "TSIZE,Defines the transaction size in bytes. The offset transfer is not included in this size."
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bitfld.long 0x18 7. "CONT,Continue to hold the bus after the current transaction if set to a 1 with a new command issued." "0,1"
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bitfld.long 0x18 5.--6. "OFFSETCNT,Number of offset bytes to use for the command - 0 1 2 3 are valid selections. The second (byte 1) and third byte (byte 2) are read from the OFFSETHI register and the low order byte is pulled from this register in the OFFSETLO field." "0,1,2,3"
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hexmask.long.byte 0x18 0.--4. 1. "CMD,Command for submodule."
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line.long 0x1C "DCX,Enables use of CE signals to transmit DCX level for SPI transactions. Only used in Apollo3 Revision B. For Revision A. this register MUST NOT be programmed!"
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bitfld.long 0x1C 4. "DCXEN,Revision A: MUST NOT be programmed! Revision B: Bit 4: DCX Signaling Enable via other CE signals. The selected DCX signal (unused CE pin) will be driven low during write of offset byte and high during transmission of data bytes." "0: Disable DCX.,1: Enable DCX."
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bitfld.long 0x1C 3. "CE3OUT,Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE3 output." "0,1"
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bitfld.long 0x1C 2. "CE2OUT,Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE2 output." "0,1"
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bitfld.long 0x1C 1. "CE1OUT,Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE1 output." "0,1"
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bitfld.long 0x1C 0. "CE0OUT,Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE0 output." "0,1"
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line.long 0x20 "OFFSETHI,High order 2 bytes of 3 byte offset for IO transaction"
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hexmask.long.word 0x20 0.--15. 1. "OFFSETHI,Holds the high order 2 bytes of the 3 byte addressing/offset field to use with IO commands. The number of offset bytes to use is specified in the command register"
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line.long 0x24 "CMDSTAT,Provides status on the execution of the command currently in progress. The fields in this register will reflect the real time status of the internal state machines and data transfers within the IOM."
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hexmask.long.word 0x24 8.--19. 1. "CTSIZE,The current number of bytes still to be transferred with this command. This field will count down to zero."
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bitfld.long 0x24 5.--7. "CMDSTAT,The current status of the command execution." "?,1: Error encountered with command,2: Actively processing command,?,4: Idle state no active command no error,?,6: Command in progress but waiting on data from host,?"
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hexmask.long.byte 0x24 0.--4. 1. "CCMD,current command that is being executed"
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group.long 0x240++0x7
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line.long 0x0 "DMATRIGEN,Provides control on which event will trigger the DMA transfer after the DMA operation is setup and enabled. The trigger event will cause a number of bytes (depending on trigger event) to be"
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bitfld.long 0x0 1. "DTHREN,Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes) the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO and will transfer (WTHR/4) number of words" "0,1"
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bitfld.long 0x0 0. "DCMDCMPEN,Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered the number of words transferred will be the lesser of the remaining TOTCOUNT bytes or" "0,1"
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line.long 0x4 "DMATRIGSTAT,Provides the status of trigger events that have occurred for the transaction. Some of the bits are read only and some can be reset via a write of 0."
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bitfld.long 0x4 2. "DTOTCMP,DMA triggered when DCMDCMP = 0 and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is" "0,1"
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bitfld.long 0x4 1. "DTHR,Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA." "0,1"
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bitfld.long 0x4 0. "DCMDCMP,Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA." "0,1"
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group.long 0x280++0x3
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line.long 0x0 "DMACFG,Configuration control of the DMA process. including the direction of DMA. and enablement of DMA"
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bitfld.long 0x0 9. "DPWROFF,Power off module after DMA is complete. If this bit is active the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain power down will not be performed." "0: Power off disabled,1: Power off enabled"
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bitfld.long 0x0 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x0 1. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction. To be..,1: Memory to Peripheral transaction. To be set when.."
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bitfld.long 0x0 0. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable DMA Function,1: Enable DMA Function"
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group.long 0x288++0x2F
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line.long 0x0 "DMATOTCOUNT,Contains the number of bytes to be transferred for this DMA transaction. This register is decremented as the data is transferred. and will be 0 at the completion of the DMA operation."
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hexmask.long.word 0x0 0.--11. 1. "TOTCOUNT,Triggered DMA from Command complete event occurred. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."
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line.long 0x4 "DMATARGADDR,The source or destination address internal the SRAM for the DMA data. For write operations. this can only be SRAM data (ADDR bit 28 = 1); For read operations. this can be either SRAM or FLASH (ADDR bit 28 = 0)"
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bitfld.long 0x4 28. "TARGADDR28,Bit 28 of the target byte address for source of DMA (either read or write). In cases of non-word aligned addresses the DMA logic will take care for ensuring only the target bytes are read/written." "0,1"
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hexmask.long.tbyte 0x4 0.--19. 1. "TARGADDR,Bits [19:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment and does not have to be word aligned. In cases of non-word aligned addresses the DMA logic will take care for ensuring only.."
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line.long 0x8 "DMASTAT,Status of the DMA operation currently in progress."
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bitfld.long 0x8 2. "DMAERR,DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set this bit will remain set until cleared by software." "0,1"
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bitfld.long 0x8 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0 and will also be cleared when a new DMA is started." "0,1"
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bitfld.long 0x8 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
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line.long 0xC "CQCFG,Controls parameters and options for execution of the command queue operation. To enable command queue. create this in memory. set the address. and enable it with a write to CQEN"
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bitfld.long 0xC 1. "CQPRI,Sets the Priority of the command queue DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0xC 0. "CQEN,Command queue enable. When set will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled using a CQ executed write to this bit as well." "0: Disable CQ Function,1: Enable CQ Function"
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line.long 0x10 "CQADDR,The SRAM address which will be fetched next execution of the CQ operation. This register is updated as the CQ operation progresses. and is the live version of the register. The register can also be written by the Command Queue operation itself..."
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bitfld.long 0x10 28. "CQADDR28,Bit 28 of target byte address for source of CQ. Used to denote Flash (0) or SRAM (1) access" "0,1"
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hexmask.long.tbyte 0x10 2.--19. 1. "CQADDR,Bits 19:2 of target byte address for source of CQ. The buffer must be aligned on a word boundary"
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line.long 0x14 "CQSTAT,Provides the status of the command queue operation. If the command queue is disabled. these bits will be cleared. The bits are read only"
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bitfld.long 0x14 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
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bitfld.long 0x14 1. "CQPAUSED,Command queue operation is currently paused." "0,1"
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bitfld.long 0x14 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
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line.long 0x18 "CQFLAGS,Command Queue Flag"
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hexmask.long.word 0x18 16.--31. 1. "CQIRQMASK,Mask the bits used to generate the command queue interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE"
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hexmask.long.word 0x18 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
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line.long 0x1C "CQSETCLEAR,Set/Clear the command queue software pause flags on a per-bit basis. Contains 3 fields. allowing for setting. clearing or toggling the value in the software flags. Priority when the same bit"
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hexmask.long.byte 0x1C 16.--23. 1. "CQFCLR,Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x1C 8.--15. 1. "CQFTGL,Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x1C 0.--7. 1. "CQFSET,Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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line.long 0x20 "CQPAUSEEN,Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the CQFLAG register is '1'. CQ processing will halt until either value is changed to '0'."
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hexmask.long.word 0x20 0.--15. 1. "CQPEN,Enables the specified event to pause command processing when active"
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line.long 0x24 "CQCURIDX,Current index value. targeted to be written by register write operations within the command queue. This is compared to the CQENDIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and"
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hexmask.long.byte 0x24 0.--7. 1. "CQCURIDX,Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x28 "CQENDIDX,End index value. targeted to be written by software to indicate the last valid register pair contained within the command queue for a register write operations within the command queue."
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hexmask.long.byte 0x28 0.--7. 1. "CQENDIDX,Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x2C "STATUS,IOM Module Status"
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bitfld.long 0x2C 2. "IDLEST,indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to hold-offs from data availability or as the command gets propagated into the logic from the registers." "?,1: The I/O state machine is in the idle state."
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bitfld.long 0x2C 1. "CMDACT,Indicates if the active I/O Command is currently processing a transaction or command is complete but the FIFO pointers are still synchronizing internally. This bit will go high at" "?,1: An I/O command is active. Indicates the active.."
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bitfld.long 0x2C 0. "ERR,Bit has been deprecated. Please refer to the other error indicators. This will always return 0." "?,1: Bit has been deprecated and will always return 0."
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group.long 0x300++0x3
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line.long 0x0 "MSPICFG,Controls the configuration of the SPI master module. including POL/PHA. LSB. flow control. and delays for MISO and MOSI"
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bitfld.long 0x0 30. "MSPIRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 27.--29. "DOUTDLY,Delay tap to use for the output signal (MOSI). This give more hold time on the output data" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 24.--26. "DINDLY,Delay tap to use for the input signal (MISO). This gives more hold time on the input data." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "SPILSB,Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first." "0: Send and receive MSB bit first,1: Send and receive LSB bit first"
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bitfld.long 0x0 22. "RDFCPOL,selects the read flow control signal polarity." "0: Flow control signal high creates flow control.,1: Flow control signal low creates flow control."
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bitfld.long 0x0 21. "WTFCPOL,selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 will allow a IRQ=1 to pause transfers)." "0: Flow control signal high(1) creates flow control..,1: Flow control signal low(0) creates flow control.."
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bitfld.long 0x0 20. "WTFCIRQ,selects the write mode flow control signal." "0: MISO is used as the write mode flow control..,1: IRQ is used as the write mode flow control signal."
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bitfld.long 0x0 18. "MOSIINV,inverts MOSI when flow control is enabled." "0: MOSI is set to 0 in read mode and 1 in write mode.,1: MOSI is set to 1 in read mode and 0 in write mode."
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bitfld.long 0x0 17. "RDFC,enables read mode flow control." "0: Read mode flow control disabled.,1: Read mode flow control enabled."
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bitfld.long 0x0 16. "WTFC,enables write mode flow control." "0: Write mode flow control disabled.,1: Write mode flow control enabled."
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bitfld.long 0x0 2. "FULLDUP,Enables full duplex mode for Master SPI write operations. Data will be captured simultaneously into the read FIFO" "0,1"
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bitfld.long 0x0 1. "SPHA,selects SPI phase." "0: Sample on the leading (first) clock edge.,1: Sample on the trailing (second) clock edge."
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bitfld.long 0x0 0. "SPOL,selects SPI polarity." "0: The base value of the clock is 0.,1: The base value of the clock is 1."
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group.long 0x400++0x7
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line.long 0x0 "MI2CCFG,Controls the configuration of the I2C bus master."
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bitfld.long 0x0 24. "STRDIS,Disable detection of clock stretch events smaller than 1 cycle" "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "SMPCNT,Number of Base clock cycles to wait before sampling the SCL clock to determine if a clock stretch event has occurred"
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hexmask.long.byte 0x0 12.--15. 1. "SDAENDLY,Number of IOCLK cycles to delay the SDA output en (all transitions affected). Used to delay data relative to clock"
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hexmask.long.byte 0x0 8.--11. 1. "SCLENDLY,Number of IOCLK cycles to delay the rising edge of the SCL output en (clock will go low on this edge). Used to allow clock shaping."
|
|
newline
|
|
bitfld.long 0x0 6. "MI2CRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
|
|
bitfld.long 0x0 4.--5. "SDADLY,Delay to enable on the SDA output. Values are 0x0-0x3." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 2. "ARBEN,Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master this function can be disabled to save clock cycles on I2C transactions" "0: Disable multi-master bus arbitration support for..,1: Enable multi-master bus arbitration support for.."
|
|
bitfld.long 0x0 1. "I2CLSB,Direction of data transmit and receive MSB(0) or LSB(1) first. Default per I2C specification is MSB first. This applies to both read and write data and read data will be bit" "0: Byte data is transmitted MSB first onto the..,1: Byte data is transmitted LSB first onto the.."
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|
newline
|
|
bitfld.long 0x0 0. "ADDRSZ,Sets the I2C master device address size to either 7 bits (0) or 10 bits (1)." "0: Use 7-bit addressing for I2C master transactions,1: Use 10-bit addressing for I2C master transactions"
|
|
line.long 0x4 "DEVCFG,Contains the I2C device address."
|
|
hexmask.long.word 0x4 0.--9. 1. "DEVADDR,I2C address of the device that the Master will use to target for read/write operations. This can be either a 7-bit or 10-bit address."
|
|
group.long 0x410++0x3
|
|
line.long 0x0 "IOMDBG,Debug control"
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|
hexmask.long 0x0 3.--31. 1. "DBGDATA,Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers."
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|
bitfld.long 0x0 2. "APBCLKON,APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "IOCLKON,IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
|
|
bitfld.long 0x0 0. "DBGEN,Debug Enable. Setting bit will enable the update of data within this register otherwise it is clock gated for power savings" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("AMA3B2KK"))
|
|
tree "IOM0"
|
|
base ad:0x50004000
|
|
group.long 0x0++0x3
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|
line.long 0x0 "FIFO,Provides direct random access to both output and input FIFOs. The state of the FIFO is not disturbed by reading these locations (i.e.. no POP will be done). FIFO0 is accessible from addresses 0x0 - 0x1C. and is used for data output from the IOM to.."
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|
hexmask.long 0x0 0.--31. 1. "FIFO,FIFO direct access. Only locations 0 - 3F will return valid information."
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|
group.long 0x100++0x17
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|
line.long 0x0 "FIFOPTR,Provides the current valid byte count of data within the FIFO as seen from the internal state machines. FIFO0 is dedicated to outgoing transactions and FIFO1 is dedicated to incoming transactions. All counts are specified in units of bytes."
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|
hexmask.long.byte 0x0 24.--31. 1. "FIFO1REM,The number of remaining data bytes slots currently in FIFO 1 (written by interface read by MCU)"
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|
hexmask.long.byte 0x0 16.--23. 1. "FIFO1SIZ,The number of valid data bytes currently in FIFO 1 (written by interface read by MCU)"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "FIFO0REM,The number of remaining data bytes slots currently in FIFO 0 (written by MCU read by interface)"
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|
hexmask.long.byte 0x0 0.--7. 1. "FIFO0SIZ,The number of valid data bytes currently in the FIFO 0 (written by MCU read by interface)"
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|
line.long 0x4 "FIFOTHR,Sets the threshold values for incoming and outgoing transactions. The threshold values are used to assert the interrupt if enabled. and also used during DMA to set the transfer size as a result of DMATHR trigger."
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|
hexmask.long.byte 0x4 8.--13. 1. "FIFOWTHR,FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the write FIFO contains FIFOWTHR free bytes as.."
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|
hexmask.long.byte 0x4 0.--5. 1. "FIFORTHR,FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the read FIFO contains FIFORTHR valid bytes of data as.."
|
|
line.long 0x8 "FIFOPOP,Will advance the internal read pointer of the incoming FIFO (FIFO1) when read. if POPWR is not active. If POPWR is active. a write to this register is needed to advance the internal FIFO pointer."
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|
hexmask.long 0x8 0.--31. 1. "FIFODOUT,This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0) the FIFO read pointer will be advanced by one word as a result of the read."
|
|
line.long 0xC "FIFOPUSH,Will write new data into the outgoing FIFO and advance the internal write pointer."
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|
hexmask.long 0xC 0.--31. 1. "FIFODIN,This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes)."
|
|
line.long 0x10 "FIFOCTRL,Provides controls for the operation of the internal FIFOs. Contains fields used to control the operation of the POP register. and also controls to reset the internal pointers of the FIFOs."
|
|
bitfld.long 0x10 1. "FIFORSTN,Active low manual reset of the FIFO. Write to 0 to reset FIFO and then write to 1 to remove the reset." "0,1"
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|
bitfld.long 0x10 0. "POPWR,Selects the mode in which 'pop' events are done for the FIFO read operations. A value of '1' will prevent a pop event on a read operation and will require a write to the FIFOPOP register to create a pop event." "0,1"
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|
line.long 0x14 "FIFOLOC,Provides a read only value of the current read and write pointers. This register is read only and can be used along with the FIFO direct access method to determine the next data to be used for input and output functions."
|
|
hexmask.long.byte 0x14 8.--11. 1. "FIFORPTR,Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1) which is used to store read data returned from external devices during a read operation."
|
|
hexmask.long.byte 0x14 0.--3. 1. "FIFOWPTR,Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0) which is used during write operations to external devices."
|
|
group.long 0x200++0x27
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 14. "CQERR,Error during command queue operations" "0,1"
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|
bitfld.long 0x0 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
|
|
bitfld.long 0x0 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0x0 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x0 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x0 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0x0 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
|
|
bitfld.long 0x0 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMDCMP,Command complete interrupt" "0,1"
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 14. "CQERR,Error during command queue operations" "0,1"
|
|
bitfld.long 0x4 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
|
|
bitfld.long 0x4 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0x4 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x4 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x4 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0x4 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
|
|
bitfld.long 0x4 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CMDCMP,Command complete interrupt" "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 14. "CQERR,Error during command queue operations" "0,1"
|
|
bitfld.long 0x8 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
|
|
bitfld.long 0x8 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0x8 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x8 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x8 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0x8 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
|
|
bitfld.long 0x8 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "CMDCMP,Command complete interrupt" "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 14. "CQERR,Error during command queue operations" "0,1"
|
|
bitfld.long 0xC 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
|
|
bitfld.long 0xC 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0xC 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0xC 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0xC 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0xC 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
|
|
bitfld.long 0xC 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "CMDCMP,Command complete interrupt" "0,1"
|
|
line.long 0x10 "CLKCFG,Provides clock related controls used internal to the BLEIF module. and enablement of 32KHz clock to the BLE Core module. The internal clock sourced is selected via the FSEL and can be further divided by 3 using the DIV3 control."
|
|
hexmask.long.byte 0x10 24.--31. 1. "TOTPER,Clock total clock count minus 1. This provides the total period of the divided clock -1 when the DIVEN is active. The"
|
|
hexmask.long.byte 0x10 16.--23. 1. "LOWPER,Clock low clock count minus 1. This provides the number of clocks the divided clock will be low when the DIVEN = 1."
|
|
newline
|
|
bitfld.long 0x10 12. "DIVEN,Enable clock division by TOTPER and LOWPER" "0: Disable TOTPER division.,1: Enable TOTPER division."
|
|
bitfld.long 0x10 11. "DIV3,Enable divide by 3 of the source IOCLK. Division by 3 is done before the DIVEN programmable divider and if enabled" "0: Select divide by 1.,1: Select divide by 3."
|
|
newline
|
|
bitfld.long 0x10 8.--10. "FSEL,Select the input clock frequency." "0: Selects the minimum power clock. This setting..,1: Selects the HFRC as the input clock.,2: Selects the HFRC / 2 as the input clock.,3: Selects the HFRC / 4 as the input clock.,4: Selects the HFRC / 8 as the input clock.,5: Selects the HFRC / 16 as the input clock.,6: Selects the HFRC / 32 as the input clock.,7: Selects the HFRC / 64 as the input clock."
|
|
bitfld.long 0x10 0. "IOCLKEN,Enable for the interface clock. Must be enabled prior to executing any IO operations." "0,1"
|
|
line.long 0x14 "SUBMODCTRL,Provides enable for each submodule. Only a single submodule can be enabled at one time."
|
|
bitfld.long 0x14 5.--7. "SMOD1TYPE,Submodule 0 module type. This is the I2C Master interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,?,?,?,7: NOT INSTALLED"
|
|
bitfld.long 0x14 4. "SMOD1EN,Submodule 1 enable (1) or disable (0)" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1.--3. "SMOD0TYPE,Submodule 0 module type. This is the SPI Master interface." "0: MSPI submodule,1: I2C Master submodule,2: SPI Slave submodule,3: I2C Slave submodule,?,?,?,7: NOT INSTALLED"
|
|
bitfld.long 0x14 0. "SMOD0EN,Submodule 0 enable (1) or disable (0)" "0,1"
|
|
line.long 0x18 "CMD,Writes to this register will start an IO transaction. as well as set various parameters for the command itself. Reads will return the command value written to the CMD register."
|
|
hexmask.long.byte 0x18 24.--31. 1. "OFFSETLO,This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command."
|
|
bitfld.long 0x18 20.--21. "CMDSEL,Command Specific selection information. Not used in Master I2C. Used as CEn select for Master SPI transactions" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x18 8.--19. 1. "TSIZE,Defines the transaction size in bytes. The offset transfer is not included in this size."
|
|
bitfld.long 0x18 7. "CONT,Continue to hold the bus after the current transaction if set to a 1 with a new command issued." "0,1"
|
|
newline
|
|
bitfld.long 0x18 5.--6. "OFFSETCNT,Number of offset bytes to use for the command - 0 1 2 3 are valid selections. The second (byte 1) and third byte (byte 2) are read from the OFFSETHI register and the low order byte is pulled from this register in the OFFSETLO field." "0,1,2,3"
|
|
hexmask.long.byte 0x18 0.--4. 1. "CMD,Command for submodule."
|
|
line.long 0x1C "DCX,Enables use of CE signals to transmit DCX level for SPI transactions. Only used in Apollo3 Revision B. For Revision A. this register MUST NOT be programmed!"
|
|
bitfld.long 0x1C 4. "DCXEN,DCX Signaling Enable The selected DCX signal (unused CE pin) will be driven low during write of offset byte and high during transmission of data bytes." "0: Disable DCX.,1: Enable DCX."
|
|
bitfld.long 0x1C 3. "CE3OUT,Enable DCX output using CE3 output" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 2. "CE2OUT,Enable DCX output using CE2 output" "0,1"
|
|
bitfld.long 0x1C 1. "CE1OUT,Enable DCX output using CE1 output" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "CE0OUT,Enable DCX output using CE0 output" "0,1"
|
|
line.long 0x20 "OFFSETHI,High order 2 bytes of 3 byte offset for IO transaction"
|
|
hexmask.long.word 0x20 0.--15. 1. "OFFSETHI,Holds the high order 2 bytes of the 3 byte addressing/offset field to use with IO commands. The number of offset bytes to use is specified in the command register"
|
|
line.long 0x24 "CMDSTAT,Provides status on the execution of the command currently in progress. The fields in this register will reflect the real time status of the internal state machines and data transfers within the IOM."
|
|
hexmask.long.word 0x24 8.--19. 1. "CTSIZE,The current number of bytes still to be transferred with this command. This field will count down to zero."
|
|
bitfld.long 0x24 5.--7. "CMDSTAT,The current status of the command execution." "?,1: Error encountered with command,2: Actively processing command,?,4: Idle state no active command no error,?,6: Command in progress but waiting on data from host,?"
|
|
newline
|
|
hexmask.long.byte 0x24 0.--4. 1. "CCMD,current command that is being executed"
|
|
group.long 0x240++0x7
|
|
line.long 0x0 "DMATRIGEN,Provides control on which event will trigger the DMA transfer after the DMA operation is setup and enabled. The trigger event will cause a number of bytes (depending on trigger event) to be"
|
|
bitfld.long 0x0 1. "DTHREN,Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes) the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO and will transfer (WTHR/4) number of words" "0,1"
|
|
bitfld.long 0x0 0. "DCMDCMPEN,Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered the number of words transferred will be the lesser of the remaining TOTCOUNT bytes or" "0,1"
|
|
line.long 0x4 "DMATRIGSTAT,Provides the status of trigger events that have occurred for the transaction. Some of the bits are read only and some can be reset via a write of 0."
|
|
bitfld.long 0x4 2. "DTOTCMP,DMA triggered when DCMDCMP = 0 and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is" "0,1"
|
|
bitfld.long 0x4 1. "DTHR,Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DCMDCMP,Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA." "0,1"
|
|
group.long 0x280++0x3
|
|
line.long 0x0 "DMACFG,Configuration control of the DMA process. including the direction of DMA. and enablement of DMA"
|
|
bitfld.long 0x0 9. "DPWROFF,Power off module after DMA is complete. If this bit is active the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain power down will not be performed." "0: Power off disabled,1: Power off enabled"
|
|
bitfld.long 0x0 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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newline
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bitfld.long 0x0 1. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction. To be..,1: Memory to Peripheral transaction. To be set when.."
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bitfld.long 0x0 0. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable DMA Function,1: Enable DMA Function"
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group.long 0x288++0x2F
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line.long 0x0 "DMATOTCOUNT,Contains the number of bytes to be transferred for this DMA transaction. This register is decremented as the data is transferred. and will be 0 at the completion of the DMA operation."
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|
hexmask.long.word 0x0 0.--11. 1. "TOTCOUNT,Triggered DMA from Command complete event occurred. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."
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line.long 0x4 "DMATARGADDR,The source or destination address internal the SRAM for the DMA data. For write operations. this can only be SRAM data (ADDR bit 28 = 1); For read operations. this can be either SRAM or FLASH (ADDR bit 28 = 0)"
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bitfld.long 0x4 28. "TARGADDR28,Bit 28 of the target byte address for source of DMA (either read or write). In cases of non-word aligned addresses the DMA logic will take care for ensuring only the target bytes are read/written." "0,1"
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hexmask.long.tbyte 0x4 0.--20. 1. "TARGADDR,Bits [19:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment and does not have to be word aligned. In cases of non-word aligned addresses the DMA logic will take care for ensuring only.."
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line.long 0x8 "DMASTAT,Status of the DMA operation currently in progress."
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bitfld.long 0x8 2. "DMAERR,DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set this bit will remain set until cleared by software." "0,1"
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bitfld.long 0x8 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0 and will also be cleared when a new DMA is started." "0,1"
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newline
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bitfld.long 0x8 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
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line.long 0xC "CQCFG,Controls parameters and options for execution of the command queue operation. To enable command queue. create this in memory. set the address. and enable it with a write to CQEN"
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bitfld.long 0xC 2.--3. "MSPIFLGSEL,Selects the MPSI modules used for sourcing the CQFLAG [11:8]." "0: Selects MPSI0 as source of signals used in..,1: Selects MPSI1 as source of signals used in..,2: Selects MPSI2 as source of signals used in..,?"
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bitfld.long 0xC 1. "CQPRI,Sets the Priority of the command queue DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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newline
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bitfld.long 0xC 0. "CQEN,Command queue enable. When set will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled using a CQ executed write to this bit as well." "0: Disable CQ Function,1: Enable CQ Function"
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line.long 0x10 "CQADDR,The SRAM address which will be fetched next execution of the CQ operation. This register is updated as the CQ operation progresses. and is the live version of the register. The register can also be written by the Command Queue operation itself..."
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bitfld.long 0x10 28. "CQADDR28,Bit 28 of target byte address for source of CQ. Used to denote Flash (0) or SRAM (1) access" "0,1"
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hexmask.long.tbyte 0x10 2.--20. 1. "CQADDR,Bits 19:2 of target byte address for source of CQ. The buffer must be aligned on a word boundary"
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line.long 0x14 "CQSTAT,Provides the status of the command queue operation. If the command queue is disabled. these bits will be cleared. The bits are read only"
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bitfld.long 0x14 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
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bitfld.long 0x14 1. "CQPAUSED,Command queue operation is currently paused." "0,1"
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newline
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bitfld.long 0x14 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
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line.long 0x18 "CQFLAGS,Command Queue Flag"
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hexmask.long.word 0x18 16.--31. 1. "CQIRQMASK,Mask the bits used to generate the command queue interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE"
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hexmask.long.word 0x18 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
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line.long 0x1C "CQSETCLEAR,Set/Clear the command queue software pause flags on a per-bit basis. Contains 3 fields. allowing for setting. clearing or toggling the value in the software flags. Priority when the same bit"
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hexmask.long.byte 0x1C 16.--23. 1. "CQFCLR,Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x1C 8.--15. 1. "CQFTGL,Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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newline
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hexmask.long.byte 0x1C 0.--7. 1. "CQFSET,Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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line.long 0x20 "CQPAUSEEN,Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the CQFLAG register is '1'. CQ processing will halt until either value is changed to '0'."
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hexmask.long.word 0x20 0.--15. 1. "CQPEN,Enables the specified event to pause command processing when active"
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line.long 0x24 "CQCURIDX,Current index value. targeted to be written by register write operations within the command queue. This is compared to the CQENDIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and"
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hexmask.long.byte 0x24 0.--7. 1. "CQCURIDX,Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x28 "CQENDIDX,End index value. targeted to be written by software to indicate the last valid register pair contained within the command queue for a register write operations within the command queue."
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hexmask.long.byte 0x28 0.--7. 1. "CQENDIDX,Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x2C "STATUS,IOM Module Status"
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bitfld.long 0x2C 2. "IDLEST,indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to hold-offs from data availability or as the command gets propagated into the logic from the registers." "?,1: The I/O state machine is in the idle state."
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bitfld.long 0x2C 1. "CMDACT,Indicates if the active I/O Command is currently processing a transaction or command is complete but the FIFO pointers are still synchronizing internally. This bit will go high at" "?,1: An I/O command is active. Indicates the active.."
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newline
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bitfld.long 0x2C 0. "ERR,Bit has been deprecated. Please refer to the other error indicators. This will always return 0." "?,1: Bit has been deprecated and will always return 0."
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group.long 0x300++0x3
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line.long 0x0 "MSPICFG,Controls the configuration of the SPI master module. including POL/PHA. LSB. flow control. and delays for MISO and MOSI"
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bitfld.long 0x0 30. "MSPIRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 27.--29. "DOUTDLY,Delay tap to use for the output signal (MOSI). This give more hold time on the output data" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x0 24.--26. "DINDLY,Delay tap to use for the input signal (MISO). This gives more hold time on the input data." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "SPILSB,Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first." "0: Send and receive MSB bit first,1: Send and receive LSB bit first"
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newline
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bitfld.long 0x0 22. "RDFCPOL,selects the read flow control signal polarity." "0: Flow control signal high creates flow control.,1: Flow control signal low creates flow control."
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bitfld.long 0x0 21. "WTFCPOL,selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 will allow a IRQ=1 to pause transfers)." "0: Flow control signal high(1) creates flow control..,1: Flow control signal low(0) creates flow control.."
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newline
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bitfld.long 0x0 20. "WTFCIRQ,selects the write mode flow control signal." "0: MISO is used as the write mode flow control..,1: IRQ is used as the write mode flow control signal."
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bitfld.long 0x0 18. "MOSIINV,inverts MOSI when flow control is enabled." "0: MOSI is set to 0 in read mode and 1 in write mode.,1: MOSI is set to 1 in read mode and 0 in write mode."
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newline
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bitfld.long 0x0 17. "RDFC,enables read mode flow control." "0: Read mode flow control disabled.,1: Read mode flow control enabled."
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bitfld.long 0x0 16. "WTFC,enables write mode flow control." "0: Write mode flow control disabled.,1: Write mode flow control enabled."
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newline
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bitfld.long 0x0 2. "FULLDUP,Enables full duplex mode for Master SPI write operations. Data will be captured simultaneously into the read FIFO" "0,1"
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bitfld.long 0x0 1. "SPHA,selects SPI phase." "0: Sample on the leading (first) clock edge.,1: Sample on the trailing (second) clock edge."
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newline
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bitfld.long 0x0 0. "SPOL,selects SPI polarity." "0: The base value of the clock is 0.,1: The base value of the clock is 1."
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group.long 0x400++0x7
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line.long 0x0 "MI2CCFG,Controls the configuration of the I2C bus master."
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bitfld.long 0x0 24. "STRDIS,Disable detection of clock stretch events smaller than 1 cycle" "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "SMPCNT,Number of Base clock cycles to wait before sampling the SCL clock to determine if a clock stretch event has occurred"
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newline
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hexmask.long.byte 0x0 12.--15. 1. "SDAENDLY,Number of IOCLK cycles to delay the SDA output en (all transitions affected). Used to delay data relative to clock"
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hexmask.long.byte 0x0 8.--11. 1. "SCLENDLY,Number of IOCLK cycles to delay the rising edge of the SCL output en (clock will go low on this edge). Used to allow clock shaping."
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newline
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bitfld.long 0x0 6. "MI2CRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 4.--5. "SDADLY,Delay to enable on the SDA output. Values are 0x0-0x3." "0,1,2,3"
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newline
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bitfld.long 0x0 2. "ARBEN,Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master this function can be disabled to save clock cycles on I2C transactions" "0: Disable multi-master bus arbitration support for..,1: Enable multi-master bus arbitration support for.."
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bitfld.long 0x0 1. "I2CLSB,Direction of data transmit and receive MSB(0) or LSB(1) first. Default per I2C specification is MSB first. This applies to both read and write data and read data will be bit" "0: Byte data is transmitted MSB first onto the..,1: Byte data is transmitted LSB first onto the.."
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newline
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bitfld.long 0x0 0. "ADDRSZ,Sets the I2C master device address size to either 7 bits (0) or 10 bits (1)." "0: Use 7-bit addressing for I2C master transactions,1: Use 10-bit addressing for I2C master transactions"
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line.long 0x4 "DEVCFG,Contains the I2C device address."
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hexmask.long.word 0x4 0.--9. 1. "DEVADDR,I2C address of the device that the Master will use to target for read/write operations. This can be either a 7-bit or 10-bit address."
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group.long 0x410++0x3
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line.long 0x0 "IOMDBG,Debug control"
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hexmask.long 0x0 3.--31. 1. "DBGDATA,Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers."
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bitfld.long 0x0 2. "APBCLKON,APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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newline
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bitfld.long 0x0 1. "IOCLKON,IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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bitfld.long 0x0 0. "DBGEN,Debug Enable. Setting bit will enable the update of data within this register otherwise it is clock gated for power savings" "0,1"
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tree.end
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endif
|
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sif (cpuis("AMA3B2KK"))
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tree "IOM1"
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base ad:0x50005000
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group.long 0x0++0x3
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line.long 0x0 "FIFO,Provides direct random access to both output and input FIFOs. The state of the FIFO is not disturbed by reading these locations (i.e.. no POP will be done). FIFO0 is accessible from addresses 0x0 - 0x1C. and is used for data output from the IOM to.."
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hexmask.long 0x0 0.--31. 1. "FIFO,FIFO direct access. Only locations 0 - 3F will return valid information."
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group.long 0x100++0x17
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line.long 0x0 "FIFOPTR,Provides the current valid byte count of data within the FIFO as seen from the internal state machines. FIFO0 is dedicated to outgoing transactions and FIFO1 is dedicated to incoming transactions. All counts are specified in units of bytes."
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hexmask.long.byte 0x0 24.--31. 1. "FIFO1REM,The number of remaining data bytes slots currently in FIFO 1 (written by interface read by MCU)"
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hexmask.long.byte 0x0 16.--23. 1. "FIFO1SIZ,The number of valid data bytes currently in FIFO 1 (written by interface read by MCU)"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "FIFO0REM,The number of remaining data bytes slots currently in FIFO 0 (written by MCU read by interface)"
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hexmask.long.byte 0x0 0.--7. 1. "FIFO0SIZ,The number of valid data bytes currently in the FIFO 0 (written by MCU read by interface)"
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line.long 0x4 "FIFOTHR,Sets the threshold values for incoming and outgoing transactions. The threshold values are used to assert the interrupt if enabled. and also used during DMA to set the transfer size as a result of DMATHR trigger."
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hexmask.long.byte 0x4 8.--13. 1. "FIFOWTHR,FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the write FIFO contains FIFOWTHR free bytes as.."
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hexmask.long.byte 0x4 0.--5. 1. "FIFORTHR,FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the read FIFO contains FIFORTHR valid bytes of data as.."
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line.long 0x8 "FIFOPOP,Will advance the internal read pointer of the incoming FIFO (FIFO1) when read. if POPWR is not active. If POPWR is active. a write to this register is needed to advance the internal FIFO pointer."
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hexmask.long 0x8 0.--31. 1. "FIFODOUT,This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0) the FIFO read pointer will be advanced by one word as a result of the read."
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line.long 0xC "FIFOPUSH,Will write new data into the outgoing FIFO and advance the internal write pointer."
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hexmask.long 0xC 0.--31. 1. "FIFODIN,This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes)."
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line.long 0x10 "FIFOCTRL,Provides controls for the operation of the internal FIFOs. Contains fields used to control the operation of the POP register. and also controls to reset the internal pointers of the FIFOs."
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bitfld.long 0x10 1. "FIFORSTN,Active low manual reset of the FIFO. Write to 0 to reset FIFO and then write to 1 to remove the reset." "0,1"
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bitfld.long 0x10 0. "POPWR,Selects the mode in which 'pop' events are done for the FIFO read operations. A value of '1' will prevent a pop event on a read operation and will require a write to the FIFOPOP register to create a pop event." "0,1"
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line.long 0x14 "FIFOLOC,Provides a read only value of the current read and write pointers. This register is read only and can be used along with the FIFO direct access method to determine the next data to be used for input and output functions."
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hexmask.long.byte 0x14 8.--11. 1. "FIFORPTR,Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1) which is used to store read data returned from external devices during a read operation."
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hexmask.long.byte 0x14 0.--3. 1. "FIFOWPTR,Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0) which is used during write operations to external devices."
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group.long 0x200++0x27
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line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
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bitfld.long 0x0 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x0 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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newline
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bitfld.long 0x0 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x0 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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newline
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bitfld.long 0x0 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x0 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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newline
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bitfld.long 0x0 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x0 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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newline
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bitfld.long 0x0 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x0 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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newline
|
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bitfld.long 0x0 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x0 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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newline
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bitfld.long 0x0 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
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bitfld.long 0x0 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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newline
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bitfld.long 0x0 0. "CMDCMP,Command complete interrupt" "0,1"
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line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
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bitfld.long 0x4 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x4 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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newline
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bitfld.long 0x4 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x4 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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newline
|
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bitfld.long 0x4 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0x4 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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|
newline
|
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bitfld.long 0x4 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x4 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x4 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0x4 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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|
newline
|
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bitfld.long 0x4 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
|
|
bitfld.long 0x4 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "CMDCMP,Command complete interrupt" "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x8 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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newline
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bitfld.long 0x8 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x8 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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|
newline
|
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bitfld.long 0x8 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0x8 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
|
|
newline
|
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bitfld.long 0x8 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x8 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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newline
|
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bitfld.long 0x8 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
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bitfld.long 0x8 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x8 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x8 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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bitfld.long 0x8 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
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bitfld.long 0x8 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x8 0. "CMDCMP,Command complete interrupt" "0,1"
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|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
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bitfld.long 0xC 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0xC 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0xC 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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|
bitfld.long 0xC 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0xC 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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|
bitfld.long 0xC 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0xC 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0xC 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0xC 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0xC 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0xC 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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|
bitfld.long 0xC 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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|
newline
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bitfld.long 0xC 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
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bitfld.long 0xC 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0xC 0. "CMDCMP,Command complete interrupt" "0,1"
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|
line.long 0x10 "CLKCFG,Provides clock related controls used internal to the BLEIF module. and enablement of 32KHz clock to the BLE Core module. The internal clock sourced is selected via the FSEL and can be further divided by 3 using the DIV3 control."
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hexmask.long.byte 0x10 24.--31. 1. "TOTPER,Clock total clock count minus 1. This provides the total period of the divided clock -1 when the DIVEN is active. The"
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hexmask.long.byte 0x10 16.--23. 1. "LOWPER,Clock low clock count minus 1. This provides the number of clocks the divided clock will be low when the DIVEN = 1."
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newline
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bitfld.long 0x10 12. "DIVEN,Enable clock division by TOTPER and LOWPER" "0: Disable TOTPER division.,1: Enable TOTPER division."
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bitfld.long 0x10 11. "DIV3,Enable divide by 3 of the source IOCLK. Division by 3 is done before the DIVEN programmable divider and if enabled" "0: Select divide by 1.,1: Select divide by 3."
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bitfld.long 0x10 8.--10. "FSEL,Select the input clock frequency." "0: Selects the minimum power clock. This setting..,1: Selects the HFRC as the input clock.,2: Selects the HFRC / 2 as the input clock.,3: Selects the HFRC / 4 as the input clock.,4: Selects the HFRC / 8 as the input clock.,5: Selects the HFRC / 16 as the input clock.,6: Selects the HFRC / 32 as the input clock.,7: Selects the HFRC / 64 as the input clock."
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bitfld.long 0x10 0. "IOCLKEN,Enable for the interface clock. Must be enabled prior to executing any IO operations." "0,1"
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line.long 0x14 "SUBMODCTRL,Provides enable for each submodule. Only a single submodule can be enabled at one time."
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bitfld.long 0x14 5.--7. "SMOD1TYPE,Submodule 0 module type. This is the I2C Master interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,?,?,?,7: NOT INSTALLED"
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bitfld.long 0x14 4. "SMOD1EN,Submodule 1 enable (1) or disable (0)" "0,1"
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bitfld.long 0x14 1.--3. "SMOD0TYPE,Submodule 0 module type. This is the SPI Master interface." "0: MSPI submodule,1: I2C Master submodule,2: SPI Slave submodule,3: I2C Slave submodule,?,?,?,7: NOT INSTALLED"
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bitfld.long 0x14 0. "SMOD0EN,Submodule 0 enable (1) or disable (0)" "0,1"
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line.long 0x18 "CMD,Writes to this register will start an IO transaction. as well as set various parameters for the command itself. Reads will return the command value written to the CMD register."
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hexmask.long.byte 0x18 24.--31. 1. "OFFSETLO,This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command."
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bitfld.long 0x18 20.--21. "CMDSEL,Command Specific selection information. Not used in Master I2C. Used as CEn select for Master SPI transactions" "0,1,2,3"
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hexmask.long.word 0x18 8.--19. 1. "TSIZE,Defines the transaction size in bytes. The offset transfer is not included in this size."
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bitfld.long 0x18 7. "CONT,Continue to hold the bus after the current transaction if set to a 1 with a new command issued." "0,1"
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bitfld.long 0x18 5.--6. "OFFSETCNT,Number of offset bytes to use for the command - 0 1 2 3 are valid selections. The second (byte 1) and third byte (byte 2) are read from the OFFSETHI register and the low order byte is pulled from this register in the OFFSETLO field." "0,1,2,3"
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hexmask.long.byte 0x18 0.--4. 1. "CMD,Command for submodule."
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line.long 0x1C "DCX,Enables use of CE signals to transmit DCX level for SPI transactions. Only used in Apollo3 Revision B. For Revision A. this register MUST NOT be programmed!"
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bitfld.long 0x1C 4. "DCXEN,DCX Signaling Enable The selected DCX signal (unused CE pin) will be driven low during write of offset byte and high during transmission of data bytes." "0: Disable DCX.,1: Enable DCX."
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bitfld.long 0x1C 3. "CE3OUT,Enable DCX output using CE3 output" "0,1"
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bitfld.long 0x1C 2. "CE2OUT,Enable DCX output using CE2 output" "0,1"
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bitfld.long 0x1C 1. "CE1OUT,Enable DCX output using CE1 output" "0,1"
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bitfld.long 0x1C 0. "CE0OUT,Enable DCX output using CE0 output" "0,1"
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line.long 0x20 "OFFSETHI,High order 2 bytes of 3 byte offset for IO transaction"
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hexmask.long.word 0x20 0.--15. 1. "OFFSETHI,Holds the high order 2 bytes of the 3 byte addressing/offset field to use with IO commands. The number of offset bytes to use is specified in the command register"
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line.long 0x24 "CMDSTAT,Provides status on the execution of the command currently in progress. The fields in this register will reflect the real time status of the internal state machines and data transfers within the IOM."
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hexmask.long.word 0x24 8.--19. 1. "CTSIZE,The current number of bytes still to be transferred with this command. This field will count down to zero."
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bitfld.long 0x24 5.--7. "CMDSTAT,The current status of the command execution." "?,1: Error encountered with command,2: Actively processing command,?,4: Idle state no active command no error,?,6: Command in progress but waiting on data from host,?"
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hexmask.long.byte 0x24 0.--4. 1. "CCMD,current command that is being executed"
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|
group.long 0x240++0x7
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line.long 0x0 "DMATRIGEN,Provides control on which event will trigger the DMA transfer after the DMA operation is setup and enabled. The trigger event will cause a number of bytes (depending on trigger event) to be"
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bitfld.long 0x0 1. "DTHREN,Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes) the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO and will transfer (WTHR/4) number of words" "0,1"
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bitfld.long 0x0 0. "DCMDCMPEN,Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered the number of words transferred will be the lesser of the remaining TOTCOUNT bytes or" "0,1"
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line.long 0x4 "DMATRIGSTAT,Provides the status of trigger events that have occurred for the transaction. Some of the bits are read only and some can be reset via a write of 0."
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bitfld.long 0x4 2. "DTOTCMP,DMA triggered when DCMDCMP = 0 and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is" "0,1"
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bitfld.long 0x4 1. "DTHR,Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA." "0,1"
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bitfld.long 0x4 0. "DCMDCMP,Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA." "0,1"
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group.long 0x280++0x3
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line.long 0x0 "DMACFG,Configuration control of the DMA process. including the direction of DMA. and enablement of DMA"
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bitfld.long 0x0 9. "DPWROFF,Power off module after DMA is complete. If this bit is active the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain power down will not be performed." "0: Power off disabled,1: Power off enabled"
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bitfld.long 0x0 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x0 1. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction. To be..,1: Memory to Peripheral transaction. To be set when.."
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bitfld.long 0x0 0. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable DMA Function,1: Enable DMA Function"
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group.long 0x288++0x2F
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line.long 0x0 "DMATOTCOUNT,Contains the number of bytes to be transferred for this DMA transaction. This register is decremented as the data is transferred. and will be 0 at the completion of the DMA operation."
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hexmask.long.word 0x0 0.--11. 1. "TOTCOUNT,Triggered DMA from Command complete event occurred. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."
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line.long 0x4 "DMATARGADDR,The source or destination address internal the SRAM for the DMA data. For write operations. this can only be SRAM data (ADDR bit 28 = 1); For read operations. this can be either SRAM or FLASH (ADDR bit 28 = 0)"
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bitfld.long 0x4 28. "TARGADDR28,Bit 28 of the target byte address for source of DMA (either read or write). In cases of non-word aligned addresses the DMA logic will take care for ensuring only the target bytes are read/written." "0,1"
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hexmask.long.tbyte 0x4 0.--20. 1. "TARGADDR,Bits [19:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment and does not have to be word aligned. In cases of non-word aligned addresses the DMA logic will take care for ensuring only.."
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line.long 0x8 "DMASTAT,Status of the DMA operation currently in progress."
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bitfld.long 0x8 2. "DMAERR,DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set this bit will remain set until cleared by software." "0,1"
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bitfld.long 0x8 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0 and will also be cleared when a new DMA is started." "0,1"
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bitfld.long 0x8 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
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line.long 0xC "CQCFG,Controls parameters and options for execution of the command queue operation. To enable command queue. create this in memory. set the address. and enable it with a write to CQEN"
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bitfld.long 0xC 2.--3. "MSPIFLGSEL,Selects the MPSI modules used for sourcing the CQFLAG [11:8]." "0: Selects MPSI0 as source of signals used in..,1: Selects MPSI1 as source of signals used in..,2: Selects MPSI2 as source of signals used in..,?"
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bitfld.long 0xC 1. "CQPRI,Sets the Priority of the command queue DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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newline
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bitfld.long 0xC 0. "CQEN,Command queue enable. When set will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled using a CQ executed write to this bit as well." "0: Disable CQ Function,1: Enable CQ Function"
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line.long 0x10 "CQADDR,The SRAM address which will be fetched next execution of the CQ operation. This register is updated as the CQ operation progresses. and is the live version of the register. The register can also be written by the Command Queue operation itself..."
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bitfld.long 0x10 28. "CQADDR28,Bit 28 of target byte address for source of CQ. Used to denote Flash (0) or SRAM (1) access" "0,1"
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hexmask.long.tbyte 0x10 2.--20. 1. "CQADDR,Bits 19:2 of target byte address for source of CQ. The buffer must be aligned on a word boundary"
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line.long 0x14 "CQSTAT,Provides the status of the command queue operation. If the command queue is disabled. these bits will be cleared. The bits are read only"
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bitfld.long 0x14 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
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bitfld.long 0x14 1. "CQPAUSED,Command queue operation is currently paused." "0,1"
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bitfld.long 0x14 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
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line.long 0x18 "CQFLAGS,Command Queue Flag"
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hexmask.long.word 0x18 16.--31. 1. "CQIRQMASK,Mask the bits used to generate the command queue interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE"
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hexmask.long.word 0x18 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
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line.long 0x1C "CQSETCLEAR,Set/Clear the command queue software pause flags on a per-bit basis. Contains 3 fields. allowing for setting. clearing or toggling the value in the software flags. Priority when the same bit"
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hexmask.long.byte 0x1C 16.--23. 1. "CQFCLR,Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x1C 8.--15. 1. "CQFTGL,Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x1C 0.--7. 1. "CQFSET,Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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line.long 0x20 "CQPAUSEEN,Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the CQFLAG register is '1'. CQ processing will halt until either value is changed to '0'."
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hexmask.long.word 0x20 0.--15. 1. "CQPEN,Enables the specified event to pause command processing when active"
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line.long 0x24 "CQCURIDX,Current index value. targeted to be written by register write operations within the command queue. This is compared to the CQENDIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and"
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|
hexmask.long.byte 0x24 0.--7. 1. "CQCURIDX,Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x28 "CQENDIDX,End index value. targeted to be written by software to indicate the last valid register pair contained within the command queue for a register write operations within the command queue."
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hexmask.long.byte 0x28 0.--7. 1. "CQENDIDX,Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x2C "STATUS,IOM Module Status"
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bitfld.long 0x2C 2. "IDLEST,indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to hold-offs from data availability or as the command gets propagated into the logic from the registers." "?,1: The I/O state machine is in the idle state."
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bitfld.long 0x2C 1. "CMDACT,Indicates if the active I/O Command is currently processing a transaction or command is complete but the FIFO pointers are still synchronizing internally. This bit will go high at" "?,1: An I/O command is active. Indicates the active.."
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bitfld.long 0x2C 0. "ERR,Bit has been deprecated. Please refer to the other error indicators. This will always return 0." "?,1: Bit has been deprecated and will always return 0."
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group.long 0x300++0x3
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line.long 0x0 "MSPICFG,Controls the configuration of the SPI master module. including POL/PHA. LSB. flow control. and delays for MISO and MOSI"
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bitfld.long 0x0 30. "MSPIRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 27.--29. "DOUTDLY,Delay tap to use for the output signal (MOSI). This give more hold time on the output data" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 24.--26. "DINDLY,Delay tap to use for the input signal (MISO). This gives more hold time on the input data." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "SPILSB,Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first." "0: Send and receive MSB bit first,1: Send and receive LSB bit first"
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bitfld.long 0x0 22. "RDFCPOL,selects the read flow control signal polarity." "0: Flow control signal high creates flow control.,1: Flow control signal low creates flow control."
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bitfld.long 0x0 21. "WTFCPOL,selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 will allow a IRQ=1 to pause transfers)." "0: Flow control signal high(1) creates flow control..,1: Flow control signal low(0) creates flow control.."
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bitfld.long 0x0 20. "WTFCIRQ,selects the write mode flow control signal." "0: MISO is used as the write mode flow control..,1: IRQ is used as the write mode flow control signal."
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bitfld.long 0x0 18. "MOSIINV,inverts MOSI when flow control is enabled." "0: MOSI is set to 0 in read mode and 1 in write mode.,1: MOSI is set to 1 in read mode and 0 in write mode."
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newline
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bitfld.long 0x0 17. "RDFC,enables read mode flow control." "0: Read mode flow control disabled.,1: Read mode flow control enabled."
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bitfld.long 0x0 16. "WTFC,enables write mode flow control." "0: Write mode flow control disabled.,1: Write mode flow control enabled."
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bitfld.long 0x0 2. "FULLDUP,Enables full duplex mode for Master SPI write operations. Data will be captured simultaneously into the read FIFO" "0,1"
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|
bitfld.long 0x0 1. "SPHA,selects SPI phase." "0: Sample on the leading (first) clock edge.,1: Sample on the trailing (second) clock edge."
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newline
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bitfld.long 0x0 0. "SPOL,selects SPI polarity." "0: The base value of the clock is 0.,1: The base value of the clock is 1."
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group.long 0x400++0x7
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line.long 0x0 "MI2CCFG,Controls the configuration of the I2C bus master."
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bitfld.long 0x0 24. "STRDIS,Disable detection of clock stretch events smaller than 1 cycle" "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "SMPCNT,Number of Base clock cycles to wait before sampling the SCL clock to determine if a clock stretch event has occurred"
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hexmask.long.byte 0x0 12.--15. 1. "SDAENDLY,Number of IOCLK cycles to delay the SDA output en (all transitions affected). Used to delay data relative to clock"
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|
hexmask.long.byte 0x0 8.--11. 1. "SCLENDLY,Number of IOCLK cycles to delay the rising edge of the SCL output en (clock will go low on this edge). Used to allow clock shaping."
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bitfld.long 0x0 6. "MI2CRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 4.--5. "SDADLY,Delay to enable on the SDA output. Values are 0x0-0x3." "0,1,2,3"
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bitfld.long 0x0 2. "ARBEN,Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master this function can be disabled to save clock cycles on I2C transactions" "0: Disable multi-master bus arbitration support for..,1: Enable multi-master bus arbitration support for.."
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|
bitfld.long 0x0 1. "I2CLSB,Direction of data transmit and receive MSB(0) or LSB(1) first. Default per I2C specification is MSB first. This applies to both read and write data and read data will be bit" "0: Byte data is transmitted MSB first onto the..,1: Byte data is transmitted LSB first onto the.."
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newline
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bitfld.long 0x0 0. "ADDRSZ,Sets the I2C master device address size to either 7 bits (0) or 10 bits (1)." "0: Use 7-bit addressing for I2C master transactions,1: Use 10-bit addressing for I2C master transactions"
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line.long 0x4 "DEVCFG,Contains the I2C device address."
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hexmask.long.word 0x4 0.--9. 1. "DEVADDR,I2C address of the device that the Master will use to target for read/write operations. This can be either a 7-bit or 10-bit address."
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group.long 0x410++0x3
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line.long 0x0 "IOMDBG,Debug control"
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|
hexmask.long 0x0 3.--31. 1. "DBGDATA,Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers."
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bitfld.long 0x0 2. "APBCLKON,APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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newline
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bitfld.long 0x0 1. "IOCLKON,IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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bitfld.long 0x0 0. "DBGEN,Debug Enable. Setting bit will enable the update of data within this register otherwise it is clock gated for power savings" "0,1"
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tree.end
|
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endif
|
|
sif (cpuis("AMA3B2KK"))
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|
tree "IOM2"
|
|
base ad:0x50006000
|
|
group.long 0x0++0x3
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line.long 0x0 "FIFO,Provides direct random access to both output and input FIFOs. The state of the FIFO is not disturbed by reading these locations (i.e.. no POP will be done). FIFO0 is accessible from addresses 0x0 - 0x1C. and is used for data output from the IOM to.."
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hexmask.long 0x0 0.--31. 1. "FIFO,FIFO direct access. Only locations 0 - 3F will return valid information."
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group.long 0x100++0x17
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line.long 0x0 "FIFOPTR,Provides the current valid byte count of data within the FIFO as seen from the internal state machines. FIFO0 is dedicated to outgoing transactions and FIFO1 is dedicated to incoming transactions. All counts are specified in units of bytes."
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hexmask.long.byte 0x0 24.--31. 1. "FIFO1REM,The number of remaining data bytes slots currently in FIFO 1 (written by interface read by MCU)"
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hexmask.long.byte 0x0 16.--23. 1. "FIFO1SIZ,The number of valid data bytes currently in FIFO 1 (written by interface read by MCU)"
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hexmask.long.byte 0x0 8.--15. 1. "FIFO0REM,The number of remaining data bytes slots currently in FIFO 0 (written by MCU read by interface)"
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hexmask.long.byte 0x0 0.--7. 1. "FIFO0SIZ,The number of valid data bytes currently in the FIFO 0 (written by MCU read by interface)"
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line.long 0x4 "FIFOTHR,Sets the threshold values for incoming and outgoing transactions. The threshold values are used to assert the interrupt if enabled. and also used during DMA to set the transfer size as a result of DMATHR trigger."
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hexmask.long.byte 0x4 8.--13. 1. "FIFOWTHR,FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the write FIFO contains FIFOWTHR free bytes as.."
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hexmask.long.byte 0x4 0.--5. 1. "FIFORTHR,FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the read FIFO contains FIFORTHR valid bytes of data as.."
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line.long 0x8 "FIFOPOP,Will advance the internal read pointer of the incoming FIFO (FIFO1) when read. if POPWR is not active. If POPWR is active. a write to this register is needed to advance the internal FIFO pointer."
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hexmask.long 0x8 0.--31. 1. "FIFODOUT,This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0) the FIFO read pointer will be advanced by one word as a result of the read."
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line.long 0xC "FIFOPUSH,Will write new data into the outgoing FIFO and advance the internal write pointer."
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hexmask.long 0xC 0.--31. 1. "FIFODIN,This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes)."
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line.long 0x10 "FIFOCTRL,Provides controls for the operation of the internal FIFOs. Contains fields used to control the operation of the POP register. and also controls to reset the internal pointers of the FIFOs."
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bitfld.long 0x10 1. "FIFORSTN,Active low manual reset of the FIFO. Write to 0 to reset FIFO and then write to 1 to remove the reset." "0,1"
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bitfld.long 0x10 0. "POPWR,Selects the mode in which 'pop' events are done for the FIFO read operations. A value of '1' will prevent a pop event on a read operation and will require a write to the FIFOPOP register to create a pop event." "0,1"
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line.long 0x14 "FIFOLOC,Provides a read only value of the current read and write pointers. This register is read only and can be used along with the FIFO direct access method to determine the next data to be used for input and output functions."
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hexmask.long.byte 0x14 8.--11. 1. "FIFORPTR,Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1) which is used to store read data returned from external devices during a read operation."
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hexmask.long.byte 0x14 0.--3. 1. "FIFOWPTR,Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0) which is used during write operations to external devices."
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group.long 0x200++0x27
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line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
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bitfld.long 0x0 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x0 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x0 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x0 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x0 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x0 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0x0 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x0 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x0 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x0 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x0 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x0 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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bitfld.long 0x0 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
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bitfld.long 0x0 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x0 0. "CMDCMP,Command complete interrupt" "0,1"
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line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
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bitfld.long 0x4 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x4 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x4 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x4 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x4 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x4 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0x4 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x4 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x4 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x4 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x4 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x4 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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bitfld.long 0x4 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
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bitfld.long 0x4 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x4 0. "CMDCMP,Command complete interrupt" "0,1"
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line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
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bitfld.long 0x8 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x8 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x8 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x8 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x8 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x8 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0x8 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x8 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x8 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x8 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x8 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x8 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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bitfld.long 0x8 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
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bitfld.long 0x8 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x8 0. "CMDCMP,Command complete interrupt" "0,1"
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line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
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bitfld.long 0xC 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0xC 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0xC 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0xC 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0xC 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0xC 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0xC 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0xC 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0xC 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0xC 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0xC 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0xC 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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bitfld.long 0xC 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
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bitfld.long 0xC 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0xC 0. "CMDCMP,Command complete interrupt" "0,1"
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line.long 0x10 "CLKCFG,Provides clock related controls used internal to the BLEIF module. and enablement of 32KHz clock to the BLE Core module. The internal clock sourced is selected via the FSEL and can be further divided by 3 using the DIV3 control."
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hexmask.long.byte 0x10 24.--31. 1. "TOTPER,Clock total clock count minus 1. This provides the total period of the divided clock -1 when the DIVEN is active. The"
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hexmask.long.byte 0x10 16.--23. 1. "LOWPER,Clock low clock count minus 1. This provides the number of clocks the divided clock will be low when the DIVEN = 1."
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bitfld.long 0x10 12. "DIVEN,Enable clock division by TOTPER and LOWPER" "0: Disable TOTPER division.,1: Enable TOTPER division."
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bitfld.long 0x10 11. "DIV3,Enable divide by 3 of the source IOCLK. Division by 3 is done before the DIVEN programmable divider and if enabled" "0: Select divide by 1.,1: Select divide by 3."
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bitfld.long 0x10 8.--10. "FSEL,Select the input clock frequency." "0: Selects the minimum power clock. This setting..,1: Selects the HFRC as the input clock.,2: Selects the HFRC / 2 as the input clock.,3: Selects the HFRC / 4 as the input clock.,4: Selects the HFRC / 8 as the input clock.,5: Selects the HFRC / 16 as the input clock.,6: Selects the HFRC / 32 as the input clock.,7: Selects the HFRC / 64 as the input clock."
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bitfld.long 0x10 0. "IOCLKEN,Enable for the interface clock. Must be enabled prior to executing any IO operations." "0,1"
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line.long 0x14 "SUBMODCTRL,Provides enable for each submodule. Only a single submodule can be enabled at one time."
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bitfld.long 0x14 5.--7. "SMOD1TYPE,Submodule 0 module type. This is the I2C Master interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,?,?,?,7: NOT INSTALLED"
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bitfld.long 0x14 4. "SMOD1EN,Submodule 1 enable (1) or disable (0)" "0,1"
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bitfld.long 0x14 1.--3. "SMOD0TYPE,Submodule 0 module type. This is the SPI Master interface." "0: MSPI submodule,1: I2C Master submodule,2: SPI Slave submodule,3: I2C Slave submodule,?,?,?,7: NOT INSTALLED"
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bitfld.long 0x14 0. "SMOD0EN,Submodule 0 enable (1) or disable (0)" "0,1"
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line.long 0x18 "CMD,Writes to this register will start an IO transaction. as well as set various parameters for the command itself. Reads will return the command value written to the CMD register."
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hexmask.long.byte 0x18 24.--31. 1. "OFFSETLO,This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command."
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bitfld.long 0x18 20.--21. "CMDSEL,Command Specific selection information. Not used in Master I2C. Used as CEn select for Master SPI transactions" "0,1,2,3"
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hexmask.long.word 0x18 8.--19. 1. "TSIZE,Defines the transaction size in bytes. The offset transfer is not included in this size."
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bitfld.long 0x18 7. "CONT,Continue to hold the bus after the current transaction if set to a 1 with a new command issued." "0,1"
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bitfld.long 0x18 5.--6. "OFFSETCNT,Number of offset bytes to use for the command - 0 1 2 3 are valid selections. The second (byte 1) and third byte (byte 2) are read from the OFFSETHI register and the low order byte is pulled from this register in the OFFSETLO field." "0,1,2,3"
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hexmask.long.byte 0x18 0.--4. 1. "CMD,Command for submodule."
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line.long 0x1C "DCX,Enables use of CE signals to transmit DCX level for SPI transactions. Only used in Apollo3 Revision B. For Revision A. this register MUST NOT be programmed!"
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bitfld.long 0x1C 4. "DCXEN,DCX Signaling Enable The selected DCX signal (unused CE pin) will be driven low during write of offset byte and high during transmission of data bytes." "0: Disable DCX.,1: Enable DCX."
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bitfld.long 0x1C 3. "CE3OUT,Enable DCX output using CE3 output" "0,1"
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bitfld.long 0x1C 2. "CE2OUT,Enable DCX output using CE2 output" "0,1"
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bitfld.long 0x1C 1. "CE1OUT,Enable DCX output using CE1 output" "0,1"
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bitfld.long 0x1C 0. "CE0OUT,Enable DCX output using CE0 output" "0,1"
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line.long 0x20 "OFFSETHI,High order 2 bytes of 3 byte offset for IO transaction"
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hexmask.long.word 0x20 0.--15. 1. "OFFSETHI,Holds the high order 2 bytes of the 3 byte addressing/offset field to use with IO commands. The number of offset bytes to use is specified in the command register"
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line.long 0x24 "CMDSTAT,Provides status on the execution of the command currently in progress. The fields in this register will reflect the real time status of the internal state machines and data transfers within the IOM."
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hexmask.long.word 0x24 8.--19. 1. "CTSIZE,The current number of bytes still to be transferred with this command. This field will count down to zero."
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bitfld.long 0x24 5.--7. "CMDSTAT,The current status of the command execution." "?,1: Error encountered with command,2: Actively processing command,?,4: Idle state no active command no error,?,6: Command in progress but waiting on data from host,?"
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newline
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hexmask.long.byte 0x24 0.--4. 1. "CCMD,current command that is being executed"
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group.long 0x240++0x7
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line.long 0x0 "DMATRIGEN,Provides control on which event will trigger the DMA transfer after the DMA operation is setup and enabled. The trigger event will cause a number of bytes (depending on trigger event) to be"
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bitfld.long 0x0 1. "DTHREN,Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes) the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO and will transfer (WTHR/4) number of words" "0,1"
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bitfld.long 0x0 0. "DCMDCMPEN,Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered the number of words transferred will be the lesser of the remaining TOTCOUNT bytes or" "0,1"
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line.long 0x4 "DMATRIGSTAT,Provides the status of trigger events that have occurred for the transaction. Some of the bits are read only and some can be reset via a write of 0."
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bitfld.long 0x4 2. "DTOTCMP,DMA triggered when DCMDCMP = 0 and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is" "0,1"
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bitfld.long 0x4 1. "DTHR,Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA." "0,1"
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bitfld.long 0x4 0. "DCMDCMP,Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA." "0,1"
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group.long 0x280++0x3
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line.long 0x0 "DMACFG,Configuration control of the DMA process. including the direction of DMA. and enablement of DMA"
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bitfld.long 0x0 9. "DPWROFF,Power off module after DMA is complete. If this bit is active the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain power down will not be performed." "0: Power off disabled,1: Power off enabled"
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bitfld.long 0x0 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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newline
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bitfld.long 0x0 1. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction. To be..,1: Memory to Peripheral transaction. To be set when.."
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bitfld.long 0x0 0. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable DMA Function,1: Enable DMA Function"
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group.long 0x288++0x2F
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line.long 0x0 "DMATOTCOUNT,Contains the number of bytes to be transferred for this DMA transaction. This register is decremented as the data is transferred. and will be 0 at the completion of the DMA operation."
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hexmask.long.word 0x0 0.--11. 1. "TOTCOUNT,Triggered DMA from Command complete event occurred. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."
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line.long 0x4 "DMATARGADDR,The source or destination address internal the SRAM for the DMA data. For write operations. this can only be SRAM data (ADDR bit 28 = 1); For read operations. this can be either SRAM or FLASH (ADDR bit 28 = 0)"
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bitfld.long 0x4 28. "TARGADDR28,Bit 28 of the target byte address for source of DMA (either read or write). In cases of non-word aligned addresses the DMA logic will take care for ensuring only the target bytes are read/written." "0,1"
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hexmask.long.tbyte 0x4 0.--20. 1. "TARGADDR,Bits [19:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment and does not have to be word aligned. In cases of non-word aligned addresses the DMA logic will take care for ensuring only.."
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line.long 0x8 "DMASTAT,Status of the DMA operation currently in progress."
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bitfld.long 0x8 2. "DMAERR,DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set this bit will remain set until cleared by software." "0,1"
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bitfld.long 0x8 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0 and will also be cleared when a new DMA is started." "0,1"
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bitfld.long 0x8 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
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line.long 0xC "CQCFG,Controls parameters and options for execution of the command queue operation. To enable command queue. create this in memory. set the address. and enable it with a write to CQEN"
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bitfld.long 0xC 2.--3. "MSPIFLGSEL,Selects the MPSI modules used for sourcing the CQFLAG [11:8]." "0: Selects MPSI0 as source of signals used in..,1: Selects MPSI1 as source of signals used in..,2: Selects MPSI2 as source of signals used in..,?"
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bitfld.long 0xC 1. "CQPRI,Sets the Priority of the command queue DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0xC 0. "CQEN,Command queue enable. When set will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled using a CQ executed write to this bit as well." "0: Disable CQ Function,1: Enable CQ Function"
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|
line.long 0x10 "CQADDR,The SRAM address which will be fetched next execution of the CQ operation. This register is updated as the CQ operation progresses. and is the live version of the register. The register can also be written by the Command Queue operation itself..."
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bitfld.long 0x10 28. "CQADDR28,Bit 28 of target byte address for source of CQ. Used to denote Flash (0) or SRAM (1) access" "0,1"
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|
hexmask.long.tbyte 0x10 2.--20. 1. "CQADDR,Bits 19:2 of target byte address for source of CQ. The buffer must be aligned on a word boundary"
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|
line.long 0x14 "CQSTAT,Provides the status of the command queue operation. If the command queue is disabled. these bits will be cleared. The bits are read only"
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|
bitfld.long 0x14 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
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|
bitfld.long 0x14 1. "CQPAUSED,Command queue operation is currently paused." "0,1"
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|
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bitfld.long 0x14 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
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|
line.long 0x18 "CQFLAGS,Command Queue Flag"
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hexmask.long.word 0x18 16.--31. 1. "CQIRQMASK,Mask the bits used to generate the command queue interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE"
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hexmask.long.word 0x18 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
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|
line.long 0x1C "CQSETCLEAR,Set/Clear the command queue software pause flags on a per-bit basis. Contains 3 fields. allowing for setting. clearing or toggling the value in the software flags. Priority when the same bit"
|
|
hexmask.long.byte 0x1C 16.--23. 1. "CQFCLR,Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field"
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|
hexmask.long.byte 0x1C 8.--15. 1. "CQFTGL,Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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|
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hexmask.long.byte 0x1C 0.--7. 1. "CQFSET,Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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line.long 0x20 "CQPAUSEEN,Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the CQFLAG register is '1'. CQ processing will halt until either value is changed to '0'."
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hexmask.long.word 0x20 0.--15. 1. "CQPEN,Enables the specified event to pause command processing when active"
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line.long 0x24 "CQCURIDX,Current index value. targeted to be written by register write operations within the command queue. This is compared to the CQENDIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and"
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|
hexmask.long.byte 0x24 0.--7. 1. "CQCURIDX,Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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|
line.long 0x28 "CQENDIDX,End index value. targeted to be written by software to indicate the last valid register pair contained within the command queue for a register write operations within the command queue."
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hexmask.long.byte 0x28 0.--7. 1. "CQENDIDX,Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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|
line.long 0x2C "STATUS,IOM Module Status"
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bitfld.long 0x2C 2. "IDLEST,indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to hold-offs from data availability or as the command gets propagated into the logic from the registers." "?,1: The I/O state machine is in the idle state."
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bitfld.long 0x2C 1. "CMDACT,Indicates if the active I/O Command is currently processing a transaction or command is complete but the FIFO pointers are still synchronizing internally. This bit will go high at" "?,1: An I/O command is active. Indicates the active.."
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bitfld.long 0x2C 0. "ERR,Bit has been deprecated. Please refer to the other error indicators. This will always return 0." "?,1: Bit has been deprecated and will always return 0."
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|
group.long 0x300++0x3
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line.long 0x0 "MSPICFG,Controls the configuration of the SPI master module. including POL/PHA. LSB. flow control. and delays for MISO and MOSI"
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bitfld.long 0x0 30. "MSPIRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 27.--29. "DOUTDLY,Delay tap to use for the output signal (MOSI). This give more hold time on the output data" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 24.--26. "DINDLY,Delay tap to use for the input signal (MISO). This gives more hold time on the input data." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "SPILSB,Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first." "0: Send and receive MSB bit first,1: Send and receive LSB bit first"
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bitfld.long 0x0 22. "RDFCPOL,selects the read flow control signal polarity." "0: Flow control signal high creates flow control.,1: Flow control signal low creates flow control."
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bitfld.long 0x0 21. "WTFCPOL,selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 will allow a IRQ=1 to pause transfers)." "0: Flow control signal high(1) creates flow control..,1: Flow control signal low(0) creates flow control.."
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bitfld.long 0x0 20. "WTFCIRQ,selects the write mode flow control signal." "0: MISO is used as the write mode flow control..,1: IRQ is used as the write mode flow control signal."
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bitfld.long 0x0 18. "MOSIINV,inverts MOSI when flow control is enabled." "0: MOSI is set to 0 in read mode and 1 in write mode.,1: MOSI is set to 1 in read mode and 0 in write mode."
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newline
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bitfld.long 0x0 17. "RDFC,enables read mode flow control." "0: Read mode flow control disabled.,1: Read mode flow control enabled."
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bitfld.long 0x0 16. "WTFC,enables write mode flow control." "0: Write mode flow control disabled.,1: Write mode flow control enabled."
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newline
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bitfld.long 0x0 2. "FULLDUP,Enables full duplex mode for Master SPI write operations. Data will be captured simultaneously into the read FIFO" "0,1"
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bitfld.long 0x0 1. "SPHA,selects SPI phase." "0: Sample on the leading (first) clock edge.,1: Sample on the trailing (second) clock edge."
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newline
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bitfld.long 0x0 0. "SPOL,selects SPI polarity." "0: The base value of the clock is 0.,1: The base value of the clock is 1."
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group.long 0x400++0x7
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line.long 0x0 "MI2CCFG,Controls the configuration of the I2C bus master."
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bitfld.long 0x0 24. "STRDIS,Disable detection of clock stretch events smaller than 1 cycle" "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "SMPCNT,Number of Base clock cycles to wait before sampling the SCL clock to determine if a clock stretch event has occurred"
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newline
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hexmask.long.byte 0x0 12.--15. 1. "SDAENDLY,Number of IOCLK cycles to delay the SDA output en (all transitions affected). Used to delay data relative to clock"
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hexmask.long.byte 0x0 8.--11. 1. "SCLENDLY,Number of IOCLK cycles to delay the rising edge of the SCL output en (clock will go low on this edge). Used to allow clock shaping."
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newline
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bitfld.long 0x0 6. "MI2CRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 4.--5. "SDADLY,Delay to enable on the SDA output. Values are 0x0-0x3." "0,1,2,3"
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newline
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bitfld.long 0x0 2. "ARBEN,Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master this function can be disabled to save clock cycles on I2C transactions" "0: Disable multi-master bus arbitration support for..,1: Enable multi-master bus arbitration support for.."
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bitfld.long 0x0 1. "I2CLSB,Direction of data transmit and receive MSB(0) or LSB(1) first. Default per I2C specification is MSB first. This applies to both read and write data and read data will be bit" "0: Byte data is transmitted MSB first onto the..,1: Byte data is transmitted LSB first onto the.."
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newline
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bitfld.long 0x0 0. "ADDRSZ,Sets the I2C master device address size to either 7 bits (0) or 10 bits (1)." "0: Use 7-bit addressing for I2C master transactions,1: Use 10-bit addressing for I2C master transactions"
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line.long 0x4 "DEVCFG,Contains the I2C device address."
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hexmask.long.word 0x4 0.--9. 1. "DEVADDR,I2C address of the device that the Master will use to target for read/write operations. This can be either a 7-bit or 10-bit address."
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group.long 0x410++0x3
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line.long 0x0 "IOMDBG,Debug control"
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hexmask.long 0x0 3.--31. 1. "DBGDATA,Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers."
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bitfld.long 0x0 2. "APBCLKON,APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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newline
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bitfld.long 0x0 1. "IOCLKON,IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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bitfld.long 0x0 0. "DBGEN,Debug Enable. Setting bit will enable the update of data within this register otherwise it is clock gated for power savings" "0,1"
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tree.end
|
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endif
|
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sif (cpuis("AMA3B2KK"))
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tree "IOM3"
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|
base ad:0x50007000
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group.long 0x0++0x3
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line.long 0x0 "FIFO,Provides direct random access to both output and input FIFOs. The state of the FIFO is not disturbed by reading these locations (i.e.. no POP will be done). FIFO0 is accessible from addresses 0x0 - 0x1C. and is used for data output from the IOM to.."
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hexmask.long 0x0 0.--31. 1. "FIFO,FIFO direct access. Only locations 0 - 3F will return valid information."
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group.long 0x100++0x17
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line.long 0x0 "FIFOPTR,Provides the current valid byte count of data within the FIFO as seen from the internal state machines. FIFO0 is dedicated to outgoing transactions and FIFO1 is dedicated to incoming transactions. All counts are specified in units of bytes."
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hexmask.long.byte 0x0 24.--31. 1. "FIFO1REM,The number of remaining data bytes slots currently in FIFO 1 (written by interface read by MCU)"
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hexmask.long.byte 0x0 16.--23. 1. "FIFO1SIZ,The number of valid data bytes currently in FIFO 1 (written by interface read by MCU)"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "FIFO0REM,The number of remaining data bytes slots currently in FIFO 0 (written by MCU read by interface)"
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hexmask.long.byte 0x0 0.--7. 1. "FIFO0SIZ,The number of valid data bytes currently in the FIFO 0 (written by MCU read by interface)"
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line.long 0x4 "FIFOTHR,Sets the threshold values for incoming and outgoing transactions. The threshold values are used to assert the interrupt if enabled. and also used during DMA to set the transfer size as a result of DMATHR trigger."
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hexmask.long.byte 0x4 8.--13. 1. "FIFOWTHR,FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the write FIFO contains FIFOWTHR free bytes as.."
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hexmask.long.byte 0x4 0.--5. 1. "FIFORTHR,FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the read FIFO contains FIFORTHR valid bytes of data as.."
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line.long 0x8 "FIFOPOP,Will advance the internal read pointer of the incoming FIFO (FIFO1) when read. if POPWR is not active. If POPWR is active. a write to this register is needed to advance the internal FIFO pointer."
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hexmask.long 0x8 0.--31. 1. "FIFODOUT,This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0) the FIFO read pointer will be advanced by one word as a result of the read."
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line.long 0xC "FIFOPUSH,Will write new data into the outgoing FIFO and advance the internal write pointer."
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hexmask.long 0xC 0.--31. 1. "FIFODIN,This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes)."
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line.long 0x10 "FIFOCTRL,Provides controls for the operation of the internal FIFOs. Contains fields used to control the operation of the POP register. and also controls to reset the internal pointers of the FIFOs."
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bitfld.long 0x10 1. "FIFORSTN,Active low manual reset of the FIFO. Write to 0 to reset FIFO and then write to 1 to remove the reset." "0,1"
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bitfld.long 0x10 0. "POPWR,Selects the mode in which 'pop' events are done for the FIFO read operations. A value of '1' will prevent a pop event on a read operation and will require a write to the FIFOPOP register to create a pop event." "0,1"
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line.long 0x14 "FIFOLOC,Provides a read only value of the current read and write pointers. This register is read only and can be used along with the FIFO direct access method to determine the next data to be used for input and output functions."
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hexmask.long.byte 0x14 8.--11. 1. "FIFORPTR,Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1) which is used to store read data returned from external devices during a read operation."
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hexmask.long.byte 0x14 0.--3. 1. "FIFOWPTR,Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0) which is used during write operations to external devices."
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group.long 0x200++0x27
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line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
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bitfld.long 0x0 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x0 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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newline
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bitfld.long 0x0 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x0 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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newline
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bitfld.long 0x0 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x0 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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newline
|
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bitfld.long 0x0 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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|
bitfld.long 0x0 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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|
newline
|
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bitfld.long 0x0 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
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bitfld.long 0x0 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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newline
|
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bitfld.long 0x0 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x0 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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newline
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bitfld.long 0x0 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
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bitfld.long 0x0 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
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newline
|
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bitfld.long 0x0 0. "CMDCMP,Command complete interrupt" "0,1"
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line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
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bitfld.long 0x4 14. "CQERR,Error during command queue operations" "0,1"
|
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bitfld.long 0x4 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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newline
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bitfld.long 0x4 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x4 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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|
newline
|
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bitfld.long 0x4 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0x4 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x4 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x4 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0x4 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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|
newline
|
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bitfld.long 0x4 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
|
|
bitfld.long 0x4 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "CMDCMP,Command complete interrupt" "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 14. "CQERR,Error during command queue operations" "0,1"
|
|
bitfld.long 0x8 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
|
|
newline
|
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bitfld.long 0x8 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
|
|
bitfld.long 0x8 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
newline
|
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bitfld.long 0x8 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0x8 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
|
|
newline
|
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bitfld.long 0x8 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x8 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
|
|
newline
|
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bitfld.long 0x8 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x8 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
|
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newline
|
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bitfld.long 0x8 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0x8 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
|
|
newline
|
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bitfld.long 0x8 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
|
|
bitfld.long 0x8 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
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bitfld.long 0x8 0. "CMDCMP,Command complete interrupt" "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 14. "CQERR,Error during command queue operations" "0,1"
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|
bitfld.long 0xC 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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newline
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bitfld.long 0xC 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
|
|
bitfld.long 0xC 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
newline
|
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bitfld.long 0xC 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0xC 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
|
|
newline
|
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bitfld.long 0xC 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0xC 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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|
newline
|
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bitfld.long 0xC 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0xC 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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|
newline
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bitfld.long 0xC 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0xC 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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bitfld.long 0xC 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
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bitfld.long 0xC 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0xC 0. "CMDCMP,Command complete interrupt" "0,1"
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|
line.long 0x10 "CLKCFG,Provides clock related controls used internal to the BLEIF module. and enablement of 32KHz clock to the BLE Core module. The internal clock sourced is selected via the FSEL and can be further divided by 3 using the DIV3 control."
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hexmask.long.byte 0x10 24.--31. 1. "TOTPER,Clock total clock count minus 1. This provides the total period of the divided clock -1 when the DIVEN is active. The"
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|
hexmask.long.byte 0x10 16.--23. 1. "LOWPER,Clock low clock count minus 1. This provides the number of clocks the divided clock will be low when the DIVEN = 1."
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|
newline
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bitfld.long 0x10 12. "DIVEN,Enable clock division by TOTPER and LOWPER" "0: Disable TOTPER division.,1: Enable TOTPER division."
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bitfld.long 0x10 11. "DIV3,Enable divide by 3 of the source IOCLK. Division by 3 is done before the DIVEN programmable divider and if enabled" "0: Select divide by 1.,1: Select divide by 3."
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bitfld.long 0x10 8.--10. "FSEL,Select the input clock frequency." "0: Selects the minimum power clock. This setting..,1: Selects the HFRC as the input clock.,2: Selects the HFRC / 2 as the input clock.,3: Selects the HFRC / 4 as the input clock.,4: Selects the HFRC / 8 as the input clock.,5: Selects the HFRC / 16 as the input clock.,6: Selects the HFRC / 32 as the input clock.,7: Selects the HFRC / 64 as the input clock."
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bitfld.long 0x10 0. "IOCLKEN,Enable for the interface clock. Must be enabled prior to executing any IO operations." "0,1"
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line.long 0x14 "SUBMODCTRL,Provides enable for each submodule. Only a single submodule can be enabled at one time."
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bitfld.long 0x14 5.--7. "SMOD1TYPE,Submodule 0 module type. This is the I2C Master interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,?,?,?,7: NOT INSTALLED"
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bitfld.long 0x14 4. "SMOD1EN,Submodule 1 enable (1) or disable (0)" "0,1"
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bitfld.long 0x14 1.--3. "SMOD0TYPE,Submodule 0 module type. This is the SPI Master interface." "0: MSPI submodule,1: I2C Master submodule,2: SPI Slave submodule,3: I2C Slave submodule,?,?,?,7: NOT INSTALLED"
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bitfld.long 0x14 0. "SMOD0EN,Submodule 0 enable (1) or disable (0)" "0,1"
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line.long 0x18 "CMD,Writes to this register will start an IO transaction. as well as set various parameters for the command itself. Reads will return the command value written to the CMD register."
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hexmask.long.byte 0x18 24.--31. 1. "OFFSETLO,This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command."
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bitfld.long 0x18 20.--21. "CMDSEL,Command Specific selection information. Not used in Master I2C. Used as CEn select for Master SPI transactions" "0,1,2,3"
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hexmask.long.word 0x18 8.--19. 1. "TSIZE,Defines the transaction size in bytes. The offset transfer is not included in this size."
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bitfld.long 0x18 7. "CONT,Continue to hold the bus after the current transaction if set to a 1 with a new command issued." "0,1"
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bitfld.long 0x18 5.--6. "OFFSETCNT,Number of offset bytes to use for the command - 0 1 2 3 are valid selections. The second (byte 1) and third byte (byte 2) are read from the OFFSETHI register and the low order byte is pulled from this register in the OFFSETLO field." "0,1,2,3"
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hexmask.long.byte 0x18 0.--4. 1. "CMD,Command for submodule."
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line.long 0x1C "DCX,Enables use of CE signals to transmit DCX level for SPI transactions. Only used in Apollo3 Revision B. For Revision A. this register MUST NOT be programmed!"
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bitfld.long 0x1C 4. "DCXEN,DCX Signaling Enable The selected DCX signal (unused CE pin) will be driven low during write of offset byte and high during transmission of data bytes." "0: Disable DCX.,1: Enable DCX."
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bitfld.long 0x1C 3. "CE3OUT,Enable DCX output using CE3 output" "0,1"
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bitfld.long 0x1C 2. "CE2OUT,Enable DCX output using CE2 output" "0,1"
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bitfld.long 0x1C 1. "CE1OUT,Enable DCX output using CE1 output" "0,1"
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bitfld.long 0x1C 0. "CE0OUT,Enable DCX output using CE0 output" "0,1"
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line.long 0x20 "OFFSETHI,High order 2 bytes of 3 byte offset for IO transaction"
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hexmask.long.word 0x20 0.--15. 1. "OFFSETHI,Holds the high order 2 bytes of the 3 byte addressing/offset field to use with IO commands. The number of offset bytes to use is specified in the command register"
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line.long 0x24 "CMDSTAT,Provides status on the execution of the command currently in progress. The fields in this register will reflect the real time status of the internal state machines and data transfers within the IOM."
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hexmask.long.word 0x24 8.--19. 1. "CTSIZE,The current number of bytes still to be transferred with this command. This field will count down to zero."
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bitfld.long 0x24 5.--7. "CMDSTAT,The current status of the command execution." "?,1: Error encountered with command,2: Actively processing command,?,4: Idle state no active command no error,?,6: Command in progress but waiting on data from host,?"
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newline
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hexmask.long.byte 0x24 0.--4. 1. "CCMD,current command that is being executed"
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group.long 0x240++0x7
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line.long 0x0 "DMATRIGEN,Provides control on which event will trigger the DMA transfer after the DMA operation is setup and enabled. The trigger event will cause a number of bytes (depending on trigger event) to be"
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bitfld.long 0x0 1. "DTHREN,Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes) the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO and will transfer (WTHR/4) number of words" "0,1"
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bitfld.long 0x0 0. "DCMDCMPEN,Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered the number of words transferred will be the lesser of the remaining TOTCOUNT bytes or" "0,1"
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line.long 0x4 "DMATRIGSTAT,Provides the status of trigger events that have occurred for the transaction. Some of the bits are read only and some can be reset via a write of 0."
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bitfld.long 0x4 2. "DTOTCMP,DMA triggered when DCMDCMP = 0 and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is" "0,1"
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bitfld.long 0x4 1. "DTHR,Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA." "0,1"
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bitfld.long 0x4 0. "DCMDCMP,Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA." "0,1"
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group.long 0x280++0x3
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line.long 0x0 "DMACFG,Configuration control of the DMA process. including the direction of DMA. and enablement of DMA"
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bitfld.long 0x0 9. "DPWROFF,Power off module after DMA is complete. If this bit is active the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain power down will not be performed." "0: Power off disabled,1: Power off enabled"
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bitfld.long 0x0 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x0 1. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction. To be..,1: Memory to Peripheral transaction. To be set when.."
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bitfld.long 0x0 0. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable DMA Function,1: Enable DMA Function"
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group.long 0x288++0x2F
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line.long 0x0 "DMATOTCOUNT,Contains the number of bytes to be transferred for this DMA transaction. This register is decremented as the data is transferred. and will be 0 at the completion of the DMA operation."
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hexmask.long.word 0x0 0.--11. 1. "TOTCOUNT,Triggered DMA from Command complete event occurred. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."
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line.long 0x4 "DMATARGADDR,The source or destination address internal the SRAM for the DMA data. For write operations. this can only be SRAM data (ADDR bit 28 = 1); For read operations. this can be either SRAM or FLASH (ADDR bit 28 = 0)"
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bitfld.long 0x4 28. "TARGADDR28,Bit 28 of the target byte address for source of DMA (either read or write). In cases of non-word aligned addresses the DMA logic will take care for ensuring only the target bytes are read/written." "0,1"
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hexmask.long.tbyte 0x4 0.--20. 1. "TARGADDR,Bits [19:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment and does not have to be word aligned. In cases of non-word aligned addresses the DMA logic will take care for ensuring only.."
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line.long 0x8 "DMASTAT,Status of the DMA operation currently in progress."
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bitfld.long 0x8 2. "DMAERR,DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set this bit will remain set until cleared by software." "0,1"
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bitfld.long 0x8 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0 and will also be cleared when a new DMA is started." "0,1"
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bitfld.long 0x8 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
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line.long 0xC "CQCFG,Controls parameters and options for execution of the command queue operation. To enable command queue. create this in memory. set the address. and enable it with a write to CQEN"
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bitfld.long 0xC 2.--3. "MSPIFLGSEL,Selects the MPSI modules used for sourcing the CQFLAG [11:8]." "0: Selects MPSI0 as source of signals used in..,1: Selects MPSI1 as source of signals used in..,2: Selects MPSI2 as source of signals used in..,?"
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bitfld.long 0xC 1. "CQPRI,Sets the Priority of the command queue DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0xC 0. "CQEN,Command queue enable. When set will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled using a CQ executed write to this bit as well." "0: Disable CQ Function,1: Enable CQ Function"
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line.long 0x10 "CQADDR,The SRAM address which will be fetched next execution of the CQ operation. This register is updated as the CQ operation progresses. and is the live version of the register. The register can also be written by the Command Queue operation itself..."
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bitfld.long 0x10 28. "CQADDR28,Bit 28 of target byte address for source of CQ. Used to denote Flash (0) or SRAM (1) access" "0,1"
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hexmask.long.tbyte 0x10 2.--20. 1. "CQADDR,Bits 19:2 of target byte address for source of CQ. The buffer must be aligned on a word boundary"
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line.long 0x14 "CQSTAT,Provides the status of the command queue operation. If the command queue is disabled. these bits will be cleared. The bits are read only"
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bitfld.long 0x14 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
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bitfld.long 0x14 1. "CQPAUSED,Command queue operation is currently paused." "0,1"
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bitfld.long 0x14 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
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line.long 0x18 "CQFLAGS,Command Queue Flag"
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hexmask.long.word 0x18 16.--31. 1. "CQIRQMASK,Mask the bits used to generate the command queue interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE"
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hexmask.long.word 0x18 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
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line.long 0x1C "CQSETCLEAR,Set/Clear the command queue software pause flags on a per-bit basis. Contains 3 fields. allowing for setting. clearing or toggling the value in the software flags. Priority when the same bit"
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hexmask.long.byte 0x1C 16.--23. 1. "CQFCLR,Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x1C 8.--15. 1. "CQFTGL,Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x1C 0.--7. 1. "CQFSET,Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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line.long 0x20 "CQPAUSEEN,Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the CQFLAG register is '1'. CQ processing will halt until either value is changed to '0'."
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hexmask.long.word 0x20 0.--15. 1. "CQPEN,Enables the specified event to pause command processing when active"
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line.long 0x24 "CQCURIDX,Current index value. targeted to be written by register write operations within the command queue. This is compared to the CQENDIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and"
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hexmask.long.byte 0x24 0.--7. 1. "CQCURIDX,Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x28 "CQENDIDX,End index value. targeted to be written by software to indicate the last valid register pair contained within the command queue for a register write operations within the command queue."
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hexmask.long.byte 0x28 0.--7. 1. "CQENDIDX,Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x2C "STATUS,IOM Module Status"
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bitfld.long 0x2C 2. "IDLEST,indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to hold-offs from data availability or as the command gets propagated into the logic from the registers." "?,1: The I/O state machine is in the idle state."
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bitfld.long 0x2C 1. "CMDACT,Indicates if the active I/O Command is currently processing a transaction or command is complete but the FIFO pointers are still synchronizing internally. This bit will go high at" "?,1: An I/O command is active. Indicates the active.."
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bitfld.long 0x2C 0. "ERR,Bit has been deprecated. Please refer to the other error indicators. This will always return 0." "?,1: Bit has been deprecated and will always return 0."
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group.long 0x300++0x3
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line.long 0x0 "MSPICFG,Controls the configuration of the SPI master module. including POL/PHA. LSB. flow control. and delays for MISO and MOSI"
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bitfld.long 0x0 30. "MSPIRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 27.--29. "DOUTDLY,Delay tap to use for the output signal (MOSI). This give more hold time on the output data" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 24.--26. "DINDLY,Delay tap to use for the input signal (MISO). This gives more hold time on the input data." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "SPILSB,Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first." "0: Send and receive MSB bit first,1: Send and receive LSB bit first"
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bitfld.long 0x0 22. "RDFCPOL,selects the read flow control signal polarity." "0: Flow control signal high creates flow control.,1: Flow control signal low creates flow control."
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bitfld.long 0x0 21. "WTFCPOL,selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 will allow a IRQ=1 to pause transfers)." "0: Flow control signal high(1) creates flow control..,1: Flow control signal low(0) creates flow control.."
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bitfld.long 0x0 20. "WTFCIRQ,selects the write mode flow control signal." "0: MISO is used as the write mode flow control..,1: IRQ is used as the write mode flow control signal."
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bitfld.long 0x0 18. "MOSIINV,inverts MOSI when flow control is enabled." "0: MOSI is set to 0 in read mode and 1 in write mode.,1: MOSI is set to 1 in read mode and 0 in write mode."
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newline
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bitfld.long 0x0 17. "RDFC,enables read mode flow control." "0: Read mode flow control disabled.,1: Read mode flow control enabled."
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bitfld.long 0x0 16. "WTFC,enables write mode flow control." "0: Write mode flow control disabled.,1: Write mode flow control enabled."
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bitfld.long 0x0 2. "FULLDUP,Enables full duplex mode for Master SPI write operations. Data will be captured simultaneously into the read FIFO" "0,1"
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bitfld.long 0x0 1. "SPHA,selects SPI phase." "0: Sample on the leading (first) clock edge.,1: Sample on the trailing (second) clock edge."
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bitfld.long 0x0 0. "SPOL,selects SPI polarity." "0: The base value of the clock is 0.,1: The base value of the clock is 1."
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group.long 0x400++0x7
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line.long 0x0 "MI2CCFG,Controls the configuration of the I2C bus master."
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bitfld.long 0x0 24. "STRDIS,Disable detection of clock stretch events smaller than 1 cycle" "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "SMPCNT,Number of Base clock cycles to wait before sampling the SCL clock to determine if a clock stretch event has occurred"
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hexmask.long.byte 0x0 12.--15. 1. "SDAENDLY,Number of IOCLK cycles to delay the SDA output en (all transitions affected). Used to delay data relative to clock"
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hexmask.long.byte 0x0 8.--11. 1. "SCLENDLY,Number of IOCLK cycles to delay the rising edge of the SCL output en (clock will go low on this edge). Used to allow clock shaping."
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bitfld.long 0x0 6. "MI2CRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 4.--5. "SDADLY,Delay to enable on the SDA output. Values are 0x0-0x3." "0,1,2,3"
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bitfld.long 0x0 2. "ARBEN,Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master this function can be disabled to save clock cycles on I2C transactions" "0: Disable multi-master bus arbitration support for..,1: Enable multi-master bus arbitration support for.."
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|
bitfld.long 0x0 1. "I2CLSB,Direction of data transmit and receive MSB(0) or LSB(1) first. Default per I2C specification is MSB first. This applies to both read and write data and read data will be bit" "0: Byte data is transmitted MSB first onto the..,1: Byte data is transmitted LSB first onto the.."
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newline
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bitfld.long 0x0 0. "ADDRSZ,Sets the I2C master device address size to either 7 bits (0) or 10 bits (1)." "0: Use 7-bit addressing for I2C master transactions,1: Use 10-bit addressing for I2C master transactions"
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line.long 0x4 "DEVCFG,Contains the I2C device address."
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hexmask.long.word 0x4 0.--9. 1. "DEVADDR,I2C address of the device that the Master will use to target for read/write operations. This can be either a 7-bit or 10-bit address."
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group.long 0x410++0x3
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line.long 0x0 "IOMDBG,Debug control"
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hexmask.long 0x0 3.--31. 1. "DBGDATA,Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers."
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bitfld.long 0x0 2. "APBCLKON,APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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newline
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bitfld.long 0x0 1. "IOCLKON,IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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bitfld.long 0x0 0. "DBGEN,Debug Enable. Setting bit will enable the update of data within this register otherwise it is clock gated for power savings" "0,1"
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|
tree.end
|
|
endif
|
|
sif (cpuis("AMA3B2KK"))
|
|
tree "IOM4"
|
|
base ad:0x50008000
|
|
group.long 0x0++0x3
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line.long 0x0 "FIFO,Provides direct random access to both output and input FIFOs. The state of the FIFO is not disturbed by reading these locations (i.e.. no POP will be done). FIFO0 is accessible from addresses 0x0 - 0x1C. and is used for data output from the IOM to.."
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hexmask.long 0x0 0.--31. 1. "FIFO,FIFO direct access. Only locations 0 - 3F will return valid information."
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group.long 0x100++0x17
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line.long 0x0 "FIFOPTR,Provides the current valid byte count of data within the FIFO as seen from the internal state machines. FIFO0 is dedicated to outgoing transactions and FIFO1 is dedicated to incoming transactions. All counts are specified in units of bytes."
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hexmask.long.byte 0x0 24.--31. 1. "FIFO1REM,The number of remaining data bytes slots currently in FIFO 1 (written by interface read by MCU)"
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hexmask.long.byte 0x0 16.--23. 1. "FIFO1SIZ,The number of valid data bytes currently in FIFO 1 (written by interface read by MCU)"
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hexmask.long.byte 0x0 8.--15. 1. "FIFO0REM,The number of remaining data bytes slots currently in FIFO 0 (written by MCU read by interface)"
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hexmask.long.byte 0x0 0.--7. 1. "FIFO0SIZ,The number of valid data bytes currently in the FIFO 0 (written by MCU read by interface)"
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line.long 0x4 "FIFOTHR,Sets the threshold values for incoming and outgoing transactions. The threshold values are used to assert the interrupt if enabled. and also used during DMA to set the transfer size as a result of DMATHR trigger."
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hexmask.long.byte 0x4 8.--13. 1. "FIFOWTHR,FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the write FIFO contains FIFOWTHR free bytes as.."
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hexmask.long.byte 0x4 0.--5. 1. "FIFORTHR,FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the read FIFO contains FIFORTHR valid bytes of data as.."
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line.long 0x8 "FIFOPOP,Will advance the internal read pointer of the incoming FIFO (FIFO1) when read. if POPWR is not active. If POPWR is active. a write to this register is needed to advance the internal FIFO pointer."
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hexmask.long 0x8 0.--31. 1. "FIFODOUT,This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0) the FIFO read pointer will be advanced by one word as a result of the read."
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|
line.long 0xC "FIFOPUSH,Will write new data into the outgoing FIFO and advance the internal write pointer."
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hexmask.long 0xC 0.--31. 1. "FIFODIN,This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes)."
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line.long 0x10 "FIFOCTRL,Provides controls for the operation of the internal FIFOs. Contains fields used to control the operation of the POP register. and also controls to reset the internal pointers of the FIFOs."
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bitfld.long 0x10 1. "FIFORSTN,Active low manual reset of the FIFO. Write to 0 to reset FIFO and then write to 1 to remove the reset." "0,1"
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bitfld.long 0x10 0. "POPWR,Selects the mode in which 'pop' events are done for the FIFO read operations. A value of '1' will prevent a pop event on a read operation and will require a write to the FIFOPOP register to create a pop event." "0,1"
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line.long 0x14 "FIFOLOC,Provides a read only value of the current read and write pointers. This register is read only and can be used along with the FIFO direct access method to determine the next data to be used for input and output functions."
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hexmask.long.byte 0x14 8.--11. 1. "FIFORPTR,Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1) which is used to store read data returned from external devices during a read operation."
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hexmask.long.byte 0x14 0.--3. 1. "FIFOWPTR,Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0) which is used during write operations to external devices."
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group.long 0x200++0x27
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line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
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bitfld.long 0x0 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x0 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x0 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x0 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x0 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x0 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0x0 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x0 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x0 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x0 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x0 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x0 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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bitfld.long 0x0 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
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bitfld.long 0x0 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x0 0. "CMDCMP,Command complete interrupt" "0,1"
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line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
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bitfld.long 0x4 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x4 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x4 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x4 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x4 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x4 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0x4 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x4 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x4 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x4 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x4 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x4 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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bitfld.long 0x4 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
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bitfld.long 0x4 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x4 0. "CMDCMP,Command complete interrupt" "0,1"
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line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
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bitfld.long 0x8 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x8 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0x8 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x8 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0x8 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x8 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0x8 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0x8 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0x8 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x8 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0x8 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x8 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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bitfld.long 0x8 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
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bitfld.long 0x8 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0x8 0. "CMDCMP,Command complete interrupt" "0,1"
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line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
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bitfld.long 0xC 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0xC 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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bitfld.long 0xC 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0xC 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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bitfld.long 0xC 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0xC 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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bitfld.long 0xC 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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bitfld.long 0xC 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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bitfld.long 0xC 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0xC 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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bitfld.long 0xC 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0xC 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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bitfld.long 0xC 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
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bitfld.long 0xC 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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bitfld.long 0xC 0. "CMDCMP,Command complete interrupt" "0,1"
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line.long 0x10 "CLKCFG,Provides clock related controls used internal to the BLEIF module. and enablement of 32KHz clock to the BLE Core module. The internal clock sourced is selected via the FSEL and can be further divided by 3 using the DIV3 control."
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hexmask.long.byte 0x10 24.--31. 1. "TOTPER,Clock total clock count minus 1. This provides the total period of the divided clock -1 when the DIVEN is active. The"
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hexmask.long.byte 0x10 16.--23. 1. "LOWPER,Clock low clock count minus 1. This provides the number of clocks the divided clock will be low when the DIVEN = 1."
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bitfld.long 0x10 12. "DIVEN,Enable clock division by TOTPER and LOWPER" "0: Disable TOTPER division.,1: Enable TOTPER division."
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bitfld.long 0x10 11. "DIV3,Enable divide by 3 of the source IOCLK. Division by 3 is done before the DIVEN programmable divider and if enabled" "0: Select divide by 1.,1: Select divide by 3."
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bitfld.long 0x10 8.--10. "FSEL,Select the input clock frequency." "0: Selects the minimum power clock. This setting..,1: Selects the HFRC as the input clock.,2: Selects the HFRC / 2 as the input clock.,3: Selects the HFRC / 4 as the input clock.,4: Selects the HFRC / 8 as the input clock.,5: Selects the HFRC / 16 as the input clock.,6: Selects the HFRC / 32 as the input clock.,7: Selects the HFRC / 64 as the input clock."
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bitfld.long 0x10 0. "IOCLKEN,Enable for the interface clock. Must be enabled prior to executing any IO operations." "0,1"
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line.long 0x14 "SUBMODCTRL,Provides enable for each submodule. Only a single submodule can be enabled at one time."
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bitfld.long 0x14 5.--7. "SMOD1TYPE,Submodule 0 module type. This is the I2C Master interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,?,?,?,7: NOT INSTALLED"
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bitfld.long 0x14 4. "SMOD1EN,Submodule 1 enable (1) or disable (0)" "0,1"
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bitfld.long 0x14 1.--3. "SMOD0TYPE,Submodule 0 module type. This is the SPI Master interface." "0: MSPI submodule,1: I2C Master submodule,2: SPI Slave submodule,3: I2C Slave submodule,?,?,?,7: NOT INSTALLED"
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bitfld.long 0x14 0. "SMOD0EN,Submodule 0 enable (1) or disable (0)" "0,1"
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line.long 0x18 "CMD,Writes to this register will start an IO transaction. as well as set various parameters for the command itself. Reads will return the command value written to the CMD register."
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hexmask.long.byte 0x18 24.--31. 1. "OFFSETLO,This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command."
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bitfld.long 0x18 20.--21. "CMDSEL,Command Specific selection information. Not used in Master I2C. Used as CEn select for Master SPI transactions" "0,1,2,3"
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hexmask.long.word 0x18 8.--19. 1. "TSIZE,Defines the transaction size in bytes. The offset transfer is not included in this size."
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bitfld.long 0x18 7. "CONT,Continue to hold the bus after the current transaction if set to a 1 with a new command issued." "0,1"
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bitfld.long 0x18 5.--6. "OFFSETCNT,Number of offset bytes to use for the command - 0 1 2 3 are valid selections. The second (byte 1) and third byte (byte 2) are read from the OFFSETHI register and the low order byte is pulled from this register in the OFFSETLO field." "0,1,2,3"
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hexmask.long.byte 0x18 0.--4. 1. "CMD,Command for submodule."
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line.long 0x1C "DCX,Enables use of CE signals to transmit DCX level for SPI transactions. Only used in Apollo3 Revision B. For Revision A. this register MUST NOT be programmed!"
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bitfld.long 0x1C 4. "DCXEN,DCX Signaling Enable The selected DCX signal (unused CE pin) will be driven low during write of offset byte and high during transmission of data bytes." "0: Disable DCX.,1: Enable DCX."
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bitfld.long 0x1C 3. "CE3OUT,Enable DCX output using CE3 output" "0,1"
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bitfld.long 0x1C 2. "CE2OUT,Enable DCX output using CE2 output" "0,1"
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bitfld.long 0x1C 1. "CE1OUT,Enable DCX output using CE1 output" "0,1"
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newline
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bitfld.long 0x1C 0. "CE0OUT,Enable DCX output using CE0 output" "0,1"
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line.long 0x20 "OFFSETHI,High order 2 bytes of 3 byte offset for IO transaction"
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hexmask.long.word 0x20 0.--15. 1. "OFFSETHI,Holds the high order 2 bytes of the 3 byte addressing/offset field to use with IO commands. The number of offset bytes to use is specified in the command register"
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line.long 0x24 "CMDSTAT,Provides status on the execution of the command currently in progress. The fields in this register will reflect the real time status of the internal state machines and data transfers within the IOM."
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hexmask.long.word 0x24 8.--19. 1. "CTSIZE,The current number of bytes still to be transferred with this command. This field will count down to zero."
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bitfld.long 0x24 5.--7. "CMDSTAT,The current status of the command execution." "?,1: Error encountered with command,2: Actively processing command,?,4: Idle state no active command no error,?,6: Command in progress but waiting on data from host,?"
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hexmask.long.byte 0x24 0.--4. 1. "CCMD,current command that is being executed"
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group.long 0x240++0x7
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line.long 0x0 "DMATRIGEN,Provides control on which event will trigger the DMA transfer after the DMA operation is setup and enabled. The trigger event will cause a number of bytes (depending on trigger event) to be"
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bitfld.long 0x0 1. "DTHREN,Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes) the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO and will transfer (WTHR/4) number of words" "0,1"
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bitfld.long 0x0 0. "DCMDCMPEN,Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered the number of words transferred will be the lesser of the remaining TOTCOUNT bytes or" "0,1"
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line.long 0x4 "DMATRIGSTAT,Provides the status of trigger events that have occurred for the transaction. Some of the bits are read only and some can be reset via a write of 0."
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bitfld.long 0x4 2. "DTOTCMP,DMA triggered when DCMDCMP = 0 and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is" "0,1"
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bitfld.long 0x4 1. "DTHR,Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA." "0,1"
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bitfld.long 0x4 0. "DCMDCMP,Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA." "0,1"
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group.long 0x280++0x3
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line.long 0x0 "DMACFG,Configuration control of the DMA process. including the direction of DMA. and enablement of DMA"
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bitfld.long 0x0 9. "DPWROFF,Power off module after DMA is complete. If this bit is active the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain power down will not be performed." "0: Power off disabled,1: Power off enabled"
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bitfld.long 0x0 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x0 1. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction. To be..,1: Memory to Peripheral transaction. To be set when.."
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bitfld.long 0x0 0. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable DMA Function,1: Enable DMA Function"
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group.long 0x288++0x2F
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line.long 0x0 "DMATOTCOUNT,Contains the number of bytes to be transferred for this DMA transaction. This register is decremented as the data is transferred. and will be 0 at the completion of the DMA operation."
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hexmask.long.word 0x0 0.--11. 1. "TOTCOUNT,Triggered DMA from Command complete event occurred. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."
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line.long 0x4 "DMATARGADDR,The source or destination address internal the SRAM for the DMA data. For write operations. this can only be SRAM data (ADDR bit 28 = 1); For read operations. this can be either SRAM or FLASH (ADDR bit 28 = 0)"
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bitfld.long 0x4 28. "TARGADDR28,Bit 28 of the target byte address for source of DMA (either read or write). In cases of non-word aligned addresses the DMA logic will take care for ensuring only the target bytes are read/written." "0,1"
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hexmask.long.tbyte 0x4 0.--20. 1. "TARGADDR,Bits [19:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment and does not have to be word aligned. In cases of non-word aligned addresses the DMA logic will take care for ensuring only.."
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line.long 0x8 "DMASTAT,Status of the DMA operation currently in progress."
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bitfld.long 0x8 2. "DMAERR,DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set this bit will remain set until cleared by software." "0,1"
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bitfld.long 0x8 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0 and will also be cleared when a new DMA is started." "0,1"
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bitfld.long 0x8 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
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line.long 0xC "CQCFG,Controls parameters and options for execution of the command queue operation. To enable command queue. create this in memory. set the address. and enable it with a write to CQEN"
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bitfld.long 0xC 2.--3. "MSPIFLGSEL,Selects the MPSI modules used for sourcing the CQFLAG [11:8]." "0: Selects MPSI0 as source of signals used in..,1: Selects MPSI1 as source of signals used in..,2: Selects MPSI2 as source of signals used in..,?"
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bitfld.long 0xC 1. "CQPRI,Sets the Priority of the command queue DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0xC 0. "CQEN,Command queue enable. When set will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled using a CQ executed write to this bit as well." "0: Disable CQ Function,1: Enable CQ Function"
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line.long 0x10 "CQADDR,The SRAM address which will be fetched next execution of the CQ operation. This register is updated as the CQ operation progresses. and is the live version of the register. The register can also be written by the Command Queue operation itself..."
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bitfld.long 0x10 28. "CQADDR28,Bit 28 of target byte address for source of CQ. Used to denote Flash (0) or SRAM (1) access" "0,1"
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hexmask.long.tbyte 0x10 2.--20. 1. "CQADDR,Bits 19:2 of target byte address for source of CQ. The buffer must be aligned on a word boundary"
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line.long 0x14 "CQSTAT,Provides the status of the command queue operation. If the command queue is disabled. these bits will be cleared. The bits are read only"
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bitfld.long 0x14 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
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bitfld.long 0x14 1. "CQPAUSED,Command queue operation is currently paused." "0,1"
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bitfld.long 0x14 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
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line.long 0x18 "CQFLAGS,Command Queue Flag"
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hexmask.long.word 0x18 16.--31. 1. "CQIRQMASK,Mask the bits used to generate the command queue interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE"
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hexmask.long.word 0x18 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
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line.long 0x1C "CQSETCLEAR,Set/Clear the command queue software pause flags on a per-bit basis. Contains 3 fields. allowing for setting. clearing or toggling the value in the software flags. Priority when the same bit"
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hexmask.long.byte 0x1C 16.--23. 1. "CQFCLR,Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x1C 8.--15. 1. "CQFTGL,Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x1C 0.--7. 1. "CQFSET,Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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|
line.long 0x20 "CQPAUSEEN,Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the CQFLAG register is '1'. CQ processing will halt until either value is changed to '0'."
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hexmask.long.word 0x20 0.--15. 1. "CQPEN,Enables the specified event to pause command processing when active"
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|
line.long 0x24 "CQCURIDX,Current index value. targeted to be written by register write operations within the command queue. This is compared to the CQENDIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and"
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|
hexmask.long.byte 0x24 0.--7. 1. "CQCURIDX,Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN."
|
|
line.long 0x28 "CQENDIDX,End index value. targeted to be written by software to indicate the last valid register pair contained within the command queue for a register write operations within the command queue."
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hexmask.long.byte 0x28 0.--7. 1. "CQENDIDX,Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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|
line.long 0x2C "STATUS,IOM Module Status"
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|
bitfld.long 0x2C 2. "IDLEST,indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to hold-offs from data availability or as the command gets propagated into the logic from the registers." "?,1: The I/O state machine is in the idle state."
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bitfld.long 0x2C 1. "CMDACT,Indicates if the active I/O Command is currently processing a transaction or command is complete but the FIFO pointers are still synchronizing internally. This bit will go high at" "?,1: An I/O command is active. Indicates the active.."
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|
newline
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bitfld.long 0x2C 0. "ERR,Bit has been deprecated. Please refer to the other error indicators. This will always return 0." "?,1: Bit has been deprecated and will always return 0."
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|
group.long 0x300++0x3
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|
line.long 0x0 "MSPICFG,Controls the configuration of the SPI master module. including POL/PHA. LSB. flow control. and delays for MISO and MOSI"
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|
bitfld.long 0x0 30. "MSPIRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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|
bitfld.long 0x0 27.--29. "DOUTDLY,Delay tap to use for the output signal (MOSI). This give more hold time on the output data" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x0 24.--26. "DINDLY,Delay tap to use for the input signal (MISO). This gives more hold time on the input data." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "SPILSB,Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first." "0: Send and receive MSB bit first,1: Send and receive LSB bit first"
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newline
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bitfld.long 0x0 22. "RDFCPOL,selects the read flow control signal polarity." "0: Flow control signal high creates flow control.,1: Flow control signal low creates flow control."
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bitfld.long 0x0 21. "WTFCPOL,selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 will allow a IRQ=1 to pause transfers)." "0: Flow control signal high(1) creates flow control..,1: Flow control signal low(0) creates flow control.."
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newline
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bitfld.long 0x0 20. "WTFCIRQ,selects the write mode flow control signal." "0: MISO is used as the write mode flow control..,1: IRQ is used as the write mode flow control signal."
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bitfld.long 0x0 18. "MOSIINV,inverts MOSI when flow control is enabled." "0: MOSI is set to 0 in read mode and 1 in write mode.,1: MOSI is set to 1 in read mode and 0 in write mode."
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newline
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bitfld.long 0x0 17. "RDFC,enables read mode flow control." "0: Read mode flow control disabled.,1: Read mode flow control enabled."
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bitfld.long 0x0 16. "WTFC,enables write mode flow control." "0: Write mode flow control disabled.,1: Write mode flow control enabled."
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newline
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bitfld.long 0x0 2. "FULLDUP,Enables full duplex mode for Master SPI write operations. Data will be captured simultaneously into the read FIFO" "0,1"
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bitfld.long 0x0 1. "SPHA,selects SPI phase." "0: Sample on the leading (first) clock edge.,1: Sample on the trailing (second) clock edge."
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newline
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bitfld.long 0x0 0. "SPOL,selects SPI polarity." "0: The base value of the clock is 0.,1: The base value of the clock is 1."
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group.long 0x400++0x7
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line.long 0x0 "MI2CCFG,Controls the configuration of the I2C bus master."
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bitfld.long 0x0 24. "STRDIS,Disable detection of clock stretch events smaller than 1 cycle" "0,1"
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|
hexmask.long.byte 0x0 16.--23. 1. "SMPCNT,Number of Base clock cycles to wait before sampling the SCL clock to determine if a clock stretch event has occurred"
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|
newline
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hexmask.long.byte 0x0 12.--15. 1. "SDAENDLY,Number of IOCLK cycles to delay the SDA output en (all transitions affected). Used to delay data relative to clock"
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|
hexmask.long.byte 0x0 8.--11. 1. "SCLENDLY,Number of IOCLK cycles to delay the rising edge of the SCL output en (clock will go low on this edge). Used to allow clock shaping."
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newline
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bitfld.long 0x0 6. "MI2CRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 4.--5. "SDADLY,Delay to enable on the SDA output. Values are 0x0-0x3." "0,1,2,3"
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newline
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bitfld.long 0x0 2. "ARBEN,Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master this function can be disabled to save clock cycles on I2C transactions" "0: Disable multi-master bus arbitration support for..,1: Enable multi-master bus arbitration support for.."
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bitfld.long 0x0 1. "I2CLSB,Direction of data transmit and receive MSB(0) or LSB(1) first. Default per I2C specification is MSB first. This applies to both read and write data and read data will be bit" "0: Byte data is transmitted MSB first onto the..,1: Byte data is transmitted LSB first onto the.."
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newline
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bitfld.long 0x0 0. "ADDRSZ,Sets the I2C master device address size to either 7 bits (0) or 10 bits (1)." "0: Use 7-bit addressing for I2C master transactions,1: Use 10-bit addressing for I2C master transactions"
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line.long 0x4 "DEVCFG,Contains the I2C device address."
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hexmask.long.word 0x4 0.--9. 1. "DEVADDR,I2C address of the device that the Master will use to target for read/write operations. This can be either a 7-bit or 10-bit address."
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group.long 0x410++0x3
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line.long 0x0 "IOMDBG,Debug control"
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hexmask.long 0x0 3.--31. 1. "DBGDATA,Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers."
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bitfld.long 0x0 2. "APBCLKON,APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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newline
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bitfld.long 0x0 1. "IOCLKON,IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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bitfld.long 0x0 0. "DBGEN,Debug Enable. Setting bit will enable the update of data within this register otherwise it is clock gated for power savings" "0,1"
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|
tree.end
|
|
endif
|
|
sif (cpuis("AMA3B2KK"))
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tree "IOM5"
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|
base ad:0x50009000
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group.long 0x0++0x3
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line.long 0x0 "FIFO,Provides direct random access to both output and input FIFOs. The state of the FIFO is not disturbed by reading these locations (i.e.. no POP will be done). FIFO0 is accessible from addresses 0x0 - 0x1C. and is used for data output from the IOM to.."
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hexmask.long 0x0 0.--31. 1. "FIFO,FIFO direct access. Only locations 0 - 3F will return valid information."
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group.long 0x100++0x17
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line.long 0x0 "FIFOPTR,Provides the current valid byte count of data within the FIFO as seen from the internal state machines. FIFO0 is dedicated to outgoing transactions and FIFO1 is dedicated to incoming transactions. All counts are specified in units of bytes."
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hexmask.long.byte 0x0 24.--31. 1. "FIFO1REM,The number of remaining data bytes slots currently in FIFO 1 (written by interface read by MCU)"
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hexmask.long.byte 0x0 16.--23. 1. "FIFO1SIZ,The number of valid data bytes currently in FIFO 1 (written by interface read by MCU)"
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|
newline
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hexmask.long.byte 0x0 8.--15. 1. "FIFO0REM,The number of remaining data bytes slots currently in FIFO 0 (written by MCU read by interface)"
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hexmask.long.byte 0x0 0.--7. 1. "FIFO0SIZ,The number of valid data bytes currently in the FIFO 0 (written by MCU read by interface)"
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line.long 0x4 "FIFOTHR,Sets the threshold values for incoming and outgoing transactions. The threshold values are used to assert the interrupt if enabled. and also used during DMA to set the transfer size as a result of DMATHR trigger."
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hexmask.long.byte 0x4 8.--13. 1. "FIFOWTHR,FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the write FIFO contains FIFOWTHR free bytes as.."
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hexmask.long.byte 0x4 0.--5. 1. "FIFORTHR,FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero it will trigger a threshold interrupt when the read FIFO contains FIFORTHR valid bytes of data as.."
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line.long 0x8 "FIFOPOP,Will advance the internal read pointer of the incoming FIFO (FIFO1) when read. if POPWR is not active. If POPWR is active. a write to this register is needed to advance the internal FIFO pointer."
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hexmask.long 0x8 0.--31. 1. "FIFODOUT,This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0) the FIFO read pointer will be advanced by one word as a result of the read."
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line.long 0xC "FIFOPUSH,Will write new data into the outgoing FIFO and advance the internal write pointer."
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hexmask.long 0xC 0.--31. 1. "FIFODIN,This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes)."
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line.long 0x10 "FIFOCTRL,Provides controls for the operation of the internal FIFOs. Contains fields used to control the operation of the POP register. and also controls to reset the internal pointers of the FIFOs."
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bitfld.long 0x10 1. "FIFORSTN,Active low manual reset of the FIFO. Write to 0 to reset FIFO and then write to 1 to remove the reset." "0,1"
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bitfld.long 0x10 0. "POPWR,Selects the mode in which 'pop' events are done for the FIFO read operations. A value of '1' will prevent a pop event on a read operation and will require a write to the FIFOPOP register to create a pop event." "0,1"
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line.long 0x14 "FIFOLOC,Provides a read only value of the current read and write pointers. This register is read only and can be used along with the FIFO direct access method to determine the next data to be used for input and output functions."
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hexmask.long.byte 0x14 8.--11. 1. "FIFORPTR,Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1) which is used to store read data returned from external devices during a read operation."
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hexmask.long.byte 0x14 0.--3. 1. "FIFOWPTR,Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0) which is used during write operations to external devices."
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group.long 0x200++0x27
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line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
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bitfld.long 0x0 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x0 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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newline
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bitfld.long 0x0 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x0 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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newline
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bitfld.long 0x0 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
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bitfld.long 0x0 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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newline
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bitfld.long 0x0 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
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|
bitfld.long 0x0 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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newline
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bitfld.long 0x0 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
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bitfld.long 0x0 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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newline
|
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bitfld.long 0x0 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
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bitfld.long 0x0 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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newline
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bitfld.long 0x0 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
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bitfld.long 0x0 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
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newline
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bitfld.long 0x0 0. "CMDCMP,Command complete interrupt" "0,1"
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line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
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bitfld.long 0x4 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0x4 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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newline
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bitfld.long 0x4 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
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bitfld.long 0x4 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
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newline
|
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bitfld.long 0x4 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0x4 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
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|
newline
|
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bitfld.long 0x4 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x4 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0x4 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0x4 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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|
newline
|
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bitfld.long 0x4 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
|
|
bitfld.long 0x4 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CMDCMP,Command complete interrupt" "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 14. "CQERR,Error during command queue operations" "0,1"
|
|
bitfld.long 0x8 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
|
|
newline
|
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bitfld.long 0x8 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
|
|
bitfld.long 0x8 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
newline
|
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bitfld.long 0x8 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0x8 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0x8 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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|
newline
|
|
bitfld.long 0x8 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
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bitfld.long 0x8 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
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newline
|
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bitfld.long 0x8 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0x8 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
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|
newline
|
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bitfld.long 0x8 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
|
|
bitfld.long 0x8 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
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bitfld.long 0x8 0. "CMDCMP,Command complete interrupt" "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 14. "CQERR,Error during command queue operations" "0,1"
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bitfld.long 0xC 13. "CQUPD,CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the.." "0,1"
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newline
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bitfld.long 0xC 12. "CQPAUSED,Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register the mask is active in the CQIRQMASK field and the event occurs." "0,1"
|
|
bitfld.long 0xC 11. "DERR,DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified." "0,1"
|
|
newline
|
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bitfld.long 0xC 10. "DCMP,DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state" "0,1"
|
|
bitfld.long 0xC 9. "ARB,Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus." "0,1"
|
|
newline
|
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bitfld.long 0xC 8. "STOP,STOP command interrupt. Asserted when another master on the bus has signaled a STOP command." "0,1"
|
|
bitfld.long 0xC 7. "START,START command interrupt. Asserted when another master on the bus has signaled a START command." "0,1"
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|
newline
|
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bitfld.long 0xC 6. "ICMD,illegal command interrupt. Asserted when a command is written when an active command is in progress." "0,1"
|
|
bitfld.long 0xC 5. "IACC,illegal FIFO access interrupt. Asserted when there is a overflow or underflow event" "0,1"
|
|
newline
|
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bitfld.long 0xC 4. "NAK,I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus." "0,1"
|
|
bitfld.long 0xC 3. "FOVFL,Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop." "0,1"
|
|
newline
|
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bitfld.long 0xC 2. "FUNDFL,Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO." "0,1"
|
|
bitfld.long 0xC 1. "THR,FIFO Threshold interrupt. For write operations asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field." "0,1"
|
|
newline
|
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bitfld.long 0xC 0. "CMDCMP,Command complete interrupt" "0,1"
|
|
line.long 0x10 "CLKCFG,Provides clock related controls used internal to the BLEIF module. and enablement of 32KHz clock to the BLE Core module. The internal clock sourced is selected via the FSEL and can be further divided by 3 using the DIV3 control."
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|
hexmask.long.byte 0x10 24.--31. 1. "TOTPER,Clock total clock count minus 1. This provides the total period of the divided clock -1 when the DIVEN is active. The"
|
|
hexmask.long.byte 0x10 16.--23. 1. "LOWPER,Clock low clock count minus 1. This provides the number of clocks the divided clock will be low when the DIVEN = 1."
|
|
newline
|
|
bitfld.long 0x10 12. "DIVEN,Enable clock division by TOTPER and LOWPER" "0: Disable TOTPER division.,1: Enable TOTPER division."
|
|
bitfld.long 0x10 11. "DIV3,Enable divide by 3 of the source IOCLK. Division by 3 is done before the DIVEN programmable divider and if enabled" "0: Select divide by 1.,1: Select divide by 3."
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|
newline
|
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bitfld.long 0x10 8.--10. "FSEL,Select the input clock frequency." "0: Selects the minimum power clock. This setting..,1: Selects the HFRC as the input clock.,2: Selects the HFRC / 2 as the input clock.,3: Selects the HFRC / 4 as the input clock.,4: Selects the HFRC / 8 as the input clock.,5: Selects the HFRC / 16 as the input clock.,6: Selects the HFRC / 32 as the input clock.,7: Selects the HFRC / 64 as the input clock."
|
|
bitfld.long 0x10 0. "IOCLKEN,Enable for the interface clock. Must be enabled prior to executing any IO operations." "0,1"
|
|
line.long 0x14 "SUBMODCTRL,Provides enable for each submodule. Only a single submodule can be enabled at one time."
|
|
bitfld.long 0x14 5.--7. "SMOD1TYPE,Submodule 0 module type. This is the I2C Master interface" "0: SPI Master submodule,1: MI2C submodule,2: SPI Slave submodule,3: I2C Slave submodule,?,?,?,7: NOT INSTALLED"
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|
bitfld.long 0x14 4. "SMOD1EN,Submodule 1 enable (1) or disable (0)" "0,1"
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|
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bitfld.long 0x14 1.--3. "SMOD0TYPE,Submodule 0 module type. This is the SPI Master interface." "0: MSPI submodule,1: I2C Master submodule,2: SPI Slave submodule,3: I2C Slave submodule,?,?,?,7: NOT INSTALLED"
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|
bitfld.long 0x14 0. "SMOD0EN,Submodule 0 enable (1) or disable (0)" "0,1"
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|
line.long 0x18 "CMD,Writes to this register will start an IO transaction. as well as set various parameters for the command itself. Reads will return the command value written to the CMD register."
|
|
hexmask.long.byte 0x18 24.--31. 1. "OFFSETLO,This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command."
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|
bitfld.long 0x18 20.--21. "CMDSEL,Command Specific selection information. Not used in Master I2C. Used as CEn select for Master SPI transactions" "0,1,2,3"
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|
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hexmask.long.word 0x18 8.--19. 1. "TSIZE,Defines the transaction size in bytes. The offset transfer is not included in this size."
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|
bitfld.long 0x18 7. "CONT,Continue to hold the bus after the current transaction if set to a 1 with a new command issued." "0,1"
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|
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bitfld.long 0x18 5.--6. "OFFSETCNT,Number of offset bytes to use for the command - 0 1 2 3 are valid selections. The second (byte 1) and third byte (byte 2) are read from the OFFSETHI register and the low order byte is pulled from this register in the OFFSETLO field." "0,1,2,3"
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|
hexmask.long.byte 0x18 0.--4. 1. "CMD,Command for submodule."
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|
line.long 0x1C "DCX,Enables use of CE signals to transmit DCX level for SPI transactions. Only used in Apollo3 Revision B. For Revision A. this register MUST NOT be programmed!"
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|
bitfld.long 0x1C 4. "DCXEN,DCX Signaling Enable The selected DCX signal (unused CE pin) will be driven low during write of offset byte and high during transmission of data bytes." "0: Disable DCX.,1: Enable DCX."
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|
bitfld.long 0x1C 3. "CE3OUT,Enable DCX output using CE3 output" "0,1"
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|
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bitfld.long 0x1C 2. "CE2OUT,Enable DCX output using CE2 output" "0,1"
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|
bitfld.long 0x1C 1. "CE1OUT,Enable DCX output using CE1 output" "0,1"
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|
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bitfld.long 0x1C 0. "CE0OUT,Enable DCX output using CE0 output" "0,1"
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|
line.long 0x20 "OFFSETHI,High order 2 bytes of 3 byte offset for IO transaction"
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|
hexmask.long.word 0x20 0.--15. 1. "OFFSETHI,Holds the high order 2 bytes of the 3 byte addressing/offset field to use with IO commands. The number of offset bytes to use is specified in the command register"
|
|
line.long 0x24 "CMDSTAT,Provides status on the execution of the command currently in progress. The fields in this register will reflect the real time status of the internal state machines and data transfers within the IOM."
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|
hexmask.long.word 0x24 8.--19. 1. "CTSIZE,The current number of bytes still to be transferred with this command. This field will count down to zero."
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|
bitfld.long 0x24 5.--7. "CMDSTAT,The current status of the command execution." "?,1: Error encountered with command,2: Actively processing command,?,4: Idle state no active command no error,?,6: Command in progress but waiting on data from host,?"
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|
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hexmask.long.byte 0x24 0.--4. 1. "CCMD,current command that is being executed"
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|
group.long 0x240++0x7
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|
line.long 0x0 "DMATRIGEN,Provides control on which event will trigger the DMA transfer after the DMA operation is setup and enabled. The trigger event will cause a number of bytes (depending on trigger event) to be"
|
|
bitfld.long 0x0 1. "DTHREN,Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes) the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO and will transfer (WTHR/4) number of words" "0,1"
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bitfld.long 0x0 0. "DCMDCMPEN,Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered the number of words transferred will be the lesser of the remaining TOTCOUNT bytes or" "0,1"
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line.long 0x4 "DMATRIGSTAT,Provides the status of trigger events that have occurred for the transaction. Some of the bits are read only and some can be reset via a write of 0."
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bitfld.long 0x4 2. "DTOTCMP,DMA triggered when DCMDCMP = 0 and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is" "0,1"
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|
bitfld.long 0x4 1. "DTHR,Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA." "0,1"
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|
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bitfld.long 0x4 0. "DCMDCMP,Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA." "0,1"
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|
group.long 0x280++0x3
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|
line.long 0x0 "DMACFG,Configuration control of the DMA process. including the direction of DMA. and enablement of DMA"
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|
bitfld.long 0x0 9. "DPWROFF,Power off module after DMA is complete. If this bit is active the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain power down will not be performed." "0: Power off disabled,1: Power off enabled"
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|
bitfld.long 0x0 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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|
newline
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bitfld.long 0x0 1. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction. To be..,1: Memory to Peripheral transaction. To be set when.."
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|
bitfld.long 0x0 0. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command" "0: Disable DMA Function,1: Enable DMA Function"
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|
group.long 0x288++0x2F
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|
line.long 0x0 "DMATOTCOUNT,Contains the number of bytes to be transferred for this DMA transaction. This register is decremented as the data is transferred. and will be 0 at the completion of the DMA operation."
|
|
hexmask.long.word 0x0 0.--11. 1. "TOTCOUNT,Triggered DMA from Command complete event occurred. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA."
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line.long 0x4 "DMATARGADDR,The source or destination address internal the SRAM for the DMA data. For write operations. this can only be SRAM data (ADDR bit 28 = 1); For read operations. this can be either SRAM or FLASH (ADDR bit 28 = 0)"
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bitfld.long 0x4 28. "TARGADDR28,Bit 28 of the target byte address for source of DMA (either read or write). In cases of non-word aligned addresses the DMA logic will take care for ensuring only the target bytes are read/written." "0,1"
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hexmask.long.tbyte 0x4 0.--20. 1. "TARGADDR,Bits [19:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment and does not have to be word aligned. In cases of non-word aligned addresses the DMA logic will take care for ensuring only.."
|
|
line.long 0x8 "DMASTAT,Status of the DMA operation currently in progress."
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bitfld.long 0x8 2. "DMAERR,DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set this bit will remain set until cleared by software." "0,1"
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|
bitfld.long 0x8 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0 and will also be cleared when a new DMA is started." "0,1"
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|
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bitfld.long 0x8 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority." "0,1"
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|
line.long 0xC "CQCFG,Controls parameters and options for execution of the command queue operation. To enable command queue. create this in memory. set the address. and enable it with a write to CQEN"
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bitfld.long 0xC 2.--3. "MSPIFLGSEL,Selects the MPSI modules used for sourcing the CQFLAG [11:8]." "0: Selects MPSI0 as source of signals used in..,1: Selects MPSI1 as source of signals used in..,2: Selects MPSI2 as source of signals used in..,?"
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bitfld.long 0xC 1. "CQPRI,Sets the Priority of the command queue DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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|
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bitfld.long 0xC 0. "CQEN,Command queue enable. When set will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled using a CQ executed write to this bit as well." "0: Disable CQ Function,1: Enable CQ Function"
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line.long 0x10 "CQADDR,The SRAM address which will be fetched next execution of the CQ operation. This register is updated as the CQ operation progresses. and is the live version of the register. The register can also be written by the Command Queue operation itself..."
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bitfld.long 0x10 28. "CQADDR28,Bit 28 of target byte address for source of CQ. Used to denote Flash (0) or SRAM (1) access" "0,1"
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hexmask.long.tbyte 0x10 2.--20. 1. "CQADDR,Bits 19:2 of target byte address for source of CQ. The buffer must be aligned on a word boundary"
|
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line.long 0x14 "CQSTAT,Provides the status of the command queue operation. If the command queue is disabled. these bits will be cleared. The bits are read only"
|
|
bitfld.long 0x14 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
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|
bitfld.long 0x14 1. "CQPAUSED,Command queue operation is currently paused." "0,1"
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bitfld.long 0x14 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
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|
line.long 0x18 "CQFLAGS,Command Queue Flag"
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|
hexmask.long.word 0x18 16.--31. 1. "CQIRQMASK,Mask the bits used to generate the command queue interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE"
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hexmask.long.word 0x18 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
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|
line.long 0x1C "CQSETCLEAR,Set/Clear the command queue software pause flags on a per-bit basis. Contains 3 fields. allowing for setting. clearing or toggling the value in the software flags. Priority when the same bit"
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hexmask.long.byte 0x1C 16.--23. 1. "CQFCLR,Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field"
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hexmask.long.byte 0x1C 8.--15. 1. "CQFTGL,Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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|
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hexmask.long.byte 0x1C 0.--7. 1. "CQFSET,Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field"
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line.long 0x20 "CQPAUSEEN,Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the CQFLAG register is '1'. CQ processing will halt until either value is changed to '0'."
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hexmask.long.word 0x20 0.--15. 1. "CQPEN,Enables the specified event to pause command processing when active"
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line.long 0x24 "CQCURIDX,Current index value. targeted to be written by register write operations within the command queue. This is compared to the CQENDIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and"
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hexmask.long.byte 0x24 0.--7. 1. "CQCURIDX,Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x28 "CQENDIDX,End index value. targeted to be written by software to indicate the last valid register pair contained within the command queue for a register write operations within the command queue."
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hexmask.long.byte 0x28 0.--7. 1. "CQENDIDX,Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match the IDXEQ pause event will be activated which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN."
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line.long 0x2C "STATUS,IOM Module Status"
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bitfld.long 0x2C 2. "IDLEST,indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to hold-offs from data availability or as the command gets propagated into the logic from the registers." "?,1: The I/O state machine is in the idle state."
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bitfld.long 0x2C 1. "CMDACT,Indicates if the active I/O Command is currently processing a transaction or command is complete but the FIFO pointers are still synchronizing internally. This bit will go high at" "?,1: An I/O command is active. Indicates the active.."
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newline
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bitfld.long 0x2C 0. "ERR,Bit has been deprecated. Please refer to the other error indicators. This will always return 0." "?,1: Bit has been deprecated and will always return 0."
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group.long 0x300++0x3
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line.long 0x0 "MSPICFG,Controls the configuration of the SPI master module. including POL/PHA. LSB. flow control. and delays for MISO and MOSI"
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bitfld.long 0x0 30. "MSPIRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
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bitfld.long 0x0 27.--29. "DOUTDLY,Delay tap to use for the output signal (MOSI). This give more hold time on the output data" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x0 24.--26. "DINDLY,Delay tap to use for the input signal (MISO). This gives more hold time on the input data." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "SPILSB,Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first." "0: Send and receive MSB bit first,1: Send and receive LSB bit first"
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bitfld.long 0x0 22. "RDFCPOL,selects the read flow control signal polarity." "0: Flow control signal high creates flow control.,1: Flow control signal low creates flow control."
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bitfld.long 0x0 21. "WTFCPOL,selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 will allow a IRQ=1 to pause transfers)." "0: Flow control signal high(1) creates flow control..,1: Flow control signal low(0) creates flow control.."
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newline
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bitfld.long 0x0 20. "WTFCIRQ,selects the write mode flow control signal." "0: MISO is used as the write mode flow control..,1: IRQ is used as the write mode flow control signal."
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bitfld.long 0x0 18. "MOSIINV,inverts MOSI when flow control is enabled." "0: MOSI is set to 0 in read mode and 1 in write mode.,1: MOSI is set to 1 in read mode and 0 in write mode."
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newline
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bitfld.long 0x0 17. "RDFC,enables read mode flow control." "0: Read mode flow control disabled.,1: Read mode flow control enabled."
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bitfld.long 0x0 16. "WTFC,enables write mode flow control." "0: Write mode flow control disabled.,1: Write mode flow control enabled."
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newline
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bitfld.long 0x0 2. "FULLDUP,Enables full duplex mode for Master SPI write operations. Data will be captured simultaneously into the read FIFO" "0,1"
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bitfld.long 0x0 1. "SPHA,selects SPI phase." "0: Sample on the leading (first) clock edge.,1: Sample on the trailing (second) clock edge."
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|
newline
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bitfld.long 0x0 0. "SPOL,selects SPI polarity." "0: The base value of the clock is 0.,1: The base value of the clock is 1."
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group.long 0x400++0x7
|
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line.long 0x0 "MI2CCFG,Controls the configuration of the I2C bus master."
|
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bitfld.long 0x0 24. "STRDIS,Disable detection of clock stretch events smaller than 1 cycle" "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "SMPCNT,Number of Base clock cycles to wait before sampling the SCL clock to determine if a clock stretch event has occurred"
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newline
|
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hexmask.long.byte 0x0 12.--15. 1. "SDAENDLY,Number of IOCLK cycles to delay the SDA output en (all transitions affected). Used to delay data relative to clock"
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hexmask.long.byte 0x0 8.--11. 1. "SCLENDLY,Number of IOCLK cycles to delay the rising edge of the SCL output en (clock will go low on this edge). Used to allow clock shaping."
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newline
|
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bitfld.long 0x0 6. "MI2CRST,Not used. To reset the module toggle the SMOD_EN for the module" "0,1"
|
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bitfld.long 0x0 4.--5. "SDADLY,Delay to enable on the SDA output. Values are 0x0-0x3." "0,1,2,3"
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newline
|
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bitfld.long 0x0 2. "ARBEN,Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master this function can be disabled to save clock cycles on I2C transactions" "0: Disable multi-master bus arbitration support for..,1: Enable multi-master bus arbitration support for.."
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bitfld.long 0x0 1. "I2CLSB,Direction of data transmit and receive MSB(0) or LSB(1) first. Default per I2C specification is MSB first. This applies to both read and write data and read data will be bit" "0: Byte data is transmitted MSB first onto the..,1: Byte data is transmitted LSB first onto the.."
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newline
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bitfld.long 0x0 0. "ADDRSZ,Sets the I2C master device address size to either 7 bits (0) or 10 bits (1)." "0: Use 7-bit addressing for I2C master transactions,1: Use 10-bit addressing for I2C master transactions"
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line.long 0x4 "DEVCFG,Contains the I2C device address."
|
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hexmask.long.word 0x4 0.--9. 1. "DEVADDR,I2C address of the device that the Master will use to target for read/write operations. This can be either a 7-bit or 10-bit address."
|
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group.long 0x410++0x3
|
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line.long 0x0 "IOMDBG,Debug control"
|
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hexmask.long 0x0 3.--31. 1. "DBGDATA,Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers."
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bitfld.long 0x0 2. "APBCLKON,APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
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newline
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bitfld.long 0x0 1. "IOCLKON,IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise the clock is controlled with gating from the logic as needed." "0,1"
|
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bitfld.long 0x0 0. "DBGEN,Debug Enable. Setting bit will enable the update of data within this register otherwise it is clock gated for power savings" "0,1"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "IOSLAVE (I2C/SPI Slave)"
|
|
base ad:0x50000000
|
|
group.long 0x100++0x27
|
|
line.long 0x0 "FIFOPTR,Current FIFO Pointer"
|
|
hexmask.long.byte 0x0 8.--15. 1. "FIFOSIZ,The number of bytes currently in the hardware FIFO."
|
|
hexmask.long.byte 0x0 0.--7. 1. "FIFOPTR,Current FIFO pointer."
|
|
line.long 0x4 "FIFOCFG,FIFO Configuration"
|
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hexmask.long.byte 0x4 24.--29. 1. "ROBASE,Defines the read-only area. The IO Slave read-only area is situated in LRAM at (ROBASE*8) to (FIFOBASE*8-1)"
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hexmask.long.byte 0x4 8.--13. 1. "FIFOMAX,These bits hold the maximum FIFO address in 8 byte segments. It is also the beginning of the RAM area of the LRAM. Note that no RAM area is configured if FIFOMAX is set to 0x1F."
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newline
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hexmask.long.byte 0x4 0.--4. 1. "FIFOBASE,These bits hold the base address of the I/O FIFO in 8 byte segments. The IO Slave FIFO is situated in LRAM at (FIFOBASE*8) to (FIFOMAX*8-1)."
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line.long 0x8 "FIFOTHR,FIFO Threshold Configuration"
|
|
hexmask.long.byte 0x8 0.--7. 1. "FIFOTHR,FIFO size interrupt threshold."
|
|
line.long 0xC "FUPD,FIFO Update Status"
|
|
bitfld.long 0xC 1. "IOREAD,This bit field indicates an IO read is active." "0,1"
|
|
bitfld.long 0xC 0. "FIFOUPD,This bit indicates that a FIFO update is underway." "0,1"
|
|
line.long 0x10 "FIFOCTR,Overall FIFO Counter"
|
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hexmask.long.word 0x10 0.--9. 1. "FIFOCTR,Virtual FIFO byte count"
|
|
line.long 0x14 "FIFOINC,Overall FIFO Counter Increment"
|
|
hexmask.long.word 0x14 0.--9. 1. "FIFOINC,Increment the Overall FIFO Counter by this value on a write"
|
|
line.long 0x18 "CFG,I/O Slave Configuration"
|
|
bitfld.long 0x18 31. "IFCEN,IOSLAVE interface enable." "0: Disable the IOSLAVE,1: Enable the IOSLAVE"
|
|
hexmask.long.word 0x18 8.--19. 1. "I2CADDR,7-bit or 10-bit I2C device address."
|
|
newline
|
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bitfld.long 0x18 4. "STARTRD,This bit holds the cycle to initiate an I/O RAM read." "0: Initiate I/O RAM read late in each transferred..,1: Initiate I/O RAM read early in each transferred.."
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bitfld.long 0x18 2. "LSB,This bit selects the transfer bit ordering." "0: Data is assumed to be sent and received with MSB..,1: Data is assumed to be sent and received with LSB.."
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newline
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bitfld.long 0x18 1. "SPOL,This bit selects SPI polarity." "0: Polarity 0 handles SPI modes 0 and 3.,1: Polarity 1 handles SPI modes 1 and 2."
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|
bitfld.long 0x18 0. "IFCSEL,This bit selects the I/O interface." "0: Selects I2C interface for the IO Slave.,1: Selects SPI interface for the IO Slave."
|
|
line.long 0x1C "PRENC,I/O Slave Interrupt Priority Encode"
|
|
hexmask.long.byte 0x1C 0.--4. 1. "PRENC,These bits hold the priority encode of the REGACC interrupts."
|
|
line.long 0x20 "IOINTCTL,I/O Interrupt Control"
|
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hexmask.long.byte 0x20 24.--31. 1. "IOINTSET,These bits set the IOINT interrupts when written with a 1."
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bitfld.long 0x20 16. "IOINTCLR,This bit clears all of the IOINT interrupts when written with a 1." "0,1"
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|
newline
|
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hexmask.long.byte 0x20 8.--15. 1. "IOINT,These bits read the IOINT interrupts."
|
|
hexmask.long.byte 0x20 0.--7. 1. "IOINTEN,These read-only bits indicate whether the IOINT interrupts are enabled."
|
|
line.long 0x24 "GENADD,General Address Data"
|
|
hexmask.long.byte 0x24 0.--7. 1. "GADATA,The data supplied on the last General Address reference."
|
|
group.long 0x200++0x1F
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 9. "XCMPWR,Transfer complete interrupt write to register space." "0,1"
|
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bitfld.long 0x0 8. "XCMPWF,Transfer complete interrupt write to FIFO space." "0,1"
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|
newline
|
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bitfld.long 0x0 7. "XCMPRR,Transfer complete interrupt read from register space." "0,1"
|
|
bitfld.long 0x0 6. "XCMPRF,Transfer complete interrupt read from FIFO space." "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "IOINTW,IO Write interrupt." "0,1"
|
|
bitfld.long 0x0 4. "GENAD,I2C General Address interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FRDERR,FIFO Read Error interrupt." "0,1"
|
|
bitfld.long 0x0 2. "FUNDFL,FIFO Underflow interrupt." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "FOVFL,FIFO Overflow interrupt." "0,1"
|
|
bitfld.long 0x0 0. "FSIZE,FIFO Size interrupt." "0,1"
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 9. "XCMPWR,Transfer complete interrupt write to register space." "0,1"
|
|
bitfld.long 0x4 8. "XCMPWF,Transfer complete interrupt write to FIFO space." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "XCMPRR,Transfer complete interrupt read from register space." "0,1"
|
|
bitfld.long 0x4 6. "XCMPRF,Transfer complete interrupt read from FIFO space." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "IOINTW,IO Write interrupt." "0,1"
|
|
bitfld.long 0x4 4. "GENAD,I2C General Address interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FRDERR,FIFO Read Error interrupt." "0,1"
|
|
bitfld.long 0x4 2. "FUNDFL,FIFO Underflow interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "FOVFL,FIFO Overflow interrupt." "0,1"
|
|
bitfld.long 0x4 0. "FSIZE,FIFO Size interrupt." "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 9. "XCMPWR,Transfer complete interrupt write to register space." "0,1"
|
|
bitfld.long 0x8 8. "XCMPWF,Transfer complete interrupt write to FIFO space." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "XCMPRR,Transfer complete interrupt read from register space." "0,1"
|
|
bitfld.long 0x8 6. "XCMPRF,Transfer complete interrupt read from FIFO space." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "IOINTW,IO Write interrupt." "0,1"
|
|
bitfld.long 0x8 4. "GENAD,I2C General Address interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FRDERR,FIFO Read Error interrupt." "0,1"
|
|
bitfld.long 0x8 2. "FUNDFL,FIFO Underflow interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "FOVFL,FIFO Overflow interrupt." "0,1"
|
|
bitfld.long 0x8 0. "FSIZE,FIFO Size interrupt." "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 9. "XCMPWR,Transfer complete interrupt write to register space." "0,1"
|
|
bitfld.long 0xC 8. "XCMPWF,Transfer complete interrupt write to FIFO space." "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "XCMPRR,Transfer complete interrupt read from register space." "0,1"
|
|
bitfld.long 0xC 6. "XCMPRF,Transfer complete interrupt read from FIFO space." "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "IOINTW,IO Write interrupt." "0,1"
|
|
bitfld.long 0xC 4. "GENAD,I2C General Address interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "FRDERR,FIFO Read Error interrupt." "0,1"
|
|
bitfld.long 0xC 2. "FUNDFL,FIFO Underflow interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "FOVFL,FIFO Overflow interrupt." "0,1"
|
|
bitfld.long 0xC 0. "FSIZE,FIFO Size interrupt." "0,1"
|
|
line.long 0x10 "REGACCINTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
hexmask.long 0x10 0.--31. 1. "REGACC,Register access interrupts."
|
|
line.long 0x14 "REGACCINTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
hexmask.long 0x14 0.--31. 1. "REGACC,Register access interrupts."
|
|
line.long 0x18 "REGACCINTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
hexmask.long 0x18 0.--31. 1. "REGACC,Register access interrupts."
|
|
line.long 0x1C "REGACCINTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
hexmask.long 0x1C 0.--31. 1. "REGACC,Register access interrupts."
|
|
tree.end
|
|
tree "MCUCTRL (MCU Miscellaneous Control Logic)"
|
|
base ad:0x40020000
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CHIPPN,Chip Information Register"
|
|
hexmask.long 0x0 0.--31. 1. "PARTNUM,BCD part number."
|
|
line.long 0x4 "CHIPID0,Unique Chip ID 0"
|
|
hexmask.long 0x4 0.--31. 1. "CHIPID0,Unique chip ID 0."
|
|
line.long 0x8 "CHIPID1,Unique Chip ID 1"
|
|
hexmask.long 0x8 0.--31. 1. "CHIPID1,Unique chip ID 1."
|
|
line.long 0xC "CHIPREV,Chip Revision"
|
|
hexmask.long.word 0xC 8.--19. 1. "SIPART,Silicon Part ID"
|
|
newline
|
|
hexmask.long.byte 0xC 4.--7. 1. "REVMAJ,Major Revision ID."
|
|
newline
|
|
hexmask.long.byte 0xC 0.--3. 1. "REVMIN,Minor Revision ID."
|
|
line.long 0x10 "VENDORID,Unique Vendor ID"
|
|
hexmask.long 0x10 0.--31. 1. "VENDORID,Unique Vendor ID"
|
|
line.long 0x14 "SKU,Unique Chip SKU"
|
|
bitfld.long 0x14 2. "SECBOOT,Secure boot feature allowed" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "ALLOWBLE,Allow BLE feature" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "ALLOWBURST,Allow Burst feature" "0,1"
|
|
line.long 0x18 "FEATUREENABLE,Feature Enable on Burst and BLE"
|
|
bitfld.long 0x18 6. "BURSTAVAIL,Availability of Burst functionality" "0: Burst functionality not available,1: Burst functionality available"
|
|
newline
|
|
bitfld.long 0x18 5. "BURSTACK,ACK for BURSTREQ" "0,1"
|
|
newline
|
|
bitfld.long 0x18 4. "BURSTREQ,Controls the Burst functionality" "0: Disable the Burst functionality,1: Enable the Burst functionality"
|
|
newline
|
|
bitfld.long 0x18 2. "BLEAVAIL,AVAILABILITY of the BLE functionality" "0: BLE functionality not available,1: BLE functionality available"
|
|
newline
|
|
bitfld.long 0x18 1. "BLEACK,ACK for BLEREQ" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "BLEREQ,Controls the BLE functionality" "0: Disable the BLE functionality,1: Enable the BLE functionality"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "DEBUGGER,Debugger Control"
|
|
bitfld.long 0x0 0. "LOCKOUT,Lockout of debugger (SWD)." "0,1"
|
|
sif (cpuis("AMA3B1KK")||cpuis("AMAP31KK"))
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "BODCTRL,BOD control Register"
|
|
bitfld.long 0x0 5. "BODHVREFSEL,BODH External Reference Select. Note: the SWE mux select in PWRSEQ2SWE must be set for this to take effect." "0,1"
|
|
bitfld.long 0x0 4. "BODLVREFSEL,BODL External Reference Select. Note: the SWE mux select in PWRSEQ2SWE must be set for this to take effect." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "BODFPWD,BODF Power Down." "0,1"
|
|
bitfld.long 0x0 2. "BODCPWD,BODC Power Down." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "BODHPWD,BODH Power Down." "0,1"
|
|
bitfld.long 0x0 0. "BODLPWD,BODL Power Down." "0,1"
|
|
group.long 0x280++0x3
|
|
line.long 0x0 "APBDMACTRL,DMA Control Register. Determines misc settings for DMA operation"
|
|
hexmask.long.byte 0x0 8.--15. 1. "HYSTERESIS,This field determines how long the DMA will remain active during deep sleep before shutting down and returning the system to full deep sleep. Values are based on a 94KHz clock and are roughly 10 us increments for a range of ~10 us to 2.55 ms"
|
|
bitfld.long 0x0 1. "DECODEABORT,APB Decode Abort. When set the APB bridge will issue a data abort (bus fault) on transactions to peripherals that are powered down. When set to 0 writes are quietly discarded and reads return 0." "0: Bus operations to powered down peripherals are..,1: Bus operations to powered down peripherals.."
|
|
newline
|
|
bitfld.long 0x0 0. "DMA_ENABLE,Enable the DMA controller. When disabled DMA requests will be ignored by the controller" "0: DMA operations disabled,1: DMA operations enabled"
|
|
endif
|
|
sif (cpuis("AMA3B2KK"))
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "DMASRAMWRITEPROTECT2,These bits write-protect system SRAM from DMA operations in 8KB chunks."
|
|
hexmask.long 0x0 0.--31. 1. "DMA_WPROT2,Write protect SRAM from DMA. Each bit provides write protection for an 8KB region of memory. When set to 1 the region will be protected from DMA writes when set to 0 DMA may write the region."
|
|
group.long 0x364++0x3
|
|
line.long 0x0 "BLEBUCK1,BLEBUCK1 Control Reg"
|
|
hexmask.long.byte 0x0 15.--18. 1. "BLEBUCKPULLUPTRIM,blebuck_pullup_trim"
|
|
group.long 0x3A8++0x7
|
|
line.long 0x0 "FLASHWPROT2,These bits write-protect flash in 16KB chunks."
|
|
hexmask.long 0x0 0.--31. 1. "FW2BITS,Write protect flash 0x00100000 - 0x0017FFFF. Each bit provides write protection for 16KB chunks of flash data space. Bits are cleared by writing a 1 to the bit. When read 0 indicates the region is protected. Bits are sticky (can be set when.."
|
|
line.long 0x4 "FLASHWPROT3,These bits write-protect flash in 16KB chunks."
|
|
hexmask.long 0x4 0.--31. 1. "FW3BITS,Write protect flash 0x00180000 - 0x001FFFFF. Each bit provides write protection for 16KB chunks of flash data space. Bits are cleared by writing a 1 to the bit. When read 0 indicates the region is protected. Bits are sticky (can be set when.."
|
|
group.long 0x3B8++0x7
|
|
line.long 0x0 "FLASHRPROT2,These bits read-protect flash in 16KB chunks."
|
|
hexmask.long 0x0 0.--31. 1. "FR2BITS,Copy (read) protect flash 0x00100000 - 0x0017FFFF. Each bit provides read protection for 16KB chunks of flash. Bits are cleared by writing a 1 to the bit. When read 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK.."
|
|
line.long 0x4 "FLASHRPROT3,These bits read-protect flash in 16KB chunks."
|
|
hexmask.long 0x4 0.--31. 1. "FR3BITS,Copy (read) protect flash 0x00180000 - 0x001FFFFF. Each bit provides read protection for 16KB chunks of flash. Bits are cleared by writing a 1 to the bit. When read 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK.."
|
|
endif
|
|
group.long 0x104++0x3
|
|
line.long 0x0 "ADCPWRDLY,ADC Power Up Delay Control"
|
|
hexmask.long.byte 0x0 8.--15. 1. "ADCPWR1,ADC Reference Keeper enable delay in 16 ADC CLK increments for ADC_CLKSEL = 0x1 8 ADC CLOCK increments for ADC_CLKSEL = 0x2."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "ADCPWR0,ADC Reference Buffer Power Enable delay in 64 ADC CLK increments for ADC_CLKSEL = 0x1 32 ADC CLOCK increments for ADC_CLKSEL = 0x2."
|
|
group.long 0x10C++0x7
|
|
line.long 0x0 "ADCCAL,ADC Calibration Control"
|
|
bitfld.long 0x0 1. "ADCCALIBRATED,Status for ADC Calibration" "0: ADC is not calibrated,1: ADC is calibrated"
|
|
newline
|
|
bitfld.long 0x0 0. "CALONPWRUP,Run ADC Calibration on initial power up sequence" "0: Disable automatic calibration on initial power up,1: Enable automatic calibration on initial power up"
|
|
line.long 0x4 "ADCBATTLOAD,ADC Battery Load Enable"
|
|
bitfld.long 0x4 0. "BATTLOAD,Enable the ADC battery load resistor" "0: Battery load is disconnected,1: Battery load is enabled"
|
|
group.long 0x118++0xF
|
|
line.long 0x0 "ADCTRIM,ADC Trims"
|
|
bitfld.long 0x0 11.--12. "ADCRFBUFIBTRIM,ADC reference buffer input bias trim" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 6.--10. 1. "ADCREFBUFTRIM,ADC Reference buffer trim"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "ADCREFKEEPIBTRIM,ADC Reference Ibias trim" "0,1,2,3"
|
|
line.long 0x4 "ADCREFCOMP,ADC Reference Keeper and Comparator Control"
|
|
bitfld.long 0x4 16. "ADCRFCMPEN,ADC Reference comparator power down" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--12. 1. "ADCREFKEEPTRIM,ADC Reference Keeper Trim"
|
|
newline
|
|
bitfld.long 0x4 0. "ADC_REFCOMP_OUT,Output of the ADC reference comparator" "0,1"
|
|
line.long 0x8 "XTALCTRL,XTAL Oscillator Control"
|
|
bitfld.long 0x8 8.--9. "XTALICOMPTRIM,XTAL ICOMP trim" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 6.--7. "XTALIBUFTRIM,XTAL IBUFF trim" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 5. "PWDBODXTAL,XTAL Power down on brown out." "0: Power up XTAL on BOD.,1: Power down XTAL on BOD."
|
|
newline
|
|
bitfld.long 0x8 4. "PDNBCMPRXTAL,XTAL Oscillator Power Down Comparator." "0: Power down XTAL oscillator comparator.,1: Power up XTAL oscillator comparator."
|
|
newline
|
|
bitfld.long 0x8 3. "PDNBCOREXTAL,XTAL Oscillator Power Down Core." "0: Power down XTAL oscillator core.,1: Power up XTAL oscillator core."
|
|
newline
|
|
bitfld.long 0x8 2. "BYPCMPRXTAL,XTAL Oscillator Bypass Comparator." "0: Use the XTAL oscillator comparator.,1: Bypass the XTAL oscillator comparator."
|
|
newline
|
|
bitfld.long 0x8 1. "FDBKDSBLXTAL,XTAL Oscillator Disable Feedback." "0: Enable XTAL oscillator comparator.,1: Disable XTAL oscillator comparator."
|
|
newline
|
|
bitfld.long 0x8 0. "XTALSWE,XTAL Software Override Enable." "0: XTAL Software Override Disable.,1: XTAL Software Override Enable."
|
|
line.long 0xC "XTALGENCTRL,XTAL Oscillator General Control"
|
|
hexmask.long.byte 0xC 8.--13. 1. "XTALKSBIASTRIM,XTAL IBIAS Kick start trim. This trim value is used during the startup process to enable a faster lock."
|
|
newline
|
|
hexmask.long.byte 0xC 2.--7. 1. "XTALBIASTRIM,XTAL BIAS trim"
|
|
newline
|
|
bitfld.long 0xC 0.--1. "ACWARMUP,Auto-calibration delay control" "0: Warm-up period of 1-2 seconds,1: Warm-up period of 2-4 seconds,2: Warm-up period of 4-8 seconds,3: Warm-up period of 8-16 seconds"
|
|
group.long 0x198++0x3
|
|
line.long 0x0 "MISCCTRL,Miscellaneous control register."
|
|
bitfld.long 0x0 5. "BLE_RESETN,BLE reset signal." "0,1"
|
|
newline
|
|
sif (cpuis("AMA3B1KK")||cpuis("AMAP31KK"))
|
|
hexmask.long.byte 0x0 0.--4. 1. "RESERVED_RW_0,Reserved bits always leave unchanged. The MISCCTRL register must be modified via atomic RMW leaving this bit field completely unmodified. Failure to do so will result in unpredictable behavior."
|
|
endif
|
|
group.long 0x1A0++0x7
|
|
line.long 0x0 "BOOTLOADER,Bootloader and secure boot functions"
|
|
bitfld.long 0x0 30.--31. "SECBOOTONRST,Indicates whether the secure boot on warm reset is enabled" "0: Secure boot disabled,1: Secure boot enabled,2: Error in secure boot configuration,?"
|
|
newline
|
|
bitfld.long 0x0 28.--29. "SECBOOT,Indicates whether the secure boot on cold reset is enabled" "0: Secure boot disabled,1: Secure boot enabled,2: Error in secure boot configuration,?"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "SECBOOTFEATURE,Indicates whether the secure boot feature is enabled." "0: Secure boot disabled,1: Secure boot enabled,2: Error in secure boot configuration,?"
|
|
newline
|
|
bitfld.long 0x0 2. "PROTLOCK,Flash protection lock. Always resets to 1 write 1 to clear. Enables writes to flash protection register set." "?,1: Enable the secure boot lock"
|
|
newline
|
|
bitfld.long 0x0 1. "SBLOCK,Secure boot lock. Always resets to 1 write 1 to clear. Enables system visibility to bootloader until set." "?,1: Enable the secure boot lock"
|
|
newline
|
|
bitfld.long 0x0 0. "BOOTLOADERLOW,Determines whether the bootloader code is visible at address 0x00000000 or not. Resets to 1 write 1 to clear." "?,1: Bootloader code at 0x00000000."
|
|
line.long 0x4 "SHADOWVALID,Register to indicate whether the shadow registers have been successfully loaded from the Flash Information Space."
|
|
bitfld.long 0x4 2. "INFO0_VALID,Indicates whether INFO0 contains valid data" "?,1: Flash INFO0 (customer) space contains valid data."
|
|
newline
|
|
bitfld.long 0x4 1. "BLDSLEEP,Indicates whether the bootloader should sleep or deep sleep if no image loaded." "?,1: Bootloader will go to deep sleep if no flash.."
|
|
newline
|
|
bitfld.long 0x4 0. "VALID,Indicates whether the shadow registers contain valid data from the Flash Information Space." "?,1: Flash information space contains valid data."
|
|
group.long 0x1B0++0x7
|
|
line.long 0x0 "SCRATCH0,Scratch register that is not reset by any reset"
|
|
hexmask.long 0x0 0.--31. 1. "SCRATCH0,Scratch register 0."
|
|
line.long 0x4 "SCRATCH1,Scratch register that is not reset by any reset"
|
|
hexmask.long 0x4 0.--31. 1. "SCRATCH1,Scratch register 1."
|
|
group.long 0x1C0++0x13
|
|
line.long 0x0 "ICODEFAULTADDR,ICODE bus address which was present when a bus fault occurred."
|
|
hexmask.long 0x0 0.--31. 1. "ICODEFAULTADDR,The ICODE bus address observed when a Bus Fault occurred. Once an address is captured in this field it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register."
|
|
line.long 0x4 "DCODEFAULTADDR,DCODE bus address which was present when a bus fault occurred."
|
|
hexmask.long 0x4 0.--31. 1. "DCODEFAULTADDR,The DCODE bus address observed when a Bus Fault occurred. Once an address is captured in this field it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register."
|
|
line.long 0x8 "SYSFAULTADDR,System bus address which was present when a bus fault occurred."
|
|
hexmask.long 0x8 0.--31. 1. "SYSFAULTADDR,SYS bus address observed when a Bus Fault occurred. Once an address is captured in this field it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register."
|
|
line.long 0xC "FAULTSTATUS,Reflects the status of the bus decoders' fault detection. Any write to this register will clear all of the status bits within the register."
|
|
bitfld.long 0xC 2. "SYSFAULT,SYS Bus Decoder Fault Detected bit. When set a fault has been detected and the SYSFAULTADDR register will contain the bus address which generated the fault." "0: No bus fault has been detected.,1: Bus fault detected."
|
|
newline
|
|
bitfld.long 0xC 1. "DCODEFAULT,DCODE Bus Decoder Fault Detected bit. When set a fault has been detected and the DCODEFAULTADDR register will contain the bus address which generated the fault." "0: No DCODE fault has been detected.,1: DCODE fault detected."
|
|
newline
|
|
bitfld.long 0xC 0. "ICODEFAULT,The ICODE Bus Decoder Fault Detected bit. When set a fault has been detected and the ICODEFAULTADDR register will contain the bus address which generated the fault." "0: No ICODE fault has been detected.,1: ICODE fault detected."
|
|
line.long 0x10 "FAULTCAPTUREEN,Enable the fault capture registers"
|
|
bitfld.long 0x10 0. "FAULTCAPTUREEN,Fault Capture Enable field. When set the Fault Capture monitors are enabled and addresses which generate a hard fault are captured into the FAULTADDR registers." "0: Disable fault capture.,1: Enable fault capture."
|
|
group.long 0x200++0x7
|
|
line.long 0x0 "DBGR1,Read-only debug register 1"
|
|
hexmask.long 0x0 0.--31. 1. "ONETO8,Read-only register for communication validation"
|
|
line.long 0x4 "DBGR2,Read-only debug register 2"
|
|
hexmask.long 0x4 0.--31. 1. "COOLCODE,Read-only register for communication validation"
|
|
group.long 0x220++0x3
|
|
line.long 0x0 "PMUENABLE,Control bit to enable/disable the PMU"
|
|
bitfld.long 0x0 0. "ENABLE,PMU Enable Control bit. When set the MCU's PMU will place the MCU into the lowest power consuming Deep Sleep mode upon execution of a WFI instruction (dependent on the setting of the SLEEPDEEP bit in the ARM SCR register). When cleared .." "0: Disable MCU power management.,1: Enable MCU power management."
|
|
group.long 0x250++0x3
|
|
line.long 0x0 "TPIUCTRL,TPIU Control Register. Determines the clock enable and frequency for the M4's TPIU interface."
|
|
bitfld.long 0x0 8.--10. "CLKSEL,This field selects the frequency of the ARM M4 TPIU port." "0: Low power state.,1: Selects HFRC divided by 2 as the source TPIU clock,2: Selects HFRC divided by 8 as the source TPIU clock,3: Selects HFRC divided by 16 as the source TPIU..,4: Selects HFRC divided by 32 as the source TPIU..,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 0. "ENABLE,TPIU Enable field. When set the ARM M4 TPIU is enabled and data can be streamed out of the MCU's SWO port using the ARM ITM and TPIU modules." "0: Disable the TPIU.,1: Enable the TPIU."
|
|
group.long 0x264++0x3
|
|
line.long 0x0 "OTAPOINTER,OTA (Over the Air) Update Pointer/Status. Reset only by POA"
|
|
hexmask.long 0x0 2.--31. 1. "OTAPOINTER,Flash page pointer with updated OTA image"
|
|
newline
|
|
bitfld.long 0x0 1. "OTASBLUPDATE,Indicates that the sbl_init has been updated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "OTAVALID,Indicates that an OTA update is valid" "0,1"
|
|
group.long 0x284++0x3
|
|
line.long 0x0 "SRAMMODE,SRAM Controller mode bits"
|
|
bitfld.long 0x0 5. "DPREFETCH_CACHE,Secondary pre-fetch feature that will cache pre-fetched data across bus wait states (requires DPREFETCH to be set)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "DPREFETCH,When set data bus accesses to the SRAM banks will be pre-fetched (normally 2 cycle read access). Use of this mode bit is only recommended if the work flow has a large number of sequential accesses." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "IPREFETCH_CACHE,Secondary pre-fetch feature that will cache pre-fetched data across bus wait states (requires IPREFETCH to be set)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IPREFETCH,When set instruction accesses to the SRAM banks will be pre-fetched (normally 2 cycle read access). Generally this mode bit should be set for improved performance when executing instructions from SRAM." "0,1"
|
|
group.long 0x348++0x3
|
|
line.long 0x0 "KEXTCLKSEL,Locks the state of the EXTCLKSEL register from writes. This is done to prevent errant writes to the register. as this could cause the chip to halt. Write a value of 0x53 to unlock write access to the EXTCLKSEL register. Once unlocked. the.."
|
|
hexmask.long 0x0 0.--31. 1. "KEXTCLKSEL,Key register value."
|
|
group.long 0x350++0xF
|
|
line.long 0x0 "SIMOBUCK1,SIMO Buck Control Reg 1"
|
|
hexmask.long.byte 0x0 28.--31. 1. "CORETEMPCOTRIM,simobuck_core_tempco_trim"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--27. 1. "SIMOBUCKMEMLPTRIM,simobuck_mem_lp_trim"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "MEMACTIVETRIM,simobuck_mem_active_trim (VDDC)"
|
|
newline
|
|
hexmask.long.byte 0x0 10.--15. 1. "SIMOBUCKCORELPTRIM,simobuck_core_lp_trim"
|
|
newline
|
|
hexmask.long.word 0x0 0.--9. 1. "COREACTIVETRIM,simobuck_core_active_trim (VDDF)"
|
|
line.long 0x4 "SIMOBUCK2,SIMO Buck Control Reg 2"
|
|
sif (cpuis("AMA3B1KK")||cpuis("AMAP31KK"))
|
|
bitfld.long 0x4 30.--31. "RESERVED_RW_30,Reserved bits always leave unchanged. The SIMOBUCK2 register must be modified via atomic RMW leaving this bit field completely unmodified. Failure to do so will result in unpredictable behavior." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 24.--27. 1. "RESERVED_RW_24,Reserved bits always leave unchanged. The SIMOBUCK2 register must be modified via atomic RMW leaving this bit field completely unmodified. Failure to do so will result in unpredictable behavior."
|
|
newline
|
|
hexmask.long.word 0x4 5.--15. 1. "RESERVED_RW_5,Reserved bits always leave unchanged. The SIMOBUCK2 register must be modified via atomic RMW leaving this bit field completely unmodified. Failure to do so will result in unpredictable behavior."
|
|
newline
|
|
endif
|
|
bitfld.long 0x4 28.--29. "SIMOBUCKCORELEAKAGETRIM,simobuck_core_leakage_trim" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--23. 1. "SIMOBUCKCORELPLOWTONTRIM,simobuck_core_lp_low_ton_trim"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--19. 1. "SIMOBUCKCORELPHIGHTONTRIM,simobuck_core_lp_high_ton_trim"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "SIMOBUCKTONGENTRIM,simobuck_tongen_trim"
|
|
line.long 0x8 "SIMOBUCK3,SIMO Buck Control Reg 3"
|
|
sif (cpuis("AMA3B1KK")||cpuis("AMAP31KK"))
|
|
bitfld.long 0x8 31. "RESERVED_RW_31,Reserved bits always leave unchanged. The SIMOBUCK2 register must be modified via atomic RMW leaving this bit field completely unmodified. Failure to do so will result in unpredictable behavior." "0,1"
|
|
newline
|
|
hexmask.long.word 0x8 16.--26. 1. "RESERVED_RW_16,Reserved bits always leave unchanged. The SIMOBUCK3 register must be modified via atomic RMW leaving this bit field completely unmodified. Failure to do so will result in unpredictable behavior."
|
|
newline
|
|
endif
|
|
hexmask.long.byte 0x8 27.--30. 1. "SIMOBUCKMEMLPHIGHTONTRIM,simobuck_mem_lp_high_ton_trim"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--15. 1. "SIMOBUCKMEMLPLOWTOFFTRIM,simobuck_mem_lp_low_toff_trim"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "SIMOBUCKMEMLPHIGHTOFFTRIM,simobuck_mem_lp_high_toff_trim"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "SIMOBUCKCORELPLOWTOFFTRIM,simobuck_core_lp_low_toff_trim"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "SIMOBUCKCORELPHIGHTOFFTRIM,simobuck_core_lp_high_toff_trim"
|
|
line.long 0xC "SIMOBUCK4,SIMO Buck Control Reg 4"
|
|
bitfld.long 0xC 24. "SIMOBUCKCOMP2TIMEOUTEN,simobuck_comp2_timeout_en" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "SIMOBUCKCOMP2LPEN,simobuck_comp2_lp_en" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21.--22. "SIMOBUCKCLKDIVSEL,simobuck_clkdiv_sel" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--3. 1. "SIMOBUCKMEMLPLOWTONTRIM,simobuck_mem_lp_low_ton_trim"
|
|
group.long 0x368++0x3
|
|
line.long 0x0 "BLEBUCK2,BLEBUCK2 Control Reg"
|
|
hexmask.long.byte 0x0 12.--17. 1. "BLEBUCKTOND2ATRIM,blebuck_ton_trim"
|
|
newline
|
|
hexmask.long.byte 0x0 6.--11. 1. "BLEBUCKTONHITRIM,blebuck_ton_hi_trim"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "BLEBUCKTONLOWTRIM,blebuck_ton_low_trim"
|
|
group.long 0x3A0++0x7
|
|
line.long 0x0 "FLASHWPROT0,These bits write-protect flash in 16KB chunks."
|
|
hexmask.long 0x0 0.--31. 1. "FW0BITS,Write protect flash 0x00000000 - 0x0007FFFF. Each bit provides write protection for 16KB chunks of flash data space. Bits are cleared by writing a 1 to the bit. When read 0 indicates the region is protected. Bits are sticky (can be set when.."
|
|
line.long 0x4 "FLASHWPROT1,These bits write-protect flash in 16KB chunks."
|
|
hexmask.long 0x4 0.--31. 1. "FW1BITS,Write protect flash 0x00080000 - 0x000FFFFF. Each bit provides write protection for 16KB chunks of flash data space. Bits are cleared by writing a 1 to the bit. When read 0 indicates the region is protected. Bits are sticky (can be set when.."
|
|
group.long 0x3B0++0x7
|
|
line.long 0x0 "FLASHRPROT0,These bits read-protect flash in 16KB chunks."
|
|
hexmask.long 0x0 0.--31. 1. "FR0BITS,Copy (read) protect flash 0x00000000 - 0x0007FFFF. Each bit provides read protection for 16KB chunks of flash. Bits are cleared by writing a 1 to the bit. When read 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK.."
|
|
line.long 0x4 "FLASHRPROT1,These bits read-protect flash in 16KB chunks."
|
|
hexmask.long 0x4 0.--31. 1. "FR1BITS,Copy (read) protect flash 0x00080000 - 0x000FFFFF. Each bit provides read protection for 16KB chunks of flash. Bits are cleared by writing a 1 to the bit. When read 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK.."
|
|
group.long 0x3C0++0x7
|
|
line.long 0x0 "DMASRAMWRITEPROTECT0,These bits write-protect system SRAM from DMA operations in 8KB chunks."
|
|
hexmask.long 0x0 0.--31. 1. "DMA_WPROT0,Write protect SRAM from DMA. Each bit provides write protection for an 8KB region of memory. When set to 1 the region will be protected from DMA writes when set to 0 DMA may write the region."
|
|
line.long 0x4 "DMASRAMWRITEPROTECT1,These bits write-protect system SRAM from DMA operations in 8KB chunks."
|
|
sif (cpuis("AMA3B1KK")||cpuis("AMAP31KK"))
|
|
hexmask.long.word 0x4 0.--15. 1. "DMA_WPROT1,Write protect SRAM from DMA. Each bit provides write protection for an 8KB region of memory. When set to 1 the region will be protected from DMA writes when set to 0 DMA may write the region."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA3B2KK"))
|
|
hexmask.long 0x4 0.--31. 1. "DMA_WPROT1,Write protect SRAM from DMA. Each bit provides write protection for an 8KB region of memory. When set to 1 the region will be protected from DMA writes when set to 0 DMA may write the region."
|
|
endif
|
|
group.long 0x3D0++0x7
|
|
line.long 0x0 "DMASRAMREADPROTECT0,These bits read-protect system SRAM from DMA operations in 8KB chunks."
|
|
hexmask.long 0x0 0.--31. 1. "DMA_RPROT0,Read protect SRAM from DMA. Each bit provides write protection for an 8KB region of memory. When set to 1 the region will be protected from DMA reads when set to 0 DMA may read the region."
|
|
line.long 0x4 "DMASRAMREADPROTECT1,These bits read-protect system SRAM from DMA operations in 8KB chunks."
|
|
sif (cpuis("AMA3B1KK")||cpuis("AMAP31KK"))
|
|
hexmask.long.word 0x4 0.--15. 1. "DMA_RPROT1,Read protect SRAM from DMA. Each bit provides write protection for an 8KB region of memory. When set to 1 the region will be protected from DMA reads when set to 0 DMA may read the region."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA3B2KK"))
|
|
hexmask.long 0x4 0.--31. 1. "DMA_RPROT1,Read protect SRAM from DMA. Each bit provides write protection for an 8KB region of memory. When set to 1 the region will be protected from DMA reads when set to 0 DMA may read the region."
|
|
endif
|
|
sif (cpuis("AMA3B2KK"))
|
|
group.long 0x3D8++0x3
|
|
line.long 0x0 "DMASRAMREADPROTECT2,These bits read-protect system SRAM from DMA operations in 8KB chunks."
|
|
hexmask.long 0x0 0.--31. 1. "DMA_RPROT2,Read protect SRAM from DMA. Each bit provides write protection for an 8KB region of memory. When set to 1 the region will be protected from DMA reads when set to 0 DMA may read the region."
|
|
endif
|
|
tree.end
|
|
tree "MSPI (Multi-bit SPI Master)"
|
|
base ad:0x0
|
|
sif (cpuis("AMA3B1KK")||cpuis("AMAP31KK"))
|
|
tree "MSPI"
|
|
base ad:0x50014000
|
|
group.long 0x0++0x23
|
|
line.long 0x0 "CTRL,This register is used to enable individual PIO based transactions to a device on the bus. The CFG register must be programmed properly for the transfer. and the ADDR and INSTR registers should be programmed if the SENDI and SENDA fields are enabled."
|
|
hexmask.long.word 0x0 16.--31. 1. "XFERBYTES,Number of bytes to transmit or receive (based on TXRX bit)"
|
|
bitfld.long 0x0 11. "PIOSCRAMBLE,Enables data scrambling for PIO operations. This should only be used for data operations and never for commands to a device." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "TXRX,1 Indicates a TX operation 0 indicates an RX operation of XFERBYTES" "0,1"
|
|
bitfld.long 0x0 9. "SENDI,Indicates whether an instruction phase should be sent (see INSTR field and ISIZE field in CFG register)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "SENDA,Indicates whether an address phase should be sent (see ADDR register and ASIZE field in CFG register)" "0,1"
|
|
bitfld.long 0x0 7. "ENTURN,Indicates whether TX->RX turnaround cycles should be enabled for this operation (see TURNAROUND field in CFG register)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "BIGENDIAN,1 indicates data in FIFO is in big endian format (MSB first); 0 indicates little endian data (default LSB first)." "0,1"
|
|
bitfld.long 0x0 3. "QUADCMD,Flag indicating that the operation is a command that should be replicated to both devices in paired QUAD mode. This is typically only used when reading/writing configuration registers in paired flash devices (do not set for memory transfers)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "BUSY,Command status: 1 indicates controller is busy (command in progress)" "0,1"
|
|
bitfld.long 0x0 1. "STATUS,Command status: 1 indicates command has completed. Cleared by writing 1 to this bit or starting a new transfer." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Write to 1 to initiate a PIO transaction on the bus (typically the entire register should be written at once with this bit set)." "0,1"
|
|
line.long 0x4 "CFG,Command formatting for PIO based transactions (initiated by writes to CTRL register)"
|
|
bitfld.long 0x4 17. "CPOL,Serial clock polarity." "0: Clock inactive state is low.,1: Clock inactive state is high."
|
|
bitfld.long 0x4 16. "CPHA,Serial clock phase." "0: Clock toggles in middle of data bit.,1: Clock toggles at start of data bit."
|
|
newline
|
|
hexmask.long.byte 0x4 8.--13. 1. "TURNAROUND,Number of turnaround cycles (for TX->RX transitions). Qualified by ENTURN or XIPENTURN bit field."
|
|
bitfld.long 0x4 7. "SEPIO,Separate IO configuration. This bit should be set when the target device has separate MOSI and MISO pins. Respective IN/OUT bits below should be set to map pins." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "ISIZE,Instruction Size" "0,1"
|
|
bitfld.long 0x4 4.--5. "ASIZE,Address Size. Address bytes to send from ADDR register" "0: Send one address byte,1: Send two address bytes,2: Send three address bytes,3: Send four address bytes"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DEVCFG,Flash configuration for XIP and AUTO DMA operations. Controls value for SER (Slave Enable) for XIP operations and address generation for DMA/XIP modes. Also used to configure SPIFRF (frame format)."
|
|
line.long 0x8 "ADDR,Optional Address field to send for PIO transfers"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,Optional Address field to send (after optional instruction field) - qualified by ASIZE in CMD register. NOTE: This register is aliased to DMADEVADDR."
|
|
line.long 0xC "INSTR,Optional Instruction field to send for PIO transfers"
|
|
hexmask.long.word 0xC 0.--15. 1. "INSTR,Optional Instruction field to send (1st byte) - qualified by ISEND/ISIZE"
|
|
line.long 0x10 "TXFIFO,TX Data FIFO"
|
|
hexmask.long 0x10 0.--31. 1. "TXFIFO,Data to be transmitted. Data should normally be aligned to the LSB (pad the upper bits with zeros) unless BIGENDIAN is set."
|
|
line.long 0x14 "RXFIFO,RX Data FIFO"
|
|
hexmask.long 0x14 0.--31. 1. "RXFIFO,Receive data. Data is aligned to the LSB (padded zeros on upper bits) unless BIGENDIAN is set."
|
|
line.long 0x18 "TXENTRIES,Number of words in TX FIFO"
|
|
hexmask.long.byte 0x18 0.--4. 1. "TXENTRIES,Number of 32-bit words/entries in TX FIFO"
|
|
line.long 0x1C "RXENTRIES,Number of words in RX FIFO"
|
|
hexmask.long.byte 0x1C 0.--4. 1. "RXENTRIES,Number of 32-bit words/entries in RX FIFO"
|
|
line.long 0x20 "THRESHOLD,Threshold levels that trigger RXFull and TXEmpty interrupts"
|
|
hexmask.long.byte 0x20 8.--12. 1. "RXTHRESH,Number of entries in TX FIFO that cause RXE interrupt"
|
|
hexmask.long.byte 0x20 0.--4. 1. "TXTHRESH,Number of entries in TX FIFO that cause TXF interrupt"
|
|
group.long 0x100++0xF
|
|
line.long 0x0 "MSPICFG,Timing configuration bits for the MSPI module. PRSTN. IPRSTN. and FIFORESET can be used to reset portions of the MSPI interface in order to clear error conditions. The remaining bits control clock frequency and TX/RX capture timings."
|
|
bitfld.long 0x0 31. "PRSTN,Peripheral reset. Master reset to the entire MSPI module (DMA XIP and transfer state machines). 1=normal operation 0=in reset." "0: in reset,1: normal operation"
|
|
bitfld.long 0x0 30. "IPRSTN,IP block reset. Write to 0 to put the transfer module in reset or 1 for normal operation. This may be required after error conditions to clear the transfer on the bus." "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "FIFORESET,Reset MSPI FIFO (active high). 1=reset FIFO 0=normal operation. May be used to manually flush the FIFO in error handling." "0: normal operation,1: reset FIFO"
|
|
hexmask.long.byte 0x0 8.--13. 1. "CLKDIV,Clock Divider. Allows dividing 48 MHz base clock by integer multiples. Enumerations are provided for common frequency but any integer divide from 48 MHz is allowed. Odd divide ratios will result in a 33/66 percent duty cycle with a long low clock.."
|
|
newline
|
|
bitfld.long 0x0 4.--6. "IOMSEL,Selects which IOM is selected for CQ handshake status." "0: Select IOM0,1: Select IOM1,2: Select IOM2,3: Select IOM3,4: Select IOM4,5: Select IOM5,?,7: No IOM selected. Signals always zero."
|
|
bitfld.long 0x0 3. "TXNEG,Launches TX data a half clock cycle (~10 ns) early. This should normally be programmed to zero (NORMAL)." "0: TX launched from posedge internal clock,1: TX data launched from negedge of internal clock"
|
|
newline
|
|
bitfld.long 0x0 2. "RXNEG,Adjusts the RX capture phase to the negedge of the 48MHz internal clock (~10 ns early). For normal operation it is expected that RXNEG will be set to 0." "0: RX data sampled on posedge of internal clock,1: RX data sampled on negedge of internal clock"
|
|
bitfld.long 0x0 1. "RXCAP,Controls RX data capture phase. A setting of 0 (NORMAL) captures read data at the normal capture point relative to the internal clock launch point. However to accommodate chip/pad/board delays a setting of RXCAP of 1 is expected to be used to.." "0: RX Capture phase aligns with CPHA setting,1: RX Capture phase is delayed from CPHA setting by.."
|
|
newline
|
|
bitfld.long 0x0 0. "APBCLK,Enable continuous APB clock. For power-efficient operation APBCLK should be set to 0." "0: Disable continuous clock.,1: Enable continuous clock."
|
|
line.long 0x4 "PADCFG,Configuration bits for the MSPI pads. Allows pads associated with the upper quad to be mapped to corresponding bits on the lower quad. Use of Quad0 pins is recommended for optimal timing."
|
|
bitfld.long 0x4 21. "REVCS,Reverse CS connections. Allows CS1 to be associated with lower data lanes and CS0 to be associated with upper data lines" "0,1"
|
|
bitfld.long 0x4 20. "IN3,Data Input pad 3 pin muxing: 0=pad[3] 1=pad[7]" "0: pad[3] 1=pad[7],?"
|
|
newline
|
|
bitfld.long 0x4 19. "IN2,Data Input pad 2 pin muxing: 0=pad[2] 1=pad[6]" "0: pad[2] 1=pad[6],?"
|
|
bitfld.long 0x4 18. "IN1,Data Input pad 1 pin muxing: 0=pad[1] 1=pad[5]" "0: pad[1] 1=pad[5],?"
|
|
newline
|
|
bitfld.long 0x4 16.--17. "IN0,Data Input pad 0 pin muxing: 0=pad[0] 1=pad[4] 2=pad[1] 3=pad[5]" "0: pad[0] 1=pad[4] 2=pad[1] 3=pad[5],?,?,?"
|
|
bitfld.long 0x4 4. "OUT7,Output pad 7 configuration. 0=data[7] 1=data[3]" "0: data[7] 1=data[3],?"
|
|
newline
|
|
bitfld.long 0x4 3. "OUT6,Output pad 6 configuration. 0=data[6] 1=data[2]" "0: data[6] 1=data[2],?"
|
|
bitfld.long 0x4 2. "OUT5,Output pad 5 configuration. 0=data[5] 1=data[1]" "0: data[5] 1=data[1],?"
|
|
newline
|
|
bitfld.long 0x4 1. "OUT4,Output pad 4 configuration. 0=data[4] 1=data[0]" "0: data[4] 1=data[0],?"
|
|
bitfld.long 0x4 0. "OUT3,Output pad 3 configuration. 0=data[3] 1=CLK" "0: data[3] 1=CLK,?"
|
|
line.long 0x8 "PADOUTEN,Enable bits for the MSPI output pads. Each active MSPI line should be set to 1 in the OUTEN field below."
|
|
hexmask.long.word 0x8 0.--8. 1. "OUTEN,Output pad enable configuration. Indicates which pads should be driven. Bits [3:0] are Quad0 data [7:4] are Quad1 data and [8] is clock."
|
|
line.long 0xC "FLASH,When any SPI flash is configured. this register must be properly programmed before XIP or AUTO DMA operations commence."
|
|
hexmask.long.byte 0xC 24.--31. 1. "READINSTR,Read command sent to flash for DMA/XIP operations"
|
|
hexmask.long.byte 0xC 16.--23. 1. "WRITEINSTR,Write command sent for DMA operations"
|
|
newline
|
|
bitfld.long 0xC 8.--10. "XIPMIXED,Provides override controls for data operations where instruction address and data may transfer in different rates." "0: Transfers all proceed using the settings in..,1: Data operations proceed in dual data rate,?,3: Address and Data operations proceed in dual data..,?,5: Data operations proceed in quad data rate,?,7: Address and Data operations proceed in quad data.."
|
|
bitfld.long 0xC 7. "XIPSENDI,Indicates whether XIP/AUTO DMA operations should send an instruction (see READINSTR field and ISIZE field in CFG)" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "XIPSENDA,Indicates whether XIP/AUTO DMA operations should send an an address phase (see DMADEVADDR register and ASIZE field in CFG)" "0,1"
|
|
bitfld.long 0xC 5. "XIPENTURN,Indicates whether XIP/AUTO DMA operations should enable TX->RX turnaround cycles" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "XIPBIGENDIAN,Indicates whether XIP/AUTO DMA data transfers are in big or little endian format" "0,1"
|
|
bitfld.long 0xC 2.--3. "XIPACK,Controls transmission of Micron XIP acknowledge cycles (Micron Flash devices only)" "0: No acknowledgment sent. Data IOs are tri-stated..,?,2: Positive acknowledgment sent. Data IOs are..,3: Negative acknowledgment sent. Data IOs are.."
|
|
newline
|
|
bitfld.long 0xC 0. "XIPEN,Enable the XIP (eXecute In Place) function which effectively enables the address decoding of the MSPI device in the flash/cache address space at address 0x04000000-0x07FFFFFF." "0,1"
|
|
group.long 0x120++0x3
|
|
line.long 0x0 "SCRAMBLING,Enables data scrambling for the specified range external flash addresses. Scrambling does not impact flash access performance."
|
|
bitfld.long 0x0 31. "SCRENABLE,Enables Data Scrambling Region. When 1 reads and writes to the range will be scrambled. When 0 data will be read/written unmodified. Address range is specified in 64K granularity and the START/END ranges are included within the range." "0,1"
|
|
hexmask.long.word 0x0 16.--25. 1. "SCREND,Scrambling region end address [25:16] (64K block granularity). The END block is the LAST block included in the scrambled address range."
|
|
newline
|
|
hexmask.long.word 0x0 0.--9. 1. "SCRSTART,Scrambling region start address [25:16] (64K block granularity). The START block is the FIRST block included in the scrambled address range."
|
|
group.long 0x200++0xF
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
|
|
bitfld.long 0x0 11. "CQERR,Command Queue Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "CQPAUSED,Command Queue is Paused." "0,1"
|
|
bitfld.long 0x0 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
|
|
bitfld.long 0x0 7. "DERR,DMA Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "DCMP,DMA Complete Interrupt" "0,1"
|
|
bitfld.long 0x0 5. "RXF,Receive FIFO full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
|
|
bitfld.long 0x0 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
|
|
bitfld.long 0x0 1. "TXE,Transmit FIFO empty." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
|
|
bitfld.long 0x4 11. "CQERR,Command Queue Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "CQPAUSED,Command Queue is Paused." "0,1"
|
|
bitfld.long 0x4 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
|
|
bitfld.long 0x4 7. "DERR,DMA Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "DCMP,DMA Complete Interrupt" "0,1"
|
|
bitfld.long 0x4 5. "RXF,Receive FIFO full" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
|
|
bitfld.long 0x4 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
|
|
bitfld.long 0x4 1. "TXE,Transmit FIFO empty." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
|
|
bitfld.long 0x8 11. "CQERR,Command Queue Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "CQPAUSED,Command Queue is Paused." "0,1"
|
|
bitfld.long 0x8 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
|
|
bitfld.long 0x8 7. "DERR,DMA Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "DCMP,DMA Complete Interrupt" "0,1"
|
|
bitfld.long 0x8 5. "RXF,Receive FIFO full" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
|
|
bitfld.long 0x8 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
|
|
bitfld.long 0x8 1. "TXE,Transmit FIFO empty." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
|
|
bitfld.long 0xC 11. "CQERR,Command Queue Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "CQPAUSED,Command Queue is Paused." "0,1"
|
|
bitfld.long 0xC 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
|
|
bitfld.long 0xC 7. "DERR,DMA Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "DCMP,DMA Complete Interrupt" "0,1"
|
|
bitfld.long 0xC 5. "RXF,Receive FIFO full" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
|
|
bitfld.long 0xC 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
|
|
bitfld.long 0xC 1. "TXE,Transmit FIFO empty." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
|
|
group.long 0x250++0x17
|
|
line.long 0x0 "DMACFG,DMA Configuration"
|
|
bitfld.long 0x0 18. "DMAPWROFF,Power off MSPI domain upon completion of DMA operation." "0,1"
|
|
bitfld.long 0x0 3.--4. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately),2: Auto Priority (priority raised once TX FIFO..,?"
|
|
newline
|
|
bitfld.long 0x0 2. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction,1: Memory to Peripheral transaction"
|
|
bitfld.long 0x0 0.--1. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation" "0: Disable DMA Function,?,?,3: Enable HW controlled DMA Function to manage DMA.."
|
|
line.long 0x4 "DMASTAT,DMA Status"
|
|
bitfld.long 0x4 3. "SCRERR,Scrambling Access Alignment Error. This active high bit signals that a scrambling operation was specified for a non-word aligned DEVADDR." "0,1"
|
|
bitfld.long 0x4 2. "DMAERR,DMA Error. This active high bit signals that an error was encountered during the DMA operation." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation." "0,1"
|
|
bitfld.long 0x4 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority. All of these will be indicated with a 1. A 0 will indicate that the DMA is.." "0,1"
|
|
line.long 0x8 "DMATARGADDR,DMA Target Address"
|
|
hexmask.long 0x8 0.--31. 1. "TARGADDR,Target byte address for source of DMA (either read or write). In cases of non-word aligned addresses the DMA logic will take care for ensuring only the target bytes are read/written."
|
|
line.long 0xC "DMADEVADDR,DMA Device Address"
|
|
hexmask.long 0xC 0.--31. 1. "DEVADDR,SPI Device address for automated DMA transactions (both read and write)."
|
|
line.long 0x10 "DMATOTCOUNT,DMA Total Transfer Count"
|
|
hexmask.long.word 0x10 0.--15. 1. "TOTCOUNT,Total Transfer Count in bytes."
|
|
line.long 0x14 "DMABCOUNT,DMA BYTE Transfer Count"
|
|
hexmask.long.byte 0x14 0.--7. 1. "BCOUNT,Burst transfer size in bytes. This is the number of bytes transferred when a FIFO trigger event occurs. Recommended values are 16 or 32."
|
|
group.long 0x278++0x3
|
|
line.long 0x0 "DMATHRESH,Indicates FIFO level at which a DMA should be triggered. For most configurations. a setting of 8 is recommended for both read and write operations."
|
|
hexmask.long.byte 0x0 0.--3. 1. "DMATHRESH,DMA transfer FIFO level trigger. For read operations DMA is triggered when the FIFO level is greater than this value. For write operations DMA is triggered when the FIFO level is less than this level. Each DMA operation will consist of BCOUNT.."
|
|
group.long 0x2A0++0x3
|
|
line.long 0x0 "CQCFG,This register controls Command Queuing (CQ) operations in a manner similar to the DMACFG register."
|
|
bitfld.long 0x0 3. "CQAUTOCLEARMASK,Enable clear of CQMASK after each pause operation. This may be useful when using software flags to pause CQ." "0,1"
|
|
bitfld.long 0x0 2. "CQPWROFF,Power off MSPI domain upon completion of DMA operation." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CQPRI,Sets the Priority of the command queue DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
|
|
bitfld.long 0x0 0. "CQEN,Command queue enable. When set will enable the processing of the command queue" "0: Disable CQ Function,1: Enable CQ Function"
|
|
group.long 0x2A8++0x13
|
|
line.long 0x0 "CQADDR,Location of the command queue in SRAM or flash memory. This register will increment as CQ operations commence. Software should only write CQADDR when CQEN is disabled. however the command queue script itself may update CQADDR in order to perform.."
|
|
hexmask.long 0x0 0.--28. 1. "CQADDR,Address of command queue buffer in SRAM or flash. The buffer address must be aligned to a word boundary."
|
|
line.long 0x4 "CQSTAT,Command Queue Status"
|
|
bitfld.long 0x4 3. "CQPAUSED,Command queue is currently paused status." "0,1"
|
|
bitfld.long 0x4 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CQCPL,Command queue operation Complete. This signals the end of the command queue operation." "0,1"
|
|
bitfld.long 0x4 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
|
|
line.long 0x8 "CQFLAGS,Command Queue Flags"
|
|
hexmask.long.word 0x8 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
|
|
line.long 0xC "CQSETCLEAR,Command Queue Flag Set/Clear"
|
|
hexmask.long.byte 0xC 16.--23. 1. "CQFCLR,Clear CQFlag status bits."
|
|
hexmask.long.byte 0xC 8.--15. 1. "CQFTOGGLE,Toggle CQFlag status bits"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CQFSET,Set CQFlag status bits. Set has priority over clear if both are high."
|
|
line.long 0x10 "CQPAUSE,Command Queue Pause Mask"
|
|
hexmask.long.word 0x10 0.--15. 1. "CQMASK,CQ will pause processing when ALL specified events are satisfied -- i.e. when (CQMASK and CQPAUSE)==CQMASK."
|
|
group.long 0x2C0++0x7
|
|
line.long 0x0 "CQCURIDX,This register can be used in conjunction with the CQENDIDX register to manage the command queue. Typically software will initialize the CQCURIDX and CQENDIDX to the same value. which will cause the CQ to be paused when enabled. Software may then.."
|
|
hexmask.long.byte 0x0 0.--7. 1. "CQCURIDX,Can be used to indicate the current position of the command queue by having CQ operations write this field. A CQ hardware status flag indicates when CURIDX and ENDIDX are not equal allowing SW to pause the CQ processing until the end index is.."
|
|
line.long 0x4 "CQENDIDX,Command Queue End Index"
|
|
hexmask.long.byte 0x4 0.--7. 1. "CQENDIDX,Can be used to indicate the end position of the command queue. A CQ hardware status bit indices when CURIDX != ENDIDX so that the CQ can be paused when it reaches the end pointer."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("AMA3B2KK"))
|
|
tree "MSPI0"
|
|
base ad:0x50014000
|
|
group.long 0x0++0x23
|
|
line.long 0x0 "CTRL,This register is used to enable individual PIO based transactions to a device on the bus. The CFG register must be programmed properly for the transfer. and the ADDR and INSTR registers should be programmed if the SENDI and SENDA fields are enabled."
|
|
hexmask.long.word 0x0 16.--31. 1. "XFERBYTES,Number of bytes to transmit or receive (based on TXRX bit)"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDCX,Enable DCX signal on data [1]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PIOSCRAMBLE,Enables data scrambling for PIO operations. This should only be used for data operations and never for commands to a device." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "TXRX,1 Indicates a TX operation 0 indicates an RX operation of XFERBYTES" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SENDI,Indicates whether an instruction phase should be sent (see INSTR field and ISIZE field in CFG register)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "SENDA,Indicates whether an address phase should be sent (see ADDR register and ASIZE field in CFG register)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ENTURN,Indicates whether TX->RX turnaround cycles should be enabled for this operation (see TURNAROUND field in CFG register)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "BIGENDIAN,1 indicates data in FIFO is in big endian format (MSB first); 0 indicates little endian data (default LSB first)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CONT,Continuation transfer. When 1 indicates that the MSPI will hold CE low after the transaction completes. This is included for compatibility with IOM module since the MSPI transfer module can handle most cases in a single transfer. NOTE: CONT.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENWLAT,Enable Write Latency Counter (time between address and first data byte). Counter value is WRITELATENCY." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "QUADCMD,Flag indicating that the operation is a command that should be replicated to both devices in paired QUAD mode. This is typically only used when reading/writing configuration registers in paired flash devices (do not set for memory transfers)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "BUSY,Command status: 1 indicates controller is busy (command in progress)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STATUS,Command status: 1 indicates command has completed. Cleared by writing 1 to this bit or starting a new transfer." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Write to 1 to initiate a PIO transaction on the bus (typically the entire register should be written at once with this bit set)." "0,1"
|
|
line.long 0x4 "CFG,Command formatting for PIO based transactions (initiated by writes to CTRL register)"
|
|
hexmask.long.byte 0x4 20.--25. 1. "WRITELATENCY,Number of cycles between addressn and TX data. Qualified by ENLAT"
|
|
newline
|
|
bitfld.long 0x4 17. "CPOL,Serial clock polarity." "0: Clock inactive state is low.,1: Clock inactive state is high."
|
|
newline
|
|
bitfld.long 0x4 16. "CPHA,Serial clock phase." "0: Clock toggles in middle of data bit.,1: Clock toggles at start of data bit."
|
|
newline
|
|
hexmask.long.byte 0x4 8.--13. 1. "TURNAROUND,Number of turnaround cycles (for TX->RX transitions). Qualified by ENTURN or XIPENTURN bit field."
|
|
newline
|
|
bitfld.long 0x4 7. "SEPIO,Separate IO configuration. This bit should be set when the target device has separate MOSI and MISO pins. Respective IN/OUT bits below should be set to map pins." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "ISIZE,Instruction Size" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--5. "ASIZE,Address Size. Address bytes to send from ADDR register" "0: Send one address byte,1: Send two address bytes,2: Send three address bytes,3: Send four address bytes"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DEVCFG,Flash configuration for XIP and AUTO DMA operations. Controls value for SER (Slave Enable) for XIP operations and address generation for DMA/XIP modes. Also used to configure SPIFRF (frame format)."
|
|
line.long 0x8 "ADDR,Optional Address field to send for PIO transfers"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,Optional Address field to send (after optional instruction field) - qualified by ASIZE in CMD register. NOTE: This register is aliased to DMADEVADDR."
|
|
line.long 0xC "INSTR,Optional Instruction field to send for PIO transfers"
|
|
hexmask.long.word 0xC 0.--15. 1. "INSTR,Optional Instruction field to send (1st byte) - qualified by ISEND/ISIZE"
|
|
line.long 0x10 "TXFIFO,TX Data FIFO"
|
|
hexmask.long 0x10 0.--31. 1. "TXFIFO,Data to be transmitted. Data should normally be aligned to the LSB (pad the upper bits with zeros) unless BIGENDIAN is set."
|
|
line.long 0x14 "RXFIFO,RX Data FIFO"
|
|
hexmask.long 0x14 0.--31. 1. "RXFIFO,Receive data. Data is aligned to the LSB (padded zeros on upper bits) unless BIGENDIAN is set."
|
|
line.long 0x18 "TXENTRIES,Number of words in TX FIFO"
|
|
hexmask.long.byte 0x18 0.--5. 1. "TXENTRIES,Number of 32-bit words/entries in TX FIFO"
|
|
line.long 0x1C "RXENTRIES,Number of words in RX FIFO"
|
|
hexmask.long.byte 0x1C 0.--5. 1. "RXENTRIES,Number of 32-bit words/entries in RX FIFO"
|
|
line.long 0x20 "THRESHOLD,Threshold levels that trigger RXFull and TXEmpty interrupts"
|
|
hexmask.long.byte 0x20 8.--13. 1. "RXTHRESH,Number of entries in TX FIFO that cause RXE interrupt"
|
|
newline
|
|
hexmask.long.byte 0x20 0.--5. 1. "TXTHRESH,Number of entries in TX FIFO that cause TXF interrupt"
|
|
group.long 0x100++0x7
|
|
line.long 0x0 "MSPICFG,Timing configuration bits for the MSPI module. PRSTN. IPRSTN. and FIFORESET can be used to reset portions of the MSPI interface in order to clear error conditions. The remaining bits control clock frequency and TX/RX capture timings."
|
|
bitfld.long 0x0 31. "PRSTN,Peripheral reset. Master reset to the entire MSPI module (DMA XIP and transfer state machines). 1=normal operation 0=in reset." "0: in reset,1: normal operation"
|
|
newline
|
|
bitfld.long 0x0 30. "IPRSTN,IP block reset. Write to 0 to put the transfer module in reset or 1 for normal operation. This may be required after error conditions to clear the transfer on the bus." "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "FIFORESET,Reset MSPI FIFO (active high). 1=reset FIFO 0=normal operation. May be used to manually flush the FIFO in error handling." "0: normal operation,1: reset FIFO"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "CLKDIV,Clock Divider. Allows dividing 48 MHz base clock by integer multiples. Enumerations are provided for common frequency but any integer divide from 48 MHz is allowed. Odd divide ratios will result in a 33/66 percent duty cycle with a long low clock.."
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "IOMSEL,Selects which IOM is selected for CQ handshake status."
|
|
newline
|
|
bitfld.long 0x0 3. "TXNEG,Launches TX data a half clock cycle (~10 ns) early. This should normally be programmed to zero (NORMAL)." "0: TX launched from posedge internal clock,1: TX data launched from negedge of internal clock"
|
|
newline
|
|
bitfld.long 0x0 2. "RXNEG,Adjusts the RX capture phase to the negedge of the 48MHz internal clock (~10 ns early). For normal operation it is expected that RXNEG will be set to 0." "0: RX data sampled on posedge of internal clock,1: RX data sampled on negedge of internal clock"
|
|
newline
|
|
bitfld.long 0x0 1. "RXCAP,Controls RX data capture phase. A setting of 0 (NORMAL) captures read data at the normal capture point relative to the internal clock launch point. However to accommodate chip/pad/board delays a setting of RXCAP of 1 is expected to be used to.." "0: RX Capture phase aligns with CPHA setting,1: RX Capture phase is delayed from CPHA setting by.."
|
|
newline
|
|
bitfld.long 0x0 0. "APBCLK,Enable continuous APB clock. For power-efficient operation APBCLK should be set to 0." "0: Disable continuous clock.,1: Enable continuous clock."
|
|
line.long 0x4 "MSPIDDR,Timing configuration bits for DDR operation of the MSPI module."
|
|
hexmask.long.byte 0x4 16.--20. 1. "TXDQSDELAY,When OVERRIDEDQSDELAY is set this sets the DQS delay line value. In ENABLEDQS mode this acts as an offset to the computed value (should be set to 0 by default)"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--12. 1. "RXDQSDELAY,When OVERRIDEDQSDELAY is set this sets the DQS delay line value. In ENABLEDQS mode this acts as an offset to the computed value (should be set to 0 by default)"
|
|
newline
|
|
bitfld.long 0x4 6. "ENABLEFINEDELAY,Enables use of delay line to provide fine control over traditional RX capture clock." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERRIDEDDRCLKOUTDELAY,Override TX delay line with the value in DQSDELAY (for TX clock offset when in QUADDDR mode)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "OVERRIDERXDQSDELAY,Override DQS delay line with the value in DQSDELAY (for RX capture in QUADDDR mode)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "DQSSYNCNEG,Use negative edge of clock for DDR data sync" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "ENABLEDQS,In EMULATEDDR mode enable DQS for read capture" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "QUADDDR,Enables use of delay line to provide fine control over traditional RX capture clock." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "EMULATEDDR,Drive external clock at 1/2 rate to emulate DDR mode" "0,1"
|
|
group.long 0x110++0x1B
|
|
line.long 0x0 "PADCFG,Configuration bits for the MSPI pads. Allows pads associated with the upper quad to be mapped to corresponding bits on the lower quad. Use of Quad0 pins is recommended for optimal timing."
|
|
bitfld.long 0x0 21. "REVCS,Reverse CS connections. Allows CS1 to be associated with lower data lanes and CS0 to be associated with upper data lines" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "IN3,Data Input pad 3 pin muxing: 0=pad[3] 1=pad[7]" "0: pad[3] 1=pad[7],?"
|
|
newline
|
|
bitfld.long 0x0 19. "IN2,Data Input pad 2 pin muxing: 0=pad[2] 1=pad[6]" "0: pad[2] 1=pad[6],?"
|
|
newline
|
|
bitfld.long 0x0 18. "IN1,Data Input pad 1 pin muxing: 0=pad[1] 1=pad[5]" "0: pad[1] 1=pad[5],?"
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bitfld.long 0x0 16.--17. "IN0,Data Input pad 0 pin muxing: 0=pad[0] 1=pad[4] 2=pad[1] 3=pad[5]" "0: pad[0] 1=pad[4] 2=pad[1] 3=pad[5],?,?,?"
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bitfld.long 0x0 4. "OUT7,Output pad 7 configuration. 0=data[7] 1=data[3]" "0: data[7] 1=data[3],?"
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bitfld.long 0x0 3. "OUT6,Output pad 6 configuration. 0=data[6] 1=data[2]" "0: data[6] 1=data[2],?"
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bitfld.long 0x0 2. "OUT5,Output pad 5 configuration. 0=data[5] 1=data[1]" "0: data[5] 1=data[1],?"
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bitfld.long 0x0 1. "OUT4,Output pad 4 configuration. 0=data[4] 1=data[0]" "0: data[4] 1=data[0],?"
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bitfld.long 0x0 0. "OUT3,Output pad 3 configuration. 0=data[3] 1=CLK" "0: data[3] 1=CLK,?"
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line.long 0x4 "PADOUTEN,Enable bits for the MSPI output pads. Each active MSPI line should be set to 1 in the OUTEN field below."
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hexmask.long.word 0x4 0.--9. 1. "OUTEN,Output pad enable configuration. Indicates which pads should be driven. Bits [3:0] are Quad0 data [7:4] are Quad1 data and [8] is clock."
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line.long 0x8 "PADOVEREN,Enables PIO-like pad override control"
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hexmask.long.word 0x8 0.--9. 1. "OVERRIDEEN,Output pad override enable. Bit mask for pad outputs. When set to 1 the values in the OVERRIDE field are driven on the pad (output enable is implicitly set in this mode). [7:0]=data [8]=clock [9]=DM"
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line.long 0xC "PADOVER,Override data value"
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hexmask.long.word 0xC 0.--9. 1. "OVERRIDE,Output pad override value. [7:0]=data [8]=clock [9]=DM"
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line.long 0x10 "FLASH,When any SPI flash is configured. this register must be properly programmed before XIP or AUTO DMA operations commence."
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bitfld.long 0x10 11. "XIPENWLAT,Enable Write Latency counter for XIP write transactions" "0,1"
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bitfld.long 0x10 8.--10. "XIPMIXED,Provides override controls for data operations where instruction address and data may transfer in different rates." "0: Transfers all proceed using the settings in..,1: Data operations proceed in dual data rate,?,3: Address and Data operations proceed in dual data..,?,5: Data operations proceed in quad data rate,?,7: Address and Data operations proceed in quad data.."
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bitfld.long 0x10 7. "XIPSENDI,Indicates whether XIP/AUTO DMA operations should send an instruction (see READINSTR field and ISIZE field in CFG)" "0,1"
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bitfld.long 0x10 6. "XIPSENDA,Indicates whether XIP/AUTO DMA operations should send an an address phase (see DMADEVADDR register and ASIZE field in CFG)" "0,1"
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bitfld.long 0x10 5. "XIPENTURN,Indicates whether XIP/AUTO DMA operations should enable TX->RX turnaround cycles" "0,1"
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bitfld.long 0x10 4. "XIPBIGENDIAN,Indicates whether XIP/AUTO DMA data transfers are in big or little endian format" "0,1"
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bitfld.long 0x10 2.--3. "XIPACK,Controls transmission of Micron XIP acknowledge cycles (Micron Flash devices only)" "0: No acknowledgment sent. Data IOs are tri-stated..,?,2: Positive acknowledgment sent. Data IOs are..,3: Negative acknowledgment sent. Data IOs are.."
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bitfld.long 0x10 1. "XIPENDCX,Enable DCX signal on data [1] for XIP/DMA operations" "0,1"
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bitfld.long 0x10 0. "XIPEN,Enable the XIP (eXecute In Place) function which effectively enables the address decoding of the MSPI device in the flash/cache address space at address 0x04000000-0x07FFFFFF." "0,1"
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line.long 0x14 "XIPINSTR,When any SPI flash is configured. this register must be properly programmed before XIP or AUTO DMA operations commence."
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hexmask.long.word 0x14 16.--31. 1. "READINSTR,Read command sent to flash for DMA/XIP operations"
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hexmask.long.word 0x14 0.--15. 1. "WRITEINSTR,Write command sent for DMA operations"
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line.long 0x18 "SCRAMBLING,Enables data scrambling for the specified range external flash addresses. Scrambling does not impact flash access performance."
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bitfld.long 0x18 31. "SCRENABLE,Enables Data Scrambling Region. When 1 reads and writes to the range will be scrambled. When 0 data will be read/written unmodified. Address range is specified in 64K granularity and the START/END ranges are included within the range." "0,1"
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hexmask.long.word 0x18 16.--25. 1. "SCREND,Scrambling region end address [25:16] (64K block granularity). The END block is the LAST block included in the scrambled address range."
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hexmask.long.word 0x18 0.--9. 1. "SCRSTART,Scrambling region start address [25:16] (64K block granularity). The START block is the FIRST block included in the scrambled address range."
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group.long 0x200++0xF
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line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
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bitfld.long 0x0 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
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bitfld.long 0x0 11. "CQERR,Command Queue Error Interrupt" "0,1"
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bitfld.long 0x0 10. "CQPAUSED,Command Queue is Paused." "0,1"
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bitfld.long 0x0 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
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bitfld.long 0x0 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
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bitfld.long 0x0 7. "DERR,DMA Error Interrupt" "0,1"
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bitfld.long 0x0 6. "DCMP,DMA Complete Interrupt" "0,1"
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bitfld.long 0x0 5. "RXF,Receive FIFO full" "0,1"
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bitfld.long 0x0 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
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bitfld.long 0x0 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
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bitfld.long 0x0 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
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bitfld.long 0x0 1. "TXE,Transmit FIFO empty." "0,1"
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bitfld.long 0x0 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
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line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
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bitfld.long 0x4 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
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bitfld.long 0x4 11. "CQERR,Command Queue Error Interrupt" "0,1"
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bitfld.long 0x4 10. "CQPAUSED,Command Queue is Paused." "0,1"
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bitfld.long 0x4 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
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bitfld.long 0x4 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
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bitfld.long 0x4 7. "DERR,DMA Error Interrupt" "0,1"
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bitfld.long 0x4 6. "DCMP,DMA Complete Interrupt" "0,1"
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bitfld.long 0x4 5. "RXF,Receive FIFO full" "0,1"
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bitfld.long 0x4 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
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bitfld.long 0x4 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
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bitfld.long 0x4 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
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bitfld.long 0x4 1. "TXE,Transmit FIFO empty." "0,1"
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bitfld.long 0x4 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
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line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
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bitfld.long 0x8 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
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bitfld.long 0x8 11. "CQERR,Command Queue Error Interrupt" "0,1"
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bitfld.long 0x8 10. "CQPAUSED,Command Queue is Paused." "0,1"
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bitfld.long 0x8 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
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bitfld.long 0x8 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
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bitfld.long 0x8 7. "DERR,DMA Error Interrupt" "0,1"
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bitfld.long 0x8 6. "DCMP,DMA Complete Interrupt" "0,1"
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bitfld.long 0x8 5. "RXF,Receive FIFO full" "0,1"
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bitfld.long 0x8 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
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bitfld.long 0x8 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
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bitfld.long 0x8 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
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bitfld.long 0x8 1. "TXE,Transmit FIFO empty." "0,1"
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bitfld.long 0x8 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
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line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
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bitfld.long 0xC 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
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bitfld.long 0xC 11. "CQERR,Command Queue Error Interrupt" "0,1"
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bitfld.long 0xC 10. "CQPAUSED,Command Queue is Paused." "0,1"
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bitfld.long 0xC 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
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bitfld.long 0xC 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
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bitfld.long 0xC 7. "DERR,DMA Error Interrupt" "0,1"
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bitfld.long 0xC 6. "DCMP,DMA Complete Interrupt" "0,1"
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bitfld.long 0xC 5. "RXF,Receive FIFO full" "0,1"
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bitfld.long 0xC 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
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bitfld.long 0xC 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
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bitfld.long 0xC 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
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bitfld.long 0xC 1. "TXE,Transmit FIFO empty." "0,1"
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bitfld.long 0xC 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
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group.long 0x250++0x1F
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line.long 0x0 "DMACFG,DMA Configuration"
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bitfld.long 0x0 18. "DMAPWROFF,Power off MSPI domain upon completion of DMA operation." "0,1"
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bitfld.long 0x0 3.--4. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately),2: Auto Priority (priority raised once TX FIFO..,?"
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bitfld.long 0x0 2. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction,1: Memory to Peripheral transaction"
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bitfld.long 0x0 0.--1. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation" "0: Disable DMA Function,?,?,3: Enable HW controlled DMA Function to manage DMA.."
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line.long 0x4 "DMASTAT,DMA Status"
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bitfld.long 0x4 3. "SCRERR,Scrambling Access Alignment Error. This active high bit signals that a scrambling operation was specified for a non-word aligned DEVADDR." "0,1"
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bitfld.long 0x4 2. "DMAERR,DMA Error. This active high bit signals that an error was encountered during the DMA operation." "0,1"
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bitfld.long 0x4 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation." "0,1"
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|
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bitfld.long 0x4 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority. All of these will be indicated with a 1. A 0 will indicate that the DMA is.." "0,1"
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line.long 0x8 "DMATARGADDR,DMA Target Address"
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hexmask.long 0x8 0.--31. 1. "TARGADDR,Target byte address for source of DMA (either read or write). In cases of non-word aligned addresses the DMA logic will take care for ensuring only the target bytes are read/written."
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line.long 0xC "DMADEVADDR,DMA Device Address"
|
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hexmask.long 0xC 0.--31. 1. "DEVADDR,SPI Device address for automated DMA transactions (both read and write)."
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line.long 0x10 "DMATOTCOUNT,DMA Total Transfer Count"
|
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hexmask.long.tbyte 0x10 0.--23. 1. "TOTCOUNT,Total Transfer Count in bytes."
|
|
line.long 0x14 "DMABCOUNT,DMA BYTE Transfer Count"
|
|
hexmask.long.byte 0x14 0.--7. 1. "BCOUNT,Burst transfer size in bytes. This is the number of bytes transferred when a FIFO trigger event occurs. Recommended value is 32."
|
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line.long 0x18 "DMATHRESH,Indicates FIFO level at which a DMA should be triggered. For most configurations. a setting of 8 is recommended for both read and write operations."
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hexmask.long.byte 0x18 8.--12. 1. "DMARXTHRESH,DMA transfer FIFO level trigger. For read operations DMA is triggered when the FIFO level is greater than this value. For write operations DMA is triggered when the FIFO level is less than this level. Each DMA operation will consist of.."
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hexmask.long.byte 0x18 0.--4. 1. "DMATXTHRESH,DMA transfer FIFO level trigger. For read operations DMA is triggered when the FIFO level is greater than this value. For write operations DMA is triggered when the FIFO level is less than this level. Each DMA operation will consist of.."
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line.long 0x1C "DMABOUNDARY,Allows large transfers to be broken up into smaller ones in hardware to accommodate needs of external devices and allow XIP/XIPMM. Only applicable for memory-mapped devices (PSRAM. Flash. etc) where address can be retransmitted without side.."
|
|
hexmask.long.byte 0x1C 12.--15. 1. "DMABOUND,DMA Address boundary"
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hexmask.long.word 0x1C 0.--11. 1. "DMATIMELIMIT,DMA time limit. Can be used to limit the transaction time on the MSPI bus. The count is in 100 ns increments. A value of 0 disables the counter."
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group.long 0x2A0++0x3
|
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line.long 0x0 "CQCFG,This register controls Command Queuing (CQ) operations in a manner similar to the DMACFG register."
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bitfld.long 0x0 3. "CQAUTOCLEARMASK,Enable clear of CQMASK after each pause operation. This may be useful when using software flags to pause CQ." "0,1"
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|
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|
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bitfld.long 0x0 2. "CQPWROFF,Power off MSPI domain upon completion of DMA operation." "0,1"
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|
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|
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bitfld.long 0x0 1. "CQPRI,Sets the Priority of the command queue DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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|
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bitfld.long 0x0 0. "CQEN,Command queue enable. When set will enable the processing of the command queue" "0: Disable CQ Function,1: Enable CQ Function"
|
|
group.long 0x2A8++0x13
|
|
line.long 0x0 "CQADDR,Location of the command queue in SRAM or flash memory. This register will increment as CQ operations commence. Software should only write CQADDR when CQEN is disabled. however the command queue script itself may update CQADDR in order to perform.."
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hexmask.long 0x0 0.--28. 1. "CQADDR,Address of command queue buffer in SRAM or flash. The buffer address must be aligned to a word boundary."
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line.long 0x4 "CQSTAT,Command Queue Status"
|
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bitfld.long 0x4 3. "CQPAUSED,Command queue is currently paused status." "0,1"
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|
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|
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bitfld.long 0x4 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
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|
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|
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bitfld.long 0x4 1. "CQCPL,Command queue operation Complete. This signals the end of the command queue operation." "0,1"
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|
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|
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bitfld.long 0x4 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
|
|
line.long 0x8 "CQFLAGS,Command Queue Flags"
|
|
hexmask.long.word 0x8 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
|
|
line.long 0xC "CQSETCLEAR,Command Queue Flag Set/Clear"
|
|
hexmask.long.byte 0xC 16.--23. 1. "CQFCLR,Clear CQFlag status bits."
|
|
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|
|
hexmask.long.byte 0xC 8.--15. 1. "CQFTOGGLE,Toggle CQFlag status bits"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CQFSET,Set CQFlag status bits. Set has priority over clear if both are high."
|
|
line.long 0x10 "CQPAUSE,Command Queue Pause Mask"
|
|
hexmask.long.word 0x10 0.--15. 1. "CQMASK,CQ will pause processing when ALL specified events are satisfied -- i.e. when (CQMASK and CQPAUSE)==CQMASK."
|
|
group.long 0x2C0++0x7
|
|
line.long 0x0 "CQCURIDX,This register can be used in conjunction with the CQENDIDX register to manage the command queue. Typically software will initialize the CQCURIDX and CQENDIDX to the same value. which will cause the CQ to be paused when enabled. Software may then.."
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|
hexmask.long.byte 0x0 0.--7. 1. "CQCURIDX,Can be used to indicate the current position of the command queue by having CQ operations write this field. A CQ hardware status flag indicates when CURIDX and ENDIDX are not equal allowing SW to pause the CQ processing until the end index is.."
|
|
line.long 0x4 "CQENDIDX,Command Queue End Index"
|
|
hexmask.long.byte 0x4 0.--7. 1. "CQENDIDX,Can be used to indicate the end position of the command queue. A CQ hardware status bit indices when CURIDX != ENDIDX so that the CQ can be paused when it reaches the end pointer."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("AMA3B2KK"))
|
|
tree "MSPI1"
|
|
base ad:0x50015000
|
|
group.long 0x0++0x23
|
|
line.long 0x0 "CTRL,This register is used to enable individual PIO based transactions to a device on the bus. The CFG register must be programmed properly for the transfer. and the ADDR and INSTR registers should be programmed if the SENDI and SENDA fields are enabled."
|
|
hexmask.long.word 0x0 16.--31. 1. "XFERBYTES,Number of bytes to transmit or receive (based on TXRX bit)"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDCX,Enable DCX signal on data [1]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PIOSCRAMBLE,Enables data scrambling for PIO operations. This should only be used for data operations and never for commands to a device." "0,1"
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|
newline
|
|
bitfld.long 0x0 10. "TXRX,1 Indicates a TX operation 0 indicates an RX operation of XFERBYTES" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SENDI,Indicates whether an instruction phase should be sent (see INSTR field and ISIZE field in CFG register)" "0,1"
|
|
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|
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bitfld.long 0x0 8. "SENDA,Indicates whether an address phase should be sent (see ADDR register and ASIZE field in CFG register)" "0,1"
|
|
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|
|
bitfld.long 0x0 7. "ENTURN,Indicates whether TX->RX turnaround cycles should be enabled for this operation (see TURNAROUND field in CFG register)." "0,1"
|
|
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|
|
bitfld.long 0x0 6. "BIGENDIAN,1 indicates data in FIFO is in big endian format (MSB first); 0 indicates little endian data (default LSB first)." "0,1"
|
|
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|
|
bitfld.long 0x0 5. "CONT,Continuation transfer. When 1 indicates that the MSPI will hold CE low after the transaction completes. This is included for compatibility with IOM module since the MSPI transfer module can handle most cases in a single transfer. NOTE: CONT.." "0,1"
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|
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|
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bitfld.long 0x0 4. "ENWLAT,Enable Write Latency Counter (time between address and first data byte). Counter value is WRITELATENCY." "0,1"
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|
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|
|
bitfld.long 0x0 3. "QUADCMD,Flag indicating that the operation is a command that should be replicated to both devices in paired QUAD mode. This is typically only used when reading/writing configuration registers in paired flash devices (do not set for memory transfers)." "0,1"
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|
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|
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bitfld.long 0x0 2. "BUSY,Command status: 1 indicates controller is busy (command in progress)" "0,1"
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|
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|
|
bitfld.long 0x0 1. "STATUS,Command status: 1 indicates command has completed. Cleared by writing 1 to this bit or starting a new transfer." "0,1"
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|
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|
|
bitfld.long 0x0 0. "START,Write to 1 to initiate a PIO transaction on the bus (typically the entire register should be written at once with this bit set)." "0,1"
|
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line.long 0x4 "CFG,Command formatting for PIO based transactions (initiated by writes to CTRL register)"
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hexmask.long.byte 0x4 20.--25. 1. "WRITELATENCY,Number of cycles between addressn and TX data. Qualified by ENLAT"
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bitfld.long 0x4 17. "CPOL,Serial clock polarity." "0: Clock inactive state is low.,1: Clock inactive state is high."
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bitfld.long 0x4 16. "CPHA,Serial clock phase." "0: Clock toggles in middle of data bit.,1: Clock toggles at start of data bit."
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hexmask.long.byte 0x4 8.--13. 1. "TURNAROUND,Number of turnaround cycles (for TX->RX transitions). Qualified by ENTURN or XIPENTURN bit field."
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bitfld.long 0x4 7. "SEPIO,Separate IO configuration. This bit should be set when the target device has separate MOSI and MISO pins. Respective IN/OUT bits below should be set to map pins." "0,1"
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bitfld.long 0x4 6. "ISIZE,Instruction Size" "0,1"
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bitfld.long 0x4 4.--5. "ASIZE,Address Size. Address bytes to send from ADDR register" "0: Send one address byte,1: Send two address bytes,2: Send three address bytes,3: Send four address bytes"
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hexmask.long.byte 0x4 0.--3. 1. "DEVCFG,Flash configuration for XIP and AUTO DMA operations. Controls value for SER (Slave Enable) for XIP operations and address generation for DMA/XIP modes. Also used to configure SPIFRF (frame format)."
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line.long 0x8 "ADDR,Optional Address field to send for PIO transfers"
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hexmask.long 0x8 0.--31. 1. "ADDR,Optional Address field to send (after optional instruction field) - qualified by ASIZE in CMD register. NOTE: This register is aliased to DMADEVADDR."
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line.long 0xC "INSTR,Optional Instruction field to send for PIO transfers"
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hexmask.long.word 0xC 0.--15. 1. "INSTR,Optional Instruction field to send (1st byte) - qualified by ISEND/ISIZE"
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line.long 0x10 "TXFIFO,TX Data FIFO"
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hexmask.long 0x10 0.--31. 1. "TXFIFO,Data to be transmitted. Data should normally be aligned to the LSB (pad the upper bits with zeros) unless BIGENDIAN is set."
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line.long 0x14 "RXFIFO,RX Data FIFO"
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hexmask.long 0x14 0.--31. 1. "RXFIFO,Receive data. Data is aligned to the LSB (padded zeros on upper bits) unless BIGENDIAN is set."
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line.long 0x18 "TXENTRIES,Number of words in TX FIFO"
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hexmask.long.byte 0x18 0.--5. 1. "TXENTRIES,Number of 32-bit words/entries in TX FIFO"
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line.long 0x1C "RXENTRIES,Number of words in RX FIFO"
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hexmask.long.byte 0x1C 0.--5. 1. "RXENTRIES,Number of 32-bit words/entries in RX FIFO"
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line.long 0x20 "THRESHOLD,Threshold levels that trigger RXFull and TXEmpty interrupts"
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hexmask.long.byte 0x20 8.--13. 1. "RXTHRESH,Number of entries in TX FIFO that cause RXE interrupt"
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hexmask.long.byte 0x20 0.--5. 1. "TXTHRESH,Number of entries in TX FIFO that cause TXF interrupt"
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group.long 0x100++0x7
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line.long 0x0 "MSPICFG,Timing configuration bits for the MSPI module. PRSTN. IPRSTN. and FIFORESET can be used to reset portions of the MSPI interface in order to clear error conditions. The remaining bits control clock frequency and TX/RX capture timings."
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bitfld.long 0x0 31. "PRSTN,Peripheral reset. Master reset to the entire MSPI module (DMA XIP and transfer state machines). 1=normal operation 0=in reset." "0: in reset,1: normal operation"
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bitfld.long 0x0 30. "IPRSTN,IP block reset. Write to 0 to put the transfer module in reset or 1 for normal operation. This may be required after error conditions to clear the transfer on the bus." "0,1"
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bitfld.long 0x0 29. "FIFORESET,Reset MSPI FIFO (active high). 1=reset FIFO 0=normal operation. May be used to manually flush the FIFO in error handling." "0: normal operation,1: reset FIFO"
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hexmask.long.byte 0x0 8.--13. 1. "CLKDIV,Clock Divider. Allows dividing 48 MHz base clock by integer multiples. Enumerations are provided for common frequency but any integer divide from 48 MHz is allowed. Odd divide ratios will result in a 33/66 percent duty cycle with a long low clock.."
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hexmask.long.byte 0x0 4.--7. 1. "IOMSEL,Selects which IOM is selected for CQ handshake status."
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bitfld.long 0x0 3. "TXNEG,Launches TX data a half clock cycle (~10 ns) early. This should normally be programmed to zero (NORMAL)." "0: TX launched from posedge internal clock,1: TX data launched from negedge of internal clock"
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bitfld.long 0x0 2. "RXNEG,Adjusts the RX capture phase to the negedge of the 48MHz internal clock (~10 ns early). For normal operation it is expected that RXNEG will be set to 0." "0: RX data sampled on posedge of internal clock,1: RX data sampled on negedge of internal clock"
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bitfld.long 0x0 1. "RXCAP,Controls RX data capture phase. A setting of 0 (NORMAL) captures read data at the normal capture point relative to the internal clock launch point. However to accommodate chip/pad/board delays a setting of RXCAP of 1 is expected to be used to.." "0: RX Capture phase aligns with CPHA setting,1: RX Capture phase is delayed from CPHA setting by.."
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bitfld.long 0x0 0. "APBCLK,Enable continuous APB clock. For power-efficient operation APBCLK should be set to 0." "0: Disable continuous clock.,1: Enable continuous clock."
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line.long 0x4 "MSPIDDR,Timing configuration bits for DDR operation of the MSPI module."
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hexmask.long.byte 0x4 16.--20. 1. "TXDQSDELAY,When OVERRIDEDQSDELAY is set this sets the DQS delay line value. In ENABLEDQS mode this acts as an offset to the computed value (should be set to 0 by default)"
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hexmask.long.byte 0x4 8.--12. 1. "RXDQSDELAY,When OVERRIDEDQSDELAY is set this sets the DQS delay line value. In ENABLEDQS mode this acts as an offset to the computed value (should be set to 0 by default)"
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bitfld.long 0x4 6. "ENABLEFINEDELAY,Enables use of delay line to provide fine control over traditional RX capture clock." "0,1"
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bitfld.long 0x4 5. "OVERRIDEDDRCLKOUTDELAY,Override TX delay line with the value in DQSDELAY (for TX clock offset when in QUADDDR mode)" "0,1"
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bitfld.long 0x4 4. "OVERRIDERXDQSDELAY,Override DQS delay line with the value in DQSDELAY (for RX capture in QUADDDR mode)" "0,1"
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bitfld.long 0x4 3. "DQSSYNCNEG,Use negative edge of clock for DDR data sync" "0,1"
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bitfld.long 0x4 2. "ENABLEDQS,In EMULATEDDR mode enable DQS for read capture" "0,1"
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bitfld.long 0x4 1. "QUADDDR,Enables use of delay line to provide fine control over traditional RX capture clock." "0,1"
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bitfld.long 0x4 0. "EMULATEDDR,Drive external clock at 1/2 rate to emulate DDR mode" "0,1"
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group.long 0x110++0x1B
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line.long 0x0 "PADCFG,Configuration bits for the MSPI pads. Allows pads associated with the upper quad to be mapped to corresponding bits on the lower quad. Use of Quad0 pins is recommended for optimal timing."
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bitfld.long 0x0 21. "REVCS,Reverse CS connections. Allows CS1 to be associated with lower data lanes and CS0 to be associated with upper data lines" "0,1"
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bitfld.long 0x0 20. "IN3,Data Input pad 3 pin muxing: 0=pad[3] 1=pad[7]" "0: pad[3] 1=pad[7],?"
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bitfld.long 0x0 19. "IN2,Data Input pad 2 pin muxing: 0=pad[2] 1=pad[6]" "0: pad[2] 1=pad[6],?"
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bitfld.long 0x0 18. "IN1,Data Input pad 1 pin muxing: 0=pad[1] 1=pad[5]" "0: pad[1] 1=pad[5],?"
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bitfld.long 0x0 16.--17. "IN0,Data Input pad 0 pin muxing: 0=pad[0] 1=pad[4] 2=pad[1] 3=pad[5]" "0: pad[0] 1=pad[4] 2=pad[1] 3=pad[5],?,?,?"
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bitfld.long 0x0 4. "OUT7,Output pad 7 configuration. 0=data[7] 1=data[3]" "0: data[7] 1=data[3],?"
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bitfld.long 0x0 3. "OUT6,Output pad 6 configuration. 0=data[6] 1=data[2]" "0: data[6] 1=data[2],?"
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bitfld.long 0x0 2. "OUT5,Output pad 5 configuration. 0=data[5] 1=data[1]" "0: data[5] 1=data[1],?"
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bitfld.long 0x0 1. "OUT4,Output pad 4 configuration. 0=data[4] 1=data[0]" "0: data[4] 1=data[0],?"
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bitfld.long 0x0 0. "OUT3,Output pad 3 configuration. 0=data[3] 1=CLK" "0: data[3] 1=CLK,?"
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line.long 0x4 "PADOUTEN,Enable bits for the MSPI output pads. Each active MSPI line should be set to 1 in the OUTEN field below."
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hexmask.long.word 0x4 0.--9. 1. "OUTEN,Output pad enable configuration. Indicates which pads should be driven. Bits [3:0] are Quad0 data [7:4] are Quad1 data and [8] is clock."
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line.long 0x8 "PADOVEREN,Enables PIO-like pad override control"
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hexmask.long.word 0x8 0.--9. 1. "OVERRIDEEN,Output pad override enable. Bit mask for pad outputs. When set to 1 the values in the OVERRIDE field are driven on the pad (output enable is implicitly set in this mode). [7:0]=data [8]=clock [9]=DM"
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line.long 0xC "PADOVER,Override data value"
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hexmask.long.word 0xC 0.--9. 1. "OVERRIDE,Output pad override value. [7:0]=data [8]=clock [9]=DM"
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line.long 0x10 "FLASH,When any SPI flash is configured. this register must be properly programmed before XIP or AUTO DMA operations commence."
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bitfld.long 0x10 11. "XIPENWLAT,Enable Write Latency counter for XIP write transactions" "0,1"
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bitfld.long 0x10 8.--10. "XIPMIXED,Provides override controls for data operations where instruction address and data may transfer in different rates." "0: Transfers all proceed using the settings in..,1: Data operations proceed in dual data rate,?,3: Address and Data operations proceed in dual data..,?,5: Data operations proceed in quad data rate,?,7: Address and Data operations proceed in quad data.."
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bitfld.long 0x10 7. "XIPSENDI,Indicates whether XIP/AUTO DMA operations should send an instruction (see READINSTR field and ISIZE field in CFG)" "0,1"
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bitfld.long 0x10 6. "XIPSENDA,Indicates whether XIP/AUTO DMA operations should send an an address phase (see DMADEVADDR register and ASIZE field in CFG)" "0,1"
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bitfld.long 0x10 5. "XIPENTURN,Indicates whether XIP/AUTO DMA operations should enable TX->RX turnaround cycles" "0,1"
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bitfld.long 0x10 4. "XIPBIGENDIAN,Indicates whether XIP/AUTO DMA data transfers are in big or little endian format" "0,1"
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bitfld.long 0x10 2.--3. "XIPACK,Controls transmission of Micron XIP acknowledge cycles (Micron Flash devices only)" "0: No acknowledgment sent. Data IOs are tri-stated..,?,2: Positive acknowledgment sent. Data IOs are..,3: Negative acknowledgment sent. Data IOs are.."
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bitfld.long 0x10 1. "XIPENDCX,Enable DCX signal on data [1] for XIP/DMA operations" "0,1"
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bitfld.long 0x10 0. "XIPEN,Enable the XIP (eXecute In Place) function which effectively enables the address decoding of the MSPI device in the flash/cache address space at address 0x04000000-0x07FFFFFF." "0,1"
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line.long 0x14 "XIPINSTR,When any SPI flash is configured. this register must be properly programmed before XIP or AUTO DMA operations commence."
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hexmask.long.word 0x14 16.--31. 1. "READINSTR,Read command sent to flash for DMA/XIP operations"
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hexmask.long.word 0x14 0.--15. 1. "WRITEINSTR,Write command sent for DMA operations"
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line.long 0x18 "SCRAMBLING,Enables data scrambling for the specified range external flash addresses. Scrambling does not impact flash access performance."
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bitfld.long 0x18 31. "SCRENABLE,Enables Data Scrambling Region. When 1 reads and writes to the range will be scrambled. When 0 data will be read/written unmodified. Address range is specified in 64K granularity and the START/END ranges are included within the range." "0,1"
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hexmask.long.word 0x18 16.--25. 1. "SCREND,Scrambling region end address [25:16] (64K block granularity). The END block is the LAST block included in the scrambled address range."
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hexmask.long.word 0x18 0.--9. 1. "SCRSTART,Scrambling region start address [25:16] (64K block granularity). The START block is the FIRST block included in the scrambled address range."
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group.long 0x200++0xF
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line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
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bitfld.long 0x0 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
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bitfld.long 0x0 11. "CQERR,Command Queue Error Interrupt" "0,1"
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bitfld.long 0x0 10. "CQPAUSED,Command Queue is Paused." "0,1"
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bitfld.long 0x0 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
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bitfld.long 0x0 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
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bitfld.long 0x0 7. "DERR,DMA Error Interrupt" "0,1"
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bitfld.long 0x0 6. "DCMP,DMA Complete Interrupt" "0,1"
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bitfld.long 0x0 5. "RXF,Receive FIFO full" "0,1"
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bitfld.long 0x0 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
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bitfld.long 0x0 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
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bitfld.long 0x0 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
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bitfld.long 0x0 1. "TXE,Transmit FIFO empty." "0,1"
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bitfld.long 0x0 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
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line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
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bitfld.long 0x4 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
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bitfld.long 0x4 11. "CQERR,Command Queue Error Interrupt" "0,1"
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bitfld.long 0x4 10. "CQPAUSED,Command Queue is Paused." "0,1"
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bitfld.long 0x4 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
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bitfld.long 0x4 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
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bitfld.long 0x4 7. "DERR,DMA Error Interrupt" "0,1"
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bitfld.long 0x4 6. "DCMP,DMA Complete Interrupt" "0,1"
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bitfld.long 0x4 5. "RXF,Receive FIFO full" "0,1"
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bitfld.long 0x4 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
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bitfld.long 0x4 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
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bitfld.long 0x4 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
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bitfld.long 0x4 1. "TXE,Transmit FIFO empty." "0,1"
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bitfld.long 0x4 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
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line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
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bitfld.long 0x8 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
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bitfld.long 0x8 11. "CQERR,Command Queue Error Interrupt" "0,1"
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bitfld.long 0x8 10. "CQPAUSED,Command Queue is Paused." "0,1"
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bitfld.long 0x8 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
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bitfld.long 0x8 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
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bitfld.long 0x8 7. "DERR,DMA Error Interrupt" "0,1"
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bitfld.long 0x8 6. "DCMP,DMA Complete Interrupt" "0,1"
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bitfld.long 0x8 5. "RXF,Receive FIFO full" "0,1"
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bitfld.long 0x8 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
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bitfld.long 0x8 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
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bitfld.long 0x8 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
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bitfld.long 0x8 1. "TXE,Transmit FIFO empty." "0,1"
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bitfld.long 0x8 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
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line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
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bitfld.long 0xC 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
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bitfld.long 0xC 11. "CQERR,Command Queue Error Interrupt" "0,1"
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bitfld.long 0xC 10. "CQPAUSED,Command Queue is Paused." "0,1"
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bitfld.long 0xC 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
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bitfld.long 0xC 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
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bitfld.long 0xC 7. "DERR,DMA Error Interrupt" "0,1"
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bitfld.long 0xC 6. "DCMP,DMA Complete Interrupt" "0,1"
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bitfld.long 0xC 5. "RXF,Receive FIFO full" "0,1"
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bitfld.long 0xC 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
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bitfld.long 0xC 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
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bitfld.long 0xC 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
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bitfld.long 0xC 1. "TXE,Transmit FIFO empty." "0,1"
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bitfld.long 0xC 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
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group.long 0x250++0x1F
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line.long 0x0 "DMACFG,DMA Configuration"
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bitfld.long 0x0 18. "DMAPWROFF,Power off MSPI domain upon completion of DMA operation." "0,1"
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bitfld.long 0x0 3.--4. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately),2: Auto Priority (priority raised once TX FIFO..,?"
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bitfld.long 0x0 2. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction,1: Memory to Peripheral transaction"
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bitfld.long 0x0 0.--1. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation" "0: Disable DMA Function,?,?,3: Enable HW controlled DMA Function to manage DMA.."
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line.long 0x4 "DMASTAT,DMA Status"
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bitfld.long 0x4 3. "SCRERR,Scrambling Access Alignment Error. This active high bit signals that a scrambling operation was specified for a non-word aligned DEVADDR." "0,1"
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bitfld.long 0x4 2. "DMAERR,DMA Error. This active high bit signals that an error was encountered during the DMA operation." "0,1"
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bitfld.long 0x4 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation." "0,1"
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bitfld.long 0x4 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority. All of these will be indicated with a 1. A 0 will indicate that the DMA is.." "0,1"
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line.long 0x8 "DMATARGADDR,DMA Target Address"
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hexmask.long 0x8 0.--31. 1. "TARGADDR,Target byte address for source of DMA (either read or write). In cases of non-word aligned addresses the DMA logic will take care for ensuring only the target bytes are read/written."
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line.long 0xC "DMADEVADDR,DMA Device Address"
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hexmask.long 0xC 0.--31. 1. "DEVADDR,SPI Device address for automated DMA transactions (both read and write)."
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line.long 0x10 "DMATOTCOUNT,DMA Total Transfer Count"
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hexmask.long.tbyte 0x10 0.--23. 1. "TOTCOUNT,Total Transfer Count in bytes."
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line.long 0x14 "DMABCOUNT,DMA BYTE Transfer Count"
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hexmask.long.byte 0x14 0.--7. 1. "BCOUNT,Burst transfer size in bytes. This is the number of bytes transferred when a FIFO trigger event occurs. Recommended value is 32."
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|
line.long 0x18 "DMATHRESH,Indicates FIFO level at which a DMA should be triggered. For most configurations. a setting of 8 is recommended for both read and write operations."
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|
hexmask.long.byte 0x18 8.--12. 1. "DMARXTHRESH,DMA transfer FIFO level trigger. For read operations DMA is triggered when the FIFO level is greater than this value. For write operations DMA is triggered when the FIFO level is less than this level. Each DMA operation will consist of.."
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hexmask.long.byte 0x18 0.--4. 1. "DMATXTHRESH,DMA transfer FIFO level trigger. For read operations DMA is triggered when the FIFO level is greater than this value. For write operations DMA is triggered when the FIFO level is less than this level. Each DMA operation will consist of.."
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|
line.long 0x1C "DMABOUNDARY,Allows large transfers to be broken up into smaller ones in hardware to accommodate needs of external devices and allow XIP/XIPMM. Only applicable for memory-mapped devices (PSRAM. Flash. etc) where address can be retransmitted without side.."
|
|
hexmask.long.byte 0x1C 12.--15. 1. "DMABOUND,DMA Address boundary"
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|
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hexmask.long.word 0x1C 0.--11. 1. "DMATIMELIMIT,DMA time limit. Can be used to limit the transaction time on the MSPI bus. The count is in 100 ns increments. A value of 0 disables the counter."
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|
group.long 0x2A0++0x3
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|
line.long 0x0 "CQCFG,This register controls Command Queuing (CQ) operations in a manner similar to the DMACFG register."
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|
bitfld.long 0x0 3. "CQAUTOCLEARMASK,Enable clear of CQMASK after each pause operation. This may be useful when using software flags to pause CQ." "0,1"
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bitfld.long 0x0 2. "CQPWROFF,Power off MSPI domain upon completion of DMA operation." "0,1"
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|
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bitfld.long 0x0 1. "CQPRI,Sets the Priority of the command queue DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
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bitfld.long 0x0 0. "CQEN,Command queue enable. When set will enable the processing of the command queue" "0: Disable CQ Function,1: Enable CQ Function"
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group.long 0x2A8++0x13
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|
line.long 0x0 "CQADDR,Location of the command queue in SRAM or flash memory. This register will increment as CQ operations commence. Software should only write CQADDR when CQEN is disabled. however the command queue script itself may update CQADDR in order to perform.."
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hexmask.long 0x0 0.--28. 1. "CQADDR,Address of command queue buffer in SRAM or flash. The buffer address must be aligned to a word boundary."
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line.long 0x4 "CQSTAT,Command Queue Status"
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bitfld.long 0x4 3. "CQPAUSED,Command queue is currently paused status." "0,1"
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bitfld.long 0x4 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
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bitfld.long 0x4 1. "CQCPL,Command queue operation Complete. This signals the end of the command queue operation." "0,1"
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bitfld.long 0x4 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
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line.long 0x8 "CQFLAGS,Command Queue Flags"
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hexmask.long.word 0x8 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
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|
line.long 0xC "CQSETCLEAR,Command Queue Flag Set/Clear"
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hexmask.long.byte 0xC 16.--23. 1. "CQFCLR,Clear CQFlag status bits."
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hexmask.long.byte 0xC 8.--15. 1. "CQFTOGGLE,Toggle CQFlag status bits"
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hexmask.long.byte 0xC 0.--7. 1. "CQFSET,Set CQFlag status bits. Set has priority over clear if both are high."
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line.long 0x10 "CQPAUSE,Command Queue Pause Mask"
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hexmask.long.word 0x10 0.--15. 1. "CQMASK,CQ will pause processing when ALL specified events are satisfied -- i.e. when (CQMASK and CQPAUSE)==CQMASK."
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group.long 0x2C0++0x7
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line.long 0x0 "CQCURIDX,This register can be used in conjunction with the CQENDIDX register to manage the command queue. Typically software will initialize the CQCURIDX and CQENDIDX to the same value. which will cause the CQ to be paused when enabled. Software may then.."
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|
hexmask.long.byte 0x0 0.--7. 1. "CQCURIDX,Can be used to indicate the current position of the command queue by having CQ operations write this field. A CQ hardware status flag indicates when CURIDX and ENDIDX are not equal allowing SW to pause the CQ processing until the end index is.."
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|
line.long 0x4 "CQENDIDX,Command Queue End Index"
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hexmask.long.byte 0x4 0.--7. 1. "CQENDIDX,Can be used to indicate the end position of the command queue. A CQ hardware status bit indices when CURIDX != ENDIDX so that the CQ can be paused when it reaches the end pointer."
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|
tree.end
|
|
endif
|
|
sif (cpuis("AMA3B2KK"))
|
|
tree "MSPI2"
|
|
base ad:0x50016000
|
|
group.long 0x0++0x23
|
|
line.long 0x0 "CTRL,This register is used to enable individual PIO based transactions to a device on the bus. The CFG register must be programmed properly for the transfer. and the ADDR and INSTR registers should be programmed if the SENDI and SENDA fields are enabled."
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hexmask.long.word 0x0 16.--31. 1. "XFERBYTES,Number of bytes to transmit or receive (based on TXRX bit)"
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bitfld.long 0x0 12. "ENDCX,Enable DCX signal on data [1]" "0,1"
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bitfld.long 0x0 11. "PIOSCRAMBLE,Enables data scrambling for PIO operations. This should only be used for data operations and never for commands to a device." "0,1"
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bitfld.long 0x0 10. "TXRX,1 Indicates a TX operation 0 indicates an RX operation of XFERBYTES" "0,1"
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bitfld.long 0x0 9. "SENDI,Indicates whether an instruction phase should be sent (see INSTR field and ISIZE field in CFG register)" "0,1"
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bitfld.long 0x0 8. "SENDA,Indicates whether an address phase should be sent (see ADDR register and ASIZE field in CFG register)" "0,1"
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bitfld.long 0x0 7. "ENTURN,Indicates whether TX->RX turnaround cycles should be enabled for this operation (see TURNAROUND field in CFG register)." "0,1"
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bitfld.long 0x0 6. "BIGENDIAN,1 indicates data in FIFO is in big endian format (MSB first); 0 indicates little endian data (default LSB first)." "0,1"
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bitfld.long 0x0 5. "CONT,Continuation transfer. When 1 indicates that the MSPI will hold CE low after the transaction completes. This is included for compatibility with IOM module since the MSPI transfer module can handle most cases in a single transfer. NOTE: CONT.." "0,1"
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bitfld.long 0x0 4. "ENWLAT,Enable Write Latency Counter (time between address and first data byte). Counter value is WRITELATENCY." "0,1"
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bitfld.long 0x0 3. "QUADCMD,Flag indicating that the operation is a command that should be replicated to both devices in paired QUAD mode. This is typically only used when reading/writing configuration registers in paired flash devices (do not set for memory transfers)." "0,1"
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bitfld.long 0x0 2. "BUSY,Command status: 1 indicates controller is busy (command in progress)" "0,1"
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bitfld.long 0x0 1. "STATUS,Command status: 1 indicates command has completed. Cleared by writing 1 to this bit or starting a new transfer." "0,1"
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bitfld.long 0x0 0. "START,Write to 1 to initiate a PIO transaction on the bus (typically the entire register should be written at once with this bit set)." "0,1"
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line.long 0x4 "CFG,Command formatting for PIO based transactions (initiated by writes to CTRL register)"
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hexmask.long.byte 0x4 20.--25. 1. "WRITELATENCY,Number of cycles between addressn and TX data. Qualified by ENLAT"
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bitfld.long 0x4 17. "CPOL,Serial clock polarity." "0: Clock inactive state is low.,1: Clock inactive state is high."
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bitfld.long 0x4 16. "CPHA,Serial clock phase." "0: Clock toggles in middle of data bit.,1: Clock toggles at start of data bit."
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hexmask.long.byte 0x4 8.--13. 1. "TURNAROUND,Number of turnaround cycles (for TX->RX transitions). Qualified by ENTURN or XIPENTURN bit field."
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bitfld.long 0x4 7. "SEPIO,Separate IO configuration. This bit should be set when the target device has separate MOSI and MISO pins. Respective IN/OUT bits below should be set to map pins." "0,1"
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bitfld.long 0x4 6. "ISIZE,Instruction Size" "0,1"
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bitfld.long 0x4 4.--5. "ASIZE,Address Size. Address bytes to send from ADDR register" "0: Send one address byte,1: Send two address bytes,2: Send three address bytes,3: Send four address bytes"
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newline
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hexmask.long.byte 0x4 0.--3. 1. "DEVCFG,Flash configuration for XIP and AUTO DMA operations. Controls value for SER (Slave Enable) for XIP operations and address generation for DMA/XIP modes. Also used to configure SPIFRF (frame format)."
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line.long 0x8 "ADDR,Optional Address field to send for PIO transfers"
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hexmask.long 0x8 0.--31. 1. "ADDR,Optional Address field to send (after optional instruction field) - qualified by ASIZE in CMD register. NOTE: This register is aliased to DMADEVADDR."
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line.long 0xC "INSTR,Optional Instruction field to send for PIO transfers"
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hexmask.long.word 0xC 0.--15. 1. "INSTR,Optional Instruction field to send (1st byte) - qualified by ISEND/ISIZE"
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line.long 0x10 "TXFIFO,TX Data FIFO"
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hexmask.long 0x10 0.--31. 1. "TXFIFO,Data to be transmitted. Data should normally be aligned to the LSB (pad the upper bits with zeros) unless BIGENDIAN is set."
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line.long 0x14 "RXFIFO,RX Data FIFO"
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hexmask.long 0x14 0.--31. 1. "RXFIFO,Receive data. Data is aligned to the LSB (padded zeros on upper bits) unless BIGENDIAN is set."
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|
line.long 0x18 "TXENTRIES,Number of words in TX FIFO"
|
|
hexmask.long.byte 0x18 0.--5. 1. "TXENTRIES,Number of 32-bit words/entries in TX FIFO"
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line.long 0x1C "RXENTRIES,Number of words in RX FIFO"
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|
hexmask.long.byte 0x1C 0.--5. 1. "RXENTRIES,Number of 32-bit words/entries in RX FIFO"
|
|
line.long 0x20 "THRESHOLD,Threshold levels that trigger RXFull and TXEmpty interrupts"
|
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hexmask.long.byte 0x20 8.--13. 1. "RXTHRESH,Number of entries in TX FIFO that cause RXE interrupt"
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|
newline
|
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hexmask.long.byte 0x20 0.--5. 1. "TXTHRESH,Number of entries in TX FIFO that cause TXF interrupt"
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group.long 0x100++0x7
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line.long 0x0 "MSPICFG,Timing configuration bits for the MSPI module. PRSTN. IPRSTN. and FIFORESET can be used to reset portions of the MSPI interface in order to clear error conditions. The remaining bits control clock frequency and TX/RX capture timings."
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bitfld.long 0x0 31. "PRSTN,Peripheral reset. Master reset to the entire MSPI module (DMA XIP and transfer state machines). 1=normal operation 0=in reset." "0: in reset,1: normal operation"
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newline
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bitfld.long 0x0 30. "IPRSTN,IP block reset. Write to 0 to put the transfer module in reset or 1 for normal operation. This may be required after error conditions to clear the transfer on the bus." "0,1"
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newline
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bitfld.long 0x0 29. "FIFORESET,Reset MSPI FIFO (active high). 1=reset FIFO 0=normal operation. May be used to manually flush the FIFO in error handling." "0: normal operation,1: reset FIFO"
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newline
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hexmask.long.byte 0x0 8.--13. 1. "CLKDIV,Clock Divider. Allows dividing 48 MHz base clock by integer multiples. Enumerations are provided for common frequency but any integer divide from 48 MHz is allowed. Odd divide ratios will result in a 33/66 percent duty cycle with a long low clock.."
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hexmask.long.byte 0x0 4.--7. 1. "IOMSEL,Selects which IOM is selected for CQ handshake status."
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bitfld.long 0x0 3. "TXNEG,Launches TX data a half clock cycle (~10 ns) early. This should normally be programmed to zero (NORMAL)." "0: TX launched from posedge internal clock,1: TX data launched from negedge of internal clock"
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bitfld.long 0x0 2. "RXNEG,Adjusts the RX capture phase to the negedge of the 48MHz internal clock (~10 ns early). For normal operation it is expected that RXNEG will be set to 0." "0: RX data sampled on posedge of internal clock,1: RX data sampled on negedge of internal clock"
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newline
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bitfld.long 0x0 1. "RXCAP,Controls RX data capture phase. A setting of 0 (NORMAL) captures read data at the normal capture point relative to the internal clock launch point. However to accommodate chip/pad/board delays a setting of RXCAP of 1 is expected to be used to.." "0: RX Capture phase aligns with CPHA setting,1: RX Capture phase is delayed from CPHA setting by.."
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newline
|
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bitfld.long 0x0 0. "APBCLK,Enable continuous APB clock. For power-efficient operation APBCLK should be set to 0." "0: Disable continuous clock.,1: Enable continuous clock."
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line.long 0x4 "MSPIDDR,Timing configuration bits for DDR operation of the MSPI module."
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hexmask.long.byte 0x4 16.--20. 1. "TXDQSDELAY,When OVERRIDEDQSDELAY is set this sets the DQS delay line value. In ENABLEDQS mode this acts as an offset to the computed value (should be set to 0 by default)"
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|
newline
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hexmask.long.byte 0x4 8.--12. 1. "RXDQSDELAY,When OVERRIDEDQSDELAY is set this sets the DQS delay line value. In ENABLEDQS mode this acts as an offset to the computed value (should be set to 0 by default)"
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newline
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bitfld.long 0x4 6. "ENABLEFINEDELAY,Enables use of delay line to provide fine control over traditional RX capture clock." "0,1"
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|
newline
|
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bitfld.long 0x4 5. "OVERRIDEDDRCLKOUTDELAY,Override TX delay line with the value in DQSDELAY (for TX clock offset when in QUADDDR mode)" "0,1"
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|
newline
|
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bitfld.long 0x4 4. "OVERRIDERXDQSDELAY,Override DQS delay line with the value in DQSDELAY (for RX capture in QUADDDR mode)" "0,1"
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|
newline
|
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bitfld.long 0x4 3. "DQSSYNCNEG,Use negative edge of clock for DDR data sync" "0,1"
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|
newline
|
|
bitfld.long 0x4 2. "ENABLEDQS,In EMULATEDDR mode enable DQS for read capture" "0,1"
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|
newline
|
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bitfld.long 0x4 1. "QUADDDR,Enables use of delay line to provide fine control over traditional RX capture clock." "0,1"
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|
newline
|
|
bitfld.long 0x4 0. "EMULATEDDR,Drive external clock at 1/2 rate to emulate DDR mode" "0,1"
|
|
group.long 0x110++0x1B
|
|
line.long 0x0 "PADCFG,Configuration bits for the MSPI pads. Allows pads associated with the upper quad to be mapped to corresponding bits on the lower quad. Use of Quad0 pins is recommended for optimal timing."
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|
bitfld.long 0x0 21. "REVCS,Reverse CS connections. Allows CS1 to be associated with lower data lanes and CS0 to be associated with upper data lines" "0,1"
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newline
|
|
bitfld.long 0x0 20. "IN3,Data Input pad 3 pin muxing: 0=pad[3] 1=pad[7]" "0: pad[3] 1=pad[7],?"
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newline
|
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bitfld.long 0x0 19. "IN2,Data Input pad 2 pin muxing: 0=pad[2] 1=pad[6]" "0: pad[2] 1=pad[6],?"
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|
newline
|
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bitfld.long 0x0 18. "IN1,Data Input pad 1 pin muxing: 0=pad[1] 1=pad[5]" "0: pad[1] 1=pad[5],?"
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|
newline
|
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bitfld.long 0x0 16.--17. "IN0,Data Input pad 0 pin muxing: 0=pad[0] 1=pad[4] 2=pad[1] 3=pad[5]" "0: pad[0] 1=pad[4] 2=pad[1] 3=pad[5],?,?,?"
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newline
|
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bitfld.long 0x0 4. "OUT7,Output pad 7 configuration. 0=data[7] 1=data[3]" "0: data[7] 1=data[3],?"
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|
newline
|
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bitfld.long 0x0 3. "OUT6,Output pad 6 configuration. 0=data[6] 1=data[2]" "0: data[6] 1=data[2],?"
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newline
|
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bitfld.long 0x0 2. "OUT5,Output pad 5 configuration. 0=data[5] 1=data[1]" "0: data[5] 1=data[1],?"
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|
newline
|
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bitfld.long 0x0 1. "OUT4,Output pad 4 configuration. 0=data[4] 1=data[0]" "0: data[4] 1=data[0],?"
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|
newline
|
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bitfld.long 0x0 0. "OUT3,Output pad 3 configuration. 0=data[3] 1=CLK" "0: data[3] 1=CLK,?"
|
|
line.long 0x4 "PADOUTEN,Enable bits for the MSPI output pads. Each active MSPI line should be set to 1 in the OUTEN field below."
|
|
hexmask.long.word 0x4 0.--9. 1. "OUTEN,Output pad enable configuration. Indicates which pads should be driven. Bits [3:0] are Quad0 data [7:4] are Quad1 data and [8] is clock."
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|
line.long 0x8 "PADOVEREN,Enables PIO-like pad override control"
|
|
hexmask.long.word 0x8 0.--9. 1. "OVERRIDEEN,Output pad override enable. Bit mask for pad outputs. When set to 1 the values in the OVERRIDE field are driven on the pad (output enable is implicitly set in this mode). [7:0]=data [8]=clock [9]=DM"
|
|
line.long 0xC "PADOVER,Override data value"
|
|
hexmask.long.word 0xC 0.--9. 1. "OVERRIDE,Output pad override value. [7:0]=data [8]=clock [9]=DM"
|
|
line.long 0x10 "FLASH,When any SPI flash is configured. this register must be properly programmed before XIP or AUTO DMA operations commence."
|
|
bitfld.long 0x10 11. "XIPENWLAT,Enable Write Latency counter for XIP write transactions" "0,1"
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|
newline
|
|
bitfld.long 0x10 8.--10. "XIPMIXED,Provides override controls for data operations where instruction address and data may transfer in different rates." "0: Transfers all proceed using the settings in..,1: Data operations proceed in dual data rate,?,3: Address and Data operations proceed in dual data..,?,5: Data operations proceed in quad data rate,?,7: Address and Data operations proceed in quad data.."
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newline
|
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bitfld.long 0x10 7. "XIPSENDI,Indicates whether XIP/AUTO DMA operations should send an instruction (see READINSTR field and ISIZE field in CFG)" "0,1"
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|
newline
|
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bitfld.long 0x10 6. "XIPSENDA,Indicates whether XIP/AUTO DMA operations should send an an address phase (see DMADEVADDR register and ASIZE field in CFG)" "0,1"
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|
newline
|
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bitfld.long 0x10 5. "XIPENTURN,Indicates whether XIP/AUTO DMA operations should enable TX->RX turnaround cycles" "0,1"
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|
newline
|
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bitfld.long 0x10 4. "XIPBIGENDIAN,Indicates whether XIP/AUTO DMA data transfers are in big or little endian format" "0,1"
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|
newline
|
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bitfld.long 0x10 2.--3. "XIPACK,Controls transmission of Micron XIP acknowledge cycles (Micron Flash devices only)" "0: No acknowledgment sent. Data IOs are tri-stated..,?,2: Positive acknowledgment sent. Data IOs are..,3: Negative acknowledgment sent. Data IOs are.."
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|
newline
|
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bitfld.long 0x10 1. "XIPENDCX,Enable DCX signal on data [1] for XIP/DMA operations" "0,1"
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|
newline
|
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bitfld.long 0x10 0. "XIPEN,Enable the XIP (eXecute In Place) function which effectively enables the address decoding of the MSPI device in the flash/cache address space at address 0x04000000-0x07FFFFFF." "0,1"
|
|
line.long 0x14 "XIPINSTR,When any SPI flash is configured. this register must be properly programmed before XIP or AUTO DMA operations commence."
|
|
hexmask.long.word 0x14 16.--31. 1. "READINSTR,Read command sent to flash for DMA/XIP operations"
|
|
newline
|
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hexmask.long.word 0x14 0.--15. 1. "WRITEINSTR,Write command sent for DMA operations"
|
|
line.long 0x18 "SCRAMBLING,Enables data scrambling for the specified range external flash addresses. Scrambling does not impact flash access performance."
|
|
bitfld.long 0x18 31. "SCRENABLE,Enables Data Scrambling Region. When 1 reads and writes to the range will be scrambled. When 0 data will be read/written unmodified. Address range is specified in 64K granularity and the START/END ranges are included within the range." "0,1"
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newline
|
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hexmask.long.word 0x18 16.--25. 1. "SCREND,Scrambling region end address [25:16] (64K block granularity). The END block is the LAST block included in the scrambled address range."
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newline
|
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hexmask.long.word 0x18 0.--9. 1. "SCRSTART,Scrambling region start address [25:16] (64K block granularity). The START block is the FIRST block included in the scrambled address range."
|
|
group.long 0x200++0xF
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
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|
newline
|
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bitfld.long 0x0 11. "CQERR,Command Queue Error Interrupt" "0,1"
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|
newline
|
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bitfld.long 0x0 10. "CQPAUSED,Command Queue is Paused." "0,1"
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|
newline
|
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bitfld.long 0x0 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
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newline
|
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bitfld.long 0x0 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
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|
newline
|
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bitfld.long 0x0 7. "DERR,DMA Error Interrupt" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "DCMP,DMA Complete Interrupt" "0,1"
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|
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|
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bitfld.long 0x0 5. "RXF,Receive FIFO full" "0,1"
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|
newline
|
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bitfld.long 0x0 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
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|
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|
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bitfld.long 0x0 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
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|
newline
|
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bitfld.long 0x0 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
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|
newline
|
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bitfld.long 0x0 1. "TXE,Transmit FIFO empty." "0,1"
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|
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|
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bitfld.long 0x0 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
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|
newline
|
|
bitfld.long 0x4 11. "CQERR,Command Queue Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "CQPAUSED,Command Queue is Paused." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "DERR,DMA Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "DCMP,DMA Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXF,Receive FIFO full" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXE,Transmit FIFO empty." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "CQERR,Command Queue Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "CQPAUSED,Command Queue is Paused." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "DERR,DMA Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "DCMP,DMA Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "RXF,Receive FIFO full" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "TXE,Transmit FIFO empty." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 12. "SCRERR,Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address." "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "CQERR,Command Queue Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "CQPAUSED,Command Queue is Paused." "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "CQUPD,Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts." "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "CQCMP,Command Queue Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "DERR,DMA Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "DCMP,DMA Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "RXF,Receive FIFO full" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "RXO,Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "RXU,Receive FIFO underflow (only occurs when SW reads from an empty FIFO)" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "TXO,Transmit FIFO Overflow (only occurs when SW writes to a full FIFO)." "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "TXE,Transmit FIFO empty." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "CMDCMP,Transfer complete. Note that DMA and CQ operations are layered so CMDCMP DCMP and CQ* can all be signaled simultaneously." "0,1"
|
|
group.long 0x250++0x1F
|
|
line.long 0x0 "DMACFG,DMA Configuration"
|
|
bitfld.long 0x0 18. "DMAPWROFF,Power off MSPI domain upon completion of DMA operation." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately),2: Auto Priority (priority raised once TX FIFO..,?"
|
|
newline
|
|
bitfld.long 0x0 2. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction,1: Memory to Peripheral transaction"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "DMAEN,DMA Enable. Setting this bit to EN will start the DMA operation" "0: Disable DMA Function,?,?,3: Enable HW controlled DMA Function to manage DMA.."
|
|
line.long 0x4 "DMASTAT,DMA Status"
|
|
bitfld.long 0x4 3. "SCRERR,Scrambling Access Alignment Error. This active high bit signals that a scrambling operation was specified for a non-word aligned DEVADDR." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DMAERR,DMA Error. This active high bit signals that an error was encountered during the DMA operation." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DMACPL,DMA Transfer Complete. This signals the end of the DMA operation." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DMATIP,DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data transferring data or waiting for priority. All of these will be indicated with a 1. A 0 will indicate that the DMA is.." "0,1"
|
|
line.long 0x8 "DMATARGADDR,DMA Target Address"
|
|
hexmask.long 0x8 0.--31. 1. "TARGADDR,Target byte address for source of DMA (either read or write). In cases of non-word aligned addresses the DMA logic will take care for ensuring only the target bytes are read/written."
|
|
line.long 0xC "DMADEVADDR,DMA Device Address"
|
|
hexmask.long 0xC 0.--31. 1. "DEVADDR,SPI Device address for automated DMA transactions (both read and write)."
|
|
line.long 0x10 "DMATOTCOUNT,DMA Total Transfer Count"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "TOTCOUNT,Total Transfer Count in bytes."
|
|
line.long 0x14 "DMABCOUNT,DMA BYTE Transfer Count"
|
|
hexmask.long.byte 0x14 0.--7. 1. "BCOUNT,Burst transfer size in bytes. This is the number of bytes transferred when a FIFO trigger event occurs. Recommended value is 32."
|
|
line.long 0x18 "DMATHRESH,Indicates FIFO level at which a DMA should be triggered. For most configurations. a setting of 8 is recommended for both read and write operations."
|
|
hexmask.long.byte 0x18 8.--12. 1. "DMARXTHRESH,DMA transfer FIFO level trigger. For read operations DMA is triggered when the FIFO level is greater than this value. For write operations DMA is triggered when the FIFO level is less than this level. Each DMA operation will consist of.."
|
|
newline
|
|
hexmask.long.byte 0x18 0.--4. 1. "DMATXTHRESH,DMA transfer FIFO level trigger. For read operations DMA is triggered when the FIFO level is greater than this value. For write operations DMA is triggered when the FIFO level is less than this level. Each DMA operation will consist of.."
|
|
line.long 0x1C "DMABOUNDARY,Allows large transfers to be broken up into smaller ones in hardware to accommodate needs of external devices and allow XIP/XIPMM. Only applicable for memory-mapped devices (PSRAM. Flash. etc) where address can be retransmitted without side.."
|
|
hexmask.long.byte 0x1C 12.--15. 1. "DMABOUND,DMA Address boundary"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--11. 1. "DMATIMELIMIT,DMA time limit. Can be used to limit the transaction time on the MSPI bus. The count is in 100 ns increments. A value of 0 disables the counter."
|
|
group.long 0x2A0++0x3
|
|
line.long 0x0 "CQCFG,This register controls Command Queuing (CQ) operations in a manner similar to the DMACFG register."
|
|
bitfld.long 0x0 3. "CQAUTOCLEARMASK,Enable clear of CQMASK after each pause operation. This may be useful when using software flags to pause CQ." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CQPWROFF,Power off MSPI domain upon completion of DMA operation." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CQPRI,Sets the Priority of the command queue DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
|
|
newline
|
|
bitfld.long 0x0 0. "CQEN,Command queue enable. When set will enable the processing of the command queue" "0: Disable CQ Function,1: Enable CQ Function"
|
|
group.long 0x2A8++0x13
|
|
line.long 0x0 "CQADDR,Location of the command queue in SRAM or flash memory. This register will increment as CQ operations commence. Software should only write CQADDR when CQEN is disabled. however the command queue script itself may update CQADDR in order to perform.."
|
|
hexmask.long 0x0 0.--28. 1. "CQADDR,Address of command queue buffer in SRAM or flash. The buffer address must be aligned to a word boundary."
|
|
line.long 0x4 "CQSTAT,Command Queue Status"
|
|
bitfld.long 0x4 3. "CQPAUSED,Command queue is currently paused status." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "CQERR,Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CQCPL,Command queue operation Complete. This signals the end of the command queue operation." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CQTIP,Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event." "0,1"
|
|
line.long 0x8 "CQFLAGS,Command Queue Flags"
|
|
hexmask.long.word 0x8 0.--15. 1. "CQFLAGS,Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status."
|
|
line.long 0xC "CQSETCLEAR,Command Queue Flag Set/Clear"
|
|
hexmask.long.byte 0xC 16.--23. 1. "CQFCLR,Clear CQFlag status bits."
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "CQFTOGGLE,Toggle CQFlag status bits"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CQFSET,Set CQFlag status bits. Set has priority over clear if both are high."
|
|
line.long 0x10 "CQPAUSE,Command Queue Pause Mask"
|
|
hexmask.long.word 0x10 0.--15. 1. "CQMASK,CQ will pause processing when ALL specified events are satisfied -- i.e. when (CQMASK and CQPAUSE)==CQMASK."
|
|
group.long 0x2C0++0x7
|
|
line.long 0x0 "CQCURIDX,This register can be used in conjunction with the CQENDIDX register to manage the command queue. Typically software will initialize the CQCURIDX and CQENDIDX to the same value. which will cause the CQ to be paused when enabled. Software may then.."
|
|
hexmask.long.byte 0x0 0.--7. 1. "CQCURIDX,Can be used to indicate the current position of the command queue by having CQ operations write this field. A CQ hardware status flag indicates when CURIDX and ENDIDX are not equal allowing SW to pause the CQ processing until the end index is.."
|
|
line.long 0x4 "CQENDIDX,Command Queue End Index"
|
|
hexmask.long.byte 0x4 0.--7. 1. "CQENDIDX,Can be used to indicate the end position of the command queue. A CQ hardware status bit indices when CURIDX != ENDIDX so that the CQ can be paused when it reaches the end pointer."
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "PDM (PDM Audio)"
|
|
base ad:0x50011000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "PCFG,PDM Configuration"
|
|
bitfld.long 0x0 31. "LRSWAP,Left/right channel swap." "0: No channel swapping (IFO Read LEFT_RIGHT).,1: Swap left and right channels (FIFO Read.."
|
|
hexmask.long.byte 0x0 26.--30. 1. "PGARIGHT,Right channel PGA gain."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "PGALEFT,Left channel PGA gain."
|
|
bitfld.long 0x0 17.--18. "MCLKDIV,PDM_CLK frequency divisor." "0: Divide input clock by 1,1: Divide input clock by 2,2: Divide input clock by 3,3: Divide input clock by 4"
|
|
newline
|
|
hexmask.long.byte 0x0 10.--16. 1. "SINCRATE,SINC decimation rate."
|
|
bitfld.long 0x0 9. "ADCHPD,High pass filter control." "0: Enable high pass filter.,1: Disable high pass filter."
|
|
newline
|
|
hexmask.long.byte 0x0 5.--8. 1. "HPCUTOFF,High pass filter coefficients."
|
|
bitfld.long 0x0 2.--4. "CYCLES,Number of clocks during gain-setting changes." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 1. "SOFTMUTE,Soft mute control." "0: Disable Soft Mute.,1: Enable Soft Mute."
|
|
bitfld.long 0x0 0. "PDMCOREEN,Data Streaming Control." "0: Disable Data Streaming.,1: Enable Data Streaming."
|
|
line.long 0x4 "VCFG,Voice Configuration"
|
|
bitfld.long 0x4 31. "IOCLKEN,Enable the IO clock." "0: Disable FIFO read.,1: Enable FIFO read."
|
|
bitfld.long 0x4 30. "RSTB,Reset the IP core." "0: Reset the core.,1: Enable the core."
|
|
newline
|
|
bitfld.long 0x4 27.--29. "PDMCLKSEL,Select the PDM input clock." "0: Static value.,1: PDM clock is 12 MHz.,2: PDM clock is 6 MHz.,3: PDM clock is 3 MHz.,4: PDM clock is 1.5 MHz.,5: PDM clock is 750 KHz.,6: PDM clock is 375 KHz.,7: PDM clock is 187.5 KHz."
|
|
bitfld.long 0x4 26. "PDMCLKEN,Enable the serial clock." "0: Disable serial clock.,1: Enable serial clock."
|
|
newline
|
|
bitfld.long 0x4 20. "I2SEN,I2S interface enable." "0: Disable I2S interface.,1: Enable I2S interface."
|
|
bitfld.long 0x4 19. "BCLKINV,I2S BCLK input inversion." "0: BCLK inverted.,1: BCLK not inverted."
|
|
newline
|
|
bitfld.long 0x4 17. "DMICKDEL,PDM clock sampling delay." "0: No delay.,1: 1 cycle delay."
|
|
bitfld.long 0x4 16. "SELAP,Select PDM input clock source." "0: Clock source from internal clock generator.,1: Clock source from I2S BCLK."
|
|
newline
|
|
bitfld.long 0x4 8. "PCMPACK,PCM data packing enable." "0: Disable PCM packing.,1: Enable PCM packing."
|
|
bitfld.long 0x4 3.--4. "CHSET,Set PCM channels." "0: Channel disabled.,1: Mono left channel.,2: Mono right channel.,3: Stereo channels."
|
|
line.long 0x8 "VOICESTAT,Voice Status"
|
|
hexmask.long.byte 0x8 0.--5. 1. "FIFOCNT,Valid 32-bit entries currently in the FIFO."
|
|
line.long 0xC "FIFOREAD,FIFO Read"
|
|
hexmask.long 0xC 0.--31. 1. "FIFOREAD,FIFO read data."
|
|
line.long 0x10 "FIFOFLUSH,FIFO Flush"
|
|
bitfld.long 0x10 0. "FIFOFLUSH,FIFO FLUSH." "0,1"
|
|
line.long 0x14 "FIFOTHR,FIFO Threshold"
|
|
hexmask.long.byte 0x14 0.--4. 1. "FIFOTHR,FIFO Threshold value. When the FIFO count is equal to or larger than this value (in words) a THR interrupt is generated (if enabled)"
|
|
group.long 0x200++0xF
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 4. "DERR,DMA Error received" "0,1"
|
|
bitfld.long 0x0 3. "DCMP,DMA completed a transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "UNDFL,This is the FIFO underflow interrupt." "0,1"
|
|
bitfld.long 0x0 1. "OVF,This is the FIFO overflow interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "THR,This is the FIFO threshold interrupt." "0,1"
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 4. "DERR,DMA Error received" "0,1"
|
|
bitfld.long 0x4 3. "DCMP,DMA completed a transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "UNDFL,This is the FIFO underflow interrupt." "0,1"
|
|
bitfld.long 0x4 1. "OVF,This is the FIFO overflow interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "THR,This is the FIFO threshold interrupt." "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 4. "DERR,DMA Error received" "0,1"
|
|
bitfld.long 0x8 3. "DCMP,DMA completed a transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "UNDFL,This is the FIFO underflow interrupt." "0,1"
|
|
bitfld.long 0x8 1. "OVF,This is the FIFO overflow interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "THR,This is the FIFO threshold interrupt." "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 4. "DERR,DMA Error received" "0,1"
|
|
bitfld.long 0xC 3. "DCMP,DMA completed a transfer" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "UNDFL,This is the FIFO underflow interrupt." "0,1"
|
|
bitfld.long 0xC 1. "OVF,This is the FIFO overflow interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "THR,This is the FIFO threshold interrupt." "0,1"
|
|
group.long 0x240++0x7
|
|
line.long 0x0 "DMATRIGEN,DMA Trigger Enable"
|
|
bitfld.long 0x0 1. "DTHR90,Trigger DMA at FIFO 90 percent full. This signal is also used internally for AUTOHIP function" "0,1"
|
|
bitfld.long 0x0 0. "DTHR,Trigger DMA upon when FIFO is filled to level indicated by the FIFO THRESHOLD at granularity of 16 bytes only" "0,1"
|
|
line.long 0x4 "DMATRIGSTAT,DMA Trigger Status"
|
|
bitfld.long 0x4 1. "DTHR90STAT,Triggered DMA from FIFO reaching 90 percent full" "0,1"
|
|
bitfld.long 0x4 0. "DTHRSTAT,Triggered DMA from FIFO reaching threshold" "0,1"
|
|
group.long 0x280++0x3
|
|
line.long 0x0 "DMACFG,DMA Configuration"
|
|
bitfld.long 0x0 10. "DPWROFF,Power Off the ADC System upon DMACPL." "0,1"
|
|
bitfld.long 0x0 9. "DAUTOHIP,Raise priority to high on FIFO full and DMAPRI set to low" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DMAPRI,Sets the Priority of the DMA request" "0: Low Priority (service as best effort),1: High Priority (service immediately)"
|
|
bitfld.long 0x0 2. "DMADIR,Direction" "0: Peripheral to Memory (SRAM) transaction. THe PDM..,1: Memory to Peripheral transaction. Not available.."
|
|
newline
|
|
bitfld.long 0x0 0. "DMAEN,DMA Enable" "0: Disable DMA Function,1: Enable DMA Function"
|
|
group.long 0x288++0xB
|
|
line.long 0x0 "DMATOTCOUNT,DMA Total Transfer Count"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "TOTCOUNT,Total Transfer Count. The transfer count must be a multiple of the THR setting to avoid DMA overruns."
|
|
line.long 0x4 "DMATARGADDR,DMA Target Address"
|
|
sif (cpuis("AMA3B2KK"))
|
|
hexmask.long.word 0x4 21.--31. 1. "UTARGADDR,SRAM Target"
|
|
endif
|
|
sif (cpuis("AMA3B1KK")||cpuis("AMAP31KK"))
|
|
hexmask.long.word 0x4 20.--31. 1. "UTARGADDR,SRAM Target"
|
|
newline
|
|
hexmask.long.tbyte 0x4 0.--19. 1. "LTARGADDR,DMA Target Address. This register is not updated with the current address of the DMA but will remain static with the original address during the DMA transfer."
|
|
endif
|
|
sif (cpuis("AMA3B2KK"))
|
|
hexmask.long.tbyte 0x4 0.--20. 1. "LTARGADDR,DMA Target Address. This register is not updated with the current address of the DMA but will remain static with the original address during the DMA transfer."
|
|
endif
|
|
line.long 0x8 "DMASTAT,DMA Status"
|
|
bitfld.long 0x8 2. "DMAERR,DMA Error" "0,1"
|
|
bitfld.long 0x8 1. "DMACPL,DMA Transfer Complete" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "DMATIP,DMA Transfer In Progress" "0,1"
|
|
tree.end
|
|
tree "PWRCTRL (PWR Controller Register Bank)"
|
|
base ad:0x40021000
|
|
group.long 0x0++0x2F
|
|
line.long 0x0 "SUPPLYSRC,This register controls the enable for BLE BUCK."
|
|
bitfld.long 0x0 0. "BLEBUCKEN,Enables and Selects the BLE Buck as the supply for the BLE power domain or for Burst LDO. It takes the initial value from Customer INFO space. Buck will be powered up only if there is an active request for BLEH domain or Burst mode and.." "0: Disable the BLE Buck.,1: Enable the BLE Buck."
|
|
line.long 0x4 "SUPPLYSTATUS,Provides an indicator for the BLE BUCK and SIMO BUCK status. Once the SIMO BUCK is powered up MEM and CORE LDOs are disabled."
|
|
bitfld.long 0x4 1. "BLEBUCKON,Indicates whether the BLE (if supported) domain and burst (if supported) domain is supplied from the LDO or the Buck. Buck will be powered up only if there is an active request for BLEH domain or Burst mode and appropriate feature is allowed." "0: Indicates the the LDO is supplying the BLE/Burst..,1: Indicates the the Buck is supplying the.."
|
|
newline
|
|
bitfld.long 0x4 0. "SIMOBUCKON,Indicates whether the Core/Mem low-voltage domains are supplied from the LDO or the Buck." "0: Indicates the the SIMO Buck is OFF.,1: Indicates the the SIMO Buck is ON."
|
|
line.long 0x8 "DEVPWREN,This enables various peripherals power domains."
|
|
sif (cpuis("AMA3B2KK"))
|
|
bitfld.long 0x8 15. "PWRBLEL,Power up BLE controller" "0: Power down BLE controller,1: Power up BLE controller"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA3B2KK"))
|
|
bitfld.long 0x8 14. "PWRPDM,Power up PDM block" "0: Power down PDM,1: Power up PDM"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA3B1KK")||cpuis("AMAP31KK"))
|
|
bitfld.long 0x8 13. "PWRBLEL,Power up BLE controller" "0: Power down BLE controller,1: Power up BLE controller"
|
|
newline
|
|
bitfld.long 0x8 12. "PWRPDM,Power up PDM block" "0: Power down PDM,1: Power up PDM"
|
|
newline
|
|
bitfld.long 0x8 11. "PWRMSPI,Power up MSPI Controller" "0: Power down MSPI,1: Power up MSPI"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA3B2KK"))
|
|
bitfld.long 0x8 13. "PWRMSPI2,Power up MSPI2 Controller" "0: Power down MSPI2,1: Power up MSPI2"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA3B2KK"))
|
|
bitfld.long 0x8 12. "PWRMSPI1,Power up MSPI1 Controller" "0: Power down MSPI1,1: Power up MSPI1"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA3B2KK"))
|
|
bitfld.long 0x8 11. "PWRMSPI0,Power up MSPI0 Controller" "0: Power down MSPI0,1: Power up MSPI0"
|
|
newline
|
|
endif
|
|
bitfld.long 0x8 10. "PWRSCARD,Power up SCARD Controller" "0: Power down SCARD,1: Power up SCARD"
|
|
newline
|
|
bitfld.long 0x8 9. "PWRADC,Power up ADC Digital Controller" "0: Power Down ADC,1: Power up ADC"
|
|
newline
|
|
bitfld.long 0x8 8. "PWRUART1,Power up UART Controller 1" "0: Power down UART 1,1: Power up UART 1"
|
|
newline
|
|
bitfld.long 0x8 7. "PWRUART0,Power up UART Controller 0" "0: Power down UART 0,1: Power up UART 0"
|
|
newline
|
|
bitfld.long 0x8 6. "PWRIOM5,Power up IO Master 5" "0: Power down IO Master 5,1: Power up IO Master 5"
|
|
newline
|
|
bitfld.long 0x8 5. "PWRIOM4,Power up IO Master 4" "0: Power down IO Master 4,1: Power up IO Master 4"
|
|
newline
|
|
bitfld.long 0x8 4. "PWRIOM3,Power up IO Master 3" "0: Power down IO Master 3,1: Power up IO Master 3"
|
|
newline
|
|
bitfld.long 0x8 3. "PWRIOM2,Power up IO Master 2" "0: Power down IO Master 2,1: Power up IO Master 2"
|
|
newline
|
|
bitfld.long 0x8 2. "PWRIOM1,Power up IO Master 1" "0: Power down IO Master 1,1: Power up IO Master 1"
|
|
newline
|
|
bitfld.long 0x8 1. "PWRIOM0,Power up IO Master 0" "0: Power down IO Master 0,1: Power up IO Master 0"
|
|
newline
|
|
bitfld.long 0x8 0. "PWRIOS,Power up IO Slave" "0: Power down IO slave,1: Power up IO slave"
|
|
line.long 0xC "MEMPWDINSLEEP,This controls the power down of the SRAM banks in deep sleep mode. If this is set. then the power for that SRAM bank will be gated when the core goes into deep sleep. Upon wake. the data within the SRAMs will be erased. If this is not set..."
|
|
bitfld.long 0xC 31. "CACHEPWDSLP,power down cache in deep sleep" "0: Retain cache in deep sleep,1: Power down cache in deep sleep"
|
|
newline
|
|
bitfld.long 0xC 14. "FLASH1PWDSLP,Power-down FLASH1 in deep sleep" "0: FLASH1 is kept powered on during deep sleep,1: FLASH1 is powered down during deep sleep"
|
|
newline
|
|
bitfld.long 0xC 13. "FLASH0PWDSLP,Power-down FLASH0 in deep sleep" "0: FLASH0 is kept powered on during deep sleep,1: FLASH0 is powered down during deep sleep"
|
|
newline
|
|
sif (cpuis("AMA3B2KK"))
|
|
hexmask.long.word 0xC 3.--12. 1. "SRAMPWDSLP,Selects which SRAM banks are powered down in deep sleep mode causing the contents of the bank to be lost."
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA3B1KK")||cpuis("AMAP31KK"))
|
|
hexmask.long.word 0xC 3.--12. 1. "SRAMPWDSLP,Selects which SRAM banks are powered down in deep sleep mode causing the contents of the bank to be lost."
|
|
newline
|
|
endif
|
|
bitfld.long 0xC 0.--2. "DTCMPWDSLP,power down DTCM in deep sleep" "0: All DTCM retained,1: Group0_DTCM0 powered down in deep sleep (0KB-8KB),2: Group0_DTCM1 powered down in deep sleep (8KB-32KB),3: Both DTCMs in group0 are powered down in deep..,4: Group1 DTCM powered down in deep sleep (32KB-64KB),?,6: Group1 and Group0_DTCM1 are powered down in deep..,7: All DTCMs powered down in deep sleep (0KB-64KB)"
|
|
line.long 0x10 "MEMPWREN,This register enables the individual banks for the memories. When set. power will be enabled to the banks. This register works in conjunction with the MEMPWDINSLEEP register. When this register is set. then the MEMPWRINSLEEP register will.."
|
|
bitfld.long 0x10 31. "CACHEB2,Power up Cache Bank 2. This works in conjunction with Cache enable from flash_cache module. To power up cache bank 2 cache has to be enabled and this bit has to be set." "0: Power down Cache Bank 2,1: Power up Cache Bank 2"
|
|
newline
|
|
bitfld.long 0x10 30. "CACHEB0,Power up Cache Bank 0. This works in conjunction with Cache enable from flash_cache module. To power up cache bank 0 cache has to be enabled and this bit has to be set." "0: Power down Cache Bank 0,1: Power up Cache Bank 0"
|
|
newline
|
|
bitfld.long 0x10 14. "FLASH1,Power up FLASH1" "0: Power down FLASH1,1: Power up FLASH1"
|
|
newline
|
|
bitfld.long 0x10 13. "FLASH0,Power up FLASH0" "0: Power down FLASH0,1: Power up FLASH0"
|
|
newline
|
|
sif (cpuis("AMA3B2KK"))
|
|
hexmask.long.word 0x10 3.--12. 1. "SRAM,Power up SRAM groups"
|
|
newline
|
|
endif
|
|
sif (cpuis("AMA3B1KK")||cpuis("AMAP31KK"))
|
|
hexmask.long.word 0x10 3.--12. 1. "SRAM,Power up SRAM groups"
|
|
newline
|
|
endif
|
|
bitfld.long 0x10 0.--2. "DTCM,Power up DTCM" "0: Do not enable power to any DTCMs,1: Power ON only GROUP0_DTCM0,2: Power ON only GROUP0_DTCM1,3: Power ON only DTCMs in group0,4: Power ON only DTCMs in group1,?,?,7: Power ON all DTCMs"
|
|
line.long 0x14 "MEMPWRSTATUS,It provides the power status for all the memory banks including- caches. FLASH (0 and 1) and all the SRAM groups. The status here should reflect the enable provided by the MEMPWREN register. There may be a lag time between setting the bits.."
|
|
bitfld.long 0x14 16. "CACHEB2,This bit is 1 if power is supplied to Cache Bank 2" "0,1"
|
|
newline
|
|
bitfld.long 0x14 15. "CACHEB0,This bit is 1 if power is supplied to Cache Bank 0" "0,1"
|
|
newline
|
|
bitfld.long 0x14 14. "FLASH1,This bit is 1 if power is supplied to FLASH 1" "0,1"
|
|
newline
|
|
bitfld.long 0x14 13. "FLASH0,This bit is 1 if power is supplied to FLASH 0" "0,1"
|
|
newline
|
|
bitfld.long 0x14 12. "SRAM9,This bit is 1 if power is supplied to SRAM GROUP9" "0,1"
|
|
newline
|
|
bitfld.long 0x14 11. "SRAM8,This bit is 1 if power is supplied to SRAM GROUP8" "0,1"
|
|
newline
|
|
bitfld.long 0x14 10. "SRAM7,This bit is 1 if power is supplied to SRAM GROUP7" "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. "SRAM6,This bit is 1 if power is supplied to SRAM GROUP6" "0,1"
|
|
newline
|
|
bitfld.long 0x14 8. "SRAM5,This bit is 1 if power is supplied to SRAM GROUP5" "0,1"
|
|
newline
|
|
bitfld.long 0x14 7. "SRAM4,This bit is 1 if power is supplied to SRAM GROUP4" "0,1"
|
|
newline
|
|
bitfld.long 0x14 6. "SRAM3,This bit is 1 if power is supplied to SRAM GROUP3" "0,1"
|
|
newline
|
|
bitfld.long 0x14 5. "SRAM2,This bit is 1 if power is supplied to SRAM GROUP2" "0,1"
|
|
newline
|
|
bitfld.long 0x14 4. "SRAM1,This bit is 1 if power is supplied to SRAM GROUP1" "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. "SRAM0,This bit is 1 if power is supplied to SRAM GROUP0" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "DTCM1,This bit is 1 if power is supplied to DTCM GROUP1" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "DTCM01,This bit is 1 if power is supplied to DTCM GROUP0_1" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "DTCM00,This bit is 1 if power is supplied to DTCM GROUP0_0" "0,1"
|
|
line.long 0x18 "DEVPWRSTATUS,This provides the power status for the peripheral devices- BLEL. PDM. PDM. MSPI. SCARD. ADC. UART0 and 1. IOM5 to 0. IOSLAVE and MCUL (DMA and Fabrics) and MCUH (ARM core). The status here should reflect the enable provided by the DEVPWREN.."
|
|
bitfld.long 0x18 9. "BLEH,This bit is 1 if power is supplied to BLEH" "0,1"
|
|
newline
|
|
bitfld.long 0x18 8. "BLEL,This bit is 1 if power is supplied to BLEL" "0,1"
|
|
newline
|
|
bitfld.long 0x18 7. "PWRPDM,This bit is 1 if power is supplied to PDM" "0,1"
|
|
newline
|
|
bitfld.long 0x18 6. "PWRMSPI,This bit is 1 if power is supplied to MSPI" "0,1"
|
|
newline
|
|
bitfld.long 0x18 5. "PWRADC,This bit is 1 if power is supplied to ADC" "0,1"
|
|
newline
|
|
bitfld.long 0x18 4. "HCPC,This bit is 1 if power is supplied to HCPC domain (IO MASTER4 5 6)" "0,1"
|
|
newline
|
|
bitfld.long 0x18 3. "HCPB,This bit is 1 if power is supplied to HCPB domain (IO MASTER 0 1 2)" "0,1"
|
|
newline
|
|
bitfld.long 0x18 2. "HCPA,This bit is 1 if power is supplied to HCPA domain (IO SLAVE UART0 UART1 SCARD)" "0,1"
|
|
newline
|
|
bitfld.long 0x18 1. "MCUH,This bit is 1 if power is supplied to MCUH" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "MCUL,This bit is 1 if power is supplied to MCUL" "0,1"
|
|
line.long 0x1C "SRAMCTRL,This register provides additional fine-tune power management controls for the SRAMs and the SRAM controller. This includes enabling light sleep for the SRAM and TCM banks. and clock gating for reduced dynamic power."
|
|
hexmask.long.word 0x1C 8.--19. 1. "SRAMLIGHTSLEEP,Light Sleep enable for each TCM/SRAM bank. When 1 corresponding bank will be put into light sleep. For optimal power banks should be put into light sleep while the system is active but the bank has minimal or no accesses."
|
|
newline
|
|
bitfld.long 0x1C 2. "SRAMMASTERCLKGATE,This bit is 1 when the master clock gate is enabled (top-level clock gate for entire SRAM block)" "0: Disables Master SRAM Clock Gating,1: Enable Master SRAM Clock Gate"
|
|
newline
|
|
bitfld.long 0x1C 1. "SRAMCLKGATE,This bit is 1 if clock gating is allowed for individual system SRAMs" "0: Disables Individual SRAM Clock Gating,1: Enable Individual SRAM Clock Gating"
|
|
line.long 0x20 "ADCSTATUS,This provides the power status for various blocks within the ADC. These status comes directly from the ADC module and is captured through this interface."
|
|
bitfld.long 0x20 5. "REFBUFPWD,This bit indicates that the ADC REFBUF is powered down" "0,1"
|
|
newline
|
|
bitfld.long 0x20 4. "REFKEEPPWD,This bit indicates that the ADC REFKEEP is powered down" "0,1"
|
|
newline
|
|
bitfld.long 0x20 3. "VBATPWD,This bit indicates that the ADC VBAT resistor divider is powered down" "0,1"
|
|
newline
|
|
bitfld.long 0x20 2. "VPTATPWD,This bit indicates that the ADC temperature sensor input buffer is powered down" "0,1"
|
|
newline
|
|
bitfld.long 0x20 1. "BGTPWD,This bit indicates that the ADC Band Gap is powered down" "0,1"
|
|
newline
|
|
bitfld.long 0x20 0. "ADCPWD,This bit indicates that the ADC is powered down" "0,1"
|
|
line.long 0x24 "MISC,This register includes additional debug control bits. This is an internal Ambiq-only register. Customers should not attempt to change this or else functionality cannot be guaranteed."
|
|
bitfld.long 0x24 6. "MEMVRLPBLE,Control Bit to let Mem VR go to lp mode in deep sleep even when BLEL or BLEH is powered on given none of the other domains require it." "0: Mem VR will stay in active mode when BLE is..,1: Mem VR can go to lp mode even when BLE is.."
|
|
newline
|
|
bitfld.long 0x24 3. "FORCEMEMVRLPTIMERS,Control Bit to force Mem VR to LP mode in deep sleep even when hfrc based ctimer or stimer is running." "0,1"
|
|
line.long 0x28 "DEVPWREVENTEN,This register controls which feature trigger will result in an event to the CPU. It includes all the power on status for the core domains. as well as the Burst event. If any bits are set. then if the domain is turned on. it will result in.."
|
|
bitfld.long 0x28 31. "BURSTEVEN,Control BURST status event" "0: Disable BURST status event,1: Enable BURST status event"
|
|
newline
|
|
bitfld.long 0x28 30. "BURSTFEATUREEVEN,Control BURSTFEATURE status event" "0: Disable BURSTFEATURE status event,1: Enable BURSTFEATURE status event"
|
|
newline
|
|
bitfld.long 0x28 29. "BLEFEATUREEVEN,Control BLEFEATURE status event" "0: Disable BLEFEATURE status event,1: Enable BLEFEATURE status event"
|
|
newline
|
|
bitfld.long 0x28 8. "BLELEVEN,Control BLE power-on status event" "0: Disable BLE power-on status event,1: Enable BLE power-on status event"
|
|
newline
|
|
bitfld.long 0x28 7. "PDMEVEN,Control PDM power-on status event" "0: Disable PDM power-on status event,1: Enable PDM power-on status event"
|
|
newline
|
|
bitfld.long 0x28 6. "MSPIEVEN,Control MSPI power-on status event" "0: Disable MSPI power-on status event,1: Enable MSPI power-on status event"
|
|
newline
|
|
bitfld.long 0x28 5. "ADCEVEN,Control ADC power-on status event" "0: Disable ADC power-on status event,1: Enable ADC power-on status event"
|
|
newline
|
|
bitfld.long 0x28 4. "HCPCEVEN,Control HCPC power-on status event" "0: Disable HCPC power-on status event,1: Enable HCPC power-on status event"
|
|
newline
|
|
bitfld.long 0x28 3. "HCPBEVEN,Control HCPB power-on status event" "0: Disable HCPB power-on status event,1: Enable HCPB power-on status event"
|
|
newline
|
|
bitfld.long 0x28 2. "HCPAEVEN,Control HCPA power-on status event" "0: Disable HCPA power-on status event,1: Enable HCPA power-on status event"
|
|
newline
|
|
bitfld.long 0x28 1. "MCUHEVEN,Control MCUH power-on status event" "0: Disable MCUH power-on status event,1: Enable MCHU power-on status event"
|
|
newline
|
|
bitfld.long 0x28 0. "MCULEVEN,Control MCUL power-on status event" "0: Disable MCUL power-on status event,1: Enable MCUL power-on status event"
|
|
line.long 0x2C "MEMPWREVENTEN,This register controls which power enable for the memories will result in an event to the CPU. It includes all the power on status for the memory domains. If any bits are set. then if the domain is turned on. it will result in an event to.."
|
|
bitfld.long 0x2C 31. "CACHEB2EN,Control CACHEB2 power-on status event" "0: Disable CACHE BANK 2 status event,1: Enable CACHE BANK 2 status event"
|
|
newline
|
|
bitfld.long 0x2C 30. "CACHEB0EN,Control CACHE BANK 0 power-on status event" "0: Disable CACHE BANK 0 status event,1: Enable CACHE BANK 0 status event"
|
|
newline
|
|
bitfld.long 0x2C 14. "FLASH1EN,Control FLASH power-on status event" "0: Disables FLASH status event,1: Enable FLASH status event"
|
|
newline
|
|
bitfld.long 0x2C 13. "FLASH0EN,Control FLASH power-on status event" "0: Disables FLASH status event,1: Enable FLASH status event"
|
|
newline
|
|
hexmask.long.word 0x2C 3.--12. 1. "SRAMEN,Control SRAM power-on status event"
|
|
newline
|
|
bitfld.long 0x2C 0.--2. "DTCMEN,Enable DTCM power-on status event" "0: Do not enable DTCM power-on status event,1: Enable GROUP0_DTCM0 power on status event,2: Enable GROUP0_DTCM1 power on status event,3: Enable DTCMs in group0 power on status event,4: Enable DTCMs in group1 power on status event,?,?,7: Enable all DTCM power on status event"
|
|
tree.end
|
|
tree "RSTGEN (MCU Reset Generator)"
|
|
base ad:0x40000000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CFG,Reset configuration register. This controls the reset enables for brownout condition. and for the expiration of the watch dog timer."
|
|
bitfld.long 0x0 1. "WDREN,Watchdog Timer Reset Enable. NOTE: The WDT module must also be configured for WDT reset. This includes enabling the RESEN bit in WDTCFG register in Watch dog timer block." "0,1"
|
|
bitfld.long 0x0 0. "BODHREN,Brown out high (2.1 V) reset enable." "0,1"
|
|
line.long 0x4 "SWPOI,This is the software POI reset. writing the key value to this register will trigger a POI to the system. This will cause a reset to all blocks except for registers in clock gen. RTC and the STIMER."
|
|
hexmask.long.byte 0x4 0.--7. 1. "SWPOIKEY,0x1B generates a software POI reset. This is a write-only register. Reading from this register will yield only all 0's."
|
|
line.long 0x8 "SWPOR,This is the software POR reset. Writing the key value to this register will trigger a POR to the system. This will cause a reset to all blocks except for registers in clock gen. RTC. power management unit. the STIMER. and the power management unit."
|
|
hexmask.long.byte 0x8 0.--7. 1. "SWPORKEY,0xD4 generates a software POR reset."
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "TPIURST,This will trigger a reset for the TPIU unit."
|
|
bitfld.long 0x0 0. "TPIURST,Static reset for the TPIU. Write to '1' to assert reset to TPIU. Write to '0' to clear the reset." "0,1"
|
|
group.long 0x200++0xF
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 0. "BODH,Enables an interrupt that triggers when VCC is below BODH level." "0,1"
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 0. "BODH,Enables an interrupt that triggers when VCC is below BODH level." "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 0. "BODH,Enables an interrupt that triggers when VCC is below BODH level." "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 0. "BODH,Enables an interrupt that triggers when VCC is below BODH level." "0,1"
|
|
group.long 0xFFFF000++0x3
|
|
line.long 0x0 "STAT,This register contains the status for brownout events and the causes for resets.\n NOTE 1: All bits in this register. including reserved bits. are writable. Therefore care should be taken not to write this register.\n NOTE 2: This register does not.."
|
|
bitfld.long 0x0 31. "SBOOT,Set when booting securely (SBL)." "0,1"
|
|
bitfld.long 0x0 30. "FBOOT,Set if current boot was initiated by soft reset and resulted in Fast Boot (SBL)." "0,1"
|
|
bitfld.long 0x0 10. "BOBSTAT,A BLE/Burst Regulator Brownout Event occurred (SBL)." "0,1"
|
|
bitfld.long 0x0 9. "BOFSTAT,A Memory Regulator Brownout Event occurred (SBL)." "0,1"
|
|
bitfld.long 0x0 8. "BOCSTAT,A Core Regulator Brownout Event occurred (SBL)." "0,1"
|
|
bitfld.long 0x0 7. "BOUSTAT,An Unregulated Supply Brownout Event occurred (SBL)." "0,1"
|
|
bitfld.long 0x0 6. "WDRSTAT,Reset was initiated by a Watchdog Timer Reset (SBL)." "0,1"
|
|
bitfld.long 0x0 5. "DBGRSTAT,Reset was a initiated by Debugger Reset (SBL)." "0,1"
|
|
bitfld.long 0x0 4. "POIRSTAT,Reset was a initiated by Software POI Reset (SBL)." "0,1"
|
|
bitfld.long 0x0 3. "SWRSTAT,Reset was a initiated by SW POR or AIRCR Reset (SBL)." "0,1"
|
|
bitfld.long 0x0 2. "BORSTAT,Reset was initiated by a Brown-Out Reset (SBL)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PORSTAT,Reset was initiated by a Power-On Reset (SBL)." "0,1"
|
|
bitfld.long 0x0 0. "EXRSTAT,Reset was initiated by an External Reset (SBL)." "0,1"
|
|
tree.end
|
|
tree "RTC (Real Time Clock)"
|
|
base ad:0x40004200
|
|
group.long 0x40++0x13
|
|
line.long 0x0 "CTRLOW,This counter contains the values for hour. minutes. seconds and 100ths of a second Counter."
|
|
hexmask.long.byte 0x0 24.--29. 1. "CTRHR,Hours Counter"
|
|
hexmask.long.byte 0x0 16.--22. 1. "CTRMIN,Minutes Counter"
|
|
hexmask.long.byte 0x0 8.--14. 1. "CTRSEC,Seconds Counter"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "CTR100,100ths of a second Counter"
|
|
line.long 0x4 "CTRUP,This register contains the day. month and year information. It contains which day in the week. and the century as well. The information of the century can also be derived from the year information. The 31st bit contains the error bit. See.."
|
|
bitfld.long 0x4 31. "CTERR,Counter read error status. Error is triggered when software reads the lower word of the counters and fails to read the upper counter within 1/100 second. This is because when the lower counter is read the upper counter is held off from.." "0: No read error occurred,1: Read error occurred"
|
|
bitfld.long 0x4 28. "CEB,Century enable" "0: Disable the Century bit from changing,1: Enable the Century bit to change"
|
|
bitfld.long 0x4 27. "CB,Century" "0: Century is 2000s,1: Century is 1900s/2100s"
|
|
newline
|
|
bitfld.long 0x4 24.--26. "CTRWKDY,Weekdays Counter" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 16.--23. 1. "CTRYR,Years Counter"
|
|
hexmask.long.byte 0x4 8.--12. 1. "CTRMO,Months Counter"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "CTRDATE,Date Counter"
|
|
line.long 0x8 "ALMLOW,This register is the Alarm settings for hours. minutes. second and 1/100th seconds settings."
|
|
hexmask.long.byte 0x8 24.--29. 1. "ALMHR,Hours Alarm"
|
|
hexmask.long.byte 0x8 16.--22. 1. "ALMMIN,Minutes Alarm"
|
|
hexmask.long.byte 0x8 8.--14. 1. "ALMSEC,Seconds Alarm"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "ALM100,100ths of a second Alarm"
|
|
line.long 0xC "ALMUP,This register is the alarm settings for week. month and day."
|
|
bitfld.long 0xC 16.--18. "ALMWKDY,Weekdays Alarm" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 8.--12. 1. "ALMMO,Months Alarm"
|
|
hexmask.long.byte 0xC 0.--5. 1. "ALMDATE,Date Alarm"
|
|
line.long 0x10 "RTCCTL,This is the register control for the RTC module. It sets the 12 or 24 hours mode. enables counter writes and sets the alarm repeat interval."
|
|
bitfld.long 0x10 5. "HR1224,Hours Counter mode" "0: Hours in 24 hour mode,1: Hours in 12 hour mode"
|
|
bitfld.long 0x10 4. "RSTOP,RTC input clock control" "0: Allow the RTC input clock to run,1: Stop the RTC input clock"
|
|
bitfld.long 0x10 1.--3. "RPT,Alarm repeat interval" "0: Alarm interrupt disabled,1: Interrupt every year,2: Interrupt every month,3: Interrupt every week,4: Interrupt every day,5: Interrupt every hour,6: Interrupt every minute,7: Interrupt every second/10th/100th"
|
|
newline
|
|
bitfld.long 0x10 0. "WRTC,Counter write control" "0: Counter writes are disabled,1: Counter writes are enabled"
|
|
group.long 0x100++0xF
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 0. "ALM,RTC Alarm interrupt" "0,1"
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 0. "ALM,RTC Alarm interrupt" "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 0. "ALM,RTC Alarm interrupt" "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 0. "ALM,RTC Alarm interrupt" "0,1"
|
|
tree.end
|
|
tree "SCARD (Serial ISO7816)"
|
|
base ad:0x40080000
|
|
group.long 0x0++0x3B
|
|
line.long 0x0 "SR,ISO7816 interrupt status"
|
|
bitfld.long 0x0 6. "FHF,FIFO Half Full." "?,1: FIFO is half full."
|
|
bitfld.long 0x0 5. "FT2REND,TX to RX finished." "0: TX to RX not completed.,1: TX to RX completed."
|
|
bitfld.long 0x0 4. "PE,Parity Error." "0: No parity error.,1: Parity error."
|
|
newline
|
|
bitfld.long 0x0 3. "OVR,RX FIFO overflow." "0: RX FIFO no overflow.,1: RX FIFO overflow."
|
|
bitfld.long 0x0 2. "FER,Framing error." "0: No framing error detected.,1: Framing error."
|
|
bitfld.long 0x0 1. "TBERBF,FIFO empty (transmit) or full (receive)." "0: Transmit: FIFO not empty.,1: Transmit: FIFO empty."
|
|
newline
|
|
bitfld.long 0x0 0. "FNE,RX FIFO not empty." "0: RX FIFO empty.,1: RX FIFO not empty."
|
|
line.long 0x4 "IER,ISO7816 interrupt enable"
|
|
bitfld.long 0x4 6. "FHFEN,FIFO Half Full interrupt enable." "0,1"
|
|
bitfld.long 0x4 5. "FT2RENDEN,TX to RX finished interrupt enable." "0,1"
|
|
bitfld.long 0x4 4. "PEEN,Parity Error interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OVREN,RX FIFOI overflow interrupt enable." "0,1"
|
|
bitfld.long 0x4 2. "FEREN,Framing error interrupt enable." "0,1"
|
|
bitfld.long 0x4 1. "TBERBFEN,FIFO empty (transmit) or full (receive) interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "FNEEN,RX FIFO not empty interrupt enable." "0,1"
|
|
line.long 0x8 "TCR,ISO7816 transmit control"
|
|
bitfld.long 0x8 7. "DMAMD,DMA direction." "0,1"
|
|
bitfld.long 0x8 6. "FIP,Parity select." "0,1"
|
|
bitfld.long 0x8 5. "AUTOCONV,Automatic conversion." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PROT,PROT control." "0,1"
|
|
bitfld.long 0x8 3. "TR,Transmit/receive mode." "0,1"
|
|
bitfld.long 0x8 2. "LCT,Fast TX to RX." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "SS,Use first byte to configure conversion." "0,1"
|
|
bitfld.long 0x8 0. "CONV,Conversion inversion control." "0,1"
|
|
line.long 0xC "UCR,ISO7816 user control"
|
|
bitfld.long 0xC 3. "RETXEN,Enable TX/RX time configuration." "0,1"
|
|
bitfld.long 0xC 2. "RSTIN,Reset polarity." "0,1"
|
|
bitfld.long 0xC 1. "RIU,ISO7816 reset. This bit is write-only." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "CST,Clock control." "0,1"
|
|
line.long 0x10 "DR,ISO7816 data"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DR,Data register."
|
|
line.long 0x14 "BPRL,ISO7816 baud rate low"
|
|
hexmask.long.byte 0x14 0.--7. 1. "BPRL,Baud rate low"
|
|
line.long 0x18 "BPRH,ISO7816 baud rate high"
|
|
hexmask.long.byte 0x18 0.--3. 1. "BPRH,Baud rate high"
|
|
line.long 0x1C "UCR1,ISO7816 user control 1"
|
|
bitfld.long 0x1C 5. "ENLASTB,Enable last byte function." "0,1"
|
|
bitfld.long 0x1C 4. "CLKIOV,Output clock level." "0,1"
|
|
bitfld.long 0x1C 3. "T1PAREN,Parity check control." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 2. "STSP,ETU counter control. This bit is write-only." "0,1"
|
|
bitfld.long 0x1C 0. "PR,Query Card Detect." "0,1"
|
|
line.long 0x20 "SR1,ISO7816 interrupt status 1"
|
|
bitfld.long 0x20 3. "IDLE,ISO7816 idle." "0: ISO7816 active.,1: ISO7816 idle."
|
|
bitfld.long 0x20 2. "SYNCEND,Write complete synchronization." "0: Incomplete.,1: Synchronization complete."
|
|
bitfld.long 0x20 1. "PRL,Card insert/remove." "?,1: Card inserted/removed."
|
|
newline
|
|
bitfld.long 0x20 0. "ECNTOVER,ETU counter overflow." "?,1: ETU overflow."
|
|
line.long 0x24 "IER1,ISO7816 interrupt enable 1"
|
|
bitfld.long 0x24 2. "SYNCENDEN,Write complete synchronization interrupt enable." "0,1"
|
|
bitfld.long 0x24 1. "PRLEN,Card insert/remove interrupt enable." "0,1"
|
|
bitfld.long 0x24 0. "ECNTOVEREN,ETU counter overflow interrupt enable." "0,1"
|
|
line.long 0x28 "ECNTL,ETU counter low"
|
|
hexmask.long.byte 0x28 0.--7. 1. "ECNTL,ETU counter low register."
|
|
line.long 0x2C "ECNTH,ETU counter high"
|
|
hexmask.long.byte 0x2C 0.--7. 1. "ECNTH,ETU counter high register."
|
|
line.long 0x30 "GTR,ISO7816 guard time configuration"
|
|
hexmask.long.byte 0x30 0.--7. 1. "GTR,Guard time configuration register."
|
|
line.long 0x34 "RETXCNT,ISO7816 resend count"
|
|
hexmask.long.byte 0x34 0.--3. 1. "RETXCNT,Resend count register."
|
|
line.long 0x38 "RETXCNTRMI,ISO7816 resent count inquiry"
|
|
hexmask.long.byte 0x38 0.--3. 1. "RETXCNTRMI,Resent count inquiry register."
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "CLKCTRL,SCARD external clock control"
|
|
bitfld.long 0x0 1. "APBCLKEN,Enable the SCARD APB clock to run continuously." "0,1"
|
|
bitfld.long 0x0 0. "CLKEN,Enable the serial source clock for SCARD." "0,1"
|
|
tree.end
|
|
tree "SECURITY (Security Interfaces)"
|
|
base ad:0x40030000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Control"
|
|
bitfld.long 0x0 31. "CRCERROR,CRC Error Status - Set to 1 if an error occurs during a CRC operation. Cleared when CTRL register is written (with any value). Usually indicates an invalid address range." "0,1"
|
|
sif (cpuis("AMA3B2KK"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "FUNCTION,Function Select"
|
|
endif
|
|
sif (cpuis("AMA3B1KK")||cpuis("AMAP31KK"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "FUNCTION,Function Select"
|
|
endif
|
|
bitfld.long 0x0 0. "ENABLE,Function Enable. Software should set the ENABLE bit to initiate a CRC operation. Hardware will clear the ENABLE bit upon completion." "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "SRCADDR,Source Address"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Source Buffer Address. Address may be byte aligned but the length must be a multiple of 4 bits."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "LEN,Length"
|
|
sif (cpuis("AMA3B1KK")||cpuis("AMAP31KK"))
|
|
hexmask.long.tbyte 0x0 2.--19. 1. "LEN,Buffer size (bottom two bits assumed to be zero to ensure a multiple of 4 bytes)"
|
|
endif
|
|
sif (cpuis("AMA3B2KK"))
|
|
hexmask.long.tbyte 0x0 2.--23. 1. "LEN,Buffer size (bottom two bits assumed to be zero to ensure a multiple of 4 bytes)"
|
|
endif
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "RESULT,CRC Seed/Result"
|
|
hexmask.long 0x0 0.--31. 1. "CRC,CRC Seed/Result. Software must seed the CRC with 0xFFFFFFFF before starting a CRC operation (unless the CRC is continued from a previous operation)."
|
|
group.long 0x78++0x17
|
|
line.long 0x0 "LOCKCTRL,LOCK Control"
|
|
hexmask.long.byte 0x0 0.--7. 1. "SELECT,LOCK Function Select register."
|
|
line.long 0x4 "LOCKSTAT,LOCK Status"
|
|
hexmask.long 0x4 0.--31. 1. "STATUS,LOCK Status register. This register is a bit mask for which resources are currently unlocked. These bits are one-hot per resource."
|
|
line.long 0x8 "KEY0,Key0"
|
|
hexmask.long 0x8 0.--31. 1. "KEY0,Bits [31:0] of the 128-bit key should be written to this register. To protect key values the register always returns 0x00000000."
|
|
line.long 0xC "KEY1,Key1"
|
|
hexmask.long 0xC 0.--31. 1. "KEY1,Bits [63:32] of the 128-bit key should be written to this register. To protect key values the register always returns 0x00000000."
|
|
line.long 0x10 "KEY2,Key2"
|
|
hexmask.long 0x10 0.--31. 1. "KEY2,Bits [95:64] of the 128-bit key should be written to this register. To protect key values the register always returns 0x00000000."
|
|
line.long 0x14 "KEY3,Key3"
|
|
hexmask.long 0x14 0.--31. 1. "KEY3,Bits [127:96] of the 128-bit key should be written to this register. To protect key values the register always returns 0x00000000."
|
|
tree.end
|
|
tree "UART (Universal Asynchronous Receiver/Transmitter)"
|
|
base ad:0x0
|
|
tree "UART0"
|
|
base ad:0x4001C000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "DR,UART Data"
|
|
bitfld.long 0x0 11. "OEDATA,This is the overrun error indicator." "0: No error on UART OEDATA overrun error indicator.,1: Error on UART OEDATA overrun error indicator."
|
|
bitfld.long 0x0 10. "BEDATA,This is the break error indicator." "0: No error on UART BEDATA break error indicator.,1: Error on UART BEDATA break error indicator."
|
|
newline
|
|
bitfld.long 0x0 9. "PEDATA,This is the parity error indicator." "0: No error on UART PEDATA parity error indicator.,1: Error on UART PEDATA parity error indicator."
|
|
bitfld.long 0x0 8. "FEDATA,This is the framing error indicator." "0: No error on UART FEDATA framing error indicator.,1: Error on UART FEDATA framing error indicator."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,This is the UART data port."
|
|
line.long 0x4 "RSR,UART Status"
|
|
bitfld.long 0x4 3. "OESTAT,This is the overrun error indicator." "0: No error on UART OESTAT overrun error indicator.,1: Error on UART OESTAT overrun error indicator."
|
|
bitfld.long 0x4 2. "BESTAT,This is the break error indicator." "0: No error on UART BESTAT break error indicator.,1: Error on UART BESTAT break error indicator."
|
|
newline
|
|
bitfld.long 0x4 1. "PESTAT,This is the parity error indicator." "0: No error on UART PESTAT parity error indicator.,1: Error on UART PESTAT parity error indicator."
|
|
bitfld.long 0x4 0. "FESTAT,This is the framing error indicator." "0: No error on UART FESTAT framing error indicator.,1: Error on UART FESTAT framing error indicator."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "FR,Flag"
|
|
bitfld.long 0x0 8. "TXBUSY,This bit holds the transmit BUSY indicator." "0,1"
|
|
bitfld.long 0x0 7. "TXFE,This bit holds the transmit FIFO empty indicator." "?,1: Transmit FIFO is empty."
|
|
newline
|
|
bitfld.long 0x0 6. "RXFF,This bit holds the receive FIFO full indicator." "?,1: Receive FIFO is full."
|
|
bitfld.long 0x0 5. "TXFF,This bit holds the transmit FIFO full indicator." "?,1: Transmit FIFO is full."
|
|
newline
|
|
bitfld.long 0x0 4. "RXFE,This bit holds the receive FIFO empty indicator." "?,1: Receive FIFO is empty."
|
|
bitfld.long 0x0 3. "BUSY,This bit holds the busy indicator." "?,1: UART busy indicator."
|
|
newline
|
|
bitfld.long 0x0 2. "DCD,This bit holds the data carrier detect indicator." "?,1: Data carrier detect detected."
|
|
bitfld.long 0x0 1. "DSR,This bit holds the data set ready indicator." "?,1: Data set ready."
|
|
newline
|
|
bitfld.long 0x0 0. "CTS,This bit holds the clear to send indicator." "?,1: Clear to send is indicated."
|
|
group.long 0x20++0x27
|
|
line.long 0x0 "ILPR,IrDA Counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ILPDVSR,These bits hold the IrDA counter divisor."
|
|
line.long 0x4 "IBRD,Integer Baud Rate Divisor"
|
|
hexmask.long.word 0x4 0.--15. 1. "DIVINT,These bits hold the baud integer divisor."
|
|
line.long 0x8 "FBRD,Fractional Baud Rate Divisor"
|
|
hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,These bits hold the baud fractional divisor."
|
|
line.long 0xC "LCRH,Line Control High"
|
|
bitfld.long 0xC 7. "SPS,This bit holds the stick parity select." "0,1"
|
|
bitfld.long 0xC 5.--6. "WLEN,These bits hold the write length." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 4. "FEN,This bit holds the FIFO enable." "0,1"
|
|
bitfld.long 0xC 3. "STP2,This bit holds the two stop bits select." "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "EPS,This bit holds the even parity select." "0,1"
|
|
bitfld.long 0xC 1. "PEN,This bit holds the parity enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "BRK,This bit holds the break set." "0,1"
|
|
line.long 0x10 "CR,Control"
|
|
bitfld.long 0x10 15. "CTSEN,This bit enables CTS hardware flow control." "0,1"
|
|
bitfld.long 0x10 14. "RTSEN,This bit enables RTS hardware flow control." "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "OUT2,This bit holds modem Out2." "0,1"
|
|
bitfld.long 0x10 12. "OUT1,This bit holds modem Out1." "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "RTS,This bit enables request to send." "0,1"
|
|
bitfld.long 0x10 10. "DTR,This bit enables data transmit ready." "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "RXE,This bit is the receive enable." "0,1"
|
|
bitfld.long 0x10 8. "TXE,This bit is the transmit enable." "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "LBE,This bit is the loopback enable." "0,1"
|
|
bitfld.long 0x10 4.--6. "CLKSEL,This bit field is the UART clock select." "0: No UART clock. This is the low power default.,1: 24 MHz clock.,2: 12 MHz clock.,3: 6 MHz clock.,4: 3 MHz clock.,?,?,?"
|
|
newline
|
|
bitfld.long 0x10 3. "CLKEN,This bit is the UART clock enable." "0,1"
|
|
bitfld.long 0x10 2. "SIRLP,This bit is the SIR low power select." "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "SIREN,This bit is the SIR ENDEC enable." "0,1"
|
|
bitfld.long 0x10 0. "UARTEN,This bit is the UART enable." "0,1"
|
|
line.long 0x14 "IFLS,FIFO Interrupt Level Select"
|
|
bitfld.long 0x14 3.--5. "RXIFLSEL,These bits hold the receive FIFO interrupt level." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 0.--2. "TXIFLSEL,These bits hold the transmit FIFO interrupt level." "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "IER,Interrupt Enable"
|
|
bitfld.long 0x18 10. "OEIM,This bit holds the overflow interrupt enable." "0,1"
|
|
bitfld.long 0x18 9. "BEIM,This bit holds the break error interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 8. "PEIM,This bit holds the parity error interrupt enable." "0,1"
|
|
bitfld.long 0x18 7. "FEIM,This bit holds the framing error interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 6. "RTIM,This bit holds the receive timeout interrupt enable." "0,1"
|
|
bitfld.long 0x18 5. "TXIM,This bit holds the transmit interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 4. "RXIM,This bit holds the receive interrupt enable." "0,1"
|
|
bitfld.long 0x18 3. "DSRMIM,This bit holds the modem DSR interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 2. "DCDMIM,This bit holds the modem DCD interrupt enable." "0,1"
|
|
bitfld.long 0x18 1. "CTSMIM,This bit holds the modem CTS interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXCMPMIM,This bit holds the modem TXCMP interrupt enable." "0,1"
|
|
line.long 0x1C "IES,Interrupt Status"
|
|
bitfld.long 0x1C 10. "OERIS,This bit holds the overflow interrupt status." "0,1"
|
|
bitfld.long 0x1C 9. "BERIS,This bit holds the break error interrupt status." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 8. "PERIS,This bit holds the parity error interrupt status." "0,1"
|
|
bitfld.long 0x1C 7. "FERIS,This bit holds the framing error interrupt status." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 6. "RTRIS,This bit holds the receive timeout interrupt status." "0,1"
|
|
bitfld.long 0x1C 5. "TXRIS,This bit holds the transmit interrupt status." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 4. "RXRIS,This bit holds the receive interrupt status." "0,1"
|
|
bitfld.long 0x1C 3. "DSRMRIS,This bit holds the modem DSR interrupt status." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 2. "DCDMRIS,This bit holds the modem DCD interrupt status." "0,1"
|
|
bitfld.long 0x1C 1. "CTSMRIS,This bit holds the modem CTS interrupt status." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "TXCMPMRIS,This bit holds the modem TXCMP interrupt status." "0,1"
|
|
line.long 0x20 "MIS,Masked Interrupt Status"
|
|
bitfld.long 0x20 10. "OEMIS,This bit holds the overflow interrupt status masked." "0,1"
|
|
bitfld.long 0x20 9. "BEMIS,This bit holds the break error interrupt status masked." "0,1"
|
|
newline
|
|
bitfld.long 0x20 8. "PEMIS,This bit holds the parity error interrupt status masked." "0,1"
|
|
bitfld.long 0x20 7. "FEMIS,This bit holds the framing error interrupt status masked." "0,1"
|
|
newline
|
|
bitfld.long 0x20 6. "RTMIS,This bit holds the receive timeout interrupt status masked." "0,1"
|
|
bitfld.long 0x20 5. "TXMIS,This bit holds the transmit interrupt status masked." "0,1"
|
|
newline
|
|
bitfld.long 0x20 4. "RXMIS,This bit holds the receive interrupt status masked." "0,1"
|
|
bitfld.long 0x20 3. "DSRMMIS,This bit holds the modem DSR interrupt status masked." "0,1"
|
|
newline
|
|
bitfld.long 0x20 2. "DCDMMIS,This bit holds the modem DCD interrupt status masked." "0,1"
|
|
bitfld.long 0x20 1. "CTSMMIS,This bit holds the modem CTS interrupt status masked." "0,1"
|
|
newline
|
|
bitfld.long 0x20 0. "TXCMPMMIS,This bit holds the modem TXCMP interrupt status masked." "0,1"
|
|
line.long 0x24 "IEC,Interrupt Clear"
|
|
bitfld.long 0x24 10. "OEIC,This bit holds the overflow interrupt clear." "0,1"
|
|
bitfld.long 0x24 9. "BEIC,This bit holds the break error interrupt clear." "0,1"
|
|
newline
|
|
bitfld.long 0x24 8. "PEIC,This bit holds the parity error interrupt clear." "0,1"
|
|
bitfld.long 0x24 7. "FEIC,This bit holds the framing error interrupt clear." "0,1"
|
|
newline
|
|
bitfld.long 0x24 6. "RTIC,This bit holds the receive timeout interrupt clear." "0,1"
|
|
bitfld.long 0x24 5. "TXIC,This bit holds the transmit interrupt clear." "0,1"
|
|
newline
|
|
bitfld.long 0x24 4. "RXIC,This bit holds the receive interrupt clear." "0,1"
|
|
bitfld.long 0x24 3. "DSRMIC,This bit holds the modem DSR interrupt clear." "0,1"
|
|
newline
|
|
bitfld.long 0x24 2. "DCDMIC,This bit holds the modem DCD interrupt clear." "0,1"
|
|
bitfld.long 0x24 1. "CTSMIC,This bit holds the modem CTS interrupt clear." "0,1"
|
|
newline
|
|
bitfld.long 0x24 0. "TXCMPMIC,This bit holds the modem TXCMP interrupt clear." "0,1"
|
|
tree.end
|
|
tree "UART1"
|
|
base ad:0x4001D000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "DR,UART Data"
|
|
bitfld.long 0x0 11. "OEDATA,This is the overrun error indicator." "0: No error on UART OEDATA overrun error indicator.,1: Error on UART OEDATA overrun error indicator."
|
|
bitfld.long 0x0 10. "BEDATA,This is the break error indicator." "0: No error on UART BEDATA break error indicator.,1: Error on UART BEDATA break error indicator."
|
|
newline
|
|
bitfld.long 0x0 9. "PEDATA,This is the parity error indicator." "0: No error on UART PEDATA parity error indicator.,1: Error on UART PEDATA parity error indicator."
|
|
bitfld.long 0x0 8. "FEDATA,This is the framing error indicator." "0: No error on UART FEDATA framing error indicator.,1: Error on UART FEDATA framing error indicator."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,This is the UART data port."
|
|
line.long 0x4 "RSR,UART Status"
|
|
bitfld.long 0x4 3. "OESTAT,This is the overrun error indicator." "0: No error on UART OESTAT overrun error indicator.,1: Error on UART OESTAT overrun error indicator."
|
|
bitfld.long 0x4 2. "BESTAT,This is the break error indicator." "0: No error on UART BESTAT break error indicator.,1: Error on UART BESTAT break error indicator."
|
|
newline
|
|
bitfld.long 0x4 1. "PESTAT,This is the parity error indicator." "0: No error on UART PESTAT parity error indicator.,1: Error on UART PESTAT parity error indicator."
|
|
bitfld.long 0x4 0. "FESTAT,This is the framing error indicator." "0: No error on UART FESTAT framing error indicator.,1: Error on UART FESTAT framing error indicator."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "FR,Flag"
|
|
bitfld.long 0x0 8. "TXBUSY,This bit holds the transmit BUSY indicator." "0,1"
|
|
bitfld.long 0x0 7. "TXFE,This bit holds the transmit FIFO empty indicator." "?,1: Transmit FIFO is empty."
|
|
newline
|
|
bitfld.long 0x0 6. "RXFF,This bit holds the receive FIFO full indicator." "?,1: Receive FIFO is full."
|
|
bitfld.long 0x0 5. "TXFF,This bit holds the transmit FIFO full indicator." "?,1: Transmit FIFO is full."
|
|
newline
|
|
bitfld.long 0x0 4. "RXFE,This bit holds the receive FIFO empty indicator." "?,1: Receive FIFO is empty."
|
|
bitfld.long 0x0 3. "BUSY,This bit holds the busy indicator." "?,1: UART busy indicator."
|
|
newline
|
|
bitfld.long 0x0 2. "DCD,This bit holds the data carrier detect indicator." "?,1: Data carrier detect detected."
|
|
bitfld.long 0x0 1. "DSR,This bit holds the data set ready indicator." "?,1: Data set ready."
|
|
newline
|
|
bitfld.long 0x0 0. "CTS,This bit holds the clear to send indicator." "?,1: Clear to send is indicated."
|
|
group.long 0x20++0x27
|
|
line.long 0x0 "ILPR,IrDA Counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ILPDVSR,These bits hold the IrDA counter divisor."
|
|
line.long 0x4 "IBRD,Integer Baud Rate Divisor"
|
|
hexmask.long.word 0x4 0.--15. 1. "DIVINT,These bits hold the baud integer divisor."
|
|
line.long 0x8 "FBRD,Fractional Baud Rate Divisor"
|
|
hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,These bits hold the baud fractional divisor."
|
|
line.long 0xC "LCRH,Line Control High"
|
|
bitfld.long 0xC 7. "SPS,This bit holds the stick parity select." "0,1"
|
|
bitfld.long 0xC 5.--6. "WLEN,These bits hold the write length." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 4. "FEN,This bit holds the FIFO enable." "0,1"
|
|
bitfld.long 0xC 3. "STP2,This bit holds the two stop bits select." "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "EPS,This bit holds the even parity select." "0,1"
|
|
bitfld.long 0xC 1. "PEN,This bit holds the parity enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "BRK,This bit holds the break set." "0,1"
|
|
line.long 0x10 "CR,Control"
|
|
bitfld.long 0x10 15. "CTSEN,This bit enables CTS hardware flow control." "0,1"
|
|
bitfld.long 0x10 14. "RTSEN,This bit enables RTS hardware flow control." "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "OUT2,This bit holds modem Out2." "0,1"
|
|
bitfld.long 0x10 12. "OUT1,This bit holds modem Out1." "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "RTS,This bit enables request to send." "0,1"
|
|
bitfld.long 0x10 10. "DTR,This bit enables data transmit ready." "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "RXE,This bit is the receive enable." "0,1"
|
|
bitfld.long 0x10 8. "TXE,This bit is the transmit enable." "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "LBE,This bit is the loopback enable." "0,1"
|
|
bitfld.long 0x10 4.--6. "CLKSEL,This bit field is the UART clock select." "0: No UART clock. This is the low power default.,1: 24 MHz clock.,2: 12 MHz clock.,3: 6 MHz clock.,4: 3 MHz clock.,?,?,?"
|
|
newline
|
|
bitfld.long 0x10 3. "CLKEN,This bit is the UART clock enable." "0,1"
|
|
bitfld.long 0x10 2. "SIRLP,This bit is the SIR low power select." "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "SIREN,This bit is the SIR ENDEC enable." "0,1"
|
|
bitfld.long 0x10 0. "UARTEN,This bit is the UART enable." "0,1"
|
|
line.long 0x14 "IFLS,FIFO Interrupt Level Select"
|
|
bitfld.long 0x14 3.--5. "RXIFLSEL,These bits hold the receive FIFO interrupt level." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 0.--2. "TXIFLSEL,These bits hold the transmit FIFO interrupt level." "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "IER,Interrupt Enable"
|
|
bitfld.long 0x18 10. "OEIM,This bit holds the overflow interrupt enable." "0,1"
|
|
bitfld.long 0x18 9. "BEIM,This bit holds the break error interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 8. "PEIM,This bit holds the parity error interrupt enable." "0,1"
|
|
bitfld.long 0x18 7. "FEIM,This bit holds the framing error interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 6. "RTIM,This bit holds the receive timeout interrupt enable." "0,1"
|
|
bitfld.long 0x18 5. "TXIM,This bit holds the transmit interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 4. "RXIM,This bit holds the receive interrupt enable." "0,1"
|
|
bitfld.long 0x18 3. "DSRMIM,This bit holds the modem DSR interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 2. "DCDMIM,This bit holds the modem DCD interrupt enable." "0,1"
|
|
bitfld.long 0x18 1. "CTSMIM,This bit holds the modem CTS interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXCMPMIM,This bit holds the modem TXCMP interrupt enable." "0,1"
|
|
line.long 0x1C "IES,Interrupt Status"
|
|
bitfld.long 0x1C 10. "OERIS,This bit holds the overflow interrupt status." "0,1"
|
|
bitfld.long 0x1C 9. "BERIS,This bit holds the break error interrupt status." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 8. "PERIS,This bit holds the parity error interrupt status." "0,1"
|
|
bitfld.long 0x1C 7. "FERIS,This bit holds the framing error interrupt status." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 6. "RTRIS,This bit holds the receive timeout interrupt status." "0,1"
|
|
bitfld.long 0x1C 5. "TXRIS,This bit holds the transmit interrupt status." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 4. "RXRIS,This bit holds the receive interrupt status." "0,1"
|
|
bitfld.long 0x1C 3. "DSRMRIS,This bit holds the modem DSR interrupt status." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 2. "DCDMRIS,This bit holds the modem DCD interrupt status." "0,1"
|
|
bitfld.long 0x1C 1. "CTSMRIS,This bit holds the modem CTS interrupt status." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "TXCMPMRIS,This bit holds the modem TXCMP interrupt status." "0,1"
|
|
line.long 0x20 "MIS,Masked Interrupt Status"
|
|
bitfld.long 0x20 10. "OEMIS,This bit holds the overflow interrupt status masked." "0,1"
|
|
bitfld.long 0x20 9. "BEMIS,This bit holds the break error interrupt status masked." "0,1"
|
|
newline
|
|
bitfld.long 0x20 8. "PEMIS,This bit holds the parity error interrupt status masked." "0,1"
|
|
bitfld.long 0x20 7. "FEMIS,This bit holds the framing error interrupt status masked." "0,1"
|
|
newline
|
|
bitfld.long 0x20 6. "RTMIS,This bit holds the receive timeout interrupt status masked." "0,1"
|
|
bitfld.long 0x20 5. "TXMIS,This bit holds the transmit interrupt status masked." "0,1"
|
|
newline
|
|
bitfld.long 0x20 4. "RXMIS,This bit holds the receive interrupt status masked." "0,1"
|
|
bitfld.long 0x20 3. "DSRMMIS,This bit holds the modem DSR interrupt status masked." "0,1"
|
|
newline
|
|
bitfld.long 0x20 2. "DCDMMIS,This bit holds the modem DCD interrupt status masked." "0,1"
|
|
bitfld.long 0x20 1. "CTSMMIS,This bit holds the modem CTS interrupt status masked." "0,1"
|
|
newline
|
|
bitfld.long 0x20 0. "TXCMPMMIS,This bit holds the modem TXCMP interrupt status masked." "0,1"
|
|
line.long 0x24 "IEC,Interrupt Clear"
|
|
bitfld.long 0x24 10. "OEIC,This bit holds the overflow interrupt clear." "0,1"
|
|
bitfld.long 0x24 9. "BEIC,This bit holds the break error interrupt clear." "0,1"
|
|
newline
|
|
bitfld.long 0x24 8. "PEIC,This bit holds the parity error interrupt clear." "0,1"
|
|
bitfld.long 0x24 7. "FEIC,This bit holds the framing error interrupt clear." "0,1"
|
|
newline
|
|
bitfld.long 0x24 6. "RTIC,This bit holds the receive timeout interrupt clear." "0,1"
|
|
bitfld.long 0x24 5. "TXIC,This bit holds the transmit interrupt clear." "0,1"
|
|
newline
|
|
bitfld.long 0x24 4. "RXIC,This bit holds the receive interrupt clear." "0,1"
|
|
bitfld.long 0x24 3. "DSRMIC,This bit holds the modem DSR interrupt clear." "0,1"
|
|
newline
|
|
bitfld.long 0x24 2. "DCDMIC,This bit holds the modem DCD interrupt clear." "0,1"
|
|
bitfld.long 0x24 1. "CTSMIC,This bit holds the modem CTS interrupt clear." "0,1"
|
|
newline
|
|
bitfld.long 0x24 0. "TXCMPMIC,This bit holds the modem TXCMP interrupt clear." "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "VCOMP (Voltage Comparator)"
|
|
base ad:0x4000C000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CFG,The Voltage Comparator Configuration Register contains the software control for selecting between the 4 options for the positive input as well as the multiple options for the reference input."
|
|
hexmask.long.byte 0x0 16.--19. 1. "LVLSEL,When the reference input NSEL is set to NSEL_DAC this bit field selects the voltage level for the negative input to the comparator."
|
|
bitfld.long 0x0 8.--9. "NSEL,This bit field selects the negative input to the comparator." "0: Use external reference 1 for reference input.,1: Use external reference 2 for reference input.,2: Use external reference 3 for reference input.,3: Use DAC output selected by LVLSEL for reference.."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "PSEL,This bit field selects the positive input to the comparator." "0: Use VDDADJ for the positive input.,1: Use the temperature sensor output for the..,2: Use external voltage 0 for positive input.,3: Use external voltage 1 for positive input."
|
|
line.long 0x4 "STAT,Status"
|
|
bitfld.long 0x4 1. "PWDSTAT,This bit indicates the power down state of the voltage comparator." "?,1: The voltage comparator is powered down."
|
|
bitfld.long 0x4 0. "CMPOUT,This bit is 1 if the positive input of the comparator is greater than the negative input." "0: The negative input of the comparator is greater..,1: The positive input of the comparator is greater.."
|
|
line.long 0x8 "PWDKEY,Write a value of 0x37 to unlock. write any other value to lock. This register also indicates lock status when read. When in the unlocked state (i.e. 0x37 has been written). it reads as 1. When in the locked state. it reads as 0."
|
|
hexmask.long 0x8 0.--31. 1. "PWDKEY,Key register value."
|
|
group.long 0x200++0xF
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 1. "OUTHI,This bit is the vcompout high interrupt." "0,1"
|
|
bitfld.long 0x0 0. "OUTLOW,This bit is the vcompout low interrupt." "0,1"
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 1. "OUTHI,This bit is the vcompout high interrupt." "0,1"
|
|
bitfld.long 0x4 0. "OUTLOW,This bit is the vcompout low interrupt." "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 1. "OUTHI,This bit is the vcompout high interrupt." "0,1"
|
|
bitfld.long 0x8 0. "OUTLOW,This bit is the vcompout low interrupt." "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 1. "OUTHI,This bit is the vcompout high interrupt." "0,1"
|
|
bitfld.long 0xC 0. "OUTLOW,This bit is the vcompout low interrupt." "0,1"
|
|
tree.end
|
|
tree "WDT (Watchdog Timer)"
|
|
base ad:0x40024000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CFG,This is the configuration register for the watch dog timer. It controls the enable. interrupt set. clocks for the timer. the compare values for the counters to trigger a reset or interrupt. This register can only be written to if the watch dog timer.."
|
|
bitfld.long 0x0 24.--26. "CLKSEL,Select the frequency for the WDT. All values not enumerated below are undefined." "0: Low Power Mode. This setting disables the watch..,1: 128 Hz LFRC clock.,2: 16 Hz LFRC clock.,3: 1 Hz LFRC clock.,4: 1/16th Hz LFRC clock.,?,?,?"
|
|
hexmask.long.byte 0x0 16.--23. 1. "INTVAL,This bit field is the compare value for counter bits 7:0 to generate a watchdog interrupt."
|
|
hexmask.long.byte 0x0 8.--15. 1. "RESVAL,This bit field is the compare value for counter bits 7:0 to generate a watchdog reset. This will cause a software reset."
|
|
bitfld.long 0x0 2. "RESEN,This bit field enables the WDT reset. This needs to be set together with the WDREN bit in REG_RSTGEN_CFG register (in reset gen) to trigger the reset." "0,1"
|
|
bitfld.long 0x0 1. "INTEN,This bit field enables the WDT interrupt. Note : This bit must be set before the interrupt status bit will reflect a watchdog timer expiration. The IER interrupt register must also be enabled for a WDT interrupt to be sent to the NVIC." "0,1"
|
|
bitfld.long 0x0 0. "WDTEN,This bit field enables the WDT." "0,1"
|
|
line.long 0x4 "RSTRT,This register will Restart the watchdog timer. Writing a special key value into this register will result in the watch dog timer being reset. so that the count will start again. It is expected that the software will periodically write to this.."
|
|
hexmask.long.byte 0x4 0.--7. 1. "RSTRT,Writing 0xB2 to WDTRSTRT restarts the watchdog timer. This is a write only register. Reading this register will only provide all 0."
|
|
line.long 0x8 "LOCK,This register locks the watch dog timer. Once it is locked. the configuration register (WDTCFG) for watch dog timer cannot be written to."
|
|
hexmask.long.byte 0x8 0.--7. 1. "LOCK,Writing 0x3A locks the watchdog timer. Once locked the WDTCFG reg cannot be written and WDTEN is set."
|
|
line.long 0xC "COUNT,This register holds the current count for the watch dog timer. This is a read only register. SW cannot set the value in the counter. but can reset it."
|
|
hexmask.long.byte 0xC 0.--7. 1. "COUNT,Read-Only current value of the WDT counter"
|
|
group.long 0x200++0xF
|
|
line.long 0x0 "INTEN,Set bits in this register to allow this module to generate the corresponding interrupt."
|
|
bitfld.long 0x0 0. "WDTINT,Watchdog Timer Interrupt." "0,1"
|
|
line.long 0x4 "INTSTAT,Read bits from this register to discover the cause of a recent interrupt."
|
|
bitfld.long 0x4 0. "WDTINT,Watchdog Timer Interrupt." "0,1"
|
|
line.long 0x8 "INTCLR,Write a 1 to a bit in this register to clear the interrupt status associated with that bit."
|
|
bitfld.long 0x8 0. "WDTINT,Watchdog Timer Interrupt." "0,1"
|
|
line.long 0xC "INTSET,Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes)."
|
|
bitfld.long 0xC 0. "WDTINT,Watchdog Timer Interrupt." "0,1"
|
|
tree.end
|
|
AUTOINDENT.OFF
|